arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17 #include <linux/sched/smt.h>
  18
  19 #include <asm/spec-ctrl.h>
  20 #include <asm/cmdline.h>
  21 #include <asm/bugs.h>
  22 #include <asm/processor.h>
  23 #include <asm/processor-flags.h>
  24 #include <asm/fpu/internal.h>
  25 #include <asm/msr.h>
  26 #include <asm/vmx.h>
  27 #include <asm/paravirt.h>
  28 #include <asm/alternative.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/set_memory.h>
  31 #include <asm/intel-family.h>
  32 #include <asm/e820/api.h>
  33 #include <asm/hypervisor.h>
  34 #include <linux/bpf.h>
  35
  36 #include "cpu.h"
  37
  38 static void __init spectre_v1_select_mitigation(void);
  39 static void __init spectre_v2_select_mitigation(void);
  40 static void __init retbleed_select_mitigation(void);
  41 static void __init spectre_v2_user_select_mitigation(void);
  42 static void __init ssb_select_mitigation(void);
  43 static void __init l1tf_select_mitigation(void);
  44 static void __init mds_select_mitigation(void);
  45 static void __init md_clear_update_mitigation(void);
  46 static void __init md_clear_select_mitigation(void);
  47 static void __init taa_select_mitigation(void);
  48 static void __init mmio_select_mitigation(void);
  49 static void __init srbds_select_mitigation(void);
  50
  51 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
  52 u64 x86_spec_ctrl_base;
  53 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  54
  55 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
  56 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
  57 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
  58
  59 static DEFINE_MUTEX(spec_ctrl_mutex);
  60
  61 /* Update SPEC_CTRL MSR and its cached copy unconditionally */
  62 static void update_spec_ctrl(u64 val)
  63 {
  64         this_cpu_write(x86_spec_ctrl_current, val);
  65         wrmsrl(MSR_IA32_SPEC_CTRL, val);
  66 }
  67
  68 /*
  69  * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
  70  * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
  71  */
  72 void update_spec_ctrl_cond(u64 val)
  73 {
  74         if (this_cpu_read(x86_spec_ctrl_current) == val)
  75                 return;
  76
  77         this_cpu_write(x86_spec_ctrl_current, val);
  78
  79         /*
  80          * When KERNEL_IBRS this MSR is written on return-to-user, unless
  81          * forced the update can be delayed until that time.
  82          */
  83         if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
  84                 wrmsrl(MSR_IA32_SPEC_CTRL, val);
  85 }
  86
  87 u64 spec_ctrl_current(void)
  88 {
  89         return this_cpu_read(x86_spec_ctrl_current);
  90 }
  91 EXPORT_SYMBOL_GPL(spec_ctrl_current);
  92
  93 /*
  94  * AMD specific MSR info for Speculative Store Bypass control.
  95  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  96  */
  97 u64 __ro_after_init x86_amd_ls_cfg_base;
  98 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  99
 100 /* Control conditional STIBP in switch_to() */
 101 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 102 /* Control conditional IBPB in switch_mm() */
 103 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 104 /* Control unconditional IBPB in switch_mm() */
 105 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 106
 107 /* Control MDS CPU buffer clear before returning to user space */
 108 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
 109 EXPORT_SYMBOL_GPL(mds_user_clear);
 110 /* Control MDS CPU buffer clear before idling (halt, mwait) */
 111 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
 112 EXPORT_SYMBOL_GPL(mds_idle_clear);
 113
 114 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
 115 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
 116 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
 117
 118 void __init check_bugs(void)
 119 {
 120         identify_boot_cpu();
 121
 122         /*
 123          * identify_boot_cpu() initialized SMT support information, let the
 124          * core code know.
 125          */
 126         cpu_smt_check_topology();
 127
 128         if (!IS_ENABLED(CONFIG_SMP)) {
 129                 pr_info("CPU: ");
 130                 print_cpu_info(&boot_cpu_data);
 131         }
 132
 133         /*
 134          * Read the SPEC_CTRL MSR to account for reserved bits which may
 135          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
 136          * init code as it is not enumerated and depends on the family.
 137          */
 138         if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
 139                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 140
 141                 /*
 142                  * Previously running kernel (kexec), may have some controls
 143                  * turned ON. Clear them and let the mitigations setup below
 144                  * rediscover them based on configuration.
 145                  */
 146                 x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
 147         }
 148
 149         /* Select the proper CPU mitigations before patching alternatives: */
 150         spectre_v1_select_mitigation();
 151         spectre_v2_select_mitigation();
 152         /*
 153          * retbleed_select_mitigation() relies on the state set by
 154          * spectre_v2_select_mitigation(); specifically it wants to know about
 155          * spectre_v2=ibrs.
 156          */
 157         retbleed_select_mitigation();
 158         /*
 159          * spectre_v2_user_select_mitigation() relies on the state set by
 160          * retbleed_select_mitigation(); specifically the STIBP selection is
 161          * forced for UNRET.
 162          */
 163         spectre_v2_user_select_mitigation();
 164         ssb_select_mitigation();
 165         l1tf_select_mitigation();
 166         md_clear_select_mitigation();
 167         srbds_select_mitigation();
 168
 169         arch_smt_update();
 170
 171 #ifdef CONFIG_X86_32
 172         /*
 173          * Check whether we are able to run this kernel safely on SMP.
 174          *
 175          * - i386 is no longer supported.
 176          * - In order to run on anything without a TSC, we need to be
 177          *   compiled for a i486.
 178          */
 179         if (boot_cpu_data.x86 < 4)
 180                 panic("Kernel requires i486+ for 'invlpg' and other features");
 181
 182         init_utsname()->machine[1] =
 183                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 184         alternative_instructions();
 185
 186         fpu__init_check_bugs();
 187 #else /* CONFIG_X86_64 */
 188         alternative_instructions();
 189
 190         /*
 191          * Make sure the first 2MB area is not mapped by huge pages
 192          * There are typically fixed size MTRRs in there and overlapping
 193          * MTRRs into large pages causes slow downs.
 194          *
 195          * Right now we don't do that with gbpages because there seems
 196          * very little benefit for that case.
 197          */
 198         if (!direct_gbpages)
 199                 set_memory_4k((unsigned long)__va(0), 1);
 200 #endif
 201 }
 202
 203 /*
 204  * NOTE: For VMX, this function is not called in the vmexit path.
 205  * It uses vmx_spec_ctrl_restore_host() instead.
 206  */
 207 void
 208 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 209 {
 210         u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
 211         struct thread_info *ti = current_thread_info();
 212
 213         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 214                 if (hostval != guestval) {
 215                         msrval = setguest ? guestval : hostval;
 216                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 217                 }
 218         }
 219
 220         /*
 221          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 222          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 223          */
 224         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 225             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 226                 return;
 227
 228         /*
 229          * If the host has SSBD mitigation enabled, force it in the host's
 230          * virtual MSR value. If its not permanently enabled, evaluate
 231          * current's TIF_SSBD thread flag.
 232          */
 233         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 234                 hostval = SPEC_CTRL_SSBD;
 235         else
 236                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 237
 238         /* Sanitize the guest value */
 239         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 240
 241         if (hostval != guestval) {
 242                 unsigned long tif;
 243
 244                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 245                                  ssbd_spec_ctrl_to_tif(hostval);
 246
 247                 speculation_ctrl_update(tif);
 248         }
 249 }
 250 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 251
 252 static void x86_amd_ssb_disable(void)
 253 {
 254         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 255
 256         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 257                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 258         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 259                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 260 }
 261
 262 #undef pr_fmt
 263 #define pr_fmt(fmt)     "MDS: " fmt
 264
 265 /* Default mitigation for MDS-affected CPUs */
 266 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
 267 static bool mds_nosmt __ro_after_init = false;
 268
 269 static const char * const mds_strings[] = {
 270         [MDS_MITIGATION_OFF]    = "Vulnerable",
 271         [MDS_MITIGATION_FULL]   = "Mitigation: Clear CPU buffers",
 272         [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
 273 };
 274
 275 static void __init mds_select_mitigation(void)
 276 {
 277         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
 278                 mds_mitigation = MDS_MITIGATION_OFF;
 279                 return;
 280         }
 281
 282         if (mds_mitigation == MDS_MITIGATION_FULL) {
 283                 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
 284                         mds_mitigation = MDS_MITIGATION_VMWERV;
 285
 286                 static_branch_enable(&mds_user_clear);
 287
 288                 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
 289                     (mds_nosmt || cpu_mitigations_auto_nosmt()))
 290                         cpu_smt_disable(false);
 291         }
 292 }
 293
 294 static int __init mds_cmdline(char *str)
 295 {
 296         if (!boot_cpu_has_bug(X86_BUG_MDS))
 297                 return 0;
 298
 299         if (!str)
 300                 return -EINVAL;
 301
 302         if (!strcmp(str, "off"))
 303                 mds_mitigation = MDS_MITIGATION_OFF;
 304         else if (!strcmp(str, "full"))
 305                 mds_mitigation = MDS_MITIGATION_FULL;
 306         else if (!strcmp(str, "full,nosmt")) {
 307                 mds_mitigation = MDS_MITIGATION_FULL;
 308                 mds_nosmt = true;
 309         }
 310
 311         return 0;
 312 }
 313 early_param("mds", mds_cmdline);
 314
 315 #undef pr_fmt
 316 #define pr_fmt(fmt)     "TAA: " fmt
 317
 318 /* Default mitigation for TAA-affected CPUs */
 319 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
 320 static bool taa_nosmt __ro_after_init;
 321
 322 static const char * const taa_strings[] = {
 323         [TAA_MITIGATION_OFF]            = "Vulnerable",
 324         [TAA_MITIGATION_UCODE_NEEDED]   = "Vulnerable: Clear CPU buffers attempted, no microcode",
 325         [TAA_MITIGATION_VERW]           = "Mitigation: Clear CPU buffers",
 326         [TAA_MITIGATION_TSX_DISABLED]   = "Mitigation: TSX disabled",
 327 };
 328
 329 static void __init taa_select_mitigation(void)
 330 {
 331         u64 ia32_cap;
 332
 333         if (!boot_cpu_has_bug(X86_BUG_TAA)) {
 334                 taa_mitigation = TAA_MITIGATION_OFF;
 335                 return;
 336         }
 337
 338         /* TSX previously disabled by tsx=off */
 339         if (!boot_cpu_has(X86_FEATURE_RTM)) {
 340                 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
 341                 return;
 342         }
 343
 344         if (cpu_mitigations_off()) {
 345                 taa_mitigation = TAA_MITIGATION_OFF;
 346                 return;
 347         }
 348
 349         /*
 350          * TAA mitigation via VERW is turned off if both
 351          * tsx_async_abort=off and mds=off are specified.
 352          */
 353         if (taa_mitigation == TAA_MITIGATION_OFF &&
 354             mds_mitigation == MDS_MITIGATION_OFF)
 355                 return;
 356
 357         if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
 358                 taa_mitigation = TAA_MITIGATION_VERW;
 359         else
 360                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 361
 362         /*
 363          * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
 364          * A microcode update fixes this behavior to clear CPU buffers. It also
 365          * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
 366          * ARCH_CAP_TSX_CTRL_MSR bit.
 367          *
 368          * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
 369          * update is required.
 370          */
 371         ia32_cap = x86_read_arch_cap_msr();
 372         if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
 373             !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
 374                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 375
 376         /*
 377          * TSX is enabled, select alternate mitigation for TAA which is
 378          * the same as MDS. Enable MDS static branch to clear CPU buffers.
 379          *
 380          * For guests that can't determine whether the correct microcode is
 381          * present on host, enable the mitigation for UCODE_NEEDED as well.
 382          */
 383         static_branch_enable(&mds_user_clear);
 384
 385         if (taa_nosmt || cpu_mitigations_auto_nosmt())
 386                 cpu_smt_disable(false);
 387 }
 388
 389 static int __init tsx_async_abort_parse_cmdline(char *str)
 390 {
 391         if (!boot_cpu_has_bug(X86_BUG_TAA))
 392                 return 0;
 393
 394         if (!str)
 395                 return -EINVAL;
 396
 397         if (!strcmp(str, "off")) {
 398                 taa_mitigation = TAA_MITIGATION_OFF;
 399         } else if (!strcmp(str, "full")) {
 400                 taa_mitigation = TAA_MITIGATION_VERW;
 401         } else if (!strcmp(str, "full,nosmt")) {
 402                 taa_mitigation = TAA_MITIGATION_VERW;
 403                 taa_nosmt = true;
 404         }
 405
 406         return 0;
 407 }
 408 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
 409
 410 #undef pr_fmt
 411 #define pr_fmt(fmt)     "MMIO Stale Data: " fmt
 412
 413 enum mmio_mitigations {
 414         MMIO_MITIGATION_OFF,
 415         MMIO_MITIGATION_UCODE_NEEDED,
 416         MMIO_MITIGATION_VERW,
 417 };
 418
 419 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
 420 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
 421 static bool mmio_nosmt __ro_after_init = false;
 422
 423 static const char * const mmio_strings[] = {
 424         [MMIO_MITIGATION_OFF]           = "Vulnerable",
 425         [MMIO_MITIGATION_UCODE_NEEDED]  = "Vulnerable: Clear CPU buffers attempted, no microcode",
 426         [MMIO_MITIGATION_VERW]          = "Mitigation: Clear CPU buffers",
 427 };
 428
 429 static void __init mmio_select_mitigation(void)
 430 {
 431         u64 ia32_cap;
 432
 433         if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
 434              boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
 435              cpu_mitigations_off()) {
 436                 mmio_mitigation = MMIO_MITIGATION_OFF;
 437                 return;
 438         }
 439
 440         if (mmio_mitigation == MMIO_MITIGATION_OFF)
 441                 return;
 442
 443         ia32_cap = x86_read_arch_cap_msr();
 444
 445         /*
 446          * Enable CPU buffer clear mitigation for host and VMM, if also affected
 447          * by MDS or TAA. Otherwise, enable mitigation for VMM only.
 448          */
 449         if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
 450                                               boot_cpu_has(X86_FEATURE_RTM)))
 451                 static_branch_enable(&mds_user_clear);
 452         else
 453                 static_branch_enable(&mmio_stale_data_clear);
 454
 455         /*
 456          * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
 457          * be propagated to uncore buffers, clearing the Fill buffers on idle
 458          * is required irrespective of SMT state.
 459          */
 460         if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
 461                 static_branch_enable(&mds_idle_clear);
 462
 463         /*
 464          * Check if the system has the right microcode.
 465          *
 466          * CPU Fill buffer clear mitigation is enumerated by either an explicit
 467          * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
 468          * affected systems.
 469          */
 470         if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
 471             (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
 472              boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
 473              !(ia32_cap & ARCH_CAP_MDS_NO)))
 474                 mmio_mitigation = MMIO_MITIGATION_VERW;
 475         else
 476                 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
 477
 478         if (mmio_nosmt || cpu_mitigations_auto_nosmt())
 479                 cpu_smt_disable(false);
 480 }
 481
 482 static int __init mmio_stale_data_parse_cmdline(char *str)
 483 {
 484         if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 485                 return 0;
 486
 487         if (!str)
 488                 return -EINVAL;
 489
 490         if (!strcmp(str, "off")) {
 491                 mmio_mitigation = MMIO_MITIGATION_OFF;
 492         } else if (!strcmp(str, "full")) {
 493                 mmio_mitigation = MMIO_MITIGATION_VERW;
 494         } else if (!strcmp(str, "full,nosmt")) {
 495                 mmio_mitigation = MMIO_MITIGATION_VERW;
 496                 mmio_nosmt = true;
 497         }
 498
 499         return 0;
 500 }
 501 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
 502
 503 #undef pr_fmt
 504 #define pr_fmt(fmt)     "" fmt
 505
 506 static void __init md_clear_update_mitigation(void)
 507 {
 508         if (cpu_mitigations_off())
 509                 return;
 510
 511         if (!static_key_enabled(&mds_user_clear))
 512                 goto out;
 513
 514         /*
 515          * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
 516          * mitigation, if necessary.
 517          */
 518         if (mds_mitigation == MDS_MITIGATION_OFF &&
 519             boot_cpu_has_bug(X86_BUG_MDS)) {
 520                 mds_mitigation = MDS_MITIGATION_FULL;
 521                 mds_select_mitigation();
 522         }
 523         if (taa_mitigation == TAA_MITIGATION_OFF &&
 524             boot_cpu_has_bug(X86_BUG_TAA)) {
 525                 taa_mitigation = TAA_MITIGATION_VERW;
 526                 taa_select_mitigation();
 527         }
 528         if (mmio_mitigation == MMIO_MITIGATION_OFF &&
 529             boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
 530                 mmio_mitigation = MMIO_MITIGATION_VERW;
 531                 mmio_select_mitigation();
 532         }
 533 out:
 534         if (boot_cpu_has_bug(X86_BUG_MDS))
 535                 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
 536         if (boot_cpu_has_bug(X86_BUG_TAA))
 537                 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
 538         if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 539                 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
 540         else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
 541                 pr_info("MMIO Stale Data: Unknown: No mitigations\n");
 542 }
 543
 544 static void __init md_clear_select_mitigation(void)
 545 {
 546         mds_select_mitigation();
 547         taa_select_mitigation();
 548         mmio_select_mitigation();
 549
 550         /*
 551          * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
 552          * and print their mitigation after MDS, TAA and MMIO Stale Data
 553          * mitigation selection is done.
 554          */
 555         md_clear_update_mitigation();
 556 }
 557
 558 #undef pr_fmt
 559 #define pr_fmt(fmt)     "SRBDS: " fmt
 560
 561 enum srbds_mitigations {
 562         SRBDS_MITIGATION_OFF,
 563         SRBDS_MITIGATION_UCODE_NEEDED,
 564         SRBDS_MITIGATION_FULL,
 565         SRBDS_MITIGATION_TSX_OFF,
 566         SRBDS_MITIGATION_HYPERVISOR,
 567 };
 568
 569 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
 570
 571 static const char * const srbds_strings[] = {
 572         [SRBDS_MITIGATION_OFF]          = "Vulnerable",
 573         [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
 574         [SRBDS_MITIGATION_FULL]         = "Mitigation: Microcode",
 575         [SRBDS_MITIGATION_TSX_OFF]      = "Mitigation: TSX disabled",
 576         [SRBDS_MITIGATION_HYPERVISOR]   = "Unknown: Dependent on hypervisor status",
 577 };
 578
 579 static bool srbds_off;
 580
 581 void update_srbds_msr(void)
 582 {
 583         u64 mcu_ctrl;
 584
 585         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 586                 return;
 587
 588         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 589                 return;
 590
 591         if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
 592                 return;
 593
 594         rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 595
 596         switch (srbds_mitigation) {
 597         case SRBDS_MITIGATION_OFF:
 598         case SRBDS_MITIGATION_TSX_OFF:
 599                 mcu_ctrl |= RNGDS_MITG_DIS;
 600                 break;
 601         case SRBDS_MITIGATION_FULL:
 602                 mcu_ctrl &= ~RNGDS_MITG_DIS;
 603                 break;
 604         default:
 605                 break;
 606         }
 607
 608         wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 609 }
 610
 611 static void __init srbds_select_mitigation(void)
 612 {
 613         u64 ia32_cap;
 614
 615         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 616                 return;
 617
 618         /*
 619          * Check to see if this is one of the MDS_NO systems supporting TSX that
 620          * are only exposed to SRBDS when TSX is enabled or when CPU is affected
 621          * by Processor MMIO Stale Data vulnerability.
 622          */
 623         ia32_cap = x86_read_arch_cap_msr();
 624         if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
 625             !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 626                 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
 627         else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 628                 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
 629         else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
 630                 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
 631         else if (cpu_mitigations_off() || srbds_off)
 632                 srbds_mitigation = SRBDS_MITIGATION_OFF;
 633
 634         update_srbds_msr();
 635         pr_info("%s\n", srbds_strings[srbds_mitigation]);
 636 }
 637
 638 static int __init srbds_parse_cmdline(char *str)
 639 {
 640         if (!str)
 641                 return -EINVAL;
 642
 643         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 644                 return 0;
 645
 646         srbds_off = !strcmp(str, "off");
 647         return 0;
 648 }
 649 early_param("srbds", srbds_parse_cmdline);
 650
 651 #undef pr_fmt
 652 #define pr_fmt(fmt)     "Spectre V1 : " fmt
 653
 654 enum spectre_v1_mitigation {
 655         SPECTRE_V1_MITIGATION_NONE,
 656         SPECTRE_V1_MITIGATION_AUTO,
 657 };
 658
 659 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
 660         SPECTRE_V1_MITIGATION_AUTO;
 661
 662 static const char * const spectre_v1_strings[] = {
 663         [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
 664         [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
 665 };
 666
 667 /*
 668  * Does SMAP provide full mitigation against speculative kernel access to
 669  * userspace?
 670  */
 671 static bool smap_works_speculatively(void)
 672 {
 673         if (!boot_cpu_has(X86_FEATURE_SMAP))
 674                 return false;
 675
 676         /*
 677          * On CPUs which are vulnerable to Meltdown, SMAP does not
 678          * prevent speculative access to user data in the L1 cache.
 679          * Consider SMAP to be non-functional as a mitigation on these
 680          * CPUs.
 681          */
 682         if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
 683                 return false;
 684
 685         return true;
 686 }
 687
 688 static void __init spectre_v1_select_mitigation(void)
 689 {
 690         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
 691                 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 692                 return;
 693         }
 694
 695         if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
 696                 /*
 697                  * With Spectre v1, a user can speculatively control either
 698                  * path of a conditional swapgs with a user-controlled GS
 699                  * value.  The mitigation is to add lfences to both code paths.
 700                  *
 701                  * If FSGSBASE is enabled, the user can put a kernel address in
 702                  * GS, in which case SMAP provides no protection.
 703                  *
 704                  * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
 705                  *         FSGSBASE enablement patches have been merged. ]
 706                  *
 707                  * If FSGSBASE is disabled, the user can only put a user space
 708                  * address in GS.  That makes an attack harder, but still
 709                  * possible if there's no SMAP protection.
 710                  */
 711                 if (!smap_works_speculatively()) {
 712                         /*
 713                          * Mitigation can be provided from SWAPGS itself or
 714                          * PTI as the CR3 write in the Meltdown mitigation
 715                          * is serializing.
 716                          *
 717                          * If neither is there, mitigate with an LFENCE to
 718                          * stop speculation through swapgs.
 719                          */
 720                         if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
 721                             !boot_cpu_has(X86_FEATURE_PTI))
 722                                 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
 723
 724                         /*
 725                          * Enable lfences in the kernel entry (non-swapgs)
 726                          * paths, to prevent user entry from speculatively
 727                          * skipping swapgs.
 728                          */
 729                         setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
 730                 }
 731         }
 732
 733         pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
 734 }
 735
 736 static int __init nospectre_v1_cmdline(char *str)
 737 {
 738         spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 739         return 0;
 740 }
 741 early_param("nospectre_v1", nospectre_v1_cmdline);
 742
 743 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 744         SPECTRE_V2_NONE;
 745
 746 #undef pr_fmt
 747 #define pr_fmt(fmt)     "RETBleed: " fmt
 748
 749 enum retbleed_mitigation {
 750         RETBLEED_MITIGATION_NONE,
 751         RETBLEED_MITIGATION_IBRS,
 752         RETBLEED_MITIGATION_EIBRS,
 753 };
 754
 755 enum retbleed_mitigation_cmd {
 756         RETBLEED_CMD_OFF,
 757         RETBLEED_CMD_AUTO,
 758 };
 759
 760 const char * const retbleed_strings[] = {
 761         [RETBLEED_MITIGATION_NONE]      = "Vulnerable",
 762         [RETBLEED_MITIGATION_IBRS]      = "Mitigation: IBRS",
 763         [RETBLEED_MITIGATION_EIBRS]     = "Mitigation: Enhanced IBRS",
 764 };
 765
 766 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
 767         RETBLEED_MITIGATION_NONE;
 768 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
 769         RETBLEED_CMD_AUTO;
 770
 771 static int __init retbleed_parse_cmdline(char *str)
 772 {
 773         if (!str)
 774                 return -EINVAL;
 775
 776         if (!strcmp(str, "off"))
 777                 retbleed_cmd = RETBLEED_CMD_OFF;
 778         else if (!strcmp(str, "auto"))
 779                 retbleed_cmd = RETBLEED_CMD_AUTO;
 780         else
 781                 pr_err("Unknown retbleed option (%s). Defaulting to 'auto'\n", str);
 782
 783         return 0;
 784 }
 785 early_param("retbleed", retbleed_parse_cmdline);
 786
 787 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
 788 #define RETBLEED_COMPILER_MSG "WARNING: kernel not compiled with RETPOLINE or -mfunction-return capable compiler!\n"
 789 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
 790
 791 static void __init retbleed_select_mitigation(void)
 792 {
 793         if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
 794                 return;
 795
 796         switch (retbleed_cmd) {
 797         case RETBLEED_CMD_OFF:
 798                 return;
 799
 800         case RETBLEED_CMD_AUTO:
 801         default:
 802                 /*
 803                  * The Intel mitigation (IBRS) was already selected in
 804                  * spectre_v2_select_mitigation().
 805                  */
 806
 807                 break;
 808         }
 809
 810         switch (retbleed_mitigation) {
 811         default:
 812                 break;
 813         }
 814
 815         /*
 816          * Let IBRS trump all on Intel without affecting the effects of the
 817          * retbleed= cmdline option.
 818          */
 819         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
 820                 switch (spectre_v2_enabled) {
 821                 case SPECTRE_V2_IBRS:
 822                         retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
 823                         break;
 824                 case SPECTRE_V2_EIBRS:
 825                 case SPECTRE_V2_EIBRS_RETPOLINE:
 826                 case SPECTRE_V2_EIBRS_LFENCE:
 827                         retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
 828                         break;
 829                 default:
 830                         pr_err(RETBLEED_INTEL_MSG);
 831                 }
 832         }
 833
 834         pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
 835 }
 836
 837 #undef pr_fmt
 838 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 839
 840 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
 841         SPECTRE_V2_USER_NONE;
 842 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
 843         SPECTRE_V2_USER_NONE;
 844
 845 #ifdef CONFIG_RETPOLINE
 846 static bool spectre_v2_bad_module;
 847
 848 bool retpoline_module_ok(bool has_retpoline)
 849 {
 850         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 851                 return true;
 852
 853         pr_err("System may be vulnerable to spectre v2\n");
 854         spectre_v2_bad_module = true;
 855         return false;
 856 }
 857
 858 static inline const char *spectre_v2_module_string(void)
 859 {
 860         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 861 }
 862 #else
 863 static inline const char *spectre_v2_module_string(void) { return ""; }
 864 #endif
 865
 866 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
 867 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
 868 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
 869 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
 870
 871 #ifdef CONFIG_BPF_SYSCALL
 872 void unpriv_ebpf_notify(int new_state)
 873 {
 874         if (new_state)
 875                 return;
 876
 877         /* Unprivileged eBPF is enabled */
 878
 879         switch (spectre_v2_enabled) {
 880         case SPECTRE_V2_EIBRS:
 881                 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
 882                 break;
 883         case SPECTRE_V2_EIBRS_LFENCE:
 884                 if (sched_smt_active())
 885                         pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
 886                 break;
 887         default:
 888                 break;
 889         }
 890 }
 891 #endif
 892
 893 static inline bool match_option(const char *arg, int arglen, const char *opt)
 894 {
 895         int len = strlen(opt);
 896
 897         return len == arglen && !strncmp(arg, opt, len);
 898 }
 899
 900 /* The kernel command line selection for spectre v2 */
 901 enum spectre_v2_mitigation_cmd {
 902         SPECTRE_V2_CMD_NONE,
 903         SPECTRE_V2_CMD_AUTO,
 904         SPECTRE_V2_CMD_FORCE,
 905         SPECTRE_V2_CMD_RETPOLINE,
 906         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 907         SPECTRE_V2_CMD_RETPOLINE_LFENCE,
 908         SPECTRE_V2_CMD_EIBRS,
 909         SPECTRE_V2_CMD_EIBRS_RETPOLINE,
 910         SPECTRE_V2_CMD_EIBRS_LFENCE,
 911         SPECTRE_V2_CMD_IBRS,
 912 };
 913
 914 enum spectre_v2_user_cmd {
 915         SPECTRE_V2_USER_CMD_NONE,
 916         SPECTRE_V2_USER_CMD_AUTO,
 917         SPECTRE_V2_USER_CMD_FORCE,
 918         SPECTRE_V2_USER_CMD_PRCTL,
 919         SPECTRE_V2_USER_CMD_PRCTL_IBPB,
 920         SPECTRE_V2_USER_CMD_SECCOMP,
 921         SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
 922 };
 923
 924 static const char * const spectre_v2_user_strings[] = {
 925         [SPECTRE_V2_USER_NONE]                  = "User space: Vulnerable",
 926         [SPECTRE_V2_USER_STRICT]                = "User space: Mitigation: STIBP protection",
 927         [SPECTRE_V2_USER_STRICT_PREFERRED]      = "User space: Mitigation: STIBP always-on protection",
 928         [SPECTRE_V2_USER_PRCTL]                 = "User space: Mitigation: STIBP via prctl",
 929         [SPECTRE_V2_USER_SECCOMP]               = "User space: Mitigation: STIBP via seccomp and prctl",
 930 };
 931
 932 static const struct {
 933         const char                      *option;
 934         enum spectre_v2_user_cmd        cmd;
 935         bool                            secure;
 936 } v2_user_options[] __initconst = {
 937         { "auto",               SPECTRE_V2_USER_CMD_AUTO,               false },
 938         { "off",                SPECTRE_V2_USER_CMD_NONE,               false },
 939         { "on",                 SPECTRE_V2_USER_CMD_FORCE,              true  },
 940         { "prctl",              SPECTRE_V2_USER_CMD_PRCTL,              false },
 941         { "prctl,ibpb",         SPECTRE_V2_USER_CMD_PRCTL_IBPB,         false },
 942         { "seccomp",            SPECTRE_V2_USER_CMD_SECCOMP,            false },
 943         { "seccomp,ibpb",       SPECTRE_V2_USER_CMD_SECCOMP_IBPB,       false },
 944 };
 945
 946 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
 947 {
 948         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 949                 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
 950 }
 951
 952 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
 953
 954 static enum spectre_v2_user_cmd __init
 955 spectre_v2_parse_user_cmdline(void)
 956 {
 957         char arg[20];
 958         int ret, i;
 959
 960         switch (spectre_v2_cmd) {
 961         case SPECTRE_V2_CMD_NONE:
 962                 return SPECTRE_V2_USER_CMD_NONE;
 963         case SPECTRE_V2_CMD_FORCE:
 964                 return SPECTRE_V2_USER_CMD_FORCE;
 965         default:
 966                 break;
 967         }
 968
 969         ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
 970                                   arg, sizeof(arg));
 971         if (ret < 0)
 972                 return SPECTRE_V2_USER_CMD_AUTO;
 973
 974         for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
 975                 if (match_option(arg, ret, v2_user_options[i].option)) {
 976                         spec_v2_user_print_cond(v2_user_options[i].option,
 977                                                 v2_user_options[i].secure);
 978                         return v2_user_options[i].cmd;
 979                 }
 980         }
 981
 982         pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
 983         return SPECTRE_V2_USER_CMD_AUTO;
 984 }
 985
 986 static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
 987 {
 988         return mode == SPECTRE_V2_EIBRS ||
 989                mode == SPECTRE_V2_EIBRS_RETPOLINE ||
 990                mode == SPECTRE_V2_EIBRS_LFENCE;
 991 }
 992
 993 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
 994 {
 995         return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS;
 996 }
 997
 998 static void __init
 999 spectre_v2_user_select_mitigation(void)
1000 {
1001         enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1002         bool smt_possible = IS_ENABLED(CONFIG_SMP);
1003         enum spectre_v2_user_cmd cmd;
1004
1005         if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1006                 return;
1007
1008         if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1009             cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1010                 smt_possible = false;
1011
1012         cmd = spectre_v2_parse_user_cmdline();
1013         switch (cmd) {
1014         case SPECTRE_V2_USER_CMD_NONE:
1015                 goto set_mode;
1016         case SPECTRE_V2_USER_CMD_FORCE:
1017                 mode = SPECTRE_V2_USER_STRICT;
1018                 break;
1019         case SPECTRE_V2_USER_CMD_PRCTL:
1020         case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1021                 mode = SPECTRE_V2_USER_PRCTL;
1022                 break;
1023         case SPECTRE_V2_USER_CMD_AUTO:
1024         case SPECTRE_V2_USER_CMD_SECCOMP:
1025         case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1026                 if (IS_ENABLED(CONFIG_SECCOMP))
1027                         mode = SPECTRE_V2_USER_SECCOMP;
1028                 else
1029                         mode = SPECTRE_V2_USER_PRCTL;
1030                 break;
1031         }
1032
1033         /* Initialize Indirect Branch Prediction Barrier */
1034         if (boot_cpu_has(X86_FEATURE_IBPB)) {
1035                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1036
1037                 spectre_v2_user_ibpb = mode;
1038                 switch (cmd) {
1039                 case SPECTRE_V2_USER_CMD_FORCE:
1040                 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1041                 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1042                         static_branch_enable(&switch_mm_always_ibpb);
1043                         spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1044                         break;
1045                 case SPECTRE_V2_USER_CMD_PRCTL:
1046                 case SPECTRE_V2_USER_CMD_AUTO:
1047                 case SPECTRE_V2_USER_CMD_SECCOMP:
1048                         static_branch_enable(&switch_mm_cond_ibpb);
1049                         break;
1050                 default:
1051                         break;
1052                 }
1053
1054                 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1055                         static_key_enabled(&switch_mm_always_ibpb) ?
1056                         "always-on" : "conditional");
1057         }
1058
1059         /*
1060          * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP
1061          * is not required.
1062          *
1063          * Enhanced IBRS also protects against cross-thread branch target
1064          * injection in user-mode as the IBRS bit remains always set which
1065          * implicitly enables cross-thread protections.  However, in legacy IBRS
1066          * mode, the IBRS bit is set only on kernel entry and cleared on return
1067          * to userspace. This disables the implicit cross-thread protection,
1068          * so allow for STIBP to be selected in that case.
1069          */
1070         if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1071             !smt_possible ||
1072             spectre_v2_in_eibrs_mode(spectre_v2_enabled))
1073                 return;
1074
1075         /*
1076          * At this point, an STIBP mode other than "off" has been set.
1077          * If STIBP support is not being forced, check if STIBP always-on
1078          * is preferred.
1079          */
1080         if (mode != SPECTRE_V2_USER_STRICT &&
1081             boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1082                 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1083
1084         spectre_v2_user_stibp = mode;
1085
1086 set_mode:
1087         pr_info("%s\n", spectre_v2_user_strings[mode]);
1088 }
1089
1090 static const char * const spectre_v2_strings[] = {
1091         [SPECTRE_V2_NONE]                       = "Vulnerable",
1092         [SPECTRE_V2_RETPOLINE]                  = "Mitigation: Retpolines",
1093         [SPECTRE_V2_LFENCE]                     = "Mitigation: LFENCE",
1094         [SPECTRE_V2_EIBRS]                      = "Mitigation: Enhanced IBRS",
1095         [SPECTRE_V2_EIBRS_LFENCE]               = "Mitigation: Enhanced IBRS + LFENCE",
1096         [SPECTRE_V2_EIBRS_RETPOLINE]            = "Mitigation: Enhanced IBRS + Retpolines",
1097         [SPECTRE_V2_IBRS]                       = "Mitigation: IBRS",
1098 };
1099
1100 static const struct {
1101         const char *option;
1102         enum spectre_v2_mitigation_cmd cmd;
1103         bool secure;
1104 } mitigation_options[] __initconst = {
1105         { "off",                SPECTRE_V2_CMD_NONE,              false },
1106         { "on",                 SPECTRE_V2_CMD_FORCE,             true  },
1107         { "retpoline",          SPECTRE_V2_CMD_RETPOLINE,         false },
1108         { "retpoline,amd",      SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1109         { "retpoline,lfence",   SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1110         { "retpoline,generic",  SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1111         { "eibrs",              SPECTRE_V2_CMD_EIBRS,             false },
1112         { "eibrs,lfence",       SPECTRE_V2_CMD_EIBRS_LFENCE,      false },
1113         { "eibrs,retpoline",    SPECTRE_V2_CMD_EIBRS_RETPOLINE,   false },
1114         { "auto",               SPECTRE_V2_CMD_AUTO,              false },
1115         { "ibrs",               SPECTRE_V2_CMD_IBRS,              false },
1116 };
1117
1118 static void __init spec_v2_print_cond(const char *reason, bool secure)
1119 {
1120         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1121                 pr_info("%s selected on command line.\n", reason);
1122 }
1123
1124 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1125 {
1126         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1127         char arg[20];
1128         int ret, i;
1129
1130         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1131             cpu_mitigations_off())
1132                 return SPECTRE_V2_CMD_NONE;
1133
1134         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1135         if (ret < 0)
1136                 return SPECTRE_V2_CMD_AUTO;
1137
1138         for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1139                 if (!match_option(arg, ret, mitigation_options[i].option))
1140                         continue;
1141                 cmd = mitigation_options[i].cmd;
1142                 break;
1143         }
1144
1145         if (i >= ARRAY_SIZE(mitigation_options)) {
1146                 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1147                 return SPECTRE_V2_CMD_AUTO;
1148         }
1149
1150         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1151              cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1152              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1153              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1154              cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1155             !IS_ENABLED(CONFIG_RETPOLINE)) {
1156                 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1157                        mitigation_options[i].option);
1158                 return SPECTRE_V2_CMD_AUTO;
1159         }
1160
1161         if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1162              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1163              cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1164             !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1165                 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1166                        mitigation_options[i].option);
1167                 return SPECTRE_V2_CMD_AUTO;
1168         }
1169
1170         if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1171              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1172             !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1173                 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1174                        mitigation_options[i].option);
1175                 return SPECTRE_V2_CMD_AUTO;
1176         }
1177
1178         if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1179                 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1180                        mitigation_options[i].option);
1181                 return SPECTRE_V2_CMD_AUTO;
1182         }
1183
1184         if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1185                 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1186                        mitigation_options[i].option);
1187                 return SPECTRE_V2_CMD_AUTO;
1188         }
1189
1190         if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1191                 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1192                        mitigation_options[i].option);
1193                 return SPECTRE_V2_CMD_AUTO;
1194         }
1195
1196         spec_v2_print_cond(mitigation_options[i].option,
1197                            mitigation_options[i].secure);
1198         return cmd;
1199 }
1200
1201 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1202 {
1203         if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1204                 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1205                 return SPECTRE_V2_NONE;
1206         }
1207
1208         return SPECTRE_V2_RETPOLINE;
1209 }
1210
1211 /* Disable in-kernel use of non-RSB RET predictors */
1212 static void __init spec_ctrl_disable_kernel_rrsba(void)
1213 {
1214         u64 ia32_cap;
1215
1216         if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1217                 return;
1218
1219         ia32_cap = x86_read_arch_cap_msr();
1220
1221         if (ia32_cap & ARCH_CAP_RRSBA) {
1222                 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1223                 update_spec_ctrl(x86_spec_ctrl_base);
1224         }
1225 }
1226
1227 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
1228 {
1229         /*
1230          * Similar to context switches, there are two types of RSB attacks
1231          * after VM exit:
1232          *
1233          * 1) RSB underflow
1234          *
1235          * 2) Poisoned RSB entry
1236          *
1237          * When retpoline is enabled, both are mitigated by filling/clearing
1238          * the RSB.
1239          *
1240          * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
1241          * prediction isolation protections, RSB still needs to be cleared
1242          * because of #2.  Note that SMEP provides no protection here, unlike
1243          * user-space-poisoned RSB entries.
1244          *
1245          * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
1246          * bug is present then a LITE version of RSB protection is required,
1247          * just a single call needs to retire before a RET is executed.
1248          */
1249         switch (mode) {
1250         case SPECTRE_V2_NONE:
1251                 return;
1252
1253         case SPECTRE_V2_EIBRS_LFENCE:
1254         case SPECTRE_V2_EIBRS:
1255                 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB) &&
1256                     (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)) {
1257                         setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
1258                         pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
1259                 }
1260                 return;
1261
1262         case SPECTRE_V2_EIBRS_RETPOLINE:
1263         case SPECTRE_V2_RETPOLINE:
1264         case SPECTRE_V2_LFENCE:
1265         case SPECTRE_V2_IBRS:
1266                 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1267                 pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n");
1268                 return;
1269         }
1270
1271         pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit");
1272         dump_stack();
1273 }
1274
1275 static void __init spectre_v2_select_mitigation(void)
1276 {
1277         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1278         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1279
1280         /*
1281          * If the CPU is not affected and the command line mode is NONE or AUTO
1282          * then nothing to do.
1283          */
1284         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1285             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1286                 return;
1287
1288         switch (cmd) {
1289         case SPECTRE_V2_CMD_NONE:
1290                 return;
1291
1292         case SPECTRE_V2_CMD_FORCE:
1293         case SPECTRE_V2_CMD_AUTO:
1294                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1295                         mode = SPECTRE_V2_EIBRS;
1296                         break;
1297                 }
1298
1299                 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1300                     retbleed_cmd != RETBLEED_CMD_OFF &&
1301                     boot_cpu_has(X86_FEATURE_IBRS) &&
1302                     boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1303                         mode = SPECTRE_V2_IBRS;
1304                         break;
1305                 }
1306
1307                 mode = spectre_v2_select_retpoline();
1308                 break;
1309
1310         case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1311                 pr_err(SPECTRE_V2_LFENCE_MSG);
1312                 mode = SPECTRE_V2_LFENCE;
1313                 break;
1314
1315         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1316                 mode = SPECTRE_V2_RETPOLINE;
1317                 break;
1318
1319         case SPECTRE_V2_CMD_RETPOLINE:
1320                 mode = spectre_v2_select_retpoline();
1321                 break;
1322
1323         case SPECTRE_V2_CMD_IBRS:
1324                 mode = SPECTRE_V2_IBRS;
1325                 break;
1326
1327         case SPECTRE_V2_CMD_EIBRS:
1328                 mode = SPECTRE_V2_EIBRS;
1329                 break;
1330
1331         case SPECTRE_V2_CMD_EIBRS_LFENCE:
1332                 mode = SPECTRE_V2_EIBRS_LFENCE;
1333                 break;
1334
1335         case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1336                 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1337                 break;
1338         }
1339
1340         if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1341                 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1342
1343         if (spectre_v2_in_ibrs_mode(mode)) {
1344                 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1345                 update_spec_ctrl(x86_spec_ctrl_base);
1346         }
1347
1348         switch (mode) {
1349         case SPECTRE_V2_NONE:
1350         case SPECTRE_V2_EIBRS:
1351                 break;
1352
1353         case SPECTRE_V2_IBRS:
1354                 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1355                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1356                         pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1357                 break;
1358
1359         case SPECTRE_V2_LFENCE:
1360         case SPECTRE_V2_EIBRS_LFENCE:
1361                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1362                 /* fallthrough */
1363
1364         case SPECTRE_V2_RETPOLINE:
1365         case SPECTRE_V2_EIBRS_RETPOLINE:
1366                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1367                 break;
1368         }
1369
1370         /*
1371          * Disable alternate RSB predictions in kernel when indirect CALLs and
1372          * JMPs gets protection against BHI and Intramode-BTI, but RET
1373          * prediction from a non-RSB predictor is still a risk.
1374          */
1375         if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1376             mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1377             mode == SPECTRE_V2_RETPOLINE)
1378                 spec_ctrl_disable_kernel_rrsba();
1379
1380         spectre_v2_enabled = mode;
1381         pr_info("%s\n", spectre_v2_strings[mode]);
1382
1383         /*
1384          * If Spectre v2 protection has been enabled, fill the RSB during a
1385          * context switch.  In general there are two types of RSB attacks
1386          * across context switches, for which the CALLs/RETs may be unbalanced.
1387          *
1388          * 1) RSB underflow
1389          *
1390          *    Some Intel parts have "bottomless RSB".  When the RSB is empty,
1391          *    speculated return targets may come from the branch predictor,
1392          *    which could have a user-poisoned BTB or BHB entry.
1393          *
1394          *    AMD has it even worse: *all* returns are speculated from the BTB,
1395          *    regardless of the state of the RSB.
1396          *
1397          *    When IBRS or eIBRS is enabled, the "user -> kernel" attack
1398          *    scenario is mitigated by the IBRS branch prediction isolation
1399          *    properties, so the RSB buffer filling wouldn't be necessary to
1400          *    protect against this type of attack.
1401          *
1402          *    The "user -> user" attack scenario is mitigated by RSB filling.
1403          *
1404          * 2) Poisoned RSB entry
1405          *
1406          *    If the 'next' in-kernel return stack is shorter than 'prev',
1407          *    'next' could be tricked into speculating with a user-poisoned RSB
1408          *    entry.
1409          *
1410          *    The "user -> kernel" attack scenario is mitigated by SMEP and
1411          *    eIBRS.
1412          *
1413          *    The "user -> user" scenario, also known as SpectreBHB, requires
1414          *    RSB clearing.
1415          *
1416          * So to mitigate all cases, unconditionally fill RSB on context
1417          * switches.
1418          *
1419          * FIXME: Is this pointless for retbleed-affected AMD?
1420          */
1421         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1422         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1423
1424         spectre_v2_determine_rsb_fill_type_at_vmexit(mode);
1425
1426         /*
1427          * Retpoline protects the kernel, but doesn't protect firmware.  IBRS
1428          * and Enhanced IBRS protect firmware too, so enable IBRS around
1429          * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1430          * enabled.
1431          *
1432          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1433          * the user might select retpoline on the kernel command line and if
1434          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1435          * enable IBRS around firmware calls.
1436          */
1437         if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1438                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1439                 pr_info("Enabling Restricted Speculation for firmware calls\n");
1440         }
1441
1442         /* Set up IBPB and STIBP depending on the general spectre V2 command */
1443         spectre_v2_cmd = cmd;
1444 }
1445
1446 static void update_stibp_msr(void * __unused)
1447 {
1448         u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1449         update_spec_ctrl(val);
1450 }
1451
1452 /* Update x86_spec_ctrl_base in case SMT state changed. */
1453 static void update_stibp_strict(void)
1454 {
1455         u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1456
1457         if (sched_smt_active())
1458                 mask |= SPEC_CTRL_STIBP;
1459
1460         if (mask == x86_spec_ctrl_base)
1461                 return;
1462
1463         pr_info("Update user space SMT mitigation: STIBP %s\n",
1464                 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1465         x86_spec_ctrl_base = mask;
1466         on_each_cpu(update_stibp_msr, NULL, 1);
1467 }
1468
1469 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1470 static void update_indir_branch_cond(void)
1471 {
1472         if (sched_smt_active())
1473                 static_branch_enable(&switch_to_cond_stibp);
1474         else
1475                 static_branch_disable(&switch_to_cond_stibp);
1476 }
1477
1478 #undef pr_fmt
1479 #define pr_fmt(fmt) fmt
1480
1481 /* Update the static key controlling the MDS CPU buffer clear in idle */
1482 static void update_mds_branch_idle(void)
1483 {
1484         u64 ia32_cap = x86_read_arch_cap_msr();
1485
1486         /*
1487          * Enable the idle clearing if SMT is active on CPUs which are
1488          * affected only by MSBDS and not any other MDS variant.
1489          *
1490          * The other variants cannot be mitigated when SMT is enabled, so
1491          * clearing the buffers on idle just to prevent the Store Buffer
1492          * repartitioning leak would be a window dressing exercise.
1493          */
1494         if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1495                 return;
1496
1497         if (sched_smt_active()) {
1498                 static_branch_enable(&mds_idle_clear);
1499         } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1500                    (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1501                 static_branch_disable(&mds_idle_clear);
1502         }
1503 }
1504
1505 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1506 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1507 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1508
1509 void arch_smt_update(void)
1510 {
1511         mutex_lock(&spec_ctrl_mutex);
1512
1513         if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1514             spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1515                 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1516
1517         switch (spectre_v2_user_stibp) {
1518         case SPECTRE_V2_USER_NONE:
1519                 break;
1520         case SPECTRE_V2_USER_STRICT:
1521         case SPECTRE_V2_USER_STRICT_PREFERRED:
1522                 update_stibp_strict();
1523                 break;
1524         case SPECTRE_V2_USER_PRCTL:
1525         case SPECTRE_V2_USER_SECCOMP:
1526                 update_indir_branch_cond();
1527                 break;
1528         }
1529
1530         switch (mds_mitigation) {
1531         case MDS_MITIGATION_FULL:
1532         case MDS_MITIGATION_VMWERV:
1533                 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1534                         pr_warn_once(MDS_MSG_SMT);
1535                 update_mds_branch_idle();
1536                 break;
1537         case MDS_MITIGATION_OFF:
1538                 break;
1539         }
1540
1541         switch (taa_mitigation) {
1542         case TAA_MITIGATION_VERW:
1543         case TAA_MITIGATION_UCODE_NEEDED:
1544                 if (sched_smt_active())
1545                         pr_warn_once(TAA_MSG_SMT);
1546                 break;
1547         case TAA_MITIGATION_TSX_DISABLED:
1548         case TAA_MITIGATION_OFF:
1549                 break;
1550         }
1551
1552         switch (mmio_mitigation) {
1553         case MMIO_MITIGATION_VERW:
1554         case MMIO_MITIGATION_UCODE_NEEDED:
1555                 if (sched_smt_active())
1556                         pr_warn_once(MMIO_MSG_SMT);
1557                 break;
1558         case MMIO_MITIGATION_OFF:
1559                 break;
1560         }
1561
1562         mutex_unlock(&spec_ctrl_mutex);
1563 }
1564
1565 #undef pr_fmt
1566 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
1567
1568 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1569
1570 /* The kernel command line selection */
1571 enum ssb_mitigation_cmd {
1572         SPEC_STORE_BYPASS_CMD_NONE,
1573         SPEC_STORE_BYPASS_CMD_AUTO,
1574         SPEC_STORE_BYPASS_CMD_ON,
1575         SPEC_STORE_BYPASS_CMD_PRCTL,
1576         SPEC_STORE_BYPASS_CMD_SECCOMP,
1577 };
1578
1579 static const char * const ssb_strings[] = {
1580         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
1581         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
1582         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
1583         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1584 };
1585
1586 static const struct {
1587         const char *option;
1588         enum ssb_mitigation_cmd cmd;
1589 } ssb_mitigation_options[]  __initconst = {
1590         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
1591         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
1592         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
1593         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
1594         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1595 };
1596
1597 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1598 {
1599         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1600         char arg[20];
1601         int ret, i;
1602
1603         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1604             cpu_mitigations_off()) {
1605                 return SPEC_STORE_BYPASS_CMD_NONE;
1606         } else {
1607                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1608                                           arg, sizeof(arg));
1609                 if (ret < 0)
1610                         return SPEC_STORE_BYPASS_CMD_AUTO;
1611
1612                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1613                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1614                                 continue;
1615
1616                         cmd = ssb_mitigation_options[i].cmd;
1617                         break;
1618                 }
1619
1620                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1621                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1622                         return SPEC_STORE_BYPASS_CMD_AUTO;
1623                 }
1624         }
1625
1626         return cmd;
1627 }
1628
1629 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1630 {
1631         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1632         enum ssb_mitigation_cmd cmd;
1633
1634         if (!boot_cpu_has(X86_FEATURE_SSBD))
1635                 return mode;
1636
1637         cmd = ssb_parse_cmdline();
1638         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1639             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1640              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1641                 return mode;
1642
1643         switch (cmd) {
1644         case SPEC_STORE_BYPASS_CMD_AUTO:
1645         case SPEC_STORE_BYPASS_CMD_SECCOMP:
1646                 /*
1647                  * Choose prctl+seccomp as the default mode if seccomp is
1648                  * enabled.
1649                  */
1650                 if (IS_ENABLED(CONFIG_SECCOMP))
1651                         mode = SPEC_STORE_BYPASS_SECCOMP;
1652                 else
1653                         mode = SPEC_STORE_BYPASS_PRCTL;
1654                 break;
1655         case SPEC_STORE_BYPASS_CMD_ON:
1656                 mode = SPEC_STORE_BYPASS_DISABLE;
1657                 break;
1658         case SPEC_STORE_BYPASS_CMD_PRCTL:
1659                 mode = SPEC_STORE_BYPASS_PRCTL;
1660                 break;
1661         case SPEC_STORE_BYPASS_CMD_NONE:
1662                 break;
1663         }
1664
1665         /*
1666          * We have three CPU feature flags that are in play here:
1667          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1668          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1669          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1670          */
1671         if (mode == SPEC_STORE_BYPASS_DISABLE) {
1672                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1673                 /*
1674                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1675                  * use a completely different MSR and bit dependent on family.
1676                  */
1677                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1678                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1679                         x86_amd_ssb_disable();
1680                 } else {
1681                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1682                         update_spec_ctrl(x86_spec_ctrl_base);
1683                 }
1684         }
1685
1686         return mode;
1687 }
1688
1689 static void ssb_select_mitigation(void)
1690 {
1691         ssb_mode = __ssb_select_mitigation();
1692
1693         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1694                 pr_info("%s\n", ssb_strings[ssb_mode]);
1695 }
1696
1697 #undef pr_fmt
1698 #define pr_fmt(fmt)     "Speculation prctl: " fmt
1699
1700 static void task_update_spec_tif(struct task_struct *tsk)
1701 {
1702         /* Force the update of the real TIF bits */
1703         set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1704
1705         /*
1706          * Immediately update the speculation control MSRs for the current
1707          * task, but for a non-current task delay setting the CPU
1708          * mitigation until it is scheduled next.
1709          *
1710          * This can only happen for SECCOMP mitigation. For PRCTL it's
1711          * always the current task.
1712          */
1713         if (tsk == current)
1714                 speculation_ctrl_update_current();
1715 }
1716
1717 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1718 {
1719         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1720             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1721                 return -ENXIO;
1722
1723         switch (ctrl) {
1724         case PR_SPEC_ENABLE:
1725                 /* If speculation is force disabled, enable is not allowed */
1726                 if (task_spec_ssb_force_disable(task))
1727                         return -EPERM;
1728                 task_clear_spec_ssb_disable(task);
1729                 task_update_spec_tif(task);
1730                 break;
1731         case PR_SPEC_DISABLE:
1732                 task_set_spec_ssb_disable(task);
1733                 task_update_spec_tif(task);
1734                 break;
1735         case PR_SPEC_FORCE_DISABLE:
1736                 task_set_spec_ssb_disable(task);
1737                 task_set_spec_ssb_force_disable(task);
1738                 task_update_spec_tif(task);
1739                 break;
1740         default:
1741                 return -ERANGE;
1742         }
1743         return 0;
1744 }
1745
1746 static bool is_spec_ib_user_controlled(void)
1747 {
1748         return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1749                 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1750                 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1751                 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1752 }
1753
1754 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1755 {
1756         switch (ctrl) {
1757         case PR_SPEC_ENABLE:
1758                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1759                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1760                         return 0;
1761                 /*
1762                  * With strict mode for both IBPB and STIBP, the instruction
1763                  * code paths avoid checking this task flag and instead,
1764                  * unconditionally run the instruction. However, STIBP and IBPB
1765                  * are independent and either can be set to conditionally
1766                  * enabled regardless of the mode of the other.
1767                  *
1768                  * If either is set to conditional, allow the task flag to be
1769                  * updated, unless it was force-disabled by a previous prctl
1770                  * call. Currently, this is possible on an AMD CPU which has the
1771                  * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1772                  * kernel is booted with 'spectre_v2_user=seccomp', then
1773                  * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1774                  * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1775                  */
1776                 if (!is_spec_ib_user_controlled() ||
1777                     task_spec_ib_force_disable(task))
1778                         return -EPERM;
1779
1780                 task_clear_spec_ib_disable(task);
1781                 task_update_spec_tif(task);
1782                 break;
1783         case PR_SPEC_DISABLE:
1784         case PR_SPEC_FORCE_DISABLE:
1785                 /*
1786                  * Indirect branch speculation is always allowed when
1787                  * mitigation is force disabled.
1788                  */
1789                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1790                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1791                         return -EPERM;
1792
1793                 if (!is_spec_ib_user_controlled())
1794                         return 0;
1795
1796                 task_set_spec_ib_disable(task);
1797                 if (ctrl == PR_SPEC_FORCE_DISABLE)
1798                         task_set_spec_ib_force_disable(task);
1799                 task_update_spec_tif(task);
1800                 if (task == current)
1801                         indirect_branch_prediction_barrier();
1802                 break;
1803         default:
1804                 return -ERANGE;
1805         }
1806         return 0;
1807 }
1808
1809 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1810                              unsigned long ctrl)
1811 {
1812         switch (which) {
1813         case PR_SPEC_STORE_BYPASS:
1814                 return ssb_prctl_set(task, ctrl);
1815         case PR_SPEC_INDIRECT_BRANCH:
1816                 return ib_prctl_set(task, ctrl);
1817         default:
1818                 return -ENODEV;
1819         }
1820 }
1821
1822 #ifdef CONFIG_SECCOMP
1823 void arch_seccomp_spec_mitigate(struct task_struct *task)
1824 {
1825         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1826                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1827         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1828             spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1829                 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1830 }
1831 #endif
1832
1833 static int ssb_prctl_get(struct task_struct *task)
1834 {
1835         switch (ssb_mode) {
1836         case SPEC_STORE_BYPASS_DISABLE:
1837                 return PR_SPEC_DISABLE;
1838         case SPEC_STORE_BYPASS_SECCOMP:
1839         case SPEC_STORE_BYPASS_PRCTL:
1840                 if (task_spec_ssb_force_disable(task))
1841                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1842                 if (task_spec_ssb_disable(task))
1843                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1844                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1845         default:
1846                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1847                         return PR_SPEC_ENABLE;
1848                 return PR_SPEC_NOT_AFFECTED;
1849         }
1850 }
1851
1852 static int ib_prctl_get(struct task_struct *task)
1853 {
1854         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1855                 return PR_SPEC_NOT_AFFECTED;
1856
1857         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1858             spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1859                 return PR_SPEC_ENABLE;
1860         else if (is_spec_ib_user_controlled()) {
1861                 if (task_spec_ib_force_disable(task))
1862                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1863                 if (task_spec_ib_disable(task))
1864                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1865                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1866         } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1867             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1868             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1869                 return PR_SPEC_DISABLE;
1870         else
1871                 return PR_SPEC_NOT_AFFECTED;
1872 }
1873
1874 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1875 {
1876         switch (which) {
1877         case PR_SPEC_STORE_BYPASS:
1878                 return ssb_prctl_get(task);
1879         case PR_SPEC_INDIRECT_BRANCH:
1880                 return ib_prctl_get(task);
1881         default:
1882                 return -ENODEV;
1883         }
1884 }
1885
1886 void x86_spec_ctrl_setup_ap(void)
1887 {
1888         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1889                 update_spec_ctrl(x86_spec_ctrl_base);
1890
1891         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1892                 x86_amd_ssb_disable();
1893 }
1894
1895 bool itlb_multihit_kvm_mitigation;
1896 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1897
1898 #undef pr_fmt
1899 #define pr_fmt(fmt)     "L1TF: " fmt
1900
1901 /* Default mitigation for L1TF-affected CPUs */
1902 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1903 #if IS_ENABLED(CONFIG_KVM_INTEL)
1904 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1905 #endif
1906 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1907 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1908
1909 /*
1910  * These CPUs all support 44bits physical address space internally in the
1911  * cache but CPUID can report a smaller number of physical address bits.
1912  *
1913  * The L1TF mitigation uses the top most address bit for the inversion of
1914  * non present PTEs. When the installed memory reaches into the top most
1915  * address bit due to memory holes, which has been observed on machines
1916  * which report 36bits physical address bits and have 32G RAM installed,
1917  * then the mitigation range check in l1tf_select_mitigation() triggers.
1918  * This is a false positive because the mitigation is still possible due to
1919  * the fact that the cache uses 44bit internally. Use the cache bits
1920  * instead of the reported physical bits and adjust them on the affected
1921  * machines to 44bit if the reported bits are less than 44.
1922  */
1923 static void override_cache_bits(struct cpuinfo_x86 *c)
1924 {
1925         if (c->x86 != 6)
1926                 return;
1927
1928         switch (c->x86_model) {
1929         case INTEL_FAM6_NEHALEM:
1930         case INTEL_FAM6_WESTMERE:
1931         case INTEL_FAM6_SANDYBRIDGE:
1932         case INTEL_FAM6_IVYBRIDGE:
1933         case INTEL_FAM6_HASWELL_CORE:
1934         case INTEL_FAM6_HASWELL_ULT:
1935         case INTEL_FAM6_HASWELL_GT3E:
1936         case INTEL_FAM6_BROADWELL_CORE:
1937         case INTEL_FAM6_BROADWELL_GT3E:
1938         case INTEL_FAM6_SKYLAKE_MOBILE:
1939         case INTEL_FAM6_SKYLAKE_DESKTOP:
1940         case INTEL_FAM6_KABYLAKE_MOBILE:
1941         case INTEL_FAM6_KABYLAKE_DESKTOP:
1942                 if (c->x86_cache_bits < 44)
1943                         c->x86_cache_bits = 44;
1944                 break;
1945         }
1946 }
1947
1948 static void __init l1tf_select_mitigation(void)
1949 {
1950         u64 half_pa;
1951
1952         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1953                 return;
1954
1955         if (cpu_mitigations_off())
1956                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1957         else if (cpu_mitigations_auto_nosmt())
1958                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1959
1960         override_cache_bits(&boot_cpu_data);
1961
1962         switch (l1tf_mitigation) {
1963         case L1TF_MITIGATION_OFF:
1964         case L1TF_MITIGATION_FLUSH_NOWARN:
1965         case L1TF_MITIGATION_FLUSH:
1966                 break;
1967         case L1TF_MITIGATION_FLUSH_NOSMT:
1968         case L1TF_MITIGATION_FULL:
1969                 cpu_smt_disable(false);
1970                 break;
1971         case L1TF_MITIGATION_FULL_FORCE:
1972                 cpu_smt_disable(true);
1973                 break;
1974         }
1975
1976 #if CONFIG_PGTABLE_LEVELS == 2
1977         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1978         return;
1979 #endif
1980
1981         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1982         if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
1983                         e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
1984                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1985                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1986                                 half_pa);
1987                 pr_info("However, doing so will make a part of your RAM unusable.\n");
1988                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1989                 return;
1990         }
1991
1992         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1993 }
1994
1995 static int __init l1tf_cmdline(char *str)
1996 {
1997         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1998                 return 0;
1999
2000         if (!str)
2001                 return -EINVAL;
2002
2003         if (!strcmp(str, "off"))
2004                 l1tf_mitigation = L1TF_MITIGATION_OFF;
2005         else if (!strcmp(str, "flush,nowarn"))
2006                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2007         else if (!strcmp(str, "flush"))
2008                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2009         else if (!strcmp(str, "flush,nosmt"))
2010                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2011         else if (!strcmp(str, "full"))
2012                 l1tf_mitigation = L1TF_MITIGATION_FULL;
2013         else if (!strcmp(str, "full,force"))
2014                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2015
2016         return 0;
2017 }
2018 early_param("l1tf", l1tf_cmdline);
2019
2020 #undef pr_fmt
2021 #define pr_fmt(fmt) fmt
2022
2023 #ifdef CONFIG_SYSFS
2024
2025 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2026
2027 #if IS_ENABLED(CONFIG_KVM_INTEL)
2028 static const char * const l1tf_vmx_states[] = {
2029         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
2030         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
2031         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
2032         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
2033         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
2034         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
2035 };
2036
2037 static ssize_t l1tf_show_state(char *buf)
2038 {
2039         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2040                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2041
2042         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2043             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2044              sched_smt_active())) {
2045                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2046                                l1tf_vmx_states[l1tf_vmx_mitigation]);
2047         }
2048
2049         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2050                        l1tf_vmx_states[l1tf_vmx_mitigation],
2051                        sched_smt_active() ? "vulnerable" : "disabled");
2052 }
2053
2054 static ssize_t itlb_multihit_show_state(char *buf)
2055 {
2056         if (itlb_multihit_kvm_mitigation)
2057                 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2058         else
2059                 return sprintf(buf, "KVM: Vulnerable\n");
2060 }
2061 #else
2062 static ssize_t l1tf_show_state(char *buf)
2063 {
2064         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2065 }
2066
2067 static ssize_t itlb_multihit_show_state(char *buf)
2068 {
2069         return sprintf(buf, "Processor vulnerable\n");
2070 }
2071 #endif
2072
2073 static ssize_t mds_show_state(char *buf)
2074 {
2075         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2076                 return sprintf(buf, "%s; SMT Host state unknown\n",
2077                                mds_strings[mds_mitigation]);
2078         }
2079
2080         if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2081                 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2082                                (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2083                                 sched_smt_active() ? "mitigated" : "disabled"));
2084         }
2085
2086         return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2087                        sched_smt_active() ? "vulnerable" : "disabled");
2088 }
2089
2090 static ssize_t tsx_async_abort_show_state(char *buf)
2091 {
2092         if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2093             (taa_mitigation == TAA_MITIGATION_OFF))
2094                 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2095
2096         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2097                 return sprintf(buf, "%s; SMT Host state unknown\n",
2098                                taa_strings[taa_mitigation]);
2099         }
2100
2101         return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2102                        sched_smt_active() ? "vulnerable" : "disabled");
2103 }
2104
2105 static ssize_t mmio_stale_data_show_state(char *buf)
2106 {
2107         if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2108                 return sysfs_emit(buf, "Unknown: No mitigations\n");
2109
2110         if (mmio_mitigation == MMIO_MITIGATION_OFF)
2111                 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2112
2113         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2114                 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2115                                   mmio_strings[mmio_mitigation]);
2116         }
2117
2118         return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2119                           sched_smt_active() ? "vulnerable" : "disabled");
2120 }
2121
2122 static char *stibp_state(void)
2123 {
2124         if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
2125                 return "";
2126
2127         switch (spectre_v2_user_stibp) {
2128         case SPECTRE_V2_USER_NONE:
2129                 return ", STIBP: disabled";
2130         case SPECTRE_V2_USER_STRICT:
2131                 return ", STIBP: forced";
2132         case SPECTRE_V2_USER_STRICT_PREFERRED:
2133                 return ", STIBP: always-on";
2134         case SPECTRE_V2_USER_PRCTL:
2135         case SPECTRE_V2_USER_SECCOMP:
2136                 if (static_key_enabled(&switch_to_cond_stibp))
2137                         return ", STIBP: conditional";
2138         }
2139         return "";
2140 }
2141
2142 static char *ibpb_state(void)
2143 {
2144         if (boot_cpu_has(X86_FEATURE_IBPB)) {
2145                 if (static_key_enabled(&switch_mm_always_ibpb))
2146                         return ", IBPB: always-on";
2147                 if (static_key_enabled(&switch_mm_cond_ibpb))
2148                         return ", IBPB: conditional";
2149                 return ", IBPB: disabled";
2150         }
2151         return "";
2152 }
2153
2154 static char *pbrsb_eibrs_state(void)
2155 {
2156         if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
2157                 if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
2158                     boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
2159                         return ", PBRSB-eIBRS: SW sequence";
2160                 else
2161                         return ", PBRSB-eIBRS: Vulnerable";
2162         } else {
2163                 return ", PBRSB-eIBRS: Not affected";
2164         }
2165 }
2166
2167 static ssize_t spectre_v2_show_state(char *buf)
2168 {
2169         if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2170                 return sprintf(buf, "Vulnerable: LFENCE\n");
2171
2172         if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2173                 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2174
2175         if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2176             spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2177                 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2178
2179         return sprintf(buf, "%s%s%s%s%s%s%s\n",
2180                        spectre_v2_strings[spectre_v2_enabled],
2181                        ibpb_state(),
2182                        boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2183                        stibp_state(),
2184                        boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2185                        pbrsb_eibrs_state(),
2186                        spectre_v2_module_string());
2187 }
2188
2189 static ssize_t srbds_show_state(char *buf)
2190 {
2191         return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2192 }
2193
2194 static ssize_t retbleed_show_state(char *buf)
2195 {
2196         return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2197 }
2198
2199 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2200                                char *buf, unsigned int bug)
2201 {
2202         if (!boot_cpu_has_bug(bug))
2203                 return sprintf(buf, "Not affected\n");
2204
2205         switch (bug) {
2206         case X86_BUG_CPU_MELTDOWN:
2207                 if (boot_cpu_has(X86_FEATURE_PTI))
2208                         return sprintf(buf, "Mitigation: PTI\n");
2209
2210                 if (hypervisor_is_type(X86_HYPER_XEN_PV))
2211                         return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2212
2213                 break;
2214
2215         case X86_BUG_SPECTRE_V1:
2216                 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2217
2218         case X86_BUG_SPECTRE_V2:
2219                 return spectre_v2_show_state(buf);
2220
2221         case X86_BUG_SPEC_STORE_BYPASS:
2222                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2223
2224         case X86_BUG_L1TF:
2225                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2226                         return l1tf_show_state(buf);
2227                 break;
2228
2229         case X86_BUG_MDS:
2230                 return mds_show_state(buf);
2231
2232         case X86_BUG_TAA:
2233                 return tsx_async_abort_show_state(buf);
2234
2235         case X86_BUG_ITLB_MULTIHIT:
2236                 return itlb_multihit_show_state(buf);
2237
2238         case X86_BUG_SRBDS:
2239                 return srbds_show_state(buf);
2240
2241         case X86_BUG_MMIO_STALE_DATA:
2242         case X86_BUG_MMIO_UNKNOWN:
2243                 return mmio_stale_data_show_state(buf);
2244
2245         case X86_BUG_RETBLEED:
2246                 return retbleed_show_state(buf);
2247
2248         default:
2249                 break;
2250         }
2251
2252         return sprintf(buf, "Vulnerable\n");
2253 }
2254
2255 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2256 {
2257         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2258 }
2259
2260 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2261 {
2262         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2263 }
2264
2265 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2266 {
2267         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2268 }
2269
2270 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2271 {
2272         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2273 }
2274
2275 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2276 {
2277         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2278 }
2279
2280 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2281 {
2282         return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2283 }
2284
2285 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2286 {
2287         return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2288 }
2289
2290 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2291 {
2292         return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2293 }
2294
2295 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2296 {
2297         return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2298 }
2299
2300 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2301 {
2302         if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2303                 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2304         else
2305                 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2306 }
2307
2308 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2309 {
2310         return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);
2311 }
2312 #endif