1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
36 #include <asm/fpu/internal.h>
38 #include <linux/numa.h>
45 #include <asm/microcode.h>
46 #include <asm/microcode_intel.h>
47 #include <asm/intel-family.h>
48 #include <asm/cpu_device_id.h>
50 #ifdef CONFIG_X86_LOCAL_APIC
51 #include <asm/uv/uv.h>
56 /* all of these masks are initialized in setup_cpu_local_masks() */
57 cpumask_var_t cpu_initialized_mask;
58 cpumask_var_t cpu_callout_mask;
59 cpumask_var_t cpu_callin_mask;
61 /* representing cpus for which sibling maps can be computed */
62 cpumask_var_t cpu_sibling_setup_mask;
64 /* Number of siblings per CPU package */
65 int smp_num_siblings = 1;
66 EXPORT_SYMBOL(smp_num_siblings);
68 /* Last level cache ID of each logical CPU */
69 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
71 /* correctly size the local cpu masks */
72 void __init setup_cpu_local_masks(void)
74 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
75 alloc_bootmem_cpumask_var(&cpu_callin_mask);
76 alloc_bootmem_cpumask_var(&cpu_callout_mask);
77 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
80 static void default_init(struct cpuinfo_x86 *c)
83 cpu_detect_cache_sizes(c);
85 /* Not much we can do here... */
86 /* Check if at least it has cpuid */
87 if (c->cpuid_level == -1) {
88 /* No cpuid. It must be an ancient CPU */
90 strcpy(c->x86_model_id, "486");
92 strcpy(c->x86_model_id, "386");
97 static const struct cpu_dev default_cpu = {
98 .c_init = default_init,
99 .c_vendor = "Unknown",
100 .c_x86_vendor = X86_VENDOR_UNKNOWN,
103 static const struct cpu_dev *this_cpu = &default_cpu;
105 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(struct gdt_page, gdt_page) = { .gdt = {
108 * We need valid kernel segments for data and code in long mode too
109 * IRET will check the segment types kkeil 2000/10/28
110 * Also sysret mandates a special GDT layout
112 * TLS descriptors are currently at a different place compared to i386.
113 * Hopefully nobody expects them at a fixed place (Wine?)
115 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
116 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
117 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
118 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
119 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
122 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
123 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
124 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
125 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
127 * Segments used for calling PnP BIOS have byte granularity.
128 * They code segments and data segments have fixed 64k limits,
129 * the transfer segment sizes are set at run time.
132 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
134 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
136 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
138 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
140 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
142 * The APM segments have byte granularity and their bases
143 * are set at run time. All have 64k limits.
146 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
148 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
150 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
152 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
153 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
154 GDT_STACK_CANARY_INIT
157 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
159 static int __init x86_mpx_setup(char *s)
161 /* require an exact match without trailing characters */
165 /* do not emit a message if the feature is not present */
166 if (!boot_cpu_has(X86_FEATURE_MPX))
169 setup_clear_cpu_cap(X86_FEATURE_MPX);
170 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
173 __setup("nompx", x86_mpx_setup);
176 static int __init x86_pcid_setup(char *s)
178 /* require an exact match without trailing characters */
182 /* do not emit a message if the feature is not present */
183 if (!boot_cpu_has(X86_FEATURE_PCID))
186 setup_clear_cpu_cap(X86_FEATURE_PCID);
187 pr_info("nopcid: PCID feature disabled\n");
190 __setup("nopcid", x86_pcid_setup);
193 static int __init x86_noinvpcid_setup(char *s)
195 /* noinvpcid doesn't accept parameters */
199 /* do not emit a message if the feature is not present */
200 if (!boot_cpu_has(X86_FEATURE_INVPCID))
203 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
204 pr_info("noinvpcid: INVPCID feature disabled\n");
207 early_param("noinvpcid", x86_noinvpcid_setup);
210 static int cachesize_override = -1;
211 static int disable_x86_serial_nr = 1;
213 static int __init cachesize_setup(char *str)
215 get_option(&str, &cachesize_override);
218 __setup("cachesize=", cachesize_setup);
220 static int __init x86_sep_setup(char *s)
222 setup_clear_cpu_cap(X86_FEATURE_SEP);
225 __setup("nosep", x86_sep_setup);
227 /* Standard macro to see if a specific flag is changeable */
228 static inline int flag_is_changeable_p(u32 flag)
233 * Cyrix and IDT cpus allow disabling of CPUID
234 * so the code below may return different results
235 * when it is executed before and after enabling
236 * the CPUID. Add "volatile" to not allow gcc to
237 * optimize the subsequent calls to this function.
239 asm volatile ("pushfl \n\t"
250 : "=&r" (f1), "=&r" (f2)
253 return ((f1^f2) & flag) != 0;
256 /* Probe for the CPUID instruction */
257 int have_cpuid_p(void)
259 return flag_is_changeable_p(X86_EFLAGS_ID);
262 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
264 unsigned long lo, hi;
266 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
269 /* Disable processor serial number: */
271 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
273 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
275 pr_notice("CPU serial number disabled.\n");
276 clear_cpu_cap(c, X86_FEATURE_PN);
278 /* Disabling the serial number may affect the cpuid level */
279 c->cpuid_level = cpuid_eax(0);
282 static int __init x86_serial_nr_setup(char *s)
284 disable_x86_serial_nr = 0;
287 __setup("serialnumber", x86_serial_nr_setup);
289 static inline int flag_is_changeable_p(u32 flag)
293 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
298 static __init int setup_disable_smep(char *arg)
300 setup_clear_cpu_cap(X86_FEATURE_SMEP);
301 /* Check for things that depend on SMEP being enabled: */
302 check_mpx_erratum(&boot_cpu_data);
305 __setup("nosmep", setup_disable_smep);
307 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
309 if (cpu_has(c, X86_FEATURE_SMEP))
310 cr4_set_bits(X86_CR4_SMEP);
313 static __init int setup_disable_smap(char *arg)
315 setup_clear_cpu_cap(X86_FEATURE_SMAP);
318 __setup("nosmap", setup_disable_smap);
320 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
322 unsigned long eflags = native_save_fl();
324 /* This should have been cleared long ago */
325 BUG_ON(eflags & X86_EFLAGS_AC);
327 if (cpu_has(c, X86_FEATURE_SMAP)) {
328 #ifdef CONFIG_X86_SMAP
329 cr4_set_bits(X86_CR4_SMAP);
331 cr4_clear_bits(X86_CR4_SMAP);
336 static void setup_pcid(struct cpuinfo_x86 *c)
338 if (cpu_has(c, X86_FEATURE_PCID)) {
339 if (cpu_has(c, X86_FEATURE_PGE) || kaiser_enabled) {
340 cr4_set_bits(X86_CR4_PCIDE);
342 * INVPCID has two "groups" of types:
343 * 1/2: Invalidate an individual address
344 * 3/4: Invalidate all contexts
346 * 1/2 take a PCID, but 3/4 do not. So, 3/4
347 * ignore the PCID argument in the descriptor.
348 * But, we have to be careful not to call 1/2
349 * with an actual non-zero PCID in them before
350 * we do the above cr4_set_bits().
352 if (cpu_has(c, X86_FEATURE_INVPCID))
353 set_cpu_cap(c, X86_FEATURE_INVPCID_SINGLE);
356 * flush_tlb_all(), as currently implemented, won't
357 * work if PCID is on but PGE is not. Since that
358 * combination doesn't exist on real hardware, there's
359 * no reason to try to fully support it, but it's
360 * polite to avoid corrupting data if we're on
361 * an improperly configured VM.
363 clear_cpu_cap(c, X86_FEATURE_PCID);
370 * Protection Keys are not available in 32-bit mode.
372 static bool pku_disabled;
374 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
376 /* check the boot processor, plus compile options for PKU: */
377 if (!cpu_feature_enabled(X86_FEATURE_PKU))
379 /* checks the actual processor's cpuid bits: */
380 if (!cpu_has(c, X86_FEATURE_PKU))
385 cr4_set_bits(X86_CR4_PKE);
387 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
388 * cpuid bit to be set. We need to ensure that we
389 * update that bit in this CPU's "cpu_info".
391 set_cpu_cap(c, X86_FEATURE_OSPKE);
394 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
395 static __init int setup_disable_pku(char *arg)
398 * Do not clear the X86_FEATURE_PKU bit. All of the
399 * runtime checks are against OSPKE so clearing the
402 * This way, we will see "pku" in cpuinfo, but not
403 * "ospke", which is exactly what we want. It shows
404 * that the CPU has PKU, but the OS has not enabled it.
405 * This happens to be exactly how a system would look
406 * if we disabled the config option.
408 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
412 __setup("nopku", setup_disable_pku);
413 #endif /* CONFIG_X86_64 */
416 * Some CPU features depend on higher CPUID levels, which may not always
417 * be available due to CPUID level capping or broken virtualization
418 * software. Add those features to this table to auto-disable them.
420 struct cpuid_dependent_feature {
425 static const struct cpuid_dependent_feature
426 cpuid_dependent_features[] = {
427 { X86_FEATURE_MWAIT, 0x00000005 },
428 { X86_FEATURE_DCA, 0x00000009 },
429 { X86_FEATURE_XSAVE, 0x0000000d },
433 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
435 const struct cpuid_dependent_feature *df;
437 for (df = cpuid_dependent_features; df->feature; df++) {
439 if (!cpu_has(c, df->feature))
442 * Note: cpuid_level is set to -1 if unavailable, but
443 * extended_extended_level is set to 0 if unavailable
444 * and the legitimate extended levels are all negative
445 * when signed; hence the weird messing around with
448 if (!((s32)df->level < 0 ?
449 (u32)df->level > (u32)c->extended_cpuid_level :
450 (s32)df->level > (s32)c->cpuid_level))
453 clear_cpu_cap(c, df->feature);
457 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
458 x86_cap_flag(df->feature), df->level);
463 * Naming convention should be: <Name> [(<Codename>)]
464 * This table only is used unless init_<vendor>() below doesn't set it;
465 * in particular, if CPUID levels 0x80000002..4 are supported, this
469 /* Look up CPU names by table lookup. */
470 static const char *table_lookup_model(struct cpuinfo_x86 *c)
473 const struct legacy_cpu_model_info *info;
475 if (c->x86_model >= 16)
476 return NULL; /* Range check */
481 info = this_cpu->legacy_models;
483 while (info->family) {
484 if (info->family == c->x86)
485 return info->model_names[c->x86_model];
489 return NULL; /* Not found */
492 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
493 __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
495 void load_percpu_segment(int cpu)
498 loadsegment(fs, __KERNEL_PERCPU);
500 __loadsegment_simple(gs, 0);
501 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
503 load_stack_canary_segment();
507 * Current gdt points %fs at the "master" per-cpu area: after this,
508 * it's on the real one.
510 void switch_to_new_gdt(int cpu)
512 struct desc_ptr gdt_descr;
514 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
515 gdt_descr.size = GDT_SIZE - 1;
516 load_gdt(&gdt_descr);
517 /* Reload the per-cpu base */
519 load_percpu_segment(cpu);
522 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
524 static void get_model_name(struct cpuinfo_x86 *c)
529 if (c->extended_cpuid_level < 0x80000004)
532 v = (unsigned int *)c->x86_model_id;
533 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
534 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
535 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
536 c->x86_model_id[48] = 0;
538 /* Trim whitespace */
539 p = q = s = &c->x86_model_id[0];
545 /* Note the last non-whitespace index */
555 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
557 unsigned int n, dummy, ebx, ecx, edx, l2size;
559 n = c->extended_cpuid_level;
561 if (n >= 0x80000005) {
562 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
563 c->x86_cache_size = (ecx>>24) + (edx>>24);
565 /* On K8 L1 TLB is inclusive, so don't count it */
570 if (n < 0x80000006) /* Some chips just has a large L1. */
573 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
577 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
579 /* do processor-specific cache resizing */
580 if (this_cpu->legacy_cache_size)
581 l2size = this_cpu->legacy_cache_size(c, l2size);
583 /* Allow user to override all this if necessary. */
584 if (cachesize_override != -1)
585 l2size = cachesize_override;
588 return; /* Again, no L2 cache is possible */
591 c->x86_cache_size = l2size;
594 u16 __read_mostly tlb_lli_4k[NR_INFO];
595 u16 __read_mostly tlb_lli_2m[NR_INFO];
596 u16 __read_mostly tlb_lli_4m[NR_INFO];
597 u16 __read_mostly tlb_lld_4k[NR_INFO];
598 u16 __read_mostly tlb_lld_2m[NR_INFO];
599 u16 __read_mostly tlb_lld_4m[NR_INFO];
600 u16 __read_mostly tlb_lld_1g[NR_INFO];
602 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
604 if (this_cpu->c_detect_tlb)
605 this_cpu->c_detect_tlb(c);
607 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
608 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
609 tlb_lli_4m[ENTRIES]);
611 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
612 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
613 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
616 int detect_ht_early(struct cpuinfo_x86 *c)
619 u32 eax, ebx, ecx, edx;
621 if (!cpu_has(c, X86_FEATURE_HT))
624 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
627 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
630 cpuid(1, &eax, &ebx, &ecx, &edx);
632 smp_num_siblings = (ebx & 0xff0000) >> 16;
633 if (smp_num_siblings == 1)
634 pr_info_once("CPU0: Hyper-Threading is disabled\n");
639 void detect_ht(struct cpuinfo_x86 *c)
642 int index_msb, core_bits;
644 if (detect_ht_early(c) < 0)
647 index_msb = get_count_order(smp_num_siblings);
648 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
650 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
652 index_msb = get_count_order(smp_num_siblings);
654 core_bits = get_count_order(c->x86_max_cores);
656 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
657 ((1 << core_bits) - 1);
661 static void get_cpu_vendor(struct cpuinfo_x86 *c)
663 char *v = c->x86_vendor_id;
666 for (i = 0; i < X86_VENDOR_NUM; i++) {
670 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
671 (cpu_devs[i]->c_ident[1] &&
672 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
674 this_cpu = cpu_devs[i];
675 c->x86_vendor = this_cpu->c_x86_vendor;
680 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
681 "CPU: Your system may be unstable.\n", v);
683 c->x86_vendor = X86_VENDOR_UNKNOWN;
684 this_cpu = &default_cpu;
687 void cpu_detect(struct cpuinfo_x86 *c)
689 /* Get vendor name */
690 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
691 (unsigned int *)&c->x86_vendor_id[0],
692 (unsigned int *)&c->x86_vendor_id[8],
693 (unsigned int *)&c->x86_vendor_id[4]);
696 /* Intel-defined flags: level 0x00000001 */
697 if (c->cpuid_level >= 0x00000001) {
698 u32 junk, tfms, cap0, misc;
700 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
701 c->x86 = x86_family(tfms);
702 c->x86_model = x86_model(tfms);
703 c->x86_stepping = x86_stepping(tfms);
705 if (cap0 & (1<<19)) {
706 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
707 c->x86_cache_alignment = c->x86_clflush_size;
712 static void apply_forced_caps(struct cpuinfo_x86 *c)
716 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
717 c->x86_capability[i] &= ~cpu_caps_cleared[i];
718 c->x86_capability[i] |= cpu_caps_set[i];
722 static void init_speculation_control(struct cpuinfo_x86 *c)
725 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
726 * and they also have a different bit for STIBP support. Also,
727 * a hypervisor might have set the individual AMD bits even on
728 * Intel CPUs, for finer-grained selection of what's available.
730 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
731 set_cpu_cap(c, X86_FEATURE_IBRS);
732 set_cpu_cap(c, X86_FEATURE_IBPB);
733 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
736 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
737 set_cpu_cap(c, X86_FEATURE_STIBP);
739 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
740 cpu_has(c, X86_FEATURE_VIRT_SSBD))
741 set_cpu_cap(c, X86_FEATURE_SSBD);
743 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
744 set_cpu_cap(c, X86_FEATURE_IBRS);
745 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
748 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
749 set_cpu_cap(c, X86_FEATURE_IBPB);
751 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
752 set_cpu_cap(c, X86_FEATURE_STIBP);
753 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
756 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
757 set_cpu_cap(c, X86_FEATURE_SSBD);
758 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
759 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
763 void get_cpu_cap(struct cpuinfo_x86 *c)
765 u32 eax, ebx, ecx, edx;
767 /* Intel-defined flags: level 0x00000001 */
768 if (c->cpuid_level >= 0x00000001) {
769 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
771 c->x86_capability[CPUID_1_ECX] = ecx;
772 c->x86_capability[CPUID_1_EDX] = edx;
775 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
776 if (c->cpuid_level >= 0x00000006)
777 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
779 /* Additional Intel-defined flags: level 0x00000007 */
780 if (c->cpuid_level >= 0x00000007) {
781 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
782 c->x86_capability[CPUID_7_0_EBX] = ebx;
783 c->x86_capability[CPUID_7_ECX] = ecx;
784 c->x86_capability[CPUID_7_EDX] = edx;
787 /* Extended state features: level 0x0000000d */
788 if (c->cpuid_level >= 0x0000000d) {
789 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
791 c->x86_capability[CPUID_D_1_EAX] = eax;
794 /* Additional Intel-defined flags: level 0x0000000F */
795 if (c->cpuid_level >= 0x0000000F) {
797 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
798 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
799 c->x86_capability[CPUID_F_0_EDX] = edx;
801 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
802 /* will be overridden if occupancy monitoring exists */
803 c->x86_cache_max_rmid = ebx;
805 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
806 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
807 c->x86_capability[CPUID_F_1_EDX] = edx;
809 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
810 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
811 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
812 c->x86_cache_max_rmid = ecx;
813 c->x86_cache_occ_scale = ebx;
816 c->x86_cache_max_rmid = -1;
817 c->x86_cache_occ_scale = -1;
821 /* AMD-defined flags: level 0x80000001 */
822 eax = cpuid_eax(0x80000000);
823 c->extended_cpuid_level = eax;
825 if ((eax & 0xffff0000) == 0x80000000) {
826 if (eax >= 0x80000001) {
827 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
829 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
830 c->x86_capability[CPUID_8000_0001_EDX] = edx;
834 if (c->extended_cpuid_level >= 0x80000007) {
835 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
837 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
841 if (c->extended_cpuid_level >= 0x80000008) {
842 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
844 c->x86_virt_bits = (eax >> 8) & 0xff;
845 c->x86_phys_bits = eax & 0xff;
846 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
849 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
850 c->x86_phys_bits = 36;
852 c->x86_cache_bits = c->x86_phys_bits;
854 if (c->extended_cpuid_level >= 0x8000000a)
855 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
857 init_scattered_cpuid_features(c);
858 init_speculation_control(c);
861 * Clear/Set all flags overridden by options, after probe.
862 * This needs to happen each time we re-probe, which may happen
863 * several times during CPU initialization.
865 apply_forced_caps(c);
868 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
874 * First of all, decide if this is a 486 or higher
875 * It's a 486 if we can modify the AC flag
877 if (flag_is_changeable_p(X86_EFLAGS_AC))
882 for (i = 0; i < X86_VENDOR_NUM; i++)
883 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
884 c->x86_vendor_id[0] = 0;
885 cpu_devs[i]->c_identify(c);
886 if (c->x86_vendor_id[0]) {
894 #define NO_SPECULATION BIT(0)
895 #define NO_MELTDOWN BIT(1)
896 #define NO_SSB BIT(2)
897 #define NO_L1TF BIT(3)
898 #define NO_MDS BIT(4)
899 #define MSBDS_ONLY BIT(5)
900 #define NO_SWAPGS BIT(6)
901 #define NO_ITLB_MULTIHIT BIT(7)
902 #define NO_MMIO BIT(8)
904 #define VULNWL(_vendor, _family, _model, _whitelist) \
905 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
907 #define VULNWL_INTEL(model, whitelist) \
908 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
910 #define VULNWL_AMD(family, whitelist) \
911 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
913 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
914 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
915 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
916 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
917 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
920 VULNWL_INTEL(TIGERLAKE, NO_MMIO),
921 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO),
922 VULNWL_INTEL(ALDERLAKE, NO_MMIO),
923 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO),
925 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
926 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
927 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
928 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
929 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
931 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
932 VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
933 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
934 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
935 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
936 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
938 VULNWL_INTEL(CORE_YONAH, NO_SSB),
940 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
942 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
943 VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
944 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
947 * Technically, swapgs isn't serializing on AMD (despite it previously
948 * being documented as such in the APM). But according to AMD, %gs is
949 * updated non-speculatively, and the issuing of %gs-relative memory
950 * operands will be blocked until the %gs update completes, which is
951 * good enough for our purposes.
954 /* AMD Family 0xf - 0x12 */
955 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
956 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
957 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
958 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
960 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
961 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
965 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
966 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
967 INTEL_FAM6_##model, steppings, \
968 X86_FEATURE_ANY, issues)
971 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
973 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
974 #define MMIO_SBDS BIT(2)
976 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
977 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
978 VULNBL_INTEL_STEPPINGS(HASWELL_CORE, X86_STEPPING_ANY, SRBDS),
979 VULNBL_INTEL_STEPPINGS(HASWELL_ULT, X86_STEPPING_ANY, SRBDS),
980 VULNBL_INTEL_STEPPINGS(HASWELL_GT3E, X86_STEPPING_ANY, SRBDS),
981 VULNBL_INTEL_STEPPINGS(HASWELL_X, BIT(2) | BIT(4), MMIO),
982 VULNBL_INTEL_STEPPINGS(BROADWELL_XEON_D,X86_STEPPINGS(0x3, 0x5), MMIO),
983 VULNBL_INTEL_STEPPINGS(BROADWELL_GT3E, X86_STEPPING_ANY, SRBDS),
984 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO),
985 VULNBL_INTEL_STEPPINGS(BROADWELL_CORE, X86_STEPPING_ANY, SRBDS),
986 VULNBL_INTEL_STEPPINGS(SKYLAKE_MOBILE, X86_STEPPINGS(0x3, 0x3), SRBDS | MMIO),
987 VULNBL_INTEL_STEPPINGS(SKYLAKE_MOBILE, X86_STEPPING_ANY, SRBDS),
988 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, BIT(3) | BIT(4) | BIT(6) |
989 BIT(7) | BIT(0xB), MMIO),
990 VULNBL_INTEL_STEPPINGS(SKYLAKE_DESKTOP, X86_STEPPINGS(0x3, 0x3), SRBDS | MMIO),
991 VULNBL_INTEL_STEPPINGS(SKYLAKE_DESKTOP, X86_STEPPING_ANY, SRBDS),
992 VULNBL_INTEL_STEPPINGS(KABYLAKE_MOBILE, X86_STEPPINGS(0x9, 0xC), SRBDS | MMIO),
993 VULNBL_INTEL_STEPPINGS(KABYLAKE_MOBILE, X86_STEPPINGS(0x0, 0x8), SRBDS),
994 VULNBL_INTEL_STEPPINGS(KABYLAKE_DESKTOP,X86_STEPPINGS(0x9, 0xD), SRBDS | MMIO),
995 VULNBL_INTEL_STEPPINGS(KABYLAKE_DESKTOP,X86_STEPPINGS(0x0, 0x8), SRBDS),
996 VULNBL_INTEL_STEPPINGS(ICELAKE_MOBILE, X86_STEPPINGS(0x5, 0x5), MMIO | MMIO_SBDS),
997 VULNBL_INTEL_STEPPINGS(ICELAKE_XEON_D, X86_STEPPINGS(0x1, 0x1), MMIO),
998 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0x6), MMIO),
999 VULNBL_INTEL_STEPPINGS(COMETLAKE, BIT(2) | BIT(3) | BIT(5), MMIO | MMIO_SBDS),
1000 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x1, 0x1), MMIO | MMIO_SBDS),
1001 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO),
1002 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPINGS(0x1, 0x1), MMIO | MMIO_SBDS),
1003 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPINGS(0x1, 0x1), MMIO),
1004 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPINGS(0x1, 0x1), MMIO | MMIO_SBDS),
1005 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_X, X86_STEPPING_ANY, MMIO),
1006 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPINGS(0x0, 0x0), MMIO | MMIO_SBDS),
1010 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1012 const struct x86_cpu_id *m = x86_match_cpu(table);
1014 return m && !!(m->driver_data & which);
1017 u64 x86_read_arch_cap_msr(void)
1021 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1022 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1027 static bool arch_cap_mmio_immune(u64 ia32_cap)
1029 return (ia32_cap & ARCH_CAP_FBSDP_NO &&
1030 ia32_cap & ARCH_CAP_PSDP_NO &&
1031 ia32_cap & ARCH_CAP_SBDR_SSDP_NO);
1034 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1036 u64 ia32_cap = x86_read_arch_cap_msr();
1038 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1039 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1040 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1041 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1043 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1046 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1047 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1049 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1050 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1051 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1052 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1054 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1055 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1057 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1058 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1059 setup_force_cpu_bug(X86_BUG_MDS);
1060 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1061 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1064 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1065 setup_force_cpu_bug(X86_BUG_SWAPGS);
1068 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1069 * - TSX is supported or
1070 * - TSX_CTRL is present
1072 * TSX_CTRL check is needed for cases when TSX could be disabled before
1073 * the kernel boot e.g. kexec.
1074 * TSX_CTRL check alone is not sufficient for cases when the microcode
1075 * update is not present or running as guest that don't get TSX_CTRL.
1077 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1078 (cpu_has(c, X86_FEATURE_RTM) ||
1079 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1080 setup_force_cpu_bug(X86_BUG_TAA);
1083 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1084 * in the vulnerability blacklist.
1086 * Some of the implications and mitigation of Shared Buffers Data
1087 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1090 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1091 cpu_has(c, X86_FEATURE_RDSEED)) &&
1092 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1093 setup_force_cpu_bug(X86_BUG_SRBDS);
1096 * Processor MMIO Stale Data bug enumeration
1098 * Affected CPU list is generally enough to enumerate the vulnerability,
1099 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1100 * not want the guest to enumerate the bug.
1102 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1103 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1105 if (!arch_cap_mmio_immune(ia32_cap)) {
1106 if (cpu_matches(cpu_vuln_blacklist, MMIO))
1107 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1108 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1109 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1112 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1115 /* Rogue Data Cache Load? No! */
1116 if (ia32_cap & ARCH_CAP_RDCL_NO)
1119 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1121 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1124 setup_force_cpu_bug(X86_BUG_L1TF);
1128 * Do minimum CPU detection early.
1129 * Fields really needed: vendor, cpuid_level, family, model, mask,
1131 * The others are not touched to avoid unwanted side effects.
1133 * WARNING: this function is only called on the BP. Don't add code here
1134 * that is supposed to run on all CPUs.
1136 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1138 #ifdef CONFIG_X86_64
1139 c->x86_clflush_size = 64;
1140 c->x86_phys_bits = 36;
1141 c->x86_virt_bits = 48;
1143 c->x86_clflush_size = 32;
1144 c->x86_phys_bits = 32;
1145 c->x86_virt_bits = 32;
1147 c->x86_cache_alignment = c->x86_clflush_size;
1149 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1150 c->extended_cpuid_level = 0;
1152 if (!have_cpuid_p())
1153 identify_cpu_without_cpuid(c);
1155 /* cyrix could have cpuid enabled via c_identify()*/
1156 if (have_cpuid_p()) {
1161 if (this_cpu->c_early_init)
1162 this_cpu->c_early_init(c);
1165 filter_cpuid_features(c, false);
1167 if (this_cpu->c_bsp_init)
1168 this_cpu->c_bsp_init(c);
1171 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1173 cpu_set_bug_bits(c);
1175 fpu__init_system(c);
1177 #ifdef CONFIG_X86_32
1179 * Regardless of whether PCID is enumerated, the SDM says
1180 * that it can't be enabled in 32-bit mode.
1182 setup_clear_cpu_cap(X86_FEATURE_PCID);
1186 void __init early_cpu_init(void)
1188 const struct cpu_dev *const *cdev;
1191 #ifdef CONFIG_PROCESSOR_SELECT
1192 pr_info("KERNEL supported cpus:\n");
1195 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1196 const struct cpu_dev *cpudev = *cdev;
1198 if (count >= X86_VENDOR_NUM)
1200 cpu_devs[count] = cpudev;
1203 #ifdef CONFIG_PROCESSOR_SELECT
1207 for (j = 0; j < 2; j++) {
1208 if (!cpudev->c_ident[j])
1210 pr_info(" %s %s\n", cpudev->c_vendor,
1211 cpudev->c_ident[j]);
1216 early_identify_cpu(&boot_cpu_data);
1220 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1221 * unfortunately, that's not true in practice because of early VIA
1222 * chips and (more importantly) broken virtualizers that are not easy
1223 * to detect. In the latter case it doesn't even *fail* reliably, so
1224 * probing for it doesn't even work. Disable it completely on 32-bit
1225 * unless we can find a reliable way to detect all the broken cases.
1226 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1228 static void detect_nopl(struct cpuinfo_x86 *c)
1230 #ifdef CONFIG_X86_32
1231 clear_cpu_cap(c, X86_FEATURE_NOPL);
1233 set_cpu_cap(c, X86_FEATURE_NOPL);
1237 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1239 #ifdef CONFIG_X86_64
1241 * Empirically, writing zero to a segment selector on AMD does
1242 * not clear the base, whereas writing zero to a segment
1243 * selector on Intel does clear the base. Intel's behavior
1244 * allows slightly faster context switches in the common case
1245 * where GS is unused by the prev and next threads.
1247 * Since neither vendor documents this anywhere that I can see,
1248 * detect it directly instead of hardcoding the choice by
1251 * I've designated AMD's behavior as the "bug" because it's
1252 * counterintuitive and less friendly.
1255 unsigned long old_base, tmp;
1256 rdmsrl(MSR_FS_BASE, old_base);
1257 wrmsrl(MSR_FS_BASE, 1);
1259 rdmsrl(MSR_FS_BASE, tmp);
1261 set_cpu_bug(c, X86_BUG_NULL_SEG);
1262 wrmsrl(MSR_FS_BASE, old_base);
1266 static void generic_identify(struct cpuinfo_x86 *c)
1268 c->extended_cpuid_level = 0;
1270 if (!have_cpuid_p())
1271 identify_cpu_without_cpuid(c);
1273 /* cyrix could have cpuid enabled via c_identify()*/
1274 if (!have_cpuid_p())
1283 if (c->cpuid_level >= 0x00000001) {
1284 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1285 #ifdef CONFIG_X86_32
1287 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1289 c->apicid = c->initial_apicid;
1292 c->phys_proc_id = c->initial_apicid;
1295 get_model_name(c); /* Default name */
1299 detect_null_seg_behavior(c);
1302 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1303 * systems that run Linux at CPL > 0 may or may not have the
1304 * issue, but, even if they have the issue, there's absolutely
1305 * nothing we can do about it because we can't use the real IRET
1308 * NB: For the time being, only 32-bit kernels support
1309 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1310 * whether to apply espfix using paravirt hooks. If any
1311 * non-paravirt system ever shows up that does *not* have the
1312 * ESPFIX issue, we can change this.
1314 #ifdef CONFIG_X86_32
1315 # ifdef CONFIG_PARAVIRT
1317 extern void native_iret(void);
1318 if (pv_cpu_ops.iret == native_iret)
1319 set_cpu_bug(c, X86_BUG_ESPFIX);
1322 set_cpu_bug(c, X86_BUG_ESPFIX);
1327 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1330 * The heavy lifting of max_rmid and cache_occ_scale are handled
1331 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1332 * in case CQM bits really aren't there in this CPU.
1334 if (c != &boot_cpu_data) {
1335 boot_cpu_data.x86_cache_max_rmid =
1336 min(boot_cpu_data.x86_cache_max_rmid,
1337 c->x86_cache_max_rmid);
1342 * Validate that ACPI/mptables have the same information about the
1343 * effective APIC id and update the package map.
1345 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1348 unsigned int apicid, cpu = smp_processor_id();
1350 apicid = apic->cpu_present_to_apicid(cpu);
1352 if (apicid != c->apicid) {
1353 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1354 cpu, apicid, c->initial_apicid);
1356 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1358 c->logical_proc_id = 0;
1363 * This does the hard work of actually picking apart the CPU stuff...
1365 static void identify_cpu(struct cpuinfo_x86 *c)
1369 c->loops_per_jiffy = loops_per_jiffy;
1370 c->x86_cache_size = 0;
1371 c->x86_vendor = X86_VENDOR_UNKNOWN;
1372 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1373 c->x86_vendor_id[0] = '\0'; /* Unset */
1374 c->x86_model_id[0] = '\0'; /* Unset */
1375 c->x86_max_cores = 1;
1376 c->x86_coreid_bits = 0;
1378 #ifdef CONFIG_X86_64
1379 c->x86_clflush_size = 64;
1380 c->x86_phys_bits = 36;
1381 c->x86_virt_bits = 48;
1383 c->cpuid_level = -1; /* CPUID not detected */
1384 c->x86_clflush_size = 32;
1385 c->x86_phys_bits = 32;
1386 c->x86_virt_bits = 32;
1388 c->x86_cache_alignment = c->x86_clflush_size;
1389 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1391 generic_identify(c);
1393 if (this_cpu->c_identify)
1394 this_cpu->c_identify(c);
1396 /* Clear/Set all flags overridden by options, after probe */
1397 apply_forced_caps(c);
1399 #ifdef CONFIG_X86_64
1400 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1404 * Vendor-specific initialization. In this section we
1405 * canonicalize the feature flags, meaning if there are
1406 * features a certain CPU supports which CPUID doesn't
1407 * tell us, CPUID claiming incorrect flags, or other bugs,
1408 * we handle them here.
1410 * At the end of this section, c->x86_capability better
1411 * indicate the features this CPU genuinely supports!
1413 if (this_cpu->c_init)
1414 this_cpu->c_init(c);
1416 /* Disable the PN if appropriate */
1417 squash_the_stupid_serial_number(c);
1419 /* Set up SMEP/SMAP */
1427 * The vendor-specific functions might have changed features.
1428 * Now we do "generic changes."
1431 /* Filter out anything that depends on CPUID levels we don't have */
1432 filter_cpuid_features(c, true);
1434 /* If the model name is still unset, do table lookup. */
1435 if (!c->x86_model_id[0]) {
1437 p = table_lookup_model(c);
1439 strcpy(c->x86_model_id, p);
1441 /* Last resort... */
1442 sprintf(c->x86_model_id, "%02x/%02x",
1443 c->x86, c->x86_model);
1446 #ifdef CONFIG_X86_64
1452 x86_init_cache_qos(c);
1456 * Clear/Set all flags overridden by options, need do it
1457 * before following smp all cpus cap AND.
1459 apply_forced_caps(c);
1462 * On SMP, boot_cpu_data holds the common feature set between
1463 * all CPUs; so make sure that we indicate which features are
1464 * common between the CPUs. The first time this routine gets
1465 * executed, c == &boot_cpu_data.
1467 if (c != &boot_cpu_data) {
1468 /* AND the already accumulated flags with these */
1469 for (i = 0; i < NCAPINTS; i++)
1470 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1472 /* OR, i.e. replicate the bug flags */
1473 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1474 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1477 /* Init Machine Check Exception if available. */
1480 select_idle_routine(c);
1483 numa_add_cpu(smp_processor_id());
1488 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1489 * on 32-bit kernels:
1491 #ifdef CONFIG_X86_32
1492 void enable_sep_cpu(void)
1494 struct tss_struct *tss;
1497 if (!boot_cpu_has(X86_FEATURE_SEP))
1501 tss = &per_cpu(cpu_tss, cpu);
1504 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1505 * see the big comment in struct x86_hw_tss's definition.
1508 tss->x86_tss.ss1 = __KERNEL_CS;
1509 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1511 wrmsr(MSR_IA32_SYSENTER_ESP,
1512 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1515 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1521 void __init identify_boot_cpu(void)
1523 identify_cpu(&boot_cpu_data);
1524 init_amd_e400_c1e_mask();
1525 #ifdef CONFIG_X86_32
1529 cpu_detect_tlb(&boot_cpu_data);
1534 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1536 BUG_ON(c == &boot_cpu_data);
1538 #ifdef CONFIG_X86_32
1542 validate_apic_and_package_id(c);
1543 x86_spec_ctrl_setup_ap();
1552 static const struct msr_range msr_range_array[] = {
1553 { 0x00000000, 0x00000418},
1554 { 0xc0000000, 0xc000040b},
1555 { 0xc0010000, 0xc0010142},
1556 { 0xc0011000, 0xc001103b},
1559 static void __print_cpu_msr(void)
1561 unsigned index_min, index_max;
1566 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1567 index_min = msr_range_array[i].min;
1568 index_max = msr_range_array[i].max;
1570 for (index = index_min; index < index_max; index++) {
1571 if (rdmsrl_safe(index, &val))
1573 pr_info(" MSR%08x: %016llx\n", index, val);
1578 static int show_msr;
1580 static __init int setup_show_msr(char *arg)
1584 get_option(&arg, &num);
1590 __setup("show_msr=", setup_show_msr);
1592 static __init int setup_noclflush(char *arg)
1594 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1595 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1598 __setup("noclflush", setup_noclflush);
1600 void print_cpu_info(struct cpuinfo_x86 *c)
1602 const char *vendor = NULL;
1604 if (c->x86_vendor < X86_VENDOR_NUM) {
1605 vendor = this_cpu->c_vendor;
1607 if (c->cpuid_level >= 0)
1608 vendor = c->x86_vendor_id;
1611 if (vendor && !strstr(c->x86_model_id, vendor))
1612 pr_cont("%s ", vendor);
1614 if (c->x86_model_id[0])
1615 pr_cont("%s", c->x86_model_id);
1617 pr_cont("%d86", c->x86);
1619 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1621 if (c->x86_stepping || c->cpuid_level >= 0)
1622 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1629 void print_cpu_msr(struct cpuinfo_x86 *c)
1631 if (c->cpu_index < show_msr)
1635 static __init int setup_disablecpuid(char *arg)
1639 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
1640 setup_clear_cpu_cap(bit);
1646 __setup("clearcpuid=", setup_disablecpuid);
1648 #ifdef CONFIG_X86_64
1649 struct desc_ptr idt_descr __ro_after_init = {
1650 .size = NR_VECTORS * 16 - 1,
1651 .address = (unsigned long) idt_table,
1653 const struct desc_ptr debug_idt_descr = {
1654 .size = NR_VECTORS * 16 - 1,
1655 .address = (unsigned long) debug_idt_table,
1658 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1659 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1662 * The following percpu variables are hot. Align current_task to
1663 * cacheline size such that they fall in the same cacheline.
1665 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1667 EXPORT_PER_CPU_SYMBOL(current_task);
1669 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1670 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1672 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1674 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1675 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1678 * Special IST stacks which the CPU switches to when it calls
1679 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1680 * limit), all of them are 4K, except the debug stack which
1683 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1684 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1685 [DEBUG_STACK - 1] = DEBUG_STKSZ
1688 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(char, exception_stacks
1689 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1691 /* May not be marked __init: used by software suspend */
1692 void syscall_init(void)
1694 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1695 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1697 #ifdef CONFIG_IA32_EMULATION
1698 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1700 * This only works on Intel CPUs.
1701 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1702 * This does not cause SYSENTER to jump to the wrong location, because
1703 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1705 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1706 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1707 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1709 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1710 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1711 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1712 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1715 /* Flags to clear on syscall */
1716 wrmsrl(MSR_SYSCALL_MASK,
1717 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1718 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1722 * Copies of the original ist values from the tss are only accessed during
1723 * debugging, no special alignment required.
1725 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1727 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1728 DEFINE_PER_CPU(int, debug_stack_usage);
1730 int is_debug_stack(unsigned long addr)
1732 return __this_cpu_read(debug_stack_usage) ||
1733 (addr <= __this_cpu_read(debug_stack_addr) &&
1734 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1736 NOKPROBE_SYMBOL(is_debug_stack);
1738 DEFINE_PER_CPU(u32, debug_idt_ctr);
1740 void debug_stack_set_zero(void)
1742 this_cpu_inc(debug_idt_ctr);
1745 NOKPROBE_SYMBOL(debug_stack_set_zero);
1747 void debug_stack_reset(void)
1749 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1751 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1754 NOKPROBE_SYMBOL(debug_stack_reset);
1756 #else /* CONFIG_X86_64 */
1758 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1759 EXPORT_PER_CPU_SYMBOL(current_task);
1760 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1761 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1764 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1765 * the top of the kernel stack. Use an extra percpu variable to track the
1766 * top of the kernel stack directly.
1768 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1769 (unsigned long)&init_thread_union + THREAD_SIZE;
1770 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1772 #ifdef CONFIG_CC_STACKPROTECTOR
1773 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1776 #endif /* CONFIG_X86_64 */
1779 * Clear all 6 debug registers:
1781 static void clear_all_debug_regs(void)
1785 for (i = 0; i < 8; i++) {
1786 /* Ignore db4, db5 */
1787 if ((i == 4) || (i == 5))
1796 * Restore debug regs if using kgdbwait and you have a kernel debugger
1797 * connection established.
1799 static void dbg_restore_debug_regs(void)
1801 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1802 arch_kgdb_ops.correct_hw_break();
1804 #else /* ! CONFIG_KGDB */
1805 #define dbg_restore_debug_regs()
1806 #endif /* ! CONFIG_KGDB */
1808 static void wait_for_master_cpu(int cpu)
1812 * wait for ACK from master CPU before continuing
1813 * with AP initialization
1815 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1816 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1822 * cpu_init() initializes state that is per-CPU. Some data is already
1823 * initialized (naturally) in the bootstrap process, such as the GDT
1824 * and IDT. We reload them nevertheless, this function acts as a
1825 * 'CPU state barrier', nothing should get across.
1826 * A lot of state is already set up in PDA init for 64 bit
1828 #ifdef CONFIG_X86_64
1832 struct orig_ist *oist;
1833 struct task_struct *me;
1834 struct tss_struct *t;
1836 int cpu = raw_smp_processor_id();
1839 wait_for_master_cpu(cpu);
1842 * Initialize the CR4 shadow before doing anything that could
1846 if (!kaiser_enabled) {
1848 * secondary_startup_64() deferred setting PGE in cr4:
1849 * probe_page_size_mask() sets it on the boot cpu,
1850 * but it needs to be set on each secondary cpu.
1852 cr4_set_bits(X86_CR4_PGE);
1856 * Load microcode on this cpu if a valid microcode is available.
1857 * This is early microcode loading procedure.
1861 t = &per_cpu(cpu_tss, cpu);
1862 oist = &per_cpu(orig_ist, cpu);
1865 if (this_cpu_read(numa_node) == 0 &&
1866 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1867 set_numa_node(early_cpu_to_node(cpu));
1872 pr_debug("Initializing CPU#%d\n", cpu);
1874 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1877 * Initialize the per-CPU GDT with the boot GDT,
1878 * and set up the GDT descriptor:
1881 switch_to_new_gdt(cpu);
1886 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1889 wrmsrl(MSR_FS_BASE, 0);
1890 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1897 * set up and load the per-CPU TSS
1899 if (!oist->ist[0]) {
1900 char *estacks = per_cpu(exception_stacks, cpu);
1902 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1903 estacks += exception_stack_sizes[v];
1904 oist->ist[v] = t->x86_tss.ist[v] =
1905 (unsigned long)estacks;
1906 if (v == DEBUG_STACK-1)
1907 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1911 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1914 * <= is required because the CPU will access up to
1915 * 8 bits beyond the end of the IO permission bitmap.
1917 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1918 t->io_bitmap[i] = ~0UL;
1920 atomic_inc(&init_mm.mm_count);
1921 me->active_mm = &init_mm;
1923 enter_lazy_tlb(&init_mm, me);
1925 load_sp0(t, ¤t->thread);
1926 set_tss_desc(cpu, t);
1928 load_mm_ldt(&init_mm);
1930 clear_all_debug_regs();
1931 dbg_restore_debug_regs();
1943 int cpu = smp_processor_id();
1944 struct task_struct *curr = current;
1945 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1946 struct thread_struct *thread = &curr->thread;
1948 wait_for_master_cpu(cpu);
1951 * Initialize the CR4 shadow before doing anything that could
1956 show_ucode_info_early();
1958 pr_info("Initializing CPU#%d\n", cpu);
1960 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1961 boot_cpu_has(X86_FEATURE_TSC) ||
1962 boot_cpu_has(X86_FEATURE_DE))
1963 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1966 switch_to_new_gdt(cpu);
1969 * Set up and load the per-CPU TSS and LDT
1971 atomic_inc(&init_mm.mm_count);
1972 curr->active_mm = &init_mm;
1974 enter_lazy_tlb(&init_mm, curr);
1976 load_sp0(t, thread);
1977 set_tss_desc(cpu, t);
1979 load_mm_ldt(&init_mm);
1981 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1983 #ifdef CONFIG_DOUBLEFAULT
1984 /* Set up doublefault TSS pointer in the GDT */
1985 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1988 clear_all_debug_regs();
1989 dbg_restore_debug_regs();
1995 static void bsp_resume(void)
1997 if (this_cpu->c_bsp_resume)
1998 this_cpu->c_bsp_resume(&boot_cpu_data);
2001 static struct syscore_ops cpu_syscore_ops = {
2002 .resume = bsp_resume,
2005 static int __init init_cpu_syscore(void)
2007 register_syscore_ops(&cpu_syscore_ops);
2010 core_initcall(init_cpu_syscore);