2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/rcupdate.h>
18 #include <linux/kobject.h>
19 #include <linux/uaccess.h>
20 #include <linux/kdebug.h>
21 #include <linux/kernel.h>
22 #include <linux/percpu.h>
23 #include <linux/string.h>
24 #include <linux/device.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/delay.h>
27 #include <linux/ctype.h>
28 #include <linux/sched.h>
29 #include <linux/sysfs.h>
30 #include <linux/types.h>
31 #include <linux/slab.h>
32 #include <linux/init.h>
33 #include <linux/kmod.h>
34 #include <linux/poll.h>
35 #include <linux/nmi.h>
36 #include <linux/cpu.h>
37 #include <linux/ras.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
44 #include <linux/jump_label.h>
45 #include <linux/set_memory.h>
47 #include <asm/intel-family.h>
48 #include <asm/processor.h>
49 #include <asm/traps.h>
50 #include <asm/tlbflush.h>
53 #include <asm/reboot.h>
55 #include "mce-internal.h"
57 static DEFINE_MUTEX(mce_log_mutex);
59 /* sysfs synchronization */
60 static DEFINE_MUTEX(mce_sysfs_mutex);
62 #define CREATE_TRACE_POINTS
63 #include <trace/events/mce.h>
65 #define SPINUNIT 100 /* 100ns */
67 DEFINE_PER_CPU(unsigned, mce_exception_count);
69 struct mce_bank *mce_banks __read_mostly;
70 struct mce_vendor_flags mce_flags __read_mostly;
72 struct mca_config mca_cfg __read_mostly = {
76 * 0: always panic on uncorrected errors, log corrected errors
77 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
78 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
79 * 3: never panic or SIGBUS, log all errors (for testing only)
85 static DEFINE_PER_CPU(struct mce, mces_seen);
86 static unsigned long mce_need_notify;
87 static int cpu_missing;
90 * MCA banks polled by the period polling timer for corrected events.
91 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
93 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
94 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
98 * MCA banks controlled through firmware first for corrected errors.
99 * This is a global list of banks for which we won't enable CMCI and we
100 * won't poll. Firmware controls these banks and is responsible for
101 * reporting corrected errors through GHES. Uncorrected/recoverable
102 * errors are still notified through a machine check.
104 mce_banks_t mce_banks_ce_disabled;
106 static struct work_struct mce_work;
107 static struct irq_work mce_irq_work;
109 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
112 * CPU/chipset specific EDAC code can register a notifier call here to print
113 * MCE errors in a human-readable form.
115 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
117 /* Do initial initialization of a struct mce */
118 void mce_setup(struct mce *m)
120 memset(m, 0, sizeof(struct mce));
121 m->cpu = m->extcpu = smp_processor_id();
122 /* need the internal __ version to avoid deadlocks */
123 m->time = __ktime_get_real_seconds();
124 m->cpuvendor = boot_cpu_data.x86_vendor;
125 m->cpuid = cpuid_eax(1);
126 m->socketid = cpu_data(m->extcpu).phys_proc_id;
127 m->apicid = cpu_data(m->extcpu).initial_apicid;
128 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
130 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
131 rdmsrl(MSR_PPIN, m->ppin);
133 m->microcode = boot_cpu_data.microcode;
136 DEFINE_PER_CPU(struct mce, injectm);
137 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
139 void mce_log(struct mce *m)
141 if (!mce_gen_pool_add(m))
142 irq_work_queue(&mce_irq_work);
145 void mce_inject_log(struct mce *m)
147 mutex_lock(&mce_log_mutex);
149 mutex_unlock(&mce_log_mutex);
151 EXPORT_SYMBOL_GPL(mce_inject_log);
153 static struct notifier_block mce_srao_nb;
156 * We run the default notifier if we have only the SRAO, the first and the
157 * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
158 * notifiers registered on the chain.
160 #define NUM_DEFAULT_NOTIFIERS 3
161 static atomic_t num_notifiers;
163 void mce_register_decode_chain(struct notifier_block *nb)
165 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
168 atomic_inc(&num_notifiers);
170 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
172 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
174 void mce_unregister_decode_chain(struct notifier_block *nb)
176 atomic_dec(&num_notifiers);
178 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
180 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
182 static inline u32 ctl_reg(int bank)
184 return MSR_IA32_MCx_CTL(bank);
187 static inline u32 status_reg(int bank)
189 return MSR_IA32_MCx_STATUS(bank);
192 static inline u32 addr_reg(int bank)
194 return MSR_IA32_MCx_ADDR(bank);
197 static inline u32 misc_reg(int bank)
199 return MSR_IA32_MCx_MISC(bank);
202 static inline u32 smca_ctl_reg(int bank)
204 return MSR_AMD64_SMCA_MCx_CTL(bank);
207 static inline u32 smca_status_reg(int bank)
209 return MSR_AMD64_SMCA_MCx_STATUS(bank);
212 static inline u32 smca_addr_reg(int bank)
214 return MSR_AMD64_SMCA_MCx_ADDR(bank);
217 static inline u32 smca_misc_reg(int bank)
219 return MSR_AMD64_SMCA_MCx_MISC(bank);
222 struct mca_msr_regs msr_ops = {
224 .status = status_reg,
229 static void __print_mce(struct mce *m)
231 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
233 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
234 m->mcgstatus, m->bank, m->status);
237 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
238 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
241 if (m->cs == __KERNEL_CS)
242 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
246 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
248 pr_cont("ADDR %llx ", m->addr);
250 pr_cont("MISC %llx ", m->misc);
252 if (mce_flags.smca) {
254 pr_cont("SYND %llx ", m->synd);
256 pr_cont("IPID %llx ", m->ipid);
261 * Note this output is parsed by external tools and old fields
262 * should not be changed.
264 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
265 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
269 static void print_mce(struct mce *m)
273 if (m->cpuvendor != X86_VENDOR_AMD)
274 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
277 #define PANIC_TIMEOUT 5 /* 5 seconds */
279 static atomic_t mce_panicked;
281 static int fake_panic;
282 static atomic_t mce_fake_panicked;
284 /* Panic in progress. Enable interrupts and wait for final IPI */
285 static void wait_for_panic(void)
287 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
291 while (timeout-- > 0)
293 if (panic_timeout == 0)
294 panic_timeout = mca_cfg.panic_timeout;
295 panic("Panicing machine check CPU died");
298 static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
300 struct llist_node *pending;
301 struct mce_evt_llist *l;
305 * Allow instrumentation around external facilities usage. Not that it
306 * matters a whole lot since the machine is going to panic anyway.
308 instrumentation_begin();
312 * Make sure only one CPU runs in machine check panic
314 if (atomic_inc_return(&mce_panicked) > 1)
321 /* Don't log too much for fake panic */
322 if (atomic_inc_return(&mce_fake_panicked) > 1)
325 pending = mce_gen_pool_prepare_records();
326 /* First print corrected ones that are still unlogged */
327 llist_for_each_entry(l, pending, llnode) {
328 struct mce *m = &l->mce;
329 if (!(m->status & MCI_STATUS_UC)) {
332 apei_err = apei_write_mce(m);
335 /* Now print uncorrected but with the final one last */
336 llist_for_each_entry(l, pending, llnode) {
337 struct mce *m = &l->mce;
338 if (!(m->status & MCI_STATUS_UC))
340 if (!final || mce_cmp(m, final)) {
343 apei_err = apei_write_mce(m);
349 apei_err = apei_write_mce(final);
352 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
354 pr_emerg(HW_ERR "Machine check: %s\n", exp);
356 if (panic_timeout == 0)
357 panic_timeout = mca_cfg.panic_timeout;
360 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
363 instrumentation_end();
366 /* Support code for software error injection */
368 static int msr_to_offset(u32 msr)
370 unsigned bank = __this_cpu_read(injectm.bank);
372 if (msr == mca_cfg.rip_msr)
373 return offsetof(struct mce, ip);
374 if (msr == msr_ops.status(bank))
375 return offsetof(struct mce, status);
376 if (msr == msr_ops.addr(bank))
377 return offsetof(struct mce, addr);
378 if (msr == msr_ops.misc(bank))
379 return offsetof(struct mce, misc);
380 if (msr == MSR_IA32_MCG_STATUS)
381 return offsetof(struct mce, mcgstatus);
385 /* MSR access wrappers used for error injection */
386 static u64 mce_rdmsrl(u32 msr)
390 if (__this_cpu_read(injectm.finished)) {
391 int offset = msr_to_offset(msr);
395 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
398 if (rdmsrl_safe(msr, &v)) {
399 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
401 * Return zero in case the access faulted. This should
402 * not happen normally but can happen if the CPU does
403 * something weird, or if the code is buggy.
411 static void mce_wrmsrl(u32 msr, u64 v)
413 if (__this_cpu_read(injectm.finished)) {
414 int offset = msr_to_offset(msr);
417 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
424 * Collect all global (w.r.t. this processor) status about this machine
425 * check into our "mce" struct so that we can use it later to assess
426 * the severity of the problem as we read per-bank specific details.
428 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
432 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
435 * Get the address of the instruction at the time of
436 * the machine check error.
438 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
443 * When in VM86 mode make the cs look like ring 3
444 * always. This is a lie, but it's better than passing
445 * the additional vm86 bit around everywhere.
447 if (v8086_mode(regs))
450 /* Use accurate RIP reporting if available. */
452 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
456 int mce_available(struct cpuinfo_x86 *c)
458 if (mca_cfg.disabled)
460 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
463 static void mce_schedule_work(void)
465 if (!mce_gen_pool_empty())
466 schedule_work(&mce_work);
469 static void mce_irq_work_cb(struct irq_work *entry)
474 static void mce_report_event(struct pt_regs *regs)
476 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
479 * Triggering the work queue here is just an insurance
480 * policy in case the syscall exit notify handler
481 * doesn't run soon enough or ends up running on the
482 * wrong CPU (can happen when audit sleeps)
488 irq_work_queue(&mce_irq_work);
492 * Check if the address reported by the CPU is in a format we can parse.
493 * It would be possible to add code for most other cases, but all would
494 * be somewhat complicated (e.g. segment offset would require an instruction
495 * parser). So only support physical addresses up to page granuality for now.
497 int mce_usable_address(struct mce *m)
499 if (!(m->status & MCI_STATUS_ADDRV))
502 /* Checks after this one are Intel-specific: */
503 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
506 if (!(m->status & MCI_STATUS_MISCV))
509 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
512 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
517 EXPORT_SYMBOL_GPL(mce_usable_address);
519 bool mce_is_memory_error(struct mce *m)
521 if (m->cpuvendor == X86_VENDOR_AMD) {
522 return amd_mce_is_memory_error(m);
524 } else if (m->cpuvendor == X86_VENDOR_INTEL) {
526 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
528 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
529 * indicating a memory error. Bit 8 is used for indicating a
530 * cache hierarchy error. The combination of bit 2 and bit 3
531 * is used for indicating a `generic' cache hierarchy error
532 * But we can't just blindly check the above bits, because if
533 * bit 11 is set, then it is a bus/interconnect error - and
534 * either way the above bits just gives more detail on what
535 * bus/interconnect error happened. Note that bit 12 can be
536 * ignored, as it's the "filter" bit.
538 return (m->status & 0xef80) == BIT(7) ||
539 (m->status & 0xef00) == BIT(8) ||
540 (m->status & 0xeffc) == 0xc;
545 EXPORT_SYMBOL_GPL(mce_is_memory_error);
547 static bool whole_page(struct mce *m)
549 if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
551 return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
554 bool mce_is_correctable(struct mce *m)
556 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
559 if (m->status & MCI_STATUS_UC)
564 EXPORT_SYMBOL_GPL(mce_is_correctable);
566 static bool cec_add_mce(struct mce *m)
571 /* We eat only correctable DRAM errors with usable addresses. */
572 if (mce_is_memory_error(m) &&
573 mce_is_correctable(m) &&
574 mce_usable_address(m))
575 if (!cec_add_elem(m->addr >> PAGE_SHIFT))
581 static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
584 struct mce *m = (struct mce *)data;
592 /* Emit the trace record: */
595 set_bit(0, &mce_need_notify);
602 static struct notifier_block first_nb = {
603 .notifier_call = mce_first_notifier,
604 .priority = MCE_PRIO_FIRST,
607 static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
610 struct mce *mce = (struct mce *)data;
616 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
617 pfn = mce->addr >> PAGE_SHIFT;
618 if (!memory_failure(pfn, 0))
619 set_mce_nospec(pfn, whole_page(mce));
624 static struct notifier_block mce_srao_nb = {
625 .notifier_call = srao_decode_notifier,
626 .priority = MCE_PRIO_SRAO,
629 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
632 struct mce *m = (struct mce *)data;
637 if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
645 static struct notifier_block mce_default_nb = {
646 .notifier_call = mce_default_notifier,
647 /* lowest prio, we want it to run last. */
648 .priority = MCE_PRIO_LOWEST,
652 * Read ADDR and MISC registers.
654 static noinstr void mce_read_aux(struct mce *m, int i)
656 if (m->status & MCI_STATUS_MISCV)
657 m->misc = mce_rdmsrl(msr_ops.misc(i));
659 if (m->status & MCI_STATUS_ADDRV) {
660 m->addr = mce_rdmsrl(msr_ops.addr(i));
663 * Mask the reported address by the reported granularity.
665 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
666 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
672 * Extract [55:<lsb>] where lsb is the least significant
673 * *valid* bit of the address bits.
675 if (mce_flags.smca) {
676 u8 lsb = (m->addr >> 56) & 0x3f;
678 m->addr &= GENMASK_ULL(55, lsb);
682 if (mce_flags.smca) {
683 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
685 if (m->status & MCI_STATUS_SYNDV)
686 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
690 DEFINE_PER_CPU(unsigned, mce_poll_count);
693 * Poll for corrected events or events that happened before reset.
694 * Those are just logged through /dev/mcelog.
696 * This is executed in standard interrupt context.
698 * Note: spec recommends to panic for fatal unsignalled
699 * errors here. However this would be quite problematic --
700 * we would need to reimplement the Monarch handling and
701 * it would mess up the exclusion between exception handler
702 * and poll hander -- * so we skip this for now.
703 * These cases should not happen anyways, or only when the CPU
704 * is already totally * confused. In this case it's likely it will
705 * not fully execute the machine check handler either.
707 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
709 bool error_seen = false;
713 this_cpu_inc(mce_poll_count);
715 mce_gather_info(&m, NULL);
717 if (flags & MCP_TIMESTAMP)
720 for (i = 0; i < mca_cfg.banks; i++) {
721 if (!mce_banks[i].ctl || !test_bit(i, *b))
729 m.status = mce_rdmsrl(msr_ops.status(i));
731 /* If this entry is not valid, ignore it */
732 if (!(m.status & MCI_STATUS_VAL))
736 * If we are logging everything (at CPU online) or this
737 * is a corrected error, then we must log it.
739 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
743 * Newer Intel systems that support software error
744 * recovery need to make additional checks. Other
745 * CPUs should skip over uncorrected errors, but log
749 if (m.status & MCI_STATUS_UC)
754 /* Log "not enabled" (speculative) errors */
755 if (!(m.status & MCI_STATUS_EN))
759 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
760 * UC == 1 && PCC == 0 && S == 0
762 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
766 * Skip anything else. Presumption is that our read of this
767 * bank is racing with a machine check. Leave the log alone
768 * for do_machine_check() to deal with it.
777 m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
780 * Don't get the IP here because it's unlikely to
781 * have anything to do with the actual error location.
783 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
785 else if (mce_usable_address(&m)) {
787 * Although we skipped logging this, we still want
788 * to take action. Add to the pool so the registered
789 * notifiers will see it.
791 if (!mce_gen_pool_add(&m))
796 * Clear state for this bank.
798 mce_wrmsrl(msr_ops.status(i), 0);
802 * Don't clear MCG_STATUS here because it's only defined for
810 EXPORT_SYMBOL_GPL(machine_check_poll);
813 * Do a quick check if any of the events requires a panic.
814 * This decides if we keep the events around or clear them.
816 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
817 struct pt_regs *regs)
822 for (i = 0; i < mca_cfg.banks; i++) {
823 m->status = mce_rdmsrl(msr_ops.status(i));
824 if (!(m->status & MCI_STATUS_VAL))
827 __set_bit(i, validp);
828 if (quirk_no_way_out)
829 quirk_no_way_out(i, m, regs);
832 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
842 * Variable to establish order between CPUs while scanning.
843 * Each CPU spins initially until executing is equal its number.
845 static atomic_t mce_executing;
848 * Defines order of CPUs on entry. First CPU becomes Monarch.
850 static atomic_t mce_callin;
853 * Check if a timeout waiting for other CPUs happened.
855 static int mce_timed_out(u64 *t, const char *msg)
858 * The others already did panic for some reason.
859 * Bail out like in a timeout.
860 * rmb() to tell the compiler that system_state
861 * might have been modified by someone else.
864 if (atomic_read(&mce_panicked))
866 if (!mca_cfg.monarch_timeout)
868 if ((s64)*t < SPINUNIT) {
869 if (mca_cfg.tolerant <= 1)
870 mce_panic(msg, NULL, NULL);
876 touch_nmi_watchdog();
881 * The Monarch's reign. The Monarch is the CPU who entered
882 * the machine check handler first. It waits for the others to
883 * raise the exception too and then grades them. When any
884 * error is fatal panic. Only then let the others continue.
886 * The other CPUs entering the MCE handler will be controlled by the
887 * Monarch. They are called Subjects.
889 * This way we prevent any potential data corruption in a unrecoverable case
890 * and also makes sure always all CPU's errors are examined.
892 * Also this detects the case of a machine check event coming from outer
893 * space (not detected by any CPUs) In this case some external agent wants
894 * us to shut down, so panic too.
896 * The other CPUs might still decide to panic if the handler happens
897 * in a unrecoverable place, but in this case the system is in a semi-stable
898 * state and won't corrupt anything by itself. It's ok to let the others
899 * continue for a bit first.
901 * All the spin loops have timeouts; when a timeout happens a CPU
902 * typically elects itself to be Monarch.
904 static void mce_reign(void)
907 struct mce *m = NULL;
908 int global_worst = 0;
913 * This CPU is the Monarch and the other CPUs have run
914 * through their handlers.
915 * Grade the severity of the errors of all the CPUs.
917 for_each_possible_cpu(cpu) {
918 int severity = mce_severity(&per_cpu(mces_seen, cpu),
921 if (severity > global_worst) {
923 global_worst = severity;
924 m = &per_cpu(mces_seen, cpu);
929 * Cannot recover? Panic here then.
930 * This dumps all the mces in the log buffer and stops the
933 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
934 mce_panic("Fatal machine check", m, msg);
937 * For UC somewhere we let the CPU who detects it handle it.
938 * Also must let continue the others, otherwise the handling
939 * CPU could deadlock on a lock.
943 * No machine check event found. Must be some external
944 * source or one CPU is hung. Panic.
946 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
947 mce_panic("Fatal machine check from unknown source", NULL, NULL);
950 * Now clear all the mces_seen so that they don't reappear on
953 for_each_possible_cpu(cpu)
954 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
957 static atomic_t global_nwo;
960 * Start of Monarch synchronization. This waits until all CPUs have
961 * entered the exception handler and then determines if any of them
962 * saw a fatal event that requires panic. Then it executes them
963 * in the entry order.
964 * TBD double check parallel CPU hotunplug
966 static int mce_start(int *no_way_out)
969 int cpus = num_online_cpus();
970 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
975 atomic_add(*no_way_out, &global_nwo);
977 * Rely on the implied barrier below, such that global_nwo
978 * is updated before mce_callin.
980 order = atomic_inc_return(&mce_callin);
985 while (atomic_read(&mce_callin) != cpus) {
986 if (mce_timed_out(&timeout,
987 "Timeout: Not all CPUs entered broadcast exception handler")) {
988 atomic_set(&global_nwo, 0);
995 * mce_callin should be read before global_nwo
1001 * Monarch: Starts executing now, the others wait.
1003 atomic_set(&mce_executing, 1);
1006 * Subject: Now start the scanning loop one by one in
1007 * the original callin order.
1008 * This way when there are any shared banks it will be
1009 * only seen by one CPU before cleared, avoiding duplicates.
1011 while (atomic_read(&mce_executing) < order) {
1012 if (mce_timed_out(&timeout,
1013 "Timeout: Subject CPUs unable to finish machine check processing")) {
1014 atomic_set(&global_nwo, 0);
1022 * Cache the global no_way_out state.
1024 *no_way_out = atomic_read(&global_nwo);
1030 * Synchronize between CPUs after main scanning loop.
1031 * This invokes the bulk of the Monarch processing.
1033 static noinstr int mce_end(int order)
1035 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1038 /* Allow instrumentation around external facilities. */
1039 instrumentation_begin();
1047 * Allow others to run.
1049 atomic_inc(&mce_executing);
1052 /* CHECKME: Can this race with a parallel hotplug? */
1053 int cpus = num_online_cpus();
1056 * Monarch: Wait for everyone to go through their scanning
1059 while (atomic_read(&mce_executing) <= cpus) {
1060 if (mce_timed_out(&timeout,
1061 "Timeout: Monarch CPU unable to finish machine check processing"))
1071 * Subject: Wait for Monarch to finish.
1073 while (atomic_read(&mce_executing) != 0) {
1074 if (mce_timed_out(&timeout,
1075 "Timeout: Monarch CPU did not finish machine check processing"))
1081 * Don't reset anything. That's done by the Monarch.
1088 * Reset all global state.
1091 atomic_set(&global_nwo, 0);
1092 atomic_set(&mce_callin, 0);
1096 * Let others run again.
1098 atomic_set(&mce_executing, 0);
1101 instrumentation_end();
1106 static void mce_clear_state(unsigned long *toclear)
1110 for (i = 0; i < mca_cfg.banks; i++) {
1111 if (test_bit(i, toclear))
1112 mce_wrmsrl(msr_ops.status(i), 0);
1116 static int do_memory_failure(struct mce *m)
1118 int flags = MF_ACTION_REQUIRED;
1121 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1122 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1123 flags |= MF_MUST_KILL;
1124 ret = memory_failure(m->addr >> PAGE_SHIFT, flags);
1126 pr_err("Memory error not recovered");
1128 set_mce_nospec(m->addr >> PAGE_SHIFT, whole_page(m));
1134 * Cases where we avoid rendezvous handler timeout:
1135 * 1) If this CPU is offline.
1137 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1138 * skip those CPUs which remain looping in the 1st kernel - see
1139 * crash_nmi_callback().
1141 * Note: there still is a small window between kexec-ing and the new,
1142 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1143 * might not get handled properly.
1145 static bool __mc_check_crashing_cpu(int cpu)
1147 if (cpu_is_offline(cpu) ||
1148 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1151 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1152 if (mcgstatus & MCG_STATUS_RIPV) {
1153 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1160 static void __mc_scan_banks(struct mce *m, struct mce *final,
1161 unsigned long *toclear, unsigned long *valid_banks,
1162 int no_way_out, int *worst)
1164 struct mca_config *cfg = &mca_cfg;
1167 for (i = 0; i < cfg->banks; i++) {
1168 __clear_bit(i, toclear);
1169 if (!test_bit(i, valid_banks))
1172 if (!mce_banks[i].ctl)
1179 m->status = mce_rdmsrl(msr_ops.status(i));
1180 if (!(m->status & MCI_STATUS_VAL))
1184 * Corrected or non-signaled errors are handled by
1185 * machine_check_poll(). Leave them alone, unless this panics.
1187 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1191 /* Set taint even when machine check was not enabled. */
1192 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1194 severity = mce_severity(m, cfg->tolerant, NULL, true);
1197 * When machine check was for corrected/deferred handler don't
1198 * touch, unless we're panicking.
1200 if ((severity == MCE_KEEP_SEVERITY ||
1201 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1204 __set_bit(i, toclear);
1206 /* Machine check event was not enabled. Clear, but ignore. */
1207 if (severity == MCE_NO_SEVERITY)
1212 /* assuming valid severity level != 0 */
1213 m->severity = severity;
1217 if (severity > *worst) {
1223 /* mce_clear_state will clear *final, save locally for use later */
1228 * The actual machine check handler. This only handles real
1229 * exceptions when something got corrupted coming in through int 18.
1231 * This is executed in NMI context not subject to normal locking rules. This
1232 * implies that most kernel services cannot be safely used. Don't even
1233 * think about putting a printk in there!
1235 * On Intel systems this is entered on all CPUs in parallel through
1236 * MCE broadcast. However some CPUs might be broken beyond repair,
1237 * so be always careful when synchronizing with others.
1239 void do_machine_check(struct pt_regs *regs, long error_code)
1241 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1242 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1243 struct mca_config *cfg = &mca_cfg;
1244 int cpu = smp_processor_id();
1245 char *msg = "Unknown";
1246 struct mce m, *final;
1250 * Establish sequential order between the CPUs entering the machine
1256 * If no_way_out gets set, there is no safe way to recover from this
1257 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1262 * If kill_it gets set, there might be a way to recover from this
1268 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1273 if (__mc_check_crashing_cpu(cpu))
1278 this_cpu_inc(mce_exception_count);
1280 mce_gather_info(&m, regs);
1283 final = this_cpu_ptr(&mces_seen);
1286 memset(valid_banks, 0, sizeof(valid_banks));
1287 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1292 * When no restart IP might need to kill or panic.
1293 * Assume the worst for now, but if we find the
1294 * severity is MCE_AR_SEVERITY we have other options.
1296 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1300 * Check if this MCE is signaled to only this logical processor,
1303 if (m.cpuvendor == X86_VENDOR_INTEL)
1304 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1307 * Local machine check may already know that we have to panic.
1308 * Broadcast machine check begins rendezvous in mce_start()
1309 * Go through all banks in exclusion of the other CPUs. This way we
1310 * don't report duplicated events on shared banks because the first one
1311 * to see it will clear it.
1315 mce_panic("Fatal local machine check", &m, msg);
1317 order = mce_start(&no_way_out);
1320 __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst);
1323 mce_clear_state(toclear);
1326 * Do most of the synchronization with other CPUs.
1327 * When there's any problem use only local no_way_out state.
1330 if (mce_end(order) < 0)
1331 no_way_out = worst >= MCE_PANIC_SEVERITY;
1334 * If there was a fatal machine check we should have
1335 * already called mce_panic earlier in this function.
1336 * Since we re-read the banks, we might have found
1337 * something new. Check again to see if we found a
1338 * fatal error. We call "mce_severity()" again to
1339 * make sure we have the right "msg".
1341 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1342 mce_severity(&m, cfg->tolerant, &msg, true);
1343 mce_panic("Local fatal machine check!", &m, msg);
1348 * If tolerant is at an insane level we drop requests to kill
1349 * processes and continue even when there is no way out.
1351 if (cfg->tolerant == 3)
1353 else if (no_way_out)
1354 mce_panic("Fatal machine check on current CPU", &m, msg);
1357 mce_report_event(regs);
1358 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1362 if (worst != MCE_AR_SEVERITY && !kill_it)
1365 /* Fault was in user mode and we need to take some action */
1366 if ((m.cs & 3) == 3) {
1367 ist_begin_non_atomic(regs);
1370 if (kill_it || do_memory_failure(&m))
1371 force_sig(SIGBUS, current);
1372 local_irq_disable();
1373 ist_end_non_atomic();
1375 if (!fixup_exception(regs, X86_TRAP_MC))
1376 mce_panic("Failed kernel mode recovery", &m, NULL);
1382 EXPORT_SYMBOL_GPL(do_machine_check);
1384 #ifndef CONFIG_MEMORY_FAILURE
1385 int memory_failure(unsigned long pfn, int flags)
1387 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1388 BUG_ON(flags & MF_ACTION_REQUIRED);
1389 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1390 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1398 * Periodic polling timer for "silent" machine check errors. If the
1399 * poller finds an MCE, poll 2x faster. When the poller finds no more
1400 * errors, poll 2x slower (up to check_interval seconds).
1402 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1404 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1405 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1407 static unsigned long mce_adjust_timer_default(unsigned long interval)
1412 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1414 static void __start_timer(struct timer_list *t, unsigned long interval)
1416 unsigned long when = jiffies + interval;
1417 unsigned long flags;
1419 local_irq_save(flags);
1421 if (!timer_pending(t) || time_before(when, t->expires))
1422 mod_timer(t, round_jiffies(when));
1424 local_irq_restore(flags);
1427 static void mce_timer_fn(struct timer_list *t)
1429 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1432 WARN_ON(cpu_t != t);
1434 iv = __this_cpu_read(mce_next_interval);
1436 if (mce_available(this_cpu_ptr(&cpu_info))) {
1437 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1439 if (mce_intel_cmci_poll()) {
1440 iv = mce_adjust_timer(iv);
1446 * Alert userspace if needed. If we logged an MCE, reduce the polling
1447 * interval, otherwise increase the polling interval.
1449 if (mce_notify_irq())
1450 iv = max(iv / 2, (unsigned long) HZ/100);
1452 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1455 __this_cpu_write(mce_next_interval, iv);
1456 __start_timer(t, iv);
1460 * Ensure that the timer is firing in @interval from now.
1462 void mce_timer_kick(unsigned long interval)
1464 struct timer_list *t = this_cpu_ptr(&mce_timer);
1465 unsigned long iv = __this_cpu_read(mce_next_interval);
1467 __start_timer(t, interval);
1470 __this_cpu_write(mce_next_interval, interval);
1473 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1474 static void mce_timer_delete_all(void)
1478 for_each_online_cpu(cpu)
1479 del_timer_sync(&per_cpu(mce_timer, cpu));
1483 * Notify the user(s) about new machine check events.
1484 * Can be called from interrupt context, but not from machine check/NMI
1487 int mce_notify_irq(void)
1489 /* Not more than two messages every minute */
1490 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1492 if (test_and_clear_bit(0, &mce_need_notify)) {
1495 if (__ratelimit(&ratelimit))
1496 pr_info(HW_ERR "Machine check events logged\n");
1502 EXPORT_SYMBOL_GPL(mce_notify_irq);
1504 static int __mcheck_cpu_mce_banks_init(void)
1508 mce_banks = kcalloc(MAX_NR_BANKS, sizeof(struct mce_bank), GFP_KERNEL);
1512 for (i = 0; i < MAX_NR_BANKS; i++) {
1513 struct mce_bank *b = &mce_banks[i];
1522 * Initialize Machine Checks for a CPU.
1524 static int __mcheck_cpu_cap_init(void)
1529 rdmsrl(MSR_IA32_MCG_CAP, cap);
1531 b = cap & MCG_BANKCNT_MASK;
1532 if (WARN_ON_ONCE(b > MAX_NR_BANKS))
1535 mca_cfg.banks = max(mca_cfg.banks, b);
1538 int err = __mcheck_cpu_mce_banks_init();
1543 /* Use accurate RIP reporting if available. */
1544 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1545 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1547 if (cap & MCG_SER_P)
1553 static void __mcheck_cpu_init_generic(void)
1555 enum mcp_flags m_fl = 0;
1556 mce_banks_t all_banks;
1559 if (!mca_cfg.bootlog)
1563 * Log the machine checks left over from the previous reset.
1565 bitmap_fill(all_banks, MAX_NR_BANKS);
1566 machine_check_poll(MCP_UC | m_fl, &all_banks);
1568 cr4_set_bits(X86_CR4_MCE);
1570 rdmsrl(MSR_IA32_MCG_CAP, cap);
1571 if (cap & MCG_CTL_P)
1572 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1575 static void __mcheck_cpu_init_clear_banks(void)
1579 for (i = 0; i < mca_cfg.banks; i++) {
1580 struct mce_bank *b = &mce_banks[i];
1584 wrmsrl(msr_ops.ctl(i), b->ctl);
1585 wrmsrl(msr_ops.status(i), 0);
1590 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1591 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1592 * Vol 3B Table 15-20). But this confuses both the code that determines
1593 * whether the machine check occurred in kernel or user mode, and also
1594 * the severity assessment code. Pretend that EIPV was set, and take the
1595 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1597 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1601 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1603 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1604 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1605 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1607 (MCI_STATUS_UC|MCI_STATUS_EN|
1608 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1609 MCI_STATUS_AR|MCACOD_INSTR))
1612 m->mcgstatus |= MCG_STATUS_EIPV;
1617 /* Add per CPU specific workarounds here */
1618 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1620 struct mca_config *cfg = &mca_cfg;
1622 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1623 pr_info("unknown CPU type - not enabling MCE support\n");
1627 /* This should be disabled by the BIOS, but isn't always */
1628 if (c->x86_vendor == X86_VENDOR_AMD) {
1629 if (c->x86 == 15 && cfg->banks > 4) {
1631 * disable GART TBL walk error reporting, which
1632 * trips off incorrectly with the IOMMU & 3ware
1635 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1637 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1639 * Lots of broken BIOS around that don't clear them
1640 * by default and leave crap in there. Don't log:
1645 * Various K7s with broken bank 0 around. Always disable
1648 if (c->x86 == 6 && cfg->banks > 0)
1649 mce_banks[0].ctl = 0;
1652 * overflow_recov is supported for F15h Models 00h-0fh
1653 * even though we don't have a CPUID bit for it.
1655 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1656 mce_flags.overflow_recov = 1;
1660 if (c->x86_vendor == X86_VENDOR_INTEL) {
1662 * SDM documents that on family 6 bank 0 should not be written
1663 * because it aliases to another special BIOS controlled
1665 * But it's not aliased anymore on model 0x1a+
1666 * Don't ignore bank 0 completely because there could be a
1667 * valid event later, merely don't write CTL0.
1670 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1671 mce_banks[0].init = 0;
1674 * All newer Intel systems support MCE broadcasting. Enable
1675 * synchronization with a one second timeout.
1677 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1678 cfg->monarch_timeout < 0)
1679 cfg->monarch_timeout = USEC_PER_SEC;
1682 * There are also broken BIOSes on some Pentium M and
1685 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1688 if (c->x86 == 6 && c->x86_model == 45)
1689 quirk_no_way_out = quirk_sandybridge_ifu;
1691 if (cfg->monarch_timeout < 0)
1692 cfg->monarch_timeout = 0;
1693 if (cfg->bootlog != 0)
1694 cfg->panic_timeout = 30;
1699 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1704 switch (c->x86_vendor) {
1705 case X86_VENDOR_INTEL:
1706 intel_p5_mcheck_init(c);
1709 case X86_VENDOR_CENTAUR:
1710 winchip_mcheck_init(c);
1721 * Init basic CPU features needed for early decoding of MCEs.
1723 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1725 if (c->x86_vendor == X86_VENDOR_AMD) {
1726 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1727 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1728 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1730 if (mce_flags.smca) {
1731 msr_ops.ctl = smca_ctl_reg;
1732 msr_ops.status = smca_status_reg;
1733 msr_ops.addr = smca_addr_reg;
1734 msr_ops.misc = smca_misc_reg;
1739 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1741 struct mca_config *cfg = &mca_cfg;
1744 * All newer Centaur CPUs support MCE broadcasting. Enable
1745 * synchronization with a one second timeout.
1747 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1749 if (cfg->monarch_timeout < 0)
1750 cfg->monarch_timeout = USEC_PER_SEC;
1754 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1756 switch (c->x86_vendor) {
1757 case X86_VENDOR_INTEL:
1758 mce_intel_feature_init(c);
1759 mce_adjust_timer = cmci_intel_adjust_timer;
1762 case X86_VENDOR_AMD: {
1763 mce_amd_feature_init(c);
1766 case X86_VENDOR_CENTAUR:
1767 mce_centaur_feature_init(c);
1775 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1777 switch (c->x86_vendor) {
1778 case X86_VENDOR_INTEL:
1779 mce_intel_feature_clear(c);
1786 static void mce_start_timer(struct timer_list *t)
1788 unsigned long iv = check_interval * HZ;
1790 if (mca_cfg.ignore_ce || !iv)
1793 this_cpu_write(mce_next_interval, iv);
1794 __start_timer(t, iv);
1797 static void __mcheck_cpu_setup_timer(void)
1799 struct timer_list *t = this_cpu_ptr(&mce_timer);
1801 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1804 static void __mcheck_cpu_init_timer(void)
1806 struct timer_list *t = this_cpu_ptr(&mce_timer);
1808 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1812 /* Handle unconfigured int18 (should never happen) */
1813 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1815 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1816 smp_processor_id());
1819 /* Call the installed machine check handler for this CPU setup. */
1820 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1821 unexpected_machine_check;
1823 dotraplinkage void do_mce(struct pt_regs *regs, long error_code)
1825 machine_check_vector(regs, error_code);
1829 * Called for each booted CPU to set up machine checks.
1830 * Must be called with preempt off:
1832 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1834 if (mca_cfg.disabled)
1837 if (__mcheck_cpu_ancient_init(c))
1840 if (!mce_available(c))
1843 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1844 mca_cfg.disabled = 1;
1848 if (mce_gen_pool_init()) {
1849 mca_cfg.disabled = 1;
1850 pr_emerg("Couldn't allocate MCE records pool!\n");
1854 machine_check_vector = do_machine_check;
1856 __mcheck_cpu_init_early(c);
1857 __mcheck_cpu_init_generic();
1858 __mcheck_cpu_init_vendor(c);
1859 __mcheck_cpu_init_clear_banks();
1860 __mcheck_cpu_setup_timer();
1864 * Called for each booted CPU to clear some machine checks opt-ins
1866 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1868 if (mca_cfg.disabled)
1871 if (!mce_available(c))
1875 * Possibly to clear general settings generic to x86
1876 * __mcheck_cpu_clear_generic(c);
1878 __mcheck_cpu_clear_vendor(c);
1882 static void __mce_disable_bank(void *arg)
1884 int bank = *((int *)arg);
1885 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1886 cmci_disable_bank(bank);
1889 void mce_disable_bank(int bank)
1891 if (bank >= mca_cfg.banks) {
1893 "Ignoring request to disable invalid MCA bank %d.\n",
1897 set_bit(bank, mce_banks_ce_disabled);
1898 on_each_cpu(__mce_disable_bank, &bank, 1);
1902 * mce=off Disables machine check
1903 * mce=no_cmci Disables CMCI
1904 * mce=no_lmce Disables LMCE
1905 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1906 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1907 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1908 * monarchtimeout is how long to wait for other CPUs on machine
1909 * check, or 0 to not wait
1910 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
1912 * mce=nobootlog Don't log MCEs from before booting.
1913 * mce=bios_cmci_threshold Don't program the CMCI threshold
1914 * mce=recovery force enable memcpy_mcsafe()
1916 static int __init mcheck_enable(char *str)
1918 struct mca_config *cfg = &mca_cfg;
1926 if (!strcmp(str, "off"))
1928 else if (!strcmp(str, "no_cmci"))
1929 cfg->cmci_disabled = true;
1930 else if (!strcmp(str, "no_lmce"))
1931 cfg->lmce_disabled = 1;
1932 else if (!strcmp(str, "dont_log_ce"))
1933 cfg->dont_log_ce = true;
1934 else if (!strcmp(str, "ignore_ce"))
1935 cfg->ignore_ce = true;
1936 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1937 cfg->bootlog = (str[0] == 'b');
1938 else if (!strcmp(str, "bios_cmci_threshold"))
1939 cfg->bios_cmci_threshold = 1;
1940 else if (!strcmp(str, "recovery"))
1942 else if (isdigit(str[0])) {
1943 if (get_option(&str, &cfg->tolerant) == 2)
1944 get_option(&str, &(cfg->monarch_timeout));
1946 pr_info("mce argument %s ignored. Please use /sys\n", str);
1951 __setup("mce", mcheck_enable);
1953 int __init mcheck_init(void)
1955 mcheck_intel_therm_init();
1956 mce_register_decode_chain(&first_nb);
1957 mce_register_decode_chain(&mce_srao_nb);
1958 mce_register_decode_chain(&mce_default_nb);
1959 mcheck_vendor_init_severity();
1961 INIT_WORK(&mce_work, mce_gen_pool_process);
1962 init_irq_work(&mce_irq_work, mce_irq_work_cb);
1968 * mce_syscore: PM support
1972 * Disable machine checks on suspend and shutdown. We can't really handle
1975 static void mce_disable_error_reporting(void)
1979 for (i = 0; i < mca_cfg.banks; i++) {
1980 struct mce_bank *b = &mce_banks[i];
1983 wrmsrl(msr_ops.ctl(i), 0);
1988 static void vendor_disable_error_reporting(void)
1991 * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
1992 * Disabling them for just a single offlined CPU is bad, since it will
1993 * inhibit reporting for all shared resources on the socket like the
1994 * last level cache (LLC), the integrated memory controller (iMC), etc.
1996 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
1997 boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
2000 mce_disable_error_reporting();
2003 static int mce_syscore_suspend(void)
2005 vendor_disable_error_reporting();
2009 static void mce_syscore_shutdown(void)
2011 vendor_disable_error_reporting();
2015 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2016 * Only one CPU is active at this time, the others get re-added later using
2019 static void mce_syscore_resume(void)
2021 __mcheck_cpu_init_generic();
2022 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2023 __mcheck_cpu_init_clear_banks();
2026 static struct syscore_ops mce_syscore_ops = {
2027 .suspend = mce_syscore_suspend,
2028 .shutdown = mce_syscore_shutdown,
2029 .resume = mce_syscore_resume,
2033 * mce_device: Sysfs support
2036 static void mce_cpu_restart(void *data)
2038 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2040 __mcheck_cpu_init_generic();
2041 __mcheck_cpu_init_clear_banks();
2042 __mcheck_cpu_init_timer();
2045 /* Reinit MCEs after user configuration changes */
2046 static void mce_restart(void)
2048 mce_timer_delete_all();
2049 on_each_cpu(mce_cpu_restart, NULL, 1);
2052 /* Toggle features for corrected errors */
2053 static void mce_disable_cmci(void *data)
2055 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2060 static void mce_enable_ce(void *all)
2062 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2067 __mcheck_cpu_init_timer();
2070 static struct bus_type mce_subsys = {
2071 .name = "machinecheck",
2072 .dev_name = "machinecheck",
2075 DEFINE_PER_CPU(struct device *, mce_device);
2077 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2079 return container_of(attr, struct mce_bank, attr);
2082 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2085 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2088 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2089 const char *buf, size_t size)
2093 if (kstrtou64(buf, 0, &new) < 0)
2096 attr_to_bank(attr)->ctl = new;
2102 static ssize_t set_ignore_ce(struct device *s,
2103 struct device_attribute *attr,
2104 const char *buf, size_t size)
2108 if (kstrtou64(buf, 0, &new) < 0)
2111 mutex_lock(&mce_sysfs_mutex);
2112 if (mca_cfg.ignore_ce ^ !!new) {
2114 /* disable ce features */
2115 mce_timer_delete_all();
2116 on_each_cpu(mce_disable_cmci, NULL, 1);
2117 mca_cfg.ignore_ce = true;
2119 /* enable ce features */
2120 mca_cfg.ignore_ce = false;
2121 on_each_cpu(mce_enable_ce, (void *)1, 1);
2124 mutex_unlock(&mce_sysfs_mutex);
2129 static ssize_t set_cmci_disabled(struct device *s,
2130 struct device_attribute *attr,
2131 const char *buf, size_t size)
2135 if (kstrtou64(buf, 0, &new) < 0)
2138 mutex_lock(&mce_sysfs_mutex);
2139 if (mca_cfg.cmci_disabled ^ !!new) {
2142 on_each_cpu(mce_disable_cmci, NULL, 1);
2143 mca_cfg.cmci_disabled = true;
2146 mca_cfg.cmci_disabled = false;
2147 on_each_cpu(mce_enable_ce, NULL, 1);
2150 mutex_unlock(&mce_sysfs_mutex);
2155 static ssize_t store_int_with_restart(struct device *s,
2156 struct device_attribute *attr,
2157 const char *buf, size_t size)
2159 unsigned long old_check_interval = check_interval;
2160 ssize_t ret = device_store_ulong(s, attr, buf, size);
2162 if (check_interval == old_check_interval)
2165 mutex_lock(&mce_sysfs_mutex);
2167 mutex_unlock(&mce_sysfs_mutex);
2172 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2173 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2174 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2176 static struct dev_ext_attribute dev_attr_check_interval = {
2177 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2181 static struct dev_ext_attribute dev_attr_ignore_ce = {
2182 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2186 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2187 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2188 &mca_cfg.cmci_disabled
2191 static struct device_attribute *mce_device_attrs[] = {
2192 &dev_attr_tolerant.attr,
2193 &dev_attr_check_interval.attr,
2194 #ifdef CONFIG_X86_MCELOG_LEGACY
2197 &dev_attr_monarch_timeout.attr,
2198 &dev_attr_dont_log_ce.attr,
2199 &dev_attr_ignore_ce.attr,
2200 &dev_attr_cmci_disabled.attr,
2204 static cpumask_var_t mce_device_initialized;
2206 static void mce_device_release(struct device *dev)
2211 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2212 static int mce_device_create(unsigned int cpu)
2218 if (!mce_available(&boot_cpu_data))
2221 dev = per_cpu(mce_device, cpu);
2225 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2229 dev->bus = &mce_subsys;
2230 dev->release = &mce_device_release;
2232 err = device_register(dev);
2238 for (i = 0; mce_device_attrs[i]; i++) {
2239 err = device_create_file(dev, mce_device_attrs[i]);
2243 for (j = 0; j < mca_cfg.banks; j++) {
2244 err = device_create_file(dev, &mce_banks[j].attr);
2248 cpumask_set_cpu(cpu, mce_device_initialized);
2249 per_cpu(mce_device, cpu) = dev;
2254 device_remove_file(dev, &mce_banks[j].attr);
2257 device_remove_file(dev, mce_device_attrs[i]);
2259 device_unregister(dev);
2264 static void mce_device_remove(unsigned int cpu)
2266 struct device *dev = per_cpu(mce_device, cpu);
2269 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2272 for (i = 0; mce_device_attrs[i]; i++)
2273 device_remove_file(dev, mce_device_attrs[i]);
2275 for (i = 0; i < mca_cfg.banks; i++)
2276 device_remove_file(dev, &mce_banks[i].attr);
2278 device_unregister(dev);
2279 cpumask_clear_cpu(cpu, mce_device_initialized);
2280 per_cpu(mce_device, cpu) = NULL;
2283 /* Make sure there are no machine checks on offlined CPUs. */
2284 static void mce_disable_cpu(void)
2286 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2289 if (!cpuhp_tasks_frozen)
2292 vendor_disable_error_reporting();
2295 static void mce_reenable_cpu(void)
2299 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2302 if (!cpuhp_tasks_frozen)
2304 for (i = 0; i < mca_cfg.banks; i++) {
2305 struct mce_bank *b = &mce_banks[i];
2308 wrmsrl(msr_ops.ctl(i), b->ctl);
2312 static int mce_cpu_dead(unsigned int cpu)
2314 mce_intel_hcpu_update(cpu);
2316 /* intentionally ignoring frozen here */
2317 if (!cpuhp_tasks_frozen)
2322 static int mce_cpu_online(unsigned int cpu)
2324 struct timer_list *t = this_cpu_ptr(&mce_timer);
2327 mce_device_create(cpu);
2329 ret = mce_threshold_create_device(cpu);
2331 mce_device_remove(cpu);
2339 static int mce_cpu_pre_down(unsigned int cpu)
2341 struct timer_list *t = this_cpu_ptr(&mce_timer);
2345 mce_threshold_remove_device(cpu);
2346 mce_device_remove(cpu);
2350 static __init void mce_init_banks(void)
2354 for (i = 0; i < mca_cfg.banks; i++) {
2355 struct mce_bank *b = &mce_banks[i];
2356 struct device_attribute *a = &b->attr;
2358 sysfs_attr_init(&a->attr);
2359 a->attr.name = b->attrname;
2360 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2362 a->attr.mode = 0644;
2363 a->show = show_bank;
2364 a->store = set_bank;
2368 static __init int mcheck_init_device(void)
2373 * Check if we have a spare virtual bit. This will only become
2374 * a problem if/when we move beyond 5-level page tables.
2376 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2378 if (!mce_available(&boot_cpu_data)) {
2383 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2390 err = subsys_system_register(&mce_subsys, NULL);
2394 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2399 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2400 mce_cpu_online, mce_cpu_pre_down);
2402 goto err_out_online;
2404 register_syscore_ops(&mce_syscore_ops);
2409 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2412 free_cpumask_var(mce_device_initialized);
2415 pr_err("Unable to init MCE device (rc: %d)\n", err);
2419 device_initcall_sync(mcheck_init_device);
2422 * Old style boot options parsing. Only for compatibility.
2424 static int __init mcheck_disable(char *str)
2426 mca_cfg.disabled = 1;
2429 __setup("nomce", mcheck_disable);
2431 #ifdef CONFIG_DEBUG_FS
2432 struct dentry *mce_get_debugfs_dir(void)
2434 static struct dentry *dmce;
2437 dmce = debugfs_create_dir("mce", NULL);
2442 static void mce_reset(void)
2445 atomic_set(&mce_fake_panicked, 0);
2446 atomic_set(&mce_executing, 0);
2447 atomic_set(&mce_callin, 0);
2448 atomic_set(&global_nwo, 0);
2451 static int fake_panic_get(void *data, u64 *val)
2457 static int fake_panic_set(void *data, u64 val)
2464 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2465 fake_panic_set, "%llu\n");
2467 static int __init mcheck_debugfs_init(void)
2469 struct dentry *dmce, *ffake_panic;
2471 dmce = mce_get_debugfs_dir();
2474 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2482 static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2485 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2486 EXPORT_SYMBOL_GPL(mcsafe_key);
2488 static int __init mcheck_late_init(void)
2490 pr_info("Using %d MCE banks\n", mca_cfg.banks);
2492 if (mca_cfg.recovery)
2493 static_branch_inc(&mcsafe_key);
2495 mcheck_debugfs_init();
2499 * Flush out everything that has been logged during early boot, now that
2500 * everything has been initialized (workqueues, decoders, ...).
2502 mce_schedule_work();
2506 late_initcall(mcheck_late_init);