arch/x86/kernel/cpu/perf_event_intel.c

   1 /*
   2  * Per core/cpu state
   3  *
   4  * Used to coordinate shared registers between HT threads or
   5  * among events on a single PMU.
   6  */
   7
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/stddef.h>
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/export.h>
  15 #include <linux/nmi.h>
  16
  17 #include <asm/cpufeature.h>
  18 #include <asm/hardirq.h>
  19 #include <asm/apic.h>
  20
  21 #include "perf_event.h"
  22
  23 /*
  24  * Intel PerfMon, used on Core and later.
  25  */
  26 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  27 {
  28         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  29         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  30         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  31         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  32         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  33         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  34         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  35         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  36 };
  37
  38 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  39 {
  40         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  41         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  42         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  43         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  44         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  45         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  46         EVENT_CONSTRAINT_END
  47 };
  48
  49 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  50 {
  51         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  52         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  53         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  54         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  55         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  56         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  57         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  58         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  59         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  60         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  61         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  62         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  63         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  64         EVENT_CONSTRAINT_END
  65 };
  66
  67 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  68 {
  69         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  70         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  71         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  72         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  73         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  74         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  75         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  76         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  77         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  78         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  79         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  80         EVENT_CONSTRAINT_END
  81 };
  82
  83 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  84 {
  85         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
  86         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  87         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  88         EVENT_EXTRA_END
  89 };
  90
  91 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  92 {
  93         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  94         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  95         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  96         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  97         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  98         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  99         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
 100         EVENT_CONSTRAINT_END
 101 };
 102
 103 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 104 {
 105         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 106         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 107         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 108         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 109         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 110         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 111         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 112         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 113         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 114         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 115         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 116         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 117
 118         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 119         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 120         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 121         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 122
 123         EVENT_CONSTRAINT_END
 124 };
 125
 126 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 127 {
 128         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 129         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 130         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 131         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 132         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
 133         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 134         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
 135         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 136         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 137         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 138         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 139         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 140         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 141
 142         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 143         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 144         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 145         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 146
 147         EVENT_CONSTRAINT_END
 148 };
 149
 150 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 151 {
 152         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 153         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 154         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 155         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 156         EVENT_EXTRA_END
 157 };
 158
 159 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 160 {
 161         EVENT_CONSTRAINT_END
 162 };
 163
 164 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 165 {
 166         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 167         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 168         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 169         EVENT_CONSTRAINT_END
 170 };
 171
 172 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 173 {
 174         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 175         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 176         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
 177         EVENT_CONSTRAINT_END
 178 };
 179
 180 struct event_constraint intel_skl_event_constraints[] = {
 181         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 182         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 183         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 184         INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2),    /* INST_RETIRED.PREC_DIST */
 185         EVENT_CONSTRAINT_END
 186 };
 187
 188 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 189         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 190         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 191         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 192         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 193         EVENT_EXTRA_END
 194 };
 195
 196 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 197         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 198         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 199         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 200         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 201         EVENT_EXTRA_END
 202 };
 203
 204 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
 205         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 206         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 207         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 208         /*
 209          * Note the low 8 bits eventsel code is not a continuous field, containing
 210          * some #GPing bits. These are masked out.
 211          */
 212         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 213         EVENT_EXTRA_END
 214 };
 215
 216 EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
 217 EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
 218 EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 219
 220 struct attribute *nhm_events_attrs[] = {
 221         EVENT_PTR(mem_ld_nhm),
 222         NULL,
 223 };
 224
 225 struct attribute *snb_events_attrs[] = {
 226         EVENT_PTR(mem_ld_snb),
 227         EVENT_PTR(mem_st_snb),
 228         NULL,
 229 };
 230
 231 static struct event_constraint intel_hsw_event_constraints[] = {
 232         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 233         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 234         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 235         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 236         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 237         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 238         /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 239         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
 240         /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 241         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
 242         /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 243         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
 244
 245         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 246         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 247         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 248         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 249
 250         EVENT_CONSTRAINT_END
 251 };
 252
 253 struct event_constraint intel_bdw_event_constraints[] = {
 254         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 255         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 256         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 257         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 258         INTEL_UEVENT_CONSTRAINT(0x8a3, 0x4),    /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
 259         EVENT_CONSTRAINT_END
 260 };
 261
 262 static u64 intel_pmu_event_map(int hw_event)
 263 {
 264         return intel_perfmon_event_map[hw_event];
 265 }
 266
 267 /*
 268  * Notes on the events:
 269  * - data reads do not include code reads (comparable to earlier tables)
 270  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 271  * - remote node access includes remote memory, remote cache, remote mmio.
 272  * - prefetches are not included in the counts.
 273  * - icache miss does not include decoded icache
 274  */
 275
 276 #define SKL_DEMAND_DATA_RD              BIT_ULL(0)
 277 #define SKL_DEMAND_RFO                  BIT_ULL(1)
 278 #define SKL_ANY_RESPONSE                BIT_ULL(16)
 279 #define SKL_SUPPLIER_NONE               BIT_ULL(17)
 280 #define SKL_L3_MISS_LOCAL_DRAM          BIT_ULL(26)
 281 #define SKL_L3_MISS_REMOTE_HOP0_DRAM    BIT_ULL(27)
 282 #define SKL_L3_MISS_REMOTE_HOP1_DRAM    BIT_ULL(28)
 283 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM   BIT_ULL(29)
 284 #define SKL_L3_MISS                     (SKL_L3_MISS_LOCAL_DRAM| \
 285                                          SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 286                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 287                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 288 #define SKL_SPL_HIT                     BIT_ULL(30)
 289 #define SKL_SNOOP_NONE                  BIT_ULL(31)
 290 #define SKL_SNOOP_NOT_NEEDED            BIT_ULL(32)
 291 #define SKL_SNOOP_MISS                  BIT_ULL(33)
 292 #define SKL_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 293 #define SKL_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 294 #define SKL_SNOOP_HITM                  BIT_ULL(36)
 295 #define SKL_SNOOP_NON_DRAM              BIT_ULL(37)
 296 #define SKL_ANY_SNOOP                   (SKL_SPL_HIT|SKL_SNOOP_NONE| \
 297                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 298                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 299                                          SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
 300 #define SKL_DEMAND_READ                 SKL_DEMAND_DATA_RD
 301 #define SKL_SNOOP_DRAM                  (SKL_SNOOP_NONE| \
 302                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 303                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 304                                          SKL_SNOOP_HITM|SKL_SPL_HIT)
 305 #define SKL_DEMAND_WRITE                SKL_DEMAND_RFO
 306 #define SKL_LLC_ACCESS                  SKL_ANY_RESPONSE
 307 #define SKL_L3_MISS_REMOTE              (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 308                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 309                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 310
 311 static __initconst const u64 skl_hw_cache_event_ids
 312                                 [PERF_COUNT_HW_CACHE_MAX]
 313                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 314                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 315 {
 316  [ C(L1D ) ] = {
 317         [ C(OP_READ) ] = {
 318                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 319                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 320         },
 321         [ C(OP_WRITE) ] = {
 322                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 323                 [ C(RESULT_MISS)   ] = 0x0,
 324         },
 325         [ C(OP_PREFETCH) ] = {
 326                 [ C(RESULT_ACCESS) ] = 0x0,
 327                 [ C(RESULT_MISS)   ] = 0x0,
 328         },
 329  },
 330  [ C(L1I ) ] = {
 331         [ C(OP_READ) ] = {
 332                 [ C(RESULT_ACCESS) ] = 0x0,
 333                 [ C(RESULT_MISS)   ] = 0x283,   /* ICACHE_64B.MISS */
 334         },
 335         [ C(OP_WRITE) ] = {
 336                 [ C(RESULT_ACCESS) ] = -1,
 337                 [ C(RESULT_MISS)   ] = -1,
 338         },
 339         [ C(OP_PREFETCH) ] = {
 340                 [ C(RESULT_ACCESS) ] = 0x0,
 341                 [ C(RESULT_MISS)   ] = 0x0,
 342         },
 343  },
 344  [ C(LL  ) ] = {
 345         [ C(OP_READ) ] = {
 346                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 347                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 348         },
 349         [ C(OP_WRITE) ] = {
 350                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 351                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 352         },
 353         [ C(OP_PREFETCH) ] = {
 354                 [ C(RESULT_ACCESS) ] = 0x0,
 355                 [ C(RESULT_MISS)   ] = 0x0,
 356         },
 357  },
 358  [ C(DTLB) ] = {
 359         [ C(OP_READ) ] = {
 360                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 361                 [ C(RESULT_MISS)   ] = 0x608,   /* DTLB_LOAD_MISSES.WALK_COMPLETED */
 362         },
 363         [ C(OP_WRITE) ] = {
 364                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 365                 [ C(RESULT_MISS)   ] = 0x649,   /* DTLB_STORE_MISSES.WALK_COMPLETED */
 366         },
 367         [ C(OP_PREFETCH) ] = {
 368                 [ C(RESULT_ACCESS) ] = 0x0,
 369                 [ C(RESULT_MISS)   ] = 0x0,
 370         },
 371  },
 372  [ C(ITLB) ] = {
 373         [ C(OP_READ) ] = {
 374                 [ C(RESULT_ACCESS) ] = 0x2085,  /* ITLB_MISSES.STLB_HIT */
 375                 [ C(RESULT_MISS)   ] = 0xe85,   /* ITLB_MISSES.WALK_COMPLETED */
 376         },
 377         [ C(OP_WRITE) ] = {
 378                 [ C(RESULT_ACCESS) ] = -1,
 379                 [ C(RESULT_MISS)   ] = -1,
 380         },
 381         [ C(OP_PREFETCH) ] = {
 382                 [ C(RESULT_ACCESS) ] = -1,
 383                 [ C(RESULT_MISS)   ] = -1,
 384         },
 385  },
 386  [ C(BPU ) ] = {
 387         [ C(OP_READ) ] = {
 388                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 389                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 390         },
 391         [ C(OP_WRITE) ] = {
 392                 [ C(RESULT_ACCESS) ] = -1,
 393                 [ C(RESULT_MISS)   ] = -1,
 394         },
 395         [ C(OP_PREFETCH) ] = {
 396                 [ C(RESULT_ACCESS) ] = -1,
 397                 [ C(RESULT_MISS)   ] = -1,
 398         },
 399  },
 400  [ C(NODE) ] = {
 401         [ C(OP_READ) ] = {
 402                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 403                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 404         },
 405         [ C(OP_WRITE) ] = {
 406                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 407                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 408         },
 409         [ C(OP_PREFETCH) ] = {
 410                 [ C(RESULT_ACCESS) ] = 0x0,
 411                 [ C(RESULT_MISS)   ] = 0x0,
 412         },
 413  },
 414 };
 415
 416 static __initconst const u64 skl_hw_cache_extra_regs
 417                                 [PERF_COUNT_HW_CACHE_MAX]
 418                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 419                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 420 {
 421  [ C(LL  ) ] = {
 422         [ C(OP_READ) ] = {
 423                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 424                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 425                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 426                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 427                                        SKL_SUPPLIER_NONE,
 428         },
 429         [ C(OP_WRITE) ] = {
 430                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 431                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 432                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 433                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 434                                        SKL_SUPPLIER_NONE,
 435         },
 436         [ C(OP_PREFETCH) ] = {
 437                 [ C(RESULT_ACCESS) ] = 0x0,
 438                 [ C(RESULT_MISS)   ] = 0x0,
 439         },
 440  },
 441  [ C(NODE) ] = {
 442         [ C(OP_READ) ] = {
 443                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 444                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 445                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 446                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 447         },
 448         [ C(OP_WRITE) ] = {
 449                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 450                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 451                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 452                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 453         },
 454         [ C(OP_PREFETCH) ] = {
 455                 [ C(RESULT_ACCESS) ] = 0x0,
 456                 [ C(RESULT_MISS)   ] = 0x0,
 457         },
 458  },
 459 };
 460
 461 #define SNB_DMND_DATA_RD        (1ULL << 0)
 462 #define SNB_DMND_RFO            (1ULL << 1)
 463 #define SNB_DMND_IFETCH         (1ULL << 2)
 464 #define SNB_DMND_WB             (1ULL << 3)
 465 #define SNB_PF_DATA_RD          (1ULL << 4)
 466 #define SNB_PF_RFO              (1ULL << 5)
 467 #define SNB_PF_IFETCH           (1ULL << 6)
 468 #define SNB_LLC_DATA_RD         (1ULL << 7)
 469 #define SNB_LLC_RFO             (1ULL << 8)
 470 #define SNB_LLC_IFETCH          (1ULL << 9)
 471 #define SNB_BUS_LOCKS           (1ULL << 10)
 472 #define SNB_STRM_ST             (1ULL << 11)
 473 #define SNB_OTHER               (1ULL << 15)
 474 #define SNB_RESP_ANY            (1ULL << 16)
 475 #define SNB_NO_SUPP             (1ULL << 17)
 476 #define SNB_LLC_HITM            (1ULL << 18)
 477 #define SNB_LLC_HITE            (1ULL << 19)
 478 #define SNB_LLC_HITS            (1ULL << 20)
 479 #define SNB_LLC_HITF            (1ULL << 21)
 480 #define SNB_LOCAL               (1ULL << 22)
 481 #define SNB_REMOTE              (0xffULL << 23)
 482 #define SNB_SNP_NONE            (1ULL << 31)
 483 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 484 #define SNB_SNP_MISS            (1ULL << 33)
 485 #define SNB_NO_FWD              (1ULL << 34)
 486 #define SNB_SNP_FWD             (1ULL << 35)
 487 #define SNB_HITM                (1ULL << 36)
 488 #define SNB_NON_DRAM            (1ULL << 37)
 489
 490 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 491 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 492 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 493
 494 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 495                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 496                                  SNB_HITM)
 497
 498 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 499 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 500
 501 #define SNB_L3_ACCESS           SNB_RESP_ANY
 502 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 503
 504 static __initconst const u64 snb_hw_cache_extra_regs
 505                                 [PERF_COUNT_HW_CACHE_MAX]
 506                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 507                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 508 {
 509  [ C(LL  ) ] = {
 510         [ C(OP_READ) ] = {
 511                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 512                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 513         },
 514         [ C(OP_WRITE) ] = {
 515                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 516                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 517         },
 518         [ C(OP_PREFETCH) ] = {
 519                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 520                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 521         },
 522  },
 523  [ C(NODE) ] = {
 524         [ C(OP_READ) ] = {
 525                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 526                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 527         },
 528         [ C(OP_WRITE) ] = {
 529                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 530                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 531         },
 532         [ C(OP_PREFETCH) ] = {
 533                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 534                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 535         },
 536  },
 537 };
 538
 539 static __initconst const u64 snb_hw_cache_event_ids
 540                                 [PERF_COUNT_HW_CACHE_MAX]
 541                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 542                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 543 {
 544  [ C(L1D) ] = {
 545         [ C(OP_READ) ] = {
 546                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 547                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 548         },
 549         [ C(OP_WRITE) ] = {
 550                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 551                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 552         },
 553         [ C(OP_PREFETCH) ] = {
 554                 [ C(RESULT_ACCESS) ] = 0x0,
 555                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 556         },
 557  },
 558  [ C(L1I ) ] = {
 559         [ C(OP_READ) ] = {
 560                 [ C(RESULT_ACCESS) ] = 0x0,
 561                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 562         },
 563         [ C(OP_WRITE) ] = {
 564                 [ C(RESULT_ACCESS) ] = -1,
 565                 [ C(RESULT_MISS)   ] = -1,
 566         },
 567         [ C(OP_PREFETCH) ] = {
 568                 [ C(RESULT_ACCESS) ] = 0x0,
 569                 [ C(RESULT_MISS)   ] = 0x0,
 570         },
 571  },
 572  [ C(LL  ) ] = {
 573         [ C(OP_READ) ] = {
 574                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 575                 [ C(RESULT_ACCESS) ] = 0x01b7,
 576                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 577                 [ C(RESULT_MISS)   ] = 0x01b7,
 578         },
 579         [ C(OP_WRITE) ] = {
 580                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 581                 [ C(RESULT_ACCESS) ] = 0x01b7,
 582                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 583                 [ C(RESULT_MISS)   ] = 0x01b7,
 584         },
 585         [ C(OP_PREFETCH) ] = {
 586                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 587                 [ C(RESULT_ACCESS) ] = 0x01b7,
 588                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 589                 [ C(RESULT_MISS)   ] = 0x01b7,
 590         },
 591  },
 592  [ C(DTLB) ] = {
 593         [ C(OP_READ) ] = {
 594                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 595                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 596         },
 597         [ C(OP_WRITE) ] = {
 598                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 599                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 600         },
 601         [ C(OP_PREFETCH) ] = {
 602                 [ C(RESULT_ACCESS) ] = 0x0,
 603                 [ C(RESULT_MISS)   ] = 0x0,
 604         },
 605  },
 606  [ C(ITLB) ] = {
 607         [ C(OP_READ) ] = {
 608                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 609                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 610         },
 611         [ C(OP_WRITE) ] = {
 612                 [ C(RESULT_ACCESS) ] = -1,
 613                 [ C(RESULT_MISS)   ] = -1,
 614         },
 615         [ C(OP_PREFETCH) ] = {
 616                 [ C(RESULT_ACCESS) ] = -1,
 617                 [ C(RESULT_MISS)   ] = -1,
 618         },
 619  },
 620  [ C(BPU ) ] = {
 621         [ C(OP_READ) ] = {
 622                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 623                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 624         },
 625         [ C(OP_WRITE) ] = {
 626                 [ C(RESULT_ACCESS) ] = -1,
 627                 [ C(RESULT_MISS)   ] = -1,
 628         },
 629         [ C(OP_PREFETCH) ] = {
 630                 [ C(RESULT_ACCESS) ] = -1,
 631                 [ C(RESULT_MISS)   ] = -1,
 632         },
 633  },
 634  [ C(NODE) ] = {
 635         [ C(OP_READ) ] = {
 636                 [ C(RESULT_ACCESS) ] = 0x01b7,
 637                 [ C(RESULT_MISS)   ] = 0x01b7,
 638         },
 639         [ C(OP_WRITE) ] = {
 640                 [ C(RESULT_ACCESS) ] = 0x01b7,
 641                 [ C(RESULT_MISS)   ] = 0x01b7,
 642         },
 643         [ C(OP_PREFETCH) ] = {
 644                 [ C(RESULT_ACCESS) ] = 0x01b7,
 645                 [ C(RESULT_MISS)   ] = 0x01b7,
 646         },
 647  },
 648
 649 };
 650
 651 /*
 652  * Notes on the events:
 653  * - data reads do not include code reads (comparable to earlier tables)
 654  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 655  * - remote node access includes remote memory, remote cache, remote mmio.
 656  * - prefetches are not included in the counts because they are not
 657  *   reliably counted.
 658  */
 659
 660 #define HSW_DEMAND_DATA_RD              BIT_ULL(0)
 661 #define HSW_DEMAND_RFO                  BIT_ULL(1)
 662 #define HSW_ANY_RESPONSE                BIT_ULL(16)
 663 #define HSW_SUPPLIER_NONE               BIT_ULL(17)
 664 #define HSW_L3_MISS_LOCAL_DRAM          BIT_ULL(22)
 665 #define HSW_L3_MISS_REMOTE_HOP0         BIT_ULL(27)
 666 #define HSW_L3_MISS_REMOTE_HOP1         BIT_ULL(28)
 667 #define HSW_L3_MISS_REMOTE_HOP2P        BIT_ULL(29)
 668 #define HSW_L3_MISS                     (HSW_L3_MISS_LOCAL_DRAM| \
 669                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 670                                          HSW_L3_MISS_REMOTE_HOP2P)
 671 #define HSW_SNOOP_NONE                  BIT_ULL(31)
 672 #define HSW_SNOOP_NOT_NEEDED            BIT_ULL(32)
 673 #define HSW_SNOOP_MISS                  BIT_ULL(33)
 674 #define HSW_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 675 #define HSW_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 676 #define HSW_SNOOP_HITM                  BIT_ULL(36)
 677 #define HSW_SNOOP_NON_DRAM              BIT_ULL(37)
 678 #define HSW_ANY_SNOOP                   (HSW_SNOOP_NONE| \
 679                                          HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
 680                                          HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
 681                                          HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
 682 #define HSW_SNOOP_DRAM                  (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
 683 #define HSW_DEMAND_READ                 HSW_DEMAND_DATA_RD
 684 #define HSW_DEMAND_WRITE                HSW_DEMAND_RFO
 685 #define HSW_L3_MISS_REMOTE              (HSW_L3_MISS_REMOTE_HOP0|\
 686                                          HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
 687 #define HSW_LLC_ACCESS                  HSW_ANY_RESPONSE
 688
 689 #define BDW_L3_MISS_LOCAL               BIT(26)
 690 #define BDW_L3_MISS                     (BDW_L3_MISS_LOCAL| \
 691                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 692                                          HSW_L3_MISS_REMOTE_HOP2P)
 693
 694
 695 static __initconst const u64 hsw_hw_cache_event_ids
 696                                 [PERF_COUNT_HW_CACHE_MAX]
 697                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 698                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 699 {
 700  [ C(L1D ) ] = {
 701         [ C(OP_READ) ] = {
 702                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 703                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 704         },
 705         [ C(OP_WRITE) ] = {
 706                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 707                 [ C(RESULT_MISS)   ] = 0x0,
 708         },
 709         [ C(OP_PREFETCH) ] = {
 710                 [ C(RESULT_ACCESS) ] = 0x0,
 711                 [ C(RESULT_MISS)   ] = 0x0,
 712         },
 713  },
 714  [ C(L1I ) ] = {
 715         [ C(OP_READ) ] = {
 716                 [ C(RESULT_ACCESS) ] = 0x0,
 717                 [ C(RESULT_MISS)   ] = 0x280,   /* ICACHE.MISSES */
 718         },
 719         [ C(OP_WRITE) ] = {
 720                 [ C(RESULT_ACCESS) ] = -1,
 721                 [ C(RESULT_MISS)   ] = -1,
 722         },
 723         [ C(OP_PREFETCH) ] = {
 724                 [ C(RESULT_ACCESS) ] = 0x0,
 725                 [ C(RESULT_MISS)   ] = 0x0,
 726         },
 727  },
 728  [ C(LL  ) ] = {
 729         [ C(OP_READ) ] = {
 730                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 731                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 732         },
 733         [ C(OP_WRITE) ] = {
 734                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 735                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 736         },
 737         [ C(OP_PREFETCH) ] = {
 738                 [ C(RESULT_ACCESS) ] = 0x0,
 739                 [ C(RESULT_MISS)   ] = 0x0,
 740         },
 741  },
 742  [ C(DTLB) ] = {
 743         [ C(OP_READ) ] = {
 744                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 745                 [ C(RESULT_MISS)   ] = 0x108,   /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
 746         },
 747         [ C(OP_WRITE) ] = {
 748                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 749                 [ C(RESULT_MISS)   ] = 0x149,   /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 750         },
 751         [ C(OP_PREFETCH) ] = {
 752                 [ C(RESULT_ACCESS) ] = 0x0,
 753                 [ C(RESULT_MISS)   ] = 0x0,
 754         },
 755  },
 756  [ C(ITLB) ] = {
 757         [ C(OP_READ) ] = {
 758                 [ C(RESULT_ACCESS) ] = 0x6085,  /* ITLB_MISSES.STLB_HIT */
 759                 [ C(RESULT_MISS)   ] = 0x185,   /* ITLB_MISSES.MISS_CAUSES_A_WALK */
 760         },
 761         [ C(OP_WRITE) ] = {
 762                 [ C(RESULT_ACCESS) ] = -1,
 763                 [ C(RESULT_MISS)   ] = -1,
 764         },
 765         [ C(OP_PREFETCH) ] = {
 766                 [ C(RESULT_ACCESS) ] = -1,
 767                 [ C(RESULT_MISS)   ] = -1,
 768         },
 769  },
 770  [ C(BPU ) ] = {
 771         [ C(OP_READ) ] = {
 772                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 773                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 774         },
 775         [ C(OP_WRITE) ] = {
 776                 [ C(RESULT_ACCESS) ] = -1,
 777                 [ C(RESULT_MISS)   ] = -1,
 778         },
 779         [ C(OP_PREFETCH) ] = {
 780                 [ C(RESULT_ACCESS) ] = -1,
 781                 [ C(RESULT_MISS)   ] = -1,
 782         },
 783  },
 784  [ C(NODE) ] = {
 785         [ C(OP_READ) ] = {
 786                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 787                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 788         },
 789         [ C(OP_WRITE) ] = {
 790                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 791                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 792         },
 793         [ C(OP_PREFETCH) ] = {
 794                 [ C(RESULT_ACCESS) ] = 0x0,
 795                 [ C(RESULT_MISS)   ] = 0x0,
 796         },
 797  },
 798 };
 799
 800 static __initconst const u64 hsw_hw_cache_extra_regs
 801                                 [PERF_COUNT_HW_CACHE_MAX]
 802                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 803                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 804 {
 805  [ C(LL  ) ] = {
 806         [ C(OP_READ) ] = {
 807                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
 808                                        HSW_LLC_ACCESS,
 809                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
 810                                        HSW_L3_MISS|HSW_ANY_SNOOP,
 811         },
 812         [ C(OP_WRITE) ] = {
 813                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
 814                                        HSW_LLC_ACCESS,
 815                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
 816                                        HSW_L3_MISS|HSW_ANY_SNOOP,
 817         },
 818         [ C(OP_PREFETCH) ] = {
 819                 [ C(RESULT_ACCESS) ] = 0x0,
 820                 [ C(RESULT_MISS)   ] = 0x0,
 821         },
 822  },
 823  [ C(NODE) ] = {
 824         [ C(OP_READ) ] = {
 825                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
 826                                        HSW_L3_MISS_LOCAL_DRAM|
 827                                        HSW_SNOOP_DRAM,
 828                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
 829                                        HSW_L3_MISS_REMOTE|
 830                                        HSW_SNOOP_DRAM,
 831         },
 832         [ C(OP_WRITE) ] = {
 833                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
 834                                        HSW_L3_MISS_LOCAL_DRAM|
 835                                        HSW_SNOOP_DRAM,
 836                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
 837                                        HSW_L3_MISS_REMOTE|
 838                                        HSW_SNOOP_DRAM,
 839         },
 840         [ C(OP_PREFETCH) ] = {
 841                 [ C(RESULT_ACCESS) ] = 0x0,
 842                 [ C(RESULT_MISS)   ] = 0x0,
 843         },
 844  },
 845 };
 846
 847 static __initconst const u64 westmere_hw_cache_event_ids
 848                                 [PERF_COUNT_HW_CACHE_MAX]
 849                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 850                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 851 {
 852  [ C(L1D) ] = {
 853         [ C(OP_READ) ] = {
 854                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 855                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 856         },
 857         [ C(OP_WRITE) ] = {
 858                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 859                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 860         },
 861         [ C(OP_PREFETCH) ] = {
 862                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 863                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 864         },
 865  },
 866  [ C(L1I ) ] = {
 867         [ C(OP_READ) ] = {
 868                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 869                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 870         },
 871         [ C(OP_WRITE) ] = {
 872                 [ C(RESULT_ACCESS) ] = -1,
 873                 [ C(RESULT_MISS)   ] = -1,
 874         },
 875         [ C(OP_PREFETCH) ] = {
 876                 [ C(RESULT_ACCESS) ] = 0x0,
 877                 [ C(RESULT_MISS)   ] = 0x0,
 878         },
 879  },
 880  [ C(LL  ) ] = {
 881         [ C(OP_READ) ] = {
 882                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 883                 [ C(RESULT_ACCESS) ] = 0x01b7,
 884                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 885                 [ C(RESULT_MISS)   ] = 0x01b7,
 886         },
 887         /*
 888          * Use RFO, not WRITEBACK, because a write miss would typically occur
 889          * on RFO.
 890          */
 891         [ C(OP_WRITE) ] = {
 892                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 893                 [ C(RESULT_ACCESS) ] = 0x01b7,
 894                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 895                 [ C(RESULT_MISS)   ] = 0x01b7,
 896         },
 897         [ C(OP_PREFETCH) ] = {
 898                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 899                 [ C(RESULT_ACCESS) ] = 0x01b7,
 900                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 901                 [ C(RESULT_MISS)   ] = 0x01b7,
 902         },
 903  },
 904  [ C(DTLB) ] = {
 905         [ C(OP_READ) ] = {
 906                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 907                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 908         },
 909         [ C(OP_WRITE) ] = {
 910                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 911                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 912         },
 913         [ C(OP_PREFETCH) ] = {
 914                 [ C(RESULT_ACCESS) ] = 0x0,
 915                 [ C(RESULT_MISS)   ] = 0x0,
 916         },
 917  },
 918  [ C(ITLB) ] = {
 919         [ C(OP_READ) ] = {
 920                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 921                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
 922         },
 923         [ C(OP_WRITE) ] = {
 924                 [ C(RESULT_ACCESS) ] = -1,
 925                 [ C(RESULT_MISS)   ] = -1,
 926         },
 927         [ C(OP_PREFETCH) ] = {
 928                 [ C(RESULT_ACCESS) ] = -1,
 929                 [ C(RESULT_MISS)   ] = -1,
 930         },
 931  },
 932  [ C(BPU ) ] = {
 933         [ C(OP_READ) ] = {
 934                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 935                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 936         },
 937         [ C(OP_WRITE) ] = {
 938                 [ C(RESULT_ACCESS) ] = -1,
 939                 [ C(RESULT_MISS)   ] = -1,
 940         },
 941         [ C(OP_PREFETCH) ] = {
 942                 [ C(RESULT_ACCESS) ] = -1,
 943                 [ C(RESULT_MISS)   ] = -1,
 944         },
 945  },
 946  [ C(NODE) ] = {
 947         [ C(OP_READ) ] = {
 948                 [ C(RESULT_ACCESS) ] = 0x01b7,
 949                 [ C(RESULT_MISS)   ] = 0x01b7,
 950         },
 951         [ C(OP_WRITE) ] = {
 952                 [ C(RESULT_ACCESS) ] = 0x01b7,
 953                 [ C(RESULT_MISS)   ] = 0x01b7,
 954         },
 955         [ C(OP_PREFETCH) ] = {
 956                 [ C(RESULT_ACCESS) ] = 0x01b7,
 957                 [ C(RESULT_MISS)   ] = 0x01b7,
 958         },
 959  },
 960 };
 961
 962 /*
 963  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
 964  * See IA32 SDM Vol 3B 30.6.1.3
 965  */
 966
 967 #define NHM_DMND_DATA_RD        (1 << 0)
 968 #define NHM_DMND_RFO            (1 << 1)
 969 #define NHM_DMND_IFETCH         (1 << 2)
 970 #define NHM_DMND_WB             (1 << 3)
 971 #define NHM_PF_DATA_RD          (1 << 4)
 972 #define NHM_PF_DATA_RFO         (1 << 5)
 973 #define NHM_PF_IFETCH           (1 << 6)
 974 #define NHM_OFFCORE_OTHER       (1 << 7)
 975 #define NHM_UNCORE_HIT          (1 << 8)
 976 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
 977 #define NHM_OTHER_CORE_HITM     (1 << 10)
 978                                 /* reserved */
 979 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
 980 #define NHM_REMOTE_DRAM         (1 << 13)
 981 #define NHM_LOCAL_DRAM          (1 << 14)
 982 #define NHM_NON_DRAM            (1 << 15)
 983
 984 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
 985 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
 986
 987 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
 988 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
 989 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
 990
 991 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
 992 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
 993 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
 994
 995 static __initconst const u64 nehalem_hw_cache_extra_regs
 996                                 [PERF_COUNT_HW_CACHE_MAX]
 997                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 998                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 999 {
1000  [ C(LL  ) ] = {
1001         [ C(OP_READ) ] = {
1002                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1003                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
1004         },
1005         [ C(OP_WRITE) ] = {
1006                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1007                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
1008         },
1009         [ C(OP_PREFETCH) ] = {
1010                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1011                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1012         },
1013  },
1014  [ C(NODE) ] = {
1015         [ C(OP_READ) ] = {
1016                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1017                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
1018         },
1019         [ C(OP_WRITE) ] = {
1020                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1021                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
1022         },
1023         [ C(OP_PREFETCH) ] = {
1024                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1025                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1026         },
1027  },
1028 };
1029
1030 static __initconst const u64 nehalem_hw_cache_event_ids
1031                                 [PERF_COUNT_HW_CACHE_MAX]
1032                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1033                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1034 {
1035  [ C(L1D) ] = {
1036         [ C(OP_READ) ] = {
1037                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1038                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1039         },
1040         [ C(OP_WRITE) ] = {
1041                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1042                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1043         },
1044         [ C(OP_PREFETCH) ] = {
1045                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1046                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1047         },
1048  },
1049  [ C(L1I ) ] = {
1050         [ C(OP_READ) ] = {
1051                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1052                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1053         },
1054         [ C(OP_WRITE) ] = {
1055                 [ C(RESULT_ACCESS) ] = -1,
1056                 [ C(RESULT_MISS)   ] = -1,
1057         },
1058         [ C(OP_PREFETCH) ] = {
1059                 [ C(RESULT_ACCESS) ] = 0x0,
1060                 [ C(RESULT_MISS)   ] = 0x0,
1061         },
1062  },
1063  [ C(LL  ) ] = {
1064         [ C(OP_READ) ] = {
1065                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1066                 [ C(RESULT_ACCESS) ] = 0x01b7,
1067                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1068                 [ C(RESULT_MISS)   ] = 0x01b7,
1069         },
1070         /*
1071          * Use RFO, not WRITEBACK, because a write miss would typically occur
1072          * on RFO.
1073          */
1074         [ C(OP_WRITE) ] = {
1075                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1076                 [ C(RESULT_ACCESS) ] = 0x01b7,
1077                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1078                 [ C(RESULT_MISS)   ] = 0x01b7,
1079         },
1080         [ C(OP_PREFETCH) ] = {
1081                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1082                 [ C(RESULT_ACCESS) ] = 0x01b7,
1083                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1084                 [ C(RESULT_MISS)   ] = 0x01b7,
1085         },
1086  },
1087  [ C(DTLB) ] = {
1088         [ C(OP_READ) ] = {
1089                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
1090                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1091         },
1092         [ C(OP_WRITE) ] = {
1093                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
1094                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1095         },
1096         [ C(OP_PREFETCH) ] = {
1097                 [ C(RESULT_ACCESS) ] = 0x0,
1098                 [ C(RESULT_MISS)   ] = 0x0,
1099         },
1100  },
1101  [ C(ITLB) ] = {
1102         [ C(OP_READ) ] = {
1103                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1104                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
1105         },
1106         [ C(OP_WRITE) ] = {
1107                 [ C(RESULT_ACCESS) ] = -1,
1108                 [ C(RESULT_MISS)   ] = -1,
1109         },
1110         [ C(OP_PREFETCH) ] = {
1111                 [ C(RESULT_ACCESS) ] = -1,
1112                 [ C(RESULT_MISS)   ] = -1,
1113         },
1114  },
1115  [ C(BPU ) ] = {
1116         [ C(OP_READ) ] = {
1117                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1118                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1119         },
1120         [ C(OP_WRITE) ] = {
1121                 [ C(RESULT_ACCESS) ] = -1,
1122                 [ C(RESULT_MISS)   ] = -1,
1123         },
1124         [ C(OP_PREFETCH) ] = {
1125                 [ C(RESULT_ACCESS) ] = -1,
1126                 [ C(RESULT_MISS)   ] = -1,
1127         },
1128  },
1129  [ C(NODE) ] = {
1130         [ C(OP_READ) ] = {
1131                 [ C(RESULT_ACCESS) ] = 0x01b7,
1132                 [ C(RESULT_MISS)   ] = 0x01b7,
1133         },
1134         [ C(OP_WRITE) ] = {
1135                 [ C(RESULT_ACCESS) ] = 0x01b7,
1136                 [ C(RESULT_MISS)   ] = 0x01b7,
1137         },
1138         [ C(OP_PREFETCH) ] = {
1139                 [ C(RESULT_ACCESS) ] = 0x01b7,
1140                 [ C(RESULT_MISS)   ] = 0x01b7,
1141         },
1142  },
1143 };
1144
1145 static __initconst const u64 core2_hw_cache_event_ids
1146                                 [PERF_COUNT_HW_CACHE_MAX]
1147                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1148                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1149 {
1150  [ C(L1D) ] = {
1151         [ C(OP_READ) ] = {
1152                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
1153                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
1154         },
1155         [ C(OP_WRITE) ] = {
1156                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
1157                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
1158         },
1159         [ C(OP_PREFETCH) ] = {
1160                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
1161                 [ C(RESULT_MISS)   ] = 0,
1162         },
1163  },
1164  [ C(L1I ) ] = {
1165         [ C(OP_READ) ] = {
1166                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
1167                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
1168         },
1169         [ C(OP_WRITE) ] = {
1170                 [ C(RESULT_ACCESS) ] = -1,
1171                 [ C(RESULT_MISS)   ] = -1,
1172         },
1173         [ C(OP_PREFETCH) ] = {
1174                 [ C(RESULT_ACCESS) ] = 0,
1175                 [ C(RESULT_MISS)   ] = 0,
1176         },
1177  },
1178  [ C(LL  ) ] = {
1179         [ C(OP_READ) ] = {
1180                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1181                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1182         },
1183         [ C(OP_WRITE) ] = {
1184                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1185                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1186         },
1187         [ C(OP_PREFETCH) ] = {
1188                 [ C(RESULT_ACCESS) ] = 0,
1189                 [ C(RESULT_MISS)   ] = 0,
1190         },
1191  },
1192  [ C(DTLB) ] = {
1193         [ C(OP_READ) ] = {
1194                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
1195                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
1196         },
1197         [ C(OP_WRITE) ] = {
1198                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
1199                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
1200         },
1201         [ C(OP_PREFETCH) ] = {
1202                 [ C(RESULT_ACCESS) ] = 0,
1203                 [ C(RESULT_MISS)   ] = 0,
1204         },
1205  },
1206  [ C(ITLB) ] = {
1207         [ C(OP_READ) ] = {
1208                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1209                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
1210         },
1211         [ C(OP_WRITE) ] = {
1212                 [ C(RESULT_ACCESS) ] = -1,
1213                 [ C(RESULT_MISS)   ] = -1,
1214         },
1215         [ C(OP_PREFETCH) ] = {
1216                 [ C(RESULT_ACCESS) ] = -1,
1217                 [ C(RESULT_MISS)   ] = -1,
1218         },
1219  },
1220  [ C(BPU ) ] = {
1221         [ C(OP_READ) ] = {
1222                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1223                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1224         },
1225         [ C(OP_WRITE) ] = {
1226                 [ C(RESULT_ACCESS) ] = -1,
1227                 [ C(RESULT_MISS)   ] = -1,
1228         },
1229         [ C(OP_PREFETCH) ] = {
1230                 [ C(RESULT_ACCESS) ] = -1,
1231                 [ C(RESULT_MISS)   ] = -1,
1232         },
1233  },
1234 };
1235
1236 static __initconst const u64 atom_hw_cache_event_ids
1237                                 [PERF_COUNT_HW_CACHE_MAX]
1238                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1239                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1240 {
1241  [ C(L1D) ] = {
1242         [ C(OP_READ) ] = {
1243                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
1244                 [ C(RESULT_MISS)   ] = 0,
1245         },
1246         [ C(OP_WRITE) ] = {
1247                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
1248                 [ C(RESULT_MISS)   ] = 0,
1249         },
1250         [ C(OP_PREFETCH) ] = {
1251                 [ C(RESULT_ACCESS) ] = 0x0,
1252                 [ C(RESULT_MISS)   ] = 0,
1253         },
1254  },
1255  [ C(L1I ) ] = {
1256         [ C(OP_READ) ] = {
1257                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
1258                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
1259         },
1260         [ C(OP_WRITE) ] = {
1261                 [ C(RESULT_ACCESS) ] = -1,
1262                 [ C(RESULT_MISS)   ] = -1,
1263         },
1264         [ C(OP_PREFETCH) ] = {
1265                 [ C(RESULT_ACCESS) ] = 0,
1266                 [ C(RESULT_MISS)   ] = 0,
1267         },
1268  },
1269  [ C(LL  ) ] = {
1270         [ C(OP_READ) ] = {
1271                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1272                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1273         },
1274         [ C(OP_WRITE) ] = {
1275                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1276                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1277         },
1278         [ C(OP_PREFETCH) ] = {
1279                 [ C(RESULT_ACCESS) ] = 0,
1280                 [ C(RESULT_MISS)   ] = 0,
1281         },
1282  },
1283  [ C(DTLB) ] = {
1284         [ C(OP_READ) ] = {
1285                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
1286                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
1287         },
1288         [ C(OP_WRITE) ] = {
1289                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
1290                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
1291         },
1292         [ C(OP_PREFETCH) ] = {
1293                 [ C(RESULT_ACCESS) ] = 0,
1294                 [ C(RESULT_MISS)   ] = 0,
1295         },
1296  },
1297  [ C(ITLB) ] = {
1298         [ C(OP_READ) ] = {
1299                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1300                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
1301         },
1302         [ C(OP_WRITE) ] = {
1303                 [ C(RESULT_ACCESS) ] = -1,
1304                 [ C(RESULT_MISS)   ] = -1,
1305         },
1306         [ C(OP_PREFETCH) ] = {
1307                 [ C(RESULT_ACCESS) ] = -1,
1308                 [ C(RESULT_MISS)   ] = -1,
1309         },
1310  },
1311  [ C(BPU ) ] = {
1312         [ C(OP_READ) ] = {
1313                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1314                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1315         },
1316         [ C(OP_WRITE) ] = {
1317                 [ C(RESULT_ACCESS) ] = -1,
1318                 [ C(RESULT_MISS)   ] = -1,
1319         },
1320         [ C(OP_PREFETCH) ] = {
1321                 [ C(RESULT_ACCESS) ] = -1,
1322                 [ C(RESULT_MISS)   ] = -1,
1323         },
1324  },
1325 };
1326
1327 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1328 {
1329         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1330         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1331         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1332         EVENT_EXTRA_END
1333 };
1334
1335 #define SLM_DMND_READ           SNB_DMND_DATA_RD
1336 #define SLM_DMND_WRITE          SNB_DMND_RFO
1337 #define SLM_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
1338
1339 #define SLM_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1340 #define SLM_LLC_ACCESS          SNB_RESP_ANY
1341 #define SLM_LLC_MISS            (SLM_SNP_ANY|SNB_NON_DRAM)
1342
1343 static __initconst const u64 slm_hw_cache_extra_regs
1344                                 [PERF_COUNT_HW_CACHE_MAX]
1345                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1346                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1347 {
1348  [ C(LL  ) ] = {
1349         [ C(OP_READ) ] = {
1350                 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1351                 [ C(RESULT_MISS)   ] = 0,
1352         },
1353         [ C(OP_WRITE) ] = {
1354                 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1355                 [ C(RESULT_MISS)   ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1356         },
1357         [ C(OP_PREFETCH) ] = {
1358                 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1359                 [ C(RESULT_MISS)   ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1360         },
1361  },
1362 };
1363
1364 static __initconst const u64 slm_hw_cache_event_ids
1365                                 [PERF_COUNT_HW_CACHE_MAX]
1366                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1367                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1368 {
1369  [ C(L1D) ] = {
1370         [ C(OP_READ) ] = {
1371                 [ C(RESULT_ACCESS) ] = 0,
1372                 [ C(RESULT_MISS)   ] = 0x0104, /* LD_DCU_MISS */
1373         },
1374         [ C(OP_WRITE) ] = {
1375                 [ C(RESULT_ACCESS) ] = 0,
1376                 [ C(RESULT_MISS)   ] = 0,
1377         },
1378         [ C(OP_PREFETCH) ] = {
1379                 [ C(RESULT_ACCESS) ] = 0,
1380                 [ C(RESULT_MISS)   ] = 0,
1381         },
1382  },
1383  [ C(L1I ) ] = {
1384         [ C(OP_READ) ] = {
1385                 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1386                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACGE.MISSES */
1387         },
1388         [ C(OP_WRITE) ] = {
1389                 [ C(RESULT_ACCESS) ] = -1,
1390                 [ C(RESULT_MISS)   ] = -1,
1391         },
1392         [ C(OP_PREFETCH) ] = {
1393                 [ C(RESULT_ACCESS) ] = 0,
1394                 [ C(RESULT_MISS)   ] = 0,
1395         },
1396  },
1397  [ C(LL  ) ] = {
1398         [ C(OP_READ) ] = {
1399                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1400                 [ C(RESULT_ACCESS) ] = 0x01b7,
1401                 [ C(RESULT_MISS)   ] = 0,
1402         },
1403         [ C(OP_WRITE) ] = {
1404                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1405                 [ C(RESULT_ACCESS) ] = 0x01b7,
1406                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1407                 [ C(RESULT_MISS)   ] = 0x01b7,
1408         },
1409         [ C(OP_PREFETCH) ] = {
1410                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1411                 [ C(RESULT_ACCESS) ] = 0x01b7,
1412                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1413                 [ C(RESULT_MISS)   ] = 0x01b7,
1414         },
1415  },
1416  [ C(DTLB) ] = {
1417         [ C(OP_READ) ] = {
1418                 [ C(RESULT_ACCESS) ] = 0,
1419                 [ C(RESULT_MISS)   ] = 0x0804, /* LD_DTLB_MISS */
1420         },
1421         [ C(OP_WRITE) ] = {
1422                 [ C(RESULT_ACCESS) ] = 0,
1423                 [ C(RESULT_MISS)   ] = 0,
1424         },
1425         [ C(OP_PREFETCH) ] = {
1426                 [ C(RESULT_ACCESS) ] = 0,
1427                 [ C(RESULT_MISS)   ] = 0,
1428         },
1429  },
1430  [ C(ITLB) ] = {
1431         [ C(OP_READ) ] = {
1432                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1433                 [ C(RESULT_MISS)   ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1434         },
1435         [ C(OP_WRITE) ] = {
1436                 [ C(RESULT_ACCESS) ] = -1,
1437                 [ C(RESULT_MISS)   ] = -1,
1438         },
1439         [ C(OP_PREFETCH) ] = {
1440                 [ C(RESULT_ACCESS) ] = -1,
1441                 [ C(RESULT_MISS)   ] = -1,
1442         },
1443  },
1444  [ C(BPU ) ] = {
1445         [ C(OP_READ) ] = {
1446                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1447                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1448         },
1449         [ C(OP_WRITE) ] = {
1450                 [ C(RESULT_ACCESS) ] = -1,
1451                 [ C(RESULT_MISS)   ] = -1,
1452         },
1453         [ C(OP_PREFETCH) ] = {
1454                 [ C(RESULT_ACCESS) ] = -1,
1455                 [ C(RESULT_MISS)   ] = -1,
1456         },
1457  },
1458 };
1459
1460 /*
1461  * Used from PMIs where the LBRs are already disabled.
1462  *
1463  * This function could be called consecutively. It is required to remain in
1464  * disabled state if called consecutively.
1465  *
1466  * During consecutive calls, the same disable value will be written to related
1467  * registers, so the PMU state remains unchanged. hw.state in
1468  * intel_bts_disable_local will remain PERF_HES_STOPPED too in consecutive
1469  * calls.
1470  */
1471 static void __intel_pmu_disable_all(void)
1472 {
1473         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1474
1475         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1476
1477         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1478                 intel_pmu_disable_bts();
1479         else
1480                 intel_bts_disable_local();
1481
1482         intel_pmu_pebs_disable_all();
1483 }
1484
1485 static void intel_pmu_disable_all(void)
1486 {
1487         __intel_pmu_disable_all();
1488         intel_pmu_lbr_disable_all();
1489 }
1490
1491 static void __intel_pmu_enable_all(int added, bool pmi)
1492 {
1493         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1494
1495         intel_pmu_pebs_enable_all();
1496         intel_pmu_lbr_enable_all(pmi);
1497         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1498                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1499
1500         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1501                 struct perf_event *event =
1502                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1503
1504                 if (WARN_ON_ONCE(!event))
1505                         return;
1506
1507                 intel_pmu_enable_bts(event->hw.config);
1508         } else
1509                 intel_bts_enable_local();
1510 }
1511
1512 static void intel_pmu_enable_all(int added)
1513 {
1514         __intel_pmu_enable_all(added, false);
1515 }
1516
1517 /*
1518  * Workaround for:
1519  *   Intel Errata AAK100 (model 26)
1520  *   Intel Errata AAP53  (model 30)
1521  *   Intel Errata BD53   (model 44)
1522  *
1523  * The official story:
1524  *   These chips need to be 'reset' when adding counters by programming the
1525  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1526  *   in sequence on the same PMC or on different PMCs.
1527  *
1528  * In practise it appears some of these events do in fact count, and
1529  * we need to programm all 4 events.
1530  */
1531 static void intel_pmu_nhm_workaround(void)
1532 {
1533         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1534         static const unsigned long nhm_magic[4] = {
1535                 0x4300B5,
1536                 0x4300D2,
1537                 0x4300B1,
1538                 0x4300B1
1539         };
1540         struct perf_event *event;
1541         int i;
1542
1543         /*
1544          * The Errata requires below steps:
1545          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1546          * 2) Configure 4 PERFEVTSELx with the magic events and clear
1547          *    the corresponding PMCx;
1548          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1549          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1550          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1551          */
1552
1553         /*
1554          * The real steps we choose are a little different from above.
1555          * A) To reduce MSR operations, we don't run step 1) as they
1556          *    are already cleared before this function is called;
1557          * B) Call x86_perf_event_update to save PMCx before configuring
1558          *    PERFEVTSELx with magic number;
1559          * C) With step 5), we do clear only when the PERFEVTSELx is
1560          *    not used currently.
1561          * D) Call x86_perf_event_set_period to restore PMCx;
1562          */
1563
1564         /* We always operate 4 pairs of PERF Counters */
1565         for (i = 0; i < 4; i++) {
1566                 event = cpuc->events[i];
1567                 if (event)
1568                         x86_perf_event_update(event);
1569         }
1570
1571         for (i = 0; i < 4; i++) {
1572                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1573                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1574         }
1575
1576         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1577         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1578
1579         for (i = 0; i < 4; i++) {
1580                 event = cpuc->events[i];
1581
1582                 if (event) {
1583                         x86_perf_event_set_period(event);
1584                         __x86_pmu_enable_event(&event->hw,
1585                                         ARCH_PERFMON_EVENTSEL_ENABLE);
1586                 } else
1587                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1588         }
1589 }
1590
1591 static void intel_pmu_nhm_enable_all(int added)
1592 {
1593         if (added)
1594                 intel_pmu_nhm_workaround();
1595         intel_pmu_enable_all(added);
1596 }
1597
1598 static inline u64 intel_pmu_get_status(void)
1599 {
1600         u64 status;
1601
1602         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1603
1604         return status;
1605 }
1606
1607 static inline void intel_pmu_ack_status(u64 ack)
1608 {
1609         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1610 }
1611
1612 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1613 {
1614         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1615         u64 ctrl_val, mask;
1616
1617         mask = 0xfULL << (idx * 4);
1618
1619         rdmsrl(hwc->config_base, ctrl_val);
1620         ctrl_val &= ~mask;
1621         wrmsrl(hwc->config_base, ctrl_val);
1622 }
1623
1624 static inline bool event_is_checkpointed(struct perf_event *event)
1625 {
1626         return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1627 }
1628
1629 static void intel_pmu_disable_event(struct perf_event *event)
1630 {
1631         struct hw_perf_event *hwc = &event->hw;
1632         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1633
1634         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1635                 intel_pmu_disable_bts();
1636                 intel_pmu_drain_bts_buffer();
1637                 return;
1638         }
1639
1640         cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1641         cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1642         cpuc->intel_cp_status &= ~(1ull << hwc->idx);
1643
1644         /*
1645          * must disable before any actual event
1646          * because any event may be combined with LBR
1647          */
1648         if (needs_branch_stack(event))
1649                 intel_pmu_lbr_disable(event);
1650
1651         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1652                 intel_pmu_disable_fixed(hwc);
1653                 return;
1654         }
1655
1656         x86_pmu_disable_event(event);
1657
1658         if (unlikely(event->attr.precise_ip))
1659                 intel_pmu_pebs_disable(event);
1660 }
1661
1662 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1663 {
1664         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1665         u64 ctrl_val, bits, mask;
1666
1667         /*
1668          * Enable IRQ generation (0x8),
1669          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1670          * if requested:
1671          */
1672         bits = 0x8ULL;
1673         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1674                 bits |= 0x2;
1675         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1676                 bits |= 0x1;
1677
1678         /*
1679          * ANY bit is supported in v3 and up
1680          */
1681         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1682                 bits |= 0x4;
1683
1684         bits <<= (idx * 4);
1685         mask = 0xfULL << (idx * 4);
1686
1687         rdmsrl(hwc->config_base, ctrl_val);
1688         ctrl_val &= ~mask;
1689         ctrl_val |= bits;
1690         wrmsrl(hwc->config_base, ctrl_val);
1691 }
1692
1693 static void intel_pmu_enable_event(struct perf_event *event)
1694 {
1695         struct hw_perf_event *hwc = &event->hw;
1696         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1697
1698         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1699                 if (!__this_cpu_read(cpu_hw_events.enabled))
1700                         return;
1701
1702                 intel_pmu_enable_bts(hwc->config);
1703                 return;
1704         }
1705         /*
1706          * must enabled before any actual event
1707          * because any event may be combined with LBR
1708          */
1709         if (needs_branch_stack(event))
1710                 intel_pmu_lbr_enable(event);
1711
1712         if (event->attr.exclude_host)
1713                 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1714         if (event->attr.exclude_guest)
1715                 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1716
1717         if (unlikely(event_is_checkpointed(event)))
1718                 cpuc->intel_cp_status |= (1ull << hwc->idx);
1719
1720         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1721                 intel_pmu_enable_fixed(hwc);
1722                 return;
1723         }
1724
1725         if (unlikely(event->attr.precise_ip))
1726                 intel_pmu_pebs_enable(event);
1727
1728         __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1729 }
1730
1731 /*
1732  * Save and restart an expired event. Called by NMI contexts,
1733  * so it has to be careful about preempting normal event ops:
1734  */
1735 int intel_pmu_save_and_restart(struct perf_event *event)
1736 {
1737         x86_perf_event_update(event);
1738         /*
1739          * For a checkpointed counter always reset back to 0.  This
1740          * avoids a situation where the counter overflows, aborts the
1741          * transaction and is then set back to shortly before the
1742          * overflow, and overflows and aborts again.
1743          */
1744         if (unlikely(event_is_checkpointed(event))) {
1745                 /* No race with NMIs because the counter should not be armed */
1746                 wrmsrl(event->hw.event_base, 0);
1747                 local64_set(&event->hw.prev_count, 0);
1748         }
1749         return x86_perf_event_set_period(event);
1750 }
1751
1752 static void intel_pmu_reset(void)
1753 {
1754         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1755         unsigned long flags;
1756         int idx;
1757
1758         if (!x86_pmu.num_counters)
1759                 return;
1760
1761         local_irq_save(flags);
1762
1763         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1764
1765         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1766                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1767                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
1768         }
1769         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1770                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1771
1772         if (ds)
1773                 ds->bts_index = ds->bts_buffer_base;
1774
1775         /* Ack all overflows and disable fixed counters */
1776         if (x86_pmu.version >= 2) {
1777                 intel_pmu_ack_status(intel_pmu_get_status());
1778                 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1779         }
1780
1781         /* Reset LBRs and LBR freezing */
1782         if (x86_pmu.lbr_nr) {
1783                 update_debugctlmsr(get_debugctlmsr() &
1784                         ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
1785         }
1786
1787         local_irq_restore(flags);
1788 }
1789
1790 /*
1791  * This handler is triggered by the local APIC, so the APIC IRQ handling
1792  * rules apply:
1793  */
1794 static int intel_pmu_handle_irq(struct pt_regs *regs)
1795 {
1796         struct perf_sample_data data;
1797         struct cpu_hw_events *cpuc;
1798         int bit, loops;
1799         u64 status;
1800         int handled;
1801
1802         cpuc = this_cpu_ptr(&cpu_hw_events);
1803
1804         /*
1805          * No known reason to not always do late ACK,
1806          * but just in case do it opt-in.
1807          */
1808         if (!x86_pmu.late_ack)
1809                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1810         __intel_pmu_disable_all();
1811         handled = intel_pmu_drain_bts_buffer();
1812         handled += intel_bts_interrupt();
1813         status = intel_pmu_get_status();
1814         if (!status)
1815                 goto done;
1816
1817         loops = 0;
1818 again:
1819         intel_pmu_lbr_read();
1820         intel_pmu_ack_status(status);
1821         if (++loops > 100) {
1822                 static bool warned = false;
1823                 if (!warned) {
1824                         WARN(1, "perfevents: irq loop stuck!\n");
1825                         perf_event_print_debug();
1826                         warned = true;
1827                 }
1828                 intel_pmu_reset();
1829                 goto done;
1830         }
1831
1832         inc_irq_stat(apic_perf_irqs);
1833
1834
1835         /*
1836          * Ignore a range of extra bits in status that do not indicate
1837          * overflow by themselves.
1838          */
1839         status &= ~(GLOBAL_STATUS_COND_CHG |
1840                     GLOBAL_STATUS_ASIF |
1841                     GLOBAL_STATUS_LBRS_FROZEN);
1842         if (!status)
1843                 goto done;
1844
1845         /*
1846          * PEBS overflow sets bit 62 in the global status register
1847          */
1848         if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1849                 handled++;
1850                 x86_pmu.drain_pebs(regs);
1851                 /*
1852                  * There are cases where, even though, the PEBS ovfl bit is set
1853                  * in GLOBAL_OVF_STATUS, the PEBS events may also have their
1854                  * overflow bits set for their counters. We must clear them
1855                  * here because they have been processed as exact samples in
1856                  * the drain_pebs() routine. They must not be processed again
1857                  * in the for_each_bit_set() loop for regular samples below.
1858                  */
1859                 status &= ~cpuc->pebs_enabled;
1860                 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
1861         }
1862
1863         /*
1864          * Intel PT
1865          */
1866         if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1867                 handled++;
1868                 intel_pt_interrupt();
1869         }
1870
1871         /*
1872          * Checkpointed counters can lead to 'spurious' PMIs because the
1873          * rollback caused by the PMI will have cleared the overflow status
1874          * bit. Therefore always force probe these counters.
1875          */
1876         status |= cpuc->intel_cp_status;
1877
1878         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1879                 struct perf_event *event = cpuc->events[bit];
1880
1881                 handled++;
1882
1883                 if (!test_bit(bit, cpuc->active_mask))
1884                         continue;
1885
1886                 if (!intel_pmu_save_and_restart(event))
1887                         continue;
1888
1889                 perf_sample_data_init(&data, 0, event->hw.last_period);
1890
1891                 if (has_branch_stack(event))
1892                         data.br_stack = &cpuc->lbr_stack;
1893
1894                 if (perf_event_overflow(event, &data, regs))
1895                         x86_pmu_stop(event, 0);
1896         }
1897
1898         /*
1899          * Repeat if there is more work to be done:
1900          */
1901         status = intel_pmu_get_status();
1902         if (status)
1903                 goto again;
1904
1905 done:
1906         /* Only restore PMU state when it's active. See x86_pmu_disable(). */
1907         if (cpuc->enabled)
1908                 __intel_pmu_enable_all(0, true);
1909
1910         /*
1911          * Only unmask the NMI after the overflow counters
1912          * have been reset. This avoids spurious NMIs on
1913          * Haswell CPUs.
1914          */
1915         if (x86_pmu.late_ack)
1916                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1917         return handled;
1918 }
1919
1920 static struct event_constraint *
1921 intel_bts_constraints(struct perf_event *event)
1922 {
1923         struct hw_perf_event *hwc = &event->hw;
1924         unsigned int hw_event, bts_event;
1925
1926         if (event->attr.freq)
1927                 return NULL;
1928
1929         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1930         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1931
1932         if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1933                 return &bts_constraint;
1934
1935         return NULL;
1936 }
1937
1938 static int intel_alt_er(int idx, u64 config)
1939 {
1940         int alt_idx = idx;
1941
1942         if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
1943                 return idx;
1944
1945         if (idx == EXTRA_REG_RSP_0)
1946                 alt_idx = EXTRA_REG_RSP_1;
1947
1948         if (idx == EXTRA_REG_RSP_1)
1949                 alt_idx = EXTRA_REG_RSP_0;
1950
1951         if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
1952                 return idx;
1953
1954         return alt_idx;
1955 }
1956
1957 static void intel_fixup_er(struct perf_event *event, int idx)
1958 {
1959         event->hw.extra_reg.idx = idx;
1960
1961         if (idx == EXTRA_REG_RSP_0) {
1962                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1963                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
1964                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1965         } else if (idx == EXTRA_REG_RSP_1) {
1966                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1967                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
1968                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1969         }
1970 }
1971
1972 /*
1973  * manage allocation of shared extra msr for certain events
1974  *
1975  * sharing can be:
1976  * per-cpu: to be shared between the various events on a single PMU
1977  * per-core: per-cpu + shared by HT threads
1978  */
1979 static struct event_constraint *
1980 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1981                                    struct perf_event *event,
1982                                    struct hw_perf_event_extra *reg)
1983 {
1984         struct event_constraint *c = &emptyconstraint;
1985         struct er_account *era;
1986         unsigned long flags;
1987         int idx = reg->idx;
1988
1989         /*
1990          * reg->alloc can be set due to existing state, so for fake cpuc we
1991          * need to ignore this, otherwise we might fail to allocate proper fake
1992          * state for this extra reg constraint. Also see the comment below.
1993          */
1994         if (reg->alloc && !cpuc->is_fake)
1995                 return NULL; /* call x86_get_event_constraint() */
1996
1997 again:
1998         era = &cpuc->shared_regs->regs[idx];
1999         /*
2000          * we use spin_lock_irqsave() to avoid lockdep issues when
2001          * passing a fake cpuc
2002          */
2003         raw_spin_lock_irqsave(&era->lock, flags);
2004
2005         if (!atomic_read(&era->ref) || era->config == reg->config) {
2006
2007                 /*
2008                  * If its a fake cpuc -- as per validate_{group,event}() we
2009                  * shouldn't touch event state and we can avoid doing so
2010                  * since both will only call get_event_constraints() once
2011                  * on each event, this avoids the need for reg->alloc.
2012                  *
2013                  * Not doing the ER fixup will only result in era->reg being
2014                  * wrong, but since we won't actually try and program hardware
2015                  * this isn't a problem either.
2016                  */
2017                 if (!cpuc->is_fake) {
2018                         if (idx != reg->idx)
2019                                 intel_fixup_er(event, idx);
2020
2021                         /*
2022                          * x86_schedule_events() can call get_event_constraints()
2023                          * multiple times on events in the case of incremental
2024                          * scheduling(). reg->alloc ensures we only do the ER
2025                          * allocation once.
2026                          */
2027                         reg->alloc = 1;
2028                 }
2029
2030                 /* lock in msr value */
2031                 era->config = reg->config;
2032                 era->reg = reg->reg;
2033
2034                 /* one more user */
2035                 atomic_inc(&era->ref);
2036
2037                 /*
2038                  * need to call x86_get_event_constraint()
2039                  * to check if associated event has constraints
2040                  */
2041                 c = NULL;
2042         } else {
2043                 idx = intel_alt_er(idx, reg->config);
2044                 if (idx != reg->idx) {
2045                         raw_spin_unlock_irqrestore(&era->lock, flags);
2046                         goto again;
2047                 }
2048         }
2049         raw_spin_unlock_irqrestore(&era->lock, flags);
2050
2051         return c;
2052 }
2053
2054 static void
2055 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2056                                    struct hw_perf_event_extra *reg)
2057 {
2058         struct er_account *era;
2059
2060         /*
2061          * Only put constraint if extra reg was actually allocated. Also takes
2062          * care of event which do not use an extra shared reg.
2063          *
2064          * Also, if this is a fake cpuc we shouldn't touch any event state
2065          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2066          * either since it'll be thrown out.
2067          */
2068         if (!reg->alloc || cpuc->is_fake)
2069                 return;
2070
2071         era = &cpuc->shared_regs->regs[reg->idx];
2072
2073         /* one fewer user */
2074         atomic_dec(&era->ref);
2075
2076         /* allocate again next time */
2077         reg->alloc = 0;
2078 }
2079
2080 static struct event_constraint *
2081 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2082                               struct perf_event *event)
2083 {
2084         struct event_constraint *c = NULL, *d;
2085         struct hw_perf_event_extra *xreg, *breg;
2086
2087         xreg = &event->hw.extra_reg;
2088         if (xreg->idx != EXTRA_REG_NONE) {
2089                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2090                 if (c == &emptyconstraint)
2091                         return c;
2092         }
2093         breg = &event->hw.branch_reg;
2094         if (breg->idx != EXTRA_REG_NONE) {
2095                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2096                 if (d == &emptyconstraint) {
2097                         __intel_shared_reg_put_constraints(cpuc, xreg);
2098                         c = d;
2099                 }
2100         }
2101         return c;
2102 }
2103
2104 struct event_constraint *
2105 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2106                           struct perf_event *event)
2107 {
2108         struct event_constraint *c;
2109
2110         if (x86_pmu.event_constraints) {
2111                 for_each_event_constraint(c, x86_pmu.event_constraints) {
2112                         if ((event->hw.config & c->cmask) == c->code) {
2113                                 event->hw.flags |= c->flags;
2114                                 return c;
2115                         }
2116                 }
2117         }
2118
2119         return &unconstrained;
2120 }
2121
2122 static struct event_constraint *
2123 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2124                             struct perf_event *event)
2125 {
2126         struct event_constraint *c;
2127
2128         c = intel_bts_constraints(event);
2129         if (c)
2130                 return c;
2131
2132         c = intel_shared_regs_constraints(cpuc, event);
2133         if (c)
2134                 return c;
2135
2136         c = intel_pebs_constraints(event);
2137         if (c)
2138                 return c;
2139
2140         return x86_get_event_constraints(cpuc, idx, event);
2141 }
2142
2143 static void
2144 intel_start_scheduling(struct cpu_hw_events *cpuc)
2145 {
2146         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2147         struct intel_excl_states *xl;
2148         int tid = cpuc->excl_thread_id;
2149
2150         /*
2151          * nothing needed if in group validation mode
2152          */
2153         if (cpuc->is_fake || !is_ht_workaround_enabled())
2154                 return;
2155
2156         /*
2157          * no exclusion needed
2158          */
2159         if (WARN_ON_ONCE(!excl_cntrs))
2160                 return;
2161
2162         xl = &excl_cntrs->states[tid];
2163
2164         xl->sched_started = true;
2165         /*
2166          * lock shared state until we are done scheduling
2167          * in stop_event_scheduling()
2168          * makes scheduling appear as a transaction
2169          */
2170         raw_spin_lock(&excl_cntrs->lock);
2171 }
2172
2173 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2174 {
2175         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2176         struct event_constraint *c = cpuc->event_constraint[idx];
2177         struct intel_excl_states *xl;
2178         int tid = cpuc->excl_thread_id;
2179
2180         if (cpuc->is_fake || !is_ht_workaround_enabled())
2181                 return;
2182
2183         if (WARN_ON_ONCE(!excl_cntrs))
2184                 return;
2185
2186         if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2187                 return;
2188
2189         xl = &excl_cntrs->states[tid];
2190
2191         lockdep_assert_held(&excl_cntrs->lock);
2192
2193         if (c->flags & PERF_X86_EVENT_EXCL)
2194                 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2195         else
2196                 xl->state[cntr] = INTEL_EXCL_SHARED;
2197 }
2198
2199 static void
2200 intel_stop_scheduling(struct cpu_hw_events *cpuc)
2201 {
2202         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2203         struct intel_excl_states *xl;
2204         int tid = cpuc->excl_thread_id;
2205
2206         /*
2207          * nothing needed if in group validation mode
2208          */
2209         if (cpuc->is_fake || !is_ht_workaround_enabled())
2210                 return;
2211         /*
2212          * no exclusion needed
2213          */
2214         if (WARN_ON_ONCE(!excl_cntrs))
2215                 return;
2216
2217         xl = &excl_cntrs->states[tid];
2218
2219         xl->sched_started = false;
2220         /*
2221          * release shared state lock (acquired in intel_start_scheduling())
2222          */
2223         raw_spin_unlock(&excl_cntrs->lock);
2224 }
2225
2226 static struct event_constraint *
2227 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2228                            int idx, struct event_constraint *c)
2229 {
2230         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2231         struct intel_excl_states *xlo;
2232         int tid = cpuc->excl_thread_id;
2233         int is_excl, i;
2234
2235         /*
2236          * validating a group does not require
2237          * enforcing cross-thread  exclusion
2238          */
2239         if (cpuc->is_fake || !is_ht_workaround_enabled())
2240                 return c;
2241
2242         /*
2243          * no exclusion needed
2244          */
2245         if (WARN_ON_ONCE(!excl_cntrs))
2246                 return c;
2247
2248         /*
2249          * because we modify the constraint, we need
2250          * to make a copy. Static constraints come
2251          * from static const tables.
2252          *
2253          * only needed when constraint has not yet
2254          * been cloned (marked dynamic)
2255          */
2256         if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2257                 struct event_constraint *cx;
2258
2259                 /*
2260                  * grab pre-allocated constraint entry
2261                  */
2262                 cx = &cpuc->constraint_list[idx];
2263
2264                 /*
2265                  * initialize dynamic constraint
2266                  * with static constraint
2267                  */
2268                 *cx = *c;
2269
2270                 /*
2271                  * mark constraint as dynamic, so we
2272                  * can free it later on
2273                  */
2274                 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2275                 c = cx;
2276         }
2277
2278         /*
2279          * From here on, the constraint is dynamic.
2280          * Either it was just allocated above, or it
2281          * was allocated during a earlier invocation
2282          * of this function
2283          */
2284
2285         /*
2286          * state of sibling HT
2287          */
2288         xlo = &excl_cntrs->states[tid ^ 1];
2289
2290         /*
2291          * event requires exclusive counter access
2292          * across HT threads
2293          */
2294         is_excl = c->flags & PERF_X86_EVENT_EXCL;
2295         if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2296                 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2297                 if (!cpuc->n_excl++)
2298                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2299         }
2300
2301         /*
2302          * Modify static constraint with current dynamic
2303          * state of thread
2304          *
2305          * EXCLUSIVE: sibling counter measuring exclusive event
2306          * SHARED   : sibling counter measuring non-exclusive event
2307          * UNUSED   : sibling counter unused
2308          */
2309         for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2310                 /*
2311                  * exclusive event in sibling counter
2312                  * our corresponding counter cannot be used
2313                  * regardless of our event
2314                  */
2315                 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
2316                         __clear_bit(i, c->idxmsk);
2317                 /*
2318                  * if measuring an exclusive event, sibling
2319                  * measuring non-exclusive, then counter cannot
2320                  * be used
2321                  */
2322                 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
2323                         __clear_bit(i, c->idxmsk);
2324         }
2325
2326         /*
2327          * recompute actual bit weight for scheduling algorithm
2328          */
2329         c->weight = hweight64(c->idxmsk64);
2330
2331         /*
2332          * if we return an empty mask, then switch
2333          * back to static empty constraint to avoid
2334          * the cost of freeing later on
2335          */
2336         if (c->weight == 0)
2337                 c = &emptyconstraint;
2338
2339         return c;
2340 }
2341
2342 static struct event_constraint *
2343 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2344                             struct perf_event *event)
2345 {
2346         struct event_constraint *c1 = NULL;
2347         struct event_constraint *c2;
2348
2349         if (idx >= 0) /* fake does < 0 */
2350                 c1 = cpuc->event_constraint[idx];
2351
2352         /*
2353          * first time only
2354          * - static constraint: no change across incremental scheduling calls
2355          * - dynamic constraint: handled by intel_get_excl_constraints()
2356          */
2357         c2 = __intel_get_event_constraints(cpuc, idx, event);
2358         if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2359                 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2360                 c1->weight = c2->weight;
2361                 c2 = c1;
2362         }
2363
2364         if (cpuc->excl_cntrs)
2365                 return intel_get_excl_constraints(cpuc, event, idx, c2);
2366
2367         return c2;
2368 }
2369
2370 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2371                 struct perf_event *event)
2372 {
2373         struct hw_perf_event *hwc = &event->hw;
2374         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2375         int tid = cpuc->excl_thread_id;
2376         struct intel_excl_states *xl;
2377
2378         /*
2379          * nothing needed if in group validation mode
2380          */
2381         if (cpuc->is_fake)
2382                 return;
2383
2384         if (WARN_ON_ONCE(!excl_cntrs))
2385                 return;
2386
2387         if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2388                 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2389                 if (!--cpuc->n_excl)
2390                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2391         }
2392
2393         /*
2394          * If event was actually assigned, then mark the counter state as
2395          * unused now.
2396          */
2397         if (hwc->idx >= 0) {
2398                 xl = &excl_cntrs->states[tid];
2399
2400                 /*
2401                  * put_constraint may be called from x86_schedule_events()
2402                  * which already has the lock held so here make locking
2403                  * conditional.
2404                  */
2405                 if (!xl->sched_started)
2406                         raw_spin_lock(&excl_cntrs->lock);
2407
2408                 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
2409
2410                 if (!xl->sched_started)
2411                         raw_spin_unlock(&excl_cntrs->lock);
2412         }
2413 }
2414
2415 static void
2416 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
2417                                         struct perf_event *event)
2418 {
2419         struct hw_perf_event_extra *reg;
2420
2421         reg = &event->hw.extra_reg;
2422         if (reg->idx != EXTRA_REG_NONE)
2423                 __intel_shared_reg_put_constraints(cpuc, reg);
2424
2425         reg = &event->hw.branch_reg;
2426         if (reg->idx != EXTRA_REG_NONE)
2427                 __intel_shared_reg_put_constraints(cpuc, reg);
2428 }
2429
2430 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2431                                         struct perf_event *event)
2432 {
2433         intel_put_shared_regs_event_constraints(cpuc, event);
2434
2435         /*
2436          * is PMU has exclusive counter restrictions, then
2437          * all events are subject to and must call the
2438          * put_excl_constraints() routine
2439          */
2440         if (cpuc->excl_cntrs)
2441                 intel_put_excl_constraints(cpuc, event);
2442 }
2443
2444 static void intel_pebs_aliases_core2(struct perf_event *event)
2445 {
2446         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2447                 /*
2448                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2449                  * (0x003c) so that we can use it with PEBS.
2450                  *
2451                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2452                  * PEBS capable. However we can use INST_RETIRED.ANY_P
2453                  * (0x00c0), which is a PEBS capable event, to get the same
2454                  * count.
2455                  *
2456                  * INST_RETIRED.ANY_P counts the number of cycles that retires
2457                  * CNTMASK instructions. By setting CNTMASK to a value (16)
2458                  * larger than the maximum number of instructions that can be
2459                  * retired per cycle (4) and then inverting the condition, we
2460                  * count all cycles that retire 16 or less instructions, which
2461                  * is every cycle.
2462                  *
2463                  * Thereby we gain a PEBS capable cycle counter.
2464                  */
2465                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2466
2467                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2468                 event->hw.config = alt_config;
2469         }
2470 }
2471
2472 static void intel_pebs_aliases_snb(struct perf_event *event)
2473 {
2474         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2475                 /*
2476                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2477                  * (0x003c) so that we can use it with PEBS.
2478                  *
2479                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2480                  * PEBS capable. However we can use UOPS_RETIRED.ALL
2481                  * (0x01c2), which is a PEBS capable event, to get the same
2482                  * count.
2483                  *
2484                  * UOPS_RETIRED.ALL counts the number of cycles that retires
2485                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2486                  * larger than the maximum number of micro-ops that can be
2487                  * retired per cycle (4) and then inverting the condition, we
2488                  * count all cycles that retire 16 or less micro-ops, which
2489                  * is every cycle.
2490                  *
2491                  * Thereby we gain a PEBS capable cycle counter.
2492                  */
2493                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
2494
2495                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2496                 event->hw.config = alt_config;
2497         }
2498 }
2499
2500 static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2501 {
2502         unsigned long flags = x86_pmu.free_running_flags;
2503
2504         if (event->attr.use_clockid)
2505                 flags &= ~PERF_SAMPLE_TIME;
2506         return flags;
2507 }
2508
2509 static int intel_pmu_hw_config(struct perf_event *event)
2510 {
2511         int ret = x86_pmu_hw_config(event);
2512
2513         if (ret)
2514                 return ret;
2515
2516         if (event->attr.precise_ip) {
2517                 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
2518                         event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
2519                         if (!(event->attr.sample_type &
2520                               ~intel_pmu_free_running_flags(event)))
2521                                 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2522                 }
2523                 if (x86_pmu.pebs_aliases)
2524                         x86_pmu.pebs_aliases(event);
2525         }
2526
2527         if (needs_branch_stack(event)) {
2528                 ret = intel_pmu_setup_lbr_filter(event);
2529                 if (ret)
2530                         return ret;
2531
2532                 /*
2533                  * BTS is set up earlier in this path, so don't account twice
2534                  */
2535                 if (!intel_pmu_has_bts(event)) {
2536                         /* disallow lbr if conflicting events are present */
2537                         if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2538                                 return -EBUSY;
2539
2540                         event->destroy = hw_perf_lbr_event_destroy;
2541                 }
2542         }
2543
2544         if (event->attr.type != PERF_TYPE_RAW)
2545                 return 0;
2546
2547         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2548                 return 0;
2549
2550         if (x86_pmu.version < 3)
2551                 return -EINVAL;
2552
2553         if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2554                 return -EACCES;
2555
2556         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2557
2558         return 0;
2559 }
2560
2561 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2562 {
2563         if (x86_pmu.guest_get_msrs)
2564                 return x86_pmu.guest_get_msrs(nr);
2565         *nr = 0;
2566         return NULL;
2567 }
2568 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2569
2570 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2571 {
2572         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2573         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2574
2575         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2576         arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2577         arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
2578         /*
2579          * If PMU counter has PEBS enabled it is not enough to disable counter
2580          * on a guest entry since PEBS memory write can overshoot guest entry
2581          * and corrupt guest memory. Disabling PEBS solves the problem.
2582          */
2583         arr[1].msr = MSR_IA32_PEBS_ENABLE;
2584         arr[1].host = cpuc->pebs_enabled;
2585         arr[1].guest = 0;
2586
2587         *nr = 2;
2588         return arr;
2589 }
2590
2591 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2592 {
2593         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2594         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2595         int idx;
2596
2597         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
2598                 struct perf_event *event = cpuc->events[idx];
2599
2600                 arr[idx].msr = x86_pmu_config_addr(idx);
2601                 arr[idx].host = arr[idx].guest = 0;
2602
2603                 if (!test_bit(idx, cpuc->active_mask))
2604                         continue;
2605
2606                 arr[idx].host = arr[idx].guest =
2607                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2608
2609                 if (event->attr.exclude_host)
2610                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2611                 else if (event->attr.exclude_guest)
2612                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2613         }
2614
2615         *nr = x86_pmu.num_counters;
2616         return arr;
2617 }
2618
2619 static void core_pmu_enable_event(struct perf_event *event)
2620 {
2621         if (!event->attr.exclude_host)
2622                 x86_pmu_enable_event(event);
2623 }
2624
2625 static void core_pmu_enable_all(int added)
2626 {
2627         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2628         int idx;
2629
2630         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2631                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2632
2633                 if (!test_bit(idx, cpuc->active_mask) ||
2634                                 cpuc->events[idx]->attr.exclude_host)
2635                         continue;
2636
2637                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2638         }
2639 }
2640
2641 static int hsw_hw_config(struct perf_event *event)
2642 {
2643         int ret = intel_pmu_hw_config(event);
2644
2645         if (ret)
2646                 return ret;
2647         if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2648                 return 0;
2649         event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2650
2651         /*
2652          * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2653          * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2654          * this combination.
2655          */
2656         if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2657              ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2658               event->attr.precise_ip > 0))
2659                 return -EOPNOTSUPP;
2660
2661         if (event_is_checkpointed(event)) {
2662                 /*
2663                  * Sampling of checkpointed events can cause situations where
2664                  * the CPU constantly aborts because of a overflow, which is
2665                  * then checkpointed back and ignored. Forbid checkpointing
2666                  * for sampling.
2667                  *
2668                  * But still allow a long sampling period, so that perf stat
2669                  * from KVM works.
2670                  */
2671                 if (event->attr.sample_period > 0 &&
2672                     event->attr.sample_period < 0x7fffffff)
2673                         return -EOPNOTSUPP;
2674         }
2675         return 0;
2676 }
2677
2678 static struct event_constraint counter2_constraint =
2679                         EVENT_CONSTRAINT(0, 0x4, 0);
2680
2681 static struct event_constraint *
2682 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2683                           struct perf_event *event)
2684 {
2685         struct event_constraint *c;
2686
2687         c = intel_get_event_constraints(cpuc, idx, event);
2688
2689         /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2690         if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2691                 if (c->idxmsk64 & (1U << 2))
2692                         return &counter2_constraint;
2693                 return &emptyconstraint;
2694         }
2695
2696         return c;
2697 }
2698
2699 /*
2700  * Broadwell:
2701  *
2702  * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2703  * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2704  * the two to enforce a minimum period of 128 (the smallest value that has bits
2705  * 0-5 cleared and >= 100).
2706  *
2707  * Because of how the code in x86_perf_event_set_period() works, the truncation
2708  * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2709  * to make up for the 'lost' events due to carrying the 'error' in period_left.
2710  *
2711  * Therefore the effective (average) period matches the requested period,
2712  * despite coarser hardware granularity.
2713  */
2714 static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2715 {
2716         if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2717                         X86_CONFIG(.event=0xc0, .umask=0x01)) {
2718                 if (left < 128)
2719                         left = 128;
2720                 left &= ~0x3fULL;
2721         }
2722         return left;
2723 }
2724
2725 PMU_FORMAT_ATTR(event,  "config:0-7"    );
2726 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
2727 PMU_FORMAT_ATTR(edge,   "config:18"     );
2728 PMU_FORMAT_ATTR(pc,     "config:19"     );
2729 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
2730 PMU_FORMAT_ATTR(inv,    "config:23"     );
2731 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
2732 PMU_FORMAT_ATTR(in_tx,  "config:32");
2733 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
2734
2735 static struct attribute *intel_arch_formats_attr[] = {
2736         &format_attr_event.attr,
2737         &format_attr_umask.attr,
2738         &format_attr_edge.attr,
2739         &format_attr_pc.attr,
2740         &format_attr_inv.attr,
2741         &format_attr_cmask.attr,
2742         NULL,
2743 };
2744
2745 ssize_t intel_event_sysfs_show(char *page, u64 config)
2746 {
2747         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2748
2749         return x86_event_sysfs_show(page, config, event);
2750 }
2751
2752 struct intel_shared_regs *allocate_shared_regs(int cpu)
2753 {
2754         struct intel_shared_regs *regs;
2755         int i;
2756
2757         regs = kzalloc_node(sizeof(struct intel_shared_regs),
2758                             GFP_KERNEL, cpu_to_node(cpu));
2759         if (regs) {
2760                 /*
2761                  * initialize the locks to keep lockdep happy
2762                  */
2763                 for (i = 0; i < EXTRA_REG_MAX; i++)
2764                         raw_spin_lock_init(&regs->regs[i].lock);
2765
2766                 regs->core_id = -1;
2767         }
2768         return regs;
2769 }
2770
2771 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2772 {
2773         struct intel_excl_cntrs *c;
2774
2775         c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2776                          GFP_KERNEL, cpu_to_node(cpu));
2777         if (c) {
2778                 raw_spin_lock_init(&c->lock);
2779                 c->core_id = -1;
2780         }
2781         return c;
2782 }
2783
2784 static int intel_pmu_cpu_prepare(int cpu)
2785 {
2786         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2787
2788         if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2789                 cpuc->shared_regs = allocate_shared_regs(cpu);
2790                 if (!cpuc->shared_regs)
2791                         goto err;
2792         }
2793
2794         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2795                 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2796
2797                 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2798                 if (!cpuc->constraint_list)
2799                         goto err_shared_regs;
2800
2801                 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
2802                 if (!cpuc->excl_cntrs)
2803                         goto err_constraint_list;
2804
2805                 cpuc->excl_thread_id = 0;
2806         }
2807
2808         return NOTIFY_OK;
2809
2810 err_constraint_list:
2811         kfree(cpuc->constraint_list);
2812         cpuc->constraint_list = NULL;
2813
2814 err_shared_regs:
2815         kfree(cpuc->shared_regs);
2816         cpuc->shared_regs = NULL;
2817
2818 err:
2819         return NOTIFY_BAD;
2820 }
2821
2822 static void intel_pmu_cpu_starting(int cpu)
2823 {
2824         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2825         int core_id = topology_core_id(cpu);
2826         int i;
2827
2828         init_debug_store_on_cpu(cpu);
2829         /*
2830          * Deal with CPUs that don't clear their LBRs on power-up.
2831          */
2832         intel_pmu_lbr_reset();
2833
2834         cpuc->lbr_sel = NULL;
2835
2836         if (!cpuc->shared_regs)
2837                 return;
2838
2839         if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
2840                 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
2841
2842                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
2843                         struct intel_shared_regs *pc;
2844
2845                         pc = per_cpu(cpu_hw_events, i).shared_regs;
2846                         if (pc && pc->core_id == core_id) {
2847                                 *onln = cpuc->shared_regs;
2848                                 cpuc->shared_regs = pc;
2849                                 break;
2850                         }
2851                 }
2852                 cpuc->shared_regs->core_id = core_id;
2853                 cpuc->shared_regs->refcnt++;
2854         }
2855
2856         if (x86_pmu.lbr_sel_map)
2857                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
2858
2859         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2860                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
2861                         struct intel_excl_cntrs *c;
2862
2863                         c = per_cpu(cpu_hw_events, i).excl_cntrs;
2864                         if (c && c->core_id == core_id) {
2865                                 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2866                                 cpuc->excl_cntrs = c;
2867                                 cpuc->excl_thread_id = 1;
2868                                 break;
2869                         }
2870                 }
2871                 cpuc->excl_cntrs->core_id = core_id;
2872                 cpuc->excl_cntrs->refcnt++;
2873         }
2874 }
2875
2876 static void free_excl_cntrs(int cpu)
2877 {
2878         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2879         struct intel_excl_cntrs *c;
2880
2881         c = cpuc->excl_cntrs;
2882         if (c) {
2883                 if (c->core_id == -1 || --c->refcnt == 0)
2884                         kfree(c);
2885                 cpuc->excl_cntrs = NULL;
2886                 kfree(cpuc->constraint_list);
2887                 cpuc->constraint_list = NULL;
2888         }
2889 }
2890
2891 static void intel_pmu_cpu_dying(int cpu)
2892 {
2893         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2894         struct intel_shared_regs *pc;
2895
2896         pc = cpuc->shared_regs;
2897         if (pc) {
2898                 if (pc->core_id == -1 || --pc->refcnt == 0)
2899                         kfree(pc);
2900                 cpuc->shared_regs = NULL;
2901         }
2902
2903         free_excl_cntrs(cpu);
2904
2905         fini_debug_store_on_cpu(cpu);
2906 }
2907
2908 static void intel_pmu_sched_task(struct perf_event_context *ctx,
2909                                  bool sched_in)
2910 {
2911         if (x86_pmu.pebs_active)
2912                 intel_pmu_pebs_sched_task(ctx, sched_in);
2913         if (x86_pmu.lbr_nr)
2914                 intel_pmu_lbr_sched_task(ctx, sched_in);
2915 }
2916
2917 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2918
2919 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2920
2921 PMU_FORMAT_ATTR(frontend, "config1:0-23");
2922
2923 static struct attribute *intel_arch3_formats_attr[] = {
2924         &format_attr_event.attr,
2925         &format_attr_umask.attr,
2926         &format_attr_edge.attr,
2927         &format_attr_pc.attr,
2928         &format_attr_any.attr,
2929         &format_attr_inv.attr,
2930         &format_attr_cmask.attr,
2931         &format_attr_in_tx.attr,
2932         &format_attr_in_tx_cp.attr,
2933
2934         &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
2935         &format_attr_ldlat.attr, /* PEBS load latency */
2936         NULL,
2937 };
2938
2939 static struct attribute *skl_format_attr[] = {
2940         &format_attr_frontend.attr,
2941         NULL,
2942 };
2943
2944 static __initconst const struct x86_pmu core_pmu = {
2945         .name                   = "core",
2946         .handle_irq             = x86_pmu_handle_irq,
2947         .disable_all            = x86_pmu_disable_all,
2948         .enable_all             = core_pmu_enable_all,
2949         .enable                 = core_pmu_enable_event,
2950         .disable                = x86_pmu_disable_event,
2951         .hw_config              = x86_pmu_hw_config,
2952         .schedule_events        = x86_schedule_events,
2953         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
2954         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
2955         .event_map              = intel_pmu_event_map,
2956         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
2957         .apic                   = 1,
2958         .free_running_flags     = PEBS_FREERUNNING_FLAGS,
2959
2960         /*
2961          * Intel PMCs cannot be accessed sanely above 32-bit width,
2962          * so we install an artificial 1<<31 period regardless of
2963          * the generic event period:
2964          */
2965         .max_period             = (1ULL<<31) - 1,
2966         .get_event_constraints  = intel_get_event_constraints,
2967         .put_event_constraints  = intel_put_event_constraints,
2968         .event_constraints      = intel_core_event_constraints,
2969         .guest_get_msrs         = core_guest_get_msrs,
2970         .format_attrs           = intel_arch_formats_attr,
2971         .events_sysfs_show      = intel_event_sysfs_show,
2972
2973         /*
2974          * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
2975          * together with PMU version 1 and thus be using core_pmu with
2976          * shared_regs. We need following callbacks here to allocate
2977          * it properly.
2978          */
2979         .cpu_prepare            = intel_pmu_cpu_prepare,
2980         .cpu_starting           = intel_pmu_cpu_starting,
2981         .cpu_dying              = intel_pmu_cpu_dying,
2982 };
2983
2984 static __initconst const struct x86_pmu intel_pmu = {
2985         .name                   = "Intel",
2986         .handle_irq             = intel_pmu_handle_irq,
2987         .disable_all            = intel_pmu_disable_all,
2988         .enable_all             = intel_pmu_enable_all,
2989         .enable                 = intel_pmu_enable_event,
2990         .disable                = intel_pmu_disable_event,
2991         .hw_config              = intel_pmu_hw_config,
2992         .schedule_events        = x86_schedule_events,
2993         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
2994         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
2995         .event_map              = intel_pmu_event_map,
2996         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
2997         .apic                   = 1,
2998         .free_running_flags     = PEBS_FREERUNNING_FLAGS,
2999         /*
3000          * Intel PMCs cannot be accessed sanely above 32 bit width,
3001          * so we install an artificial 1<<31 period regardless of
3002          * the generic event period:
3003          */
3004         .max_period             = (1ULL << 31) - 1,
3005         .get_event_constraints  = intel_get_event_constraints,
3006         .put_event_constraints  = intel_put_event_constraints,
3007         .pebs_aliases           = intel_pebs_aliases_core2,
3008
3009         .format_attrs           = intel_arch3_formats_attr,
3010         .events_sysfs_show      = intel_event_sysfs_show,
3011
3012         .cpu_prepare            = intel_pmu_cpu_prepare,
3013         .cpu_starting           = intel_pmu_cpu_starting,
3014         .cpu_dying              = intel_pmu_cpu_dying,
3015         .guest_get_msrs         = intel_guest_get_msrs,
3016         .sched_task             = intel_pmu_sched_task,
3017 };
3018
3019 static __init void intel_clovertown_quirk(void)
3020 {
3021         /*
3022          * PEBS is unreliable due to:
3023          *
3024          *   AJ67  - PEBS may experience CPL leaks
3025          *   AJ68  - PEBS PMI may be delayed by one event
3026          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3027          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3028          *
3029          * AJ67 could be worked around by restricting the OS/USR flags.
3030          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3031          *
3032          * AJ106 could possibly be worked around by not allowing LBR
3033          *       usage from PEBS, including the fixup.
3034          * AJ68  could possibly be worked around by always programming
3035          *       a pebs_event_reset[0] value and coping with the lost events.
3036          *
3037          * But taken together it might just make sense to not enable PEBS on
3038          * these chips.
3039          */
3040         pr_warn("PEBS disabled due to CPU errata\n");
3041         x86_pmu.pebs = 0;
3042         x86_pmu.pebs_constraints = NULL;
3043 }
3044
3045 static int intel_snb_pebs_broken(int cpu)
3046 {
3047         u32 rev = UINT_MAX; /* default to broken for unknown models */
3048
3049         switch (cpu_data(cpu).x86_model) {
3050         case 42: /* SNB */
3051                 rev = 0x28;
3052                 break;
3053
3054         case 45: /* SNB-EP */
3055                 switch (cpu_data(cpu).x86_stepping) {
3056                 case 6: rev = 0x618; break;
3057                 case 7: rev = 0x70c; break;
3058                 }
3059         }
3060
3061         return (cpu_data(cpu).microcode < rev);
3062 }
3063
3064 static void intel_snb_check_microcode(void)
3065 {
3066         int pebs_broken = 0;
3067         int cpu;
3068
3069         get_online_cpus();
3070         for_each_online_cpu(cpu) {
3071                 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3072                         break;
3073         }
3074         put_online_cpus();
3075
3076         if (pebs_broken == x86_pmu.pebs_broken)
3077                 return;
3078
3079         /*
3080          * Serialized by the microcode lock..
3081          */
3082         if (x86_pmu.pebs_broken) {
3083                 pr_info("PEBS enabled due to microcode update\n");
3084                 x86_pmu.pebs_broken = 0;
3085         } else {
3086                 pr_info("PEBS disabled due to CPU errata/*(DEBLOBBED)*/\n");
3087                 x86_pmu.pebs_broken = 1;
3088         }
3089 }
3090
3091 /*
3092  * Under certain circumstances, access certain MSR may cause #GP.
3093  * The function tests if the input MSR can be safely accessed.
3094  */
3095 static bool check_msr(unsigned long msr, u64 mask)
3096 {
3097         u64 val_old, val_new, val_tmp;
3098
3099         /*
3100          * Read the current value, change it and read it back to see if it
3101          * matches, this is needed to detect certain hardware emulators
3102          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3103          */
3104         if (rdmsrl_safe(msr, &val_old))
3105                 return false;
3106
3107         /*
3108          * Only change the bits which can be updated by wrmsrl.
3109          */
3110         val_tmp = val_old ^ mask;
3111         if (wrmsrl_safe(msr, val_tmp) ||
3112             rdmsrl_safe(msr, &val_new))
3113                 return false;
3114
3115         if (val_new != val_tmp)
3116                 return false;
3117
3118         /* Here it's sure that the MSR can be safely accessed.
3119          * Restore the old value and return.
3120          */
3121         wrmsrl(msr, val_old);
3122
3123         return true;
3124 }
3125
3126 static __init void intel_sandybridge_quirk(void)
3127 {
3128         x86_pmu.check_microcode = intel_snb_check_microcode;
3129         intel_snb_check_microcode();
3130 }
3131
3132 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3133         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3134         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3135         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3136         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3137         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3138         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3139         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
3140 };
3141
3142 static __init void intel_arch_events_quirk(void)
3143 {
3144         int bit;
3145
3146         /* disable event that reported as not presend by cpuid */
3147         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3148                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
3149                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3150                         intel_arch_events_map[bit].name);
3151         }
3152 }
3153
3154 static __init void intel_nehalem_quirk(void)
3155 {
3156         union cpuid10_ebx ebx;
3157
3158         ebx.full = x86_pmu.events_maskl;
3159         if (ebx.split.no_branch_misses_retired) {
3160                 /*
3161                  * Erratum AAJ80 detected, we work it around by using
3162                  * the BR_MISP_EXEC.ANY event. This will over-count
3163                  * branch-misses, but it's still much better than the
3164                  * architectural event which is often completely bogus:
3165                  */
3166                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3167                 ebx.split.no_branch_misses_retired = 0;
3168                 x86_pmu.events_maskl = ebx.full;
3169                 pr_info("CPU erratum AAJ80 worked around\n");
3170         }
3171 }
3172
3173 /*
3174  * enable software workaround for errata:
3175  * SNB: BJ122
3176  * IVB: BV98
3177  * HSW: HSD29
3178  *
3179  * Only needed when HT is enabled. However detecting
3180  * if HT is enabled is difficult (model specific). So instead,
3181  * we enable the workaround in the early boot, and verify if
3182  * it is needed in a later initcall phase once we have valid
3183  * topology information to check if HT is actually enabled
3184  */
3185 static __init void intel_ht_bug(void)
3186 {
3187         x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
3188
3189         x86_pmu.start_scheduling = intel_start_scheduling;
3190         x86_pmu.commit_scheduling = intel_commit_scheduling;
3191         x86_pmu.stop_scheduling = intel_stop_scheduling;
3192 }
3193
3194 EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
3195 EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
3196
3197 /* Haswell special events */
3198 EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
3199 EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
3200 EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
3201 EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
3202 EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
3203 EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
3204 EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
3205 EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
3206 EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
3207 EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
3208 EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
3209 EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
3210
3211 static struct attribute *hsw_events_attrs[] = {
3212         EVENT_PTR(tx_start),
3213         EVENT_PTR(tx_commit),
3214         EVENT_PTR(tx_abort),
3215         EVENT_PTR(tx_capacity),
3216         EVENT_PTR(tx_conflict),
3217         EVENT_PTR(el_start),
3218         EVENT_PTR(el_commit),
3219         EVENT_PTR(el_abort),
3220         EVENT_PTR(el_capacity),
3221         EVENT_PTR(el_conflict),
3222         EVENT_PTR(cycles_t),
3223         EVENT_PTR(cycles_ct),
3224         EVENT_PTR(mem_ld_hsw),
3225         EVENT_PTR(mem_st_hsw),
3226         NULL
3227 };
3228
3229 __init int intel_pmu_init(void)
3230 {
3231         union cpuid10_edx edx;
3232         union cpuid10_eax eax;
3233         union cpuid10_ebx ebx;
3234         struct event_constraint *c;
3235         unsigned int unused;
3236         struct extra_reg *er;
3237         int version, i;
3238
3239         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
3240                 switch (boot_cpu_data.x86) {
3241                 case 0x6:
3242                         return p6_pmu_init();
3243                 case 0xb:
3244                         return knc_pmu_init();
3245                 case 0xf:
3246                         return p4_pmu_init();
3247                 }
3248                 return -ENODEV;
3249         }
3250
3251         /*
3252          * Check whether the Architectural PerfMon supports
3253          * Branch Misses Retired hw_event or not.
3254          */
3255         cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3256         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
3257                 return -ENODEV;
3258
3259         version = eax.split.version_id;
3260         if (version < 2)
3261                 x86_pmu = core_pmu;
3262         else
3263                 x86_pmu = intel_pmu;
3264
3265         x86_pmu.version                 = version;
3266         x86_pmu.num_counters            = eax.split.num_counters;
3267         x86_pmu.cntval_bits             = eax.split.bit_width;
3268         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
3269
3270         x86_pmu.events_maskl            = ebx.full;
3271         x86_pmu.events_mask_len         = eax.split.mask_length;
3272
3273         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3274
3275         /*
3276          * Quirk: v2 perfmon does not report fixed-purpose events, so
3277          * assume at least 3 events:
3278          */
3279         if (version > 1)
3280                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
3281
3282         if (boot_cpu_has(X86_FEATURE_PDCM)) {
3283                 u64 capabilities;
3284
3285                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3286                 x86_pmu.intel_cap.capabilities = capabilities;
3287         }
3288
3289         intel_ds_init();
3290
3291         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3292
3293         /*
3294          * Install the hw-cache-events table:
3295          */
3296         switch (boot_cpu_data.x86_model) {
3297         case 14: /* 65nm Core "Yonah" */
3298                 pr_cont("Core events, ");
3299                 break;
3300
3301         case 15: /* 65nm Core2 "Merom"          */
3302                 x86_add_quirk(intel_clovertown_quirk);
3303         case 22: /* 65nm Core2 "Merom-L"        */
3304         case 23: /* 45nm Core2 "Penryn"         */
3305         case 29: /* 45nm Core2 "Dunnington (MP) */
3306                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3307                        sizeof(hw_cache_event_ids));
3308
3309                 intel_pmu_lbr_init_core();
3310
3311                 x86_pmu.event_constraints = intel_core2_event_constraints;
3312                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
3313                 pr_cont("Core2 events, ");
3314                 break;
3315
3316         case 30: /* 45nm Nehalem    */
3317         case 26: /* 45nm Nehalem-EP */
3318         case 46: /* 45nm Nehalem-EX */
3319                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3320                        sizeof(hw_cache_event_ids));
3321                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3322                        sizeof(hw_cache_extra_regs));
3323
3324                 intel_pmu_lbr_init_nhm();
3325
3326                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
3327                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
3328                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3329                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
3330
3331                 x86_pmu.cpu_events = nhm_events_attrs;
3332
3333                 /* UOPS_ISSUED.STALLED_CYCLES */
3334                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3335                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3336                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3337                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3338                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3339
3340                 intel_pmu_pebs_data_source_nhm();
3341                 x86_add_quirk(intel_nehalem_quirk);
3342
3343                 pr_cont("Nehalem events, ");
3344                 break;
3345
3346         case 28: /* 45nm Atom "Pineview"   */
3347         case 38: /* 45nm Atom "Lincroft"   */
3348         case 39: /* 32nm Atom "Penwell"    */
3349         case 53: /* 32nm Atom "Cloverview" */
3350         case 54: /* 32nm Atom "Cedarview"  */
3351                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3352                        sizeof(hw_cache_event_ids));
3353
3354                 intel_pmu_lbr_init_atom();
3355
3356                 x86_pmu.event_constraints = intel_gen_event_constraints;
3357                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
3358                 pr_cont("Atom events, ");
3359                 break;
3360
3361         case 55: /* 22nm Atom "Silvermont"                */
3362         case 76: /* 14nm Atom "Airmont"                   */
3363         case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
3364                 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3365                         sizeof(hw_cache_event_ids));
3366                 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3367                        sizeof(hw_cache_extra_regs));
3368
3369                 intel_pmu_lbr_init_atom();
3370
3371                 x86_pmu.event_constraints = intel_slm_event_constraints;
3372                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3373                 x86_pmu.extra_regs = intel_slm_extra_regs;
3374                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3375                 pr_cont("Silvermont events, ");
3376                 break;
3377
3378         case 37: /* 32nm Westmere    */
3379         case 44: /* 32nm Westmere-EP */
3380         case 47: /* 32nm Westmere-EX */
3381                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3382                        sizeof(hw_cache_event_ids));
3383                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3384                        sizeof(hw_cache_extra_regs));
3385
3386                 intel_pmu_lbr_init_nhm();
3387
3388                 x86_pmu.event_constraints = intel_westmere_event_constraints;
3389                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3390                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
3391                 x86_pmu.extra_regs = intel_westmere_extra_regs;
3392                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3393
3394                 x86_pmu.cpu_events = nhm_events_attrs;
3395
3396                 /* UOPS_ISSUED.STALLED_CYCLES */
3397                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3398                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3399                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3400                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3401                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3402
3403                 intel_pmu_pebs_data_source_nhm();
3404                 pr_cont("Westmere events, ");
3405                 break;
3406
3407         case 42: /* 32nm SandyBridge         */
3408         case 45: /* 32nm SandyBridge-E/EN/EP */
3409                 x86_add_quirk(intel_sandybridge_quirk);
3410                 x86_add_quirk(intel_ht_bug);
3411                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3412                        sizeof(hw_cache_event_ids));
3413                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3414                        sizeof(hw_cache_extra_regs));
3415
3416                 intel_pmu_lbr_init_snb();
3417
3418                 x86_pmu.event_constraints = intel_snb_event_constraints;
3419                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
3420                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3421                 if (boot_cpu_data.x86_model == 45)
3422                         x86_pmu.extra_regs = intel_snbep_extra_regs;
3423                 else
3424                         x86_pmu.extra_regs = intel_snb_extra_regs;
3425
3426
3427                 /* all extra regs are per-cpu when HT is on */
3428                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3429                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3430
3431                 x86_pmu.cpu_events = snb_events_attrs;
3432
3433                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3434                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3435                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3436                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
3437                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3438                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
3439
3440                 pr_cont("SandyBridge events, ");
3441                 break;
3442
3443         case 58: /* 22nm IvyBridge       */
3444         case 62: /* 22nm IvyBridge-EP/EX */
3445                 x86_add_quirk(intel_ht_bug);
3446                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3447                        sizeof(hw_cache_event_ids));
3448                 /* dTLB-load-misses on IVB is different than SNB */
3449                 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3450
3451                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3452                        sizeof(hw_cache_extra_regs));
3453
3454                 intel_pmu_lbr_init_snb();
3455
3456                 x86_pmu.event_constraints = intel_ivb_event_constraints;
3457                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3458                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3459                 if (boot_cpu_data.x86_model == 62)
3460                         x86_pmu.extra_regs = intel_snbep_extra_regs;
3461                 else
3462                         x86_pmu.extra_regs = intel_snb_extra_regs;
3463                 /* all extra regs are per-cpu when HT is on */
3464                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3465                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3466
3467                 x86_pmu.cpu_events = snb_events_attrs;
3468
3469                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3470                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3471                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3472
3473                 pr_cont("IvyBridge events, ");
3474                 break;
3475
3476
3477         case 60: /* 22nm Haswell Core */
3478         case 63: /* 22nm Haswell Server */
3479         case 69: /* 22nm Haswell ULT */
3480         case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
3481                 x86_add_quirk(intel_ht_bug);
3482                 x86_pmu.late_ack = true;
3483                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3484                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3485
3486                 intel_pmu_lbr_init_hsw();
3487
3488                 x86_pmu.event_constraints = intel_hsw_event_constraints;
3489                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3490                 x86_pmu.extra_regs = intel_snbep_extra_regs;
3491                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3492                 /* all extra regs are per-cpu when HT is on */
3493                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3494                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3495
3496                 x86_pmu.hw_config = hsw_hw_config;
3497                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3498                 x86_pmu.cpu_events = hsw_events_attrs;
3499                 x86_pmu.lbr_double_abort = true;
3500                 pr_cont("Haswell events, ");
3501                 break;
3502
3503         case 61: /* 14nm Broadwell Core-M */
3504         case 86: /* 14nm Broadwell Xeon D */
3505         case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
3506         case 79: /* 14nm Broadwell Server */
3507                 x86_pmu.late_ack = true;
3508                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3509                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3510
3511                 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3512                 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3513                                                                          BDW_L3_MISS|HSW_SNOOP_DRAM;
3514                 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3515                                                                           HSW_SNOOP_DRAM;
3516                 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3517                                                                              BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3518                 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3519                                                                               BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3520
3521                 intel_pmu_lbr_init_hsw();
3522
3523                 x86_pmu.event_constraints = intel_bdw_event_constraints;
3524                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3525                 x86_pmu.extra_regs = intel_snbep_extra_regs;
3526                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3527                 /* all extra regs are per-cpu when HT is on */
3528                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3529                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3530
3531                 x86_pmu.hw_config = hsw_hw_config;
3532                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3533                 x86_pmu.cpu_events = hsw_events_attrs;
3534                 x86_pmu.limit_period = bdw_limit_period;
3535                 pr_cont("Broadwell events, ");
3536                 break;
3537
3538         case 78: /* 14nm Skylake Mobile */
3539         case 94: /* 14nm Skylake Desktop */
3540                 x86_pmu.late_ack = true;
3541                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3542                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3543                 intel_pmu_lbr_init_skl();
3544
3545                 x86_pmu.event_constraints = intel_skl_event_constraints;
3546                 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3547                 x86_pmu.extra_regs = intel_skl_extra_regs;
3548                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3549                 /* all extra regs are per-cpu when HT is on */
3550                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3551                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3552
3553                 x86_pmu.hw_config = hsw_hw_config;
3554                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3555                 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
3556                                                   skl_format_attr);
3557                 WARN_ON(!x86_pmu.format_attrs);
3558                 x86_pmu.cpu_events = hsw_events_attrs;
3559                 pr_cont("Skylake events, ");
3560                 break;
3561
3562         default:
3563                 switch (x86_pmu.version) {
3564                 case 1:
3565                         x86_pmu.event_constraints = intel_v1_event_constraints;
3566                         pr_cont("generic architected perfmon v1, ");
3567                         break;
3568                 default:
3569                         /*
3570                          * default constraints for v2 and up
3571                          */
3572                         x86_pmu.event_constraints = intel_gen_event_constraints;
3573                         pr_cont("generic architected perfmon, ");
3574                         break;
3575                 }
3576         }
3577
3578         if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3579                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3580                      x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3581                 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3582         }
3583         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3584
3585         if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3586                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3587                      x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3588                 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3589         }
3590
3591         x86_pmu.intel_ctrl |=
3592                 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3593
3594         if (x86_pmu.event_constraints) {
3595                 /*
3596                  * event on fixed counter2 (REF_CYCLES) only works on this
3597                  * counter, so do not extend mask to generic counters
3598                  */
3599                 for_each_event_constraint(c, x86_pmu.event_constraints) {
3600                         if (c->cmask == FIXED_EVENT_FLAGS
3601                             && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3602                                 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
3603                         }
3604                         c->idxmsk64 &=
3605                                 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
3606                         c->weight = hweight64(c->idxmsk64);
3607                 }
3608         }
3609
3610         /*
3611          * Access LBR MSR may cause #GP under certain circumstances.
3612          * E.g. KVM doesn't support LBR MSR
3613          * Check all LBT MSR here.
3614          * Disable LBR access if any LBR MSRs can not be accessed.
3615          */
3616         if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3617                 x86_pmu.lbr_nr = 0;
3618         for (i = 0; i < x86_pmu.lbr_nr; i++) {
3619                 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3620                       check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3621                         x86_pmu.lbr_nr = 0;
3622         }
3623
3624         /*
3625          * Access extra MSR may cause #GP under certain circumstances.
3626          * E.g. KVM doesn't support offcore event
3627          * Check all extra_regs here.
3628          */
3629         if (x86_pmu.extra_regs) {
3630                 for (er = x86_pmu.extra_regs; er->msr; er++) {
3631                         er->extra_msr_access = check_msr(er->msr, 0x11UL);
3632                         /* Disable LBR select mapping */
3633                         if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3634                                 x86_pmu.lbr_sel_map = NULL;
3635                 }
3636         }
3637
3638         /* Support full width counters using alternative MSR range */
3639         if (x86_pmu.intel_cap.full_width_write) {
3640                 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
3641                 x86_pmu.perfctr = MSR_IA32_PMC0;
3642                 pr_cont("full-width counters, ");
3643         }
3644
3645         return 0;
3646 }
3647
3648 /*
3649  * HT bug: phase 2 init
3650  * Called once we have valid topology information to check
3651  * whether or not HT is enabled
3652  * If HT is off, then we disable the workaround
3653  */
3654 static __init int fixup_ht_bug(void)
3655 {
3656         int cpu = smp_processor_id();
3657         int w, c;
3658         /*
3659          * problem not present on this CPU model, nothing to do
3660          */
3661         if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3662                 return 0;
3663
3664         w = cpumask_weight(topology_sibling_cpumask(cpu));
3665         if (w > 1) {
3666                 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3667                 return 0;
3668         }
3669
3670         if (lockup_detector_suspend() != 0) {
3671                 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
3672                 return 0;
3673         }
3674
3675         x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3676
3677         x86_pmu.start_scheduling = NULL;
3678         x86_pmu.commit_scheduling = NULL;
3679         x86_pmu.stop_scheduling = NULL;
3680
3681         lockup_detector_resume();
3682
3683         get_online_cpus();
3684
3685         for_each_online_cpu(c) {
3686                 free_excl_cntrs(c);
3687         }
3688
3689         put_online_cpus();
3690         pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3691         return 0;
3692 }
3693 subsys_initcall(fixup_ht_bug)