arch/x86/kernel/fpu/regset.c

   1 /*
   2  * FPU register's regset abstraction, for ptrace, core dumps, etc.
   3  */
   4 #include <asm/fpu/internal.h>
   5 #include <asm/fpu/signal.h>
   6 #include <asm/fpu/regset.h>
   7
   8 /*
   9  * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
  10  * as the "regset->n" for the xstate regset will be updated based on the feature
  11  * capabilites supported by the xsave.
  12  */
  13 int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
  14 {
  15         struct fpu *target_fpu = &target->thread.fpu;
  16
  17         return target_fpu->fpstate_active ? regset->n : 0;
  18 }
  19
  20 int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
  21 {
  22         struct fpu *target_fpu = &target->thread.fpu;
  23
  24         return (cpu_has_fxsr && target_fpu->fpstate_active) ? regset->n : 0;
  25 }
  26
  27 int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
  28                 unsigned int pos, unsigned int count,
  29                 void *kbuf, void __user *ubuf)
  30 {
  31         struct fpu *fpu = &target->thread.fpu;
  32
  33         if (!cpu_has_fxsr)
  34                 return -ENODEV;
  35
  36         fpu__activate_fpstate_read(fpu);
  37         fpstate_sanitize_xstate(fpu);
  38
  39         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  40                                    &fpu->state.fxsave, 0, -1);
  41 }
  42
  43 int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
  44                 unsigned int pos, unsigned int count,
  45                 const void *kbuf, const void __user *ubuf)
  46 {
  47         struct fpu *fpu = &target->thread.fpu;
  48         int ret;
  49
  50         if (!cpu_has_fxsr)
  51                 return -ENODEV;
  52
  53         fpu__activate_fpstate_write(fpu);
  54         fpstate_sanitize_xstate(fpu);
  55
  56         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  57                                  &fpu->state.fxsave, 0, -1);
  58
  59         /*
  60          * mxcsr reserved bits must be masked to zero for security reasons.
  61          */
  62         fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
  63
  64         /*
  65          * update the header bits in the xsave header, indicating the
  66          * presence of FP and SSE state.
  67          */
  68         if (cpu_has_xsave)
  69                 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
  70
  71         return ret;
  72 }
  73
  74 int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
  75                 unsigned int pos, unsigned int count,
  76                 void *kbuf, void __user *ubuf)
  77 {
  78         struct fpu *fpu = &target->thread.fpu;
  79         struct xregs_state *xsave;
  80         int ret;
  81
  82         if (!cpu_has_xsave)
  83                 return -ENODEV;
  84
  85         fpu__activate_fpstate_read(fpu);
  86
  87         xsave = &fpu->state.xsave;
  88
  89         /*
  90          * Copy the 48bytes defined by the software first into the xstate
  91          * memory layout in the thread struct, so that we can copy the entire
  92          * xstateregs to the user using one user_regset_copyout().
  93          */
  94         memcpy(&xsave->i387.sw_reserved,
  95                 xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
  96         /*
  97          * Copy the xstate memory layout.
  98          */
  99         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
 100         return ret;
 101 }
 102
 103 int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
 104                   unsigned int pos, unsigned int count,
 105                   const void *kbuf, const void __user *ubuf)
 106 {
 107         struct fpu *fpu = &target->thread.fpu;
 108         struct xregs_state *xsave;
 109         int ret;
 110
 111         if (!cpu_has_xsave)
 112                 return -ENODEV;
 113
 114         fpu__activate_fpstate_write(fpu);
 115
 116         xsave = &fpu->state.xsave;
 117
 118         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
 119
 120         /* xcomp_bv must be 0 when using uncompacted format */
 121         if (!ret && xsave->header.xcomp_bv)
 122                 ret = -EINVAL;
 123
 124         /*
 125          * mxcsr reserved bits must be masked to zero for security reasons.
 126          */
 127         xsave->i387.mxcsr &= mxcsr_feature_mask;
 128         xsave->header.xfeatures &= xfeatures_mask;
 129         /*
 130          * These bits must be zero.
 131          */
 132         memset(&xsave->header.reserved, 0, 48);
 133
 134         /*
 135          * In case of failure, mark all states as init:
 136          */
 137         if (ret)
 138                 fpstate_init(&fpu->state);
 139
 140         return ret;
 141 }
 142
 143 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
 144
 145 /*
 146  * FPU tag word conversions.
 147  */
 148
 149 static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
 150 {
 151         unsigned int tmp; /* to avoid 16 bit prefixes in the code */
 152
 153         /* Transform each pair of bits into 01 (valid) or 00 (empty) */
 154         tmp = ~twd;
 155         tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
 156         /* and move the valid bits to the lower byte. */
 157         tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
 158         tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
 159         tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
 160
 161         return tmp;
 162 }
 163
 164 #define FPREG_ADDR(f, n)        ((void *)&(f)->st_space + (n) * 16)
 165 #define FP_EXP_TAG_VALID        0
 166 #define FP_EXP_TAG_ZERO         1
 167 #define FP_EXP_TAG_SPECIAL      2
 168 #define FP_EXP_TAG_EMPTY        3
 169
 170 static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
 171 {
 172         struct _fpxreg *st;
 173         u32 tos = (fxsave->swd >> 11) & 7;
 174         u32 twd = (unsigned long) fxsave->twd;
 175         u32 tag;
 176         u32 ret = 0xffff0000u;
 177         int i;
 178
 179         for (i = 0; i < 8; i++, twd >>= 1) {
 180                 if (twd & 0x1) {
 181                         st = FPREG_ADDR(fxsave, (i - tos) & 7);
 182
 183                         switch (st->exponent & 0x7fff) {
 184                         case 0x7fff:
 185                                 tag = FP_EXP_TAG_SPECIAL;
 186                                 break;
 187                         case 0x0000:
 188                                 if (!st->significand[0] &&
 189                                     !st->significand[1] &&
 190                                     !st->significand[2] &&
 191                                     !st->significand[3])
 192                                         tag = FP_EXP_TAG_ZERO;
 193                                 else
 194                                         tag = FP_EXP_TAG_SPECIAL;
 195                                 break;
 196                         default:
 197                                 if (st->significand[3] & 0x8000)
 198                                         tag = FP_EXP_TAG_VALID;
 199                                 else
 200                                         tag = FP_EXP_TAG_SPECIAL;
 201                                 break;
 202                         }
 203                 } else {
 204                         tag = FP_EXP_TAG_EMPTY;
 205                 }
 206                 ret |= tag << (2 * i);
 207         }
 208         return ret;
 209 }
 210
 211 /*
 212  * FXSR floating point environment conversions.
 213  */
 214
 215 void
 216 convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
 217 {
 218         struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
 219         struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
 220         struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
 221         int i;
 222
 223         env->cwd = fxsave->cwd | 0xffff0000u;
 224         env->swd = fxsave->swd | 0xffff0000u;
 225         env->twd = twd_fxsr_to_i387(fxsave);
 226
 227 #ifdef CONFIG_X86_64
 228         env->fip = fxsave->rip;
 229         env->foo = fxsave->rdp;
 230         /*
 231          * should be actually ds/cs at fpu exception time, but
 232          * that information is not available in 64bit mode.
 233          */
 234         env->fcs = task_pt_regs(tsk)->cs;
 235         if (tsk == current) {
 236                 savesegment(ds, env->fos);
 237         } else {
 238                 env->fos = tsk->thread.ds;
 239         }
 240         env->fos |= 0xffff0000;
 241 #else
 242         env->fip = fxsave->fip;
 243         env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
 244         env->foo = fxsave->foo;
 245         env->fos = fxsave->fos;
 246 #endif
 247
 248         for (i = 0; i < 8; ++i)
 249                 memcpy(&to[i], &from[i], sizeof(to[0]));
 250 }
 251
 252 void convert_to_fxsr(struct task_struct *tsk,
 253                      const struct user_i387_ia32_struct *env)
 254
 255 {
 256         struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
 257         struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
 258         struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
 259         int i;
 260
 261         fxsave->cwd = env->cwd;
 262         fxsave->swd = env->swd;
 263         fxsave->twd = twd_i387_to_fxsr(env->twd);
 264         fxsave->fop = (u16) ((u32) env->fcs >> 16);
 265 #ifdef CONFIG_X86_64
 266         fxsave->rip = env->fip;
 267         fxsave->rdp = env->foo;
 268         /* cs and ds ignored */
 269 #else
 270         fxsave->fip = env->fip;
 271         fxsave->fcs = (env->fcs & 0xffff);
 272         fxsave->foo = env->foo;
 273         fxsave->fos = env->fos;
 274 #endif
 275
 276         for (i = 0; i < 8; ++i)
 277                 memcpy(&to[i], &from[i], sizeof(from[0]));
 278 }
 279
 280 int fpregs_get(struct task_struct *target, const struct user_regset *regset,
 281                unsigned int pos, unsigned int count,
 282                void *kbuf, void __user *ubuf)
 283 {
 284         struct fpu *fpu = &target->thread.fpu;
 285         struct user_i387_ia32_struct env;
 286
 287         fpu__activate_fpstate_read(fpu);
 288
 289         if (!static_cpu_has(X86_FEATURE_FPU))
 290                 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
 291
 292         if (!cpu_has_fxsr)
 293                 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 294                                            &fpu->state.fsave, 0,
 295                                            -1);
 296
 297         fpstate_sanitize_xstate(fpu);
 298
 299         if (kbuf && pos == 0 && count == sizeof(env)) {
 300                 convert_from_fxsr(kbuf, target);
 301                 return 0;
 302         }
 303
 304         convert_from_fxsr(&env, target);
 305
 306         return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
 307 }
 308
 309 int fpregs_set(struct task_struct *target, const struct user_regset *regset,
 310                unsigned int pos, unsigned int count,
 311                const void *kbuf, const void __user *ubuf)
 312 {
 313         struct fpu *fpu = &target->thread.fpu;
 314         struct user_i387_ia32_struct env;
 315         int ret;
 316
 317         fpu__activate_fpstate_write(fpu);
 318         fpstate_sanitize_xstate(fpu);
 319
 320         if (!static_cpu_has(X86_FEATURE_FPU))
 321                 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
 322
 323         if (!cpu_has_fxsr)
 324                 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 325                                           &fpu->state.fsave, 0,
 326                                           -1);
 327
 328         if (pos > 0 || count < sizeof(env))
 329                 convert_from_fxsr(&env, target);
 330
 331         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
 332         if (!ret)
 333                 convert_to_fxsr(target, &env);
 334
 335         /*
 336          * update the header bit in the xsave header, indicating the
 337          * presence of FP.
 338          */
 339         if (cpu_has_xsave)
 340                 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
 341         return ret;
 342 }
 343
 344 /*
 345  * FPU state for core dumps.
 346  * This is only used for a.out dumps now.
 347  * It is declared generically using elf_fpregset_t (which is
 348  * struct user_i387_struct) but is in fact only used for 32-bit
 349  * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
 350  */
 351 int dump_fpu(struct pt_regs *regs, struct user_i387_struct *ufpu)
 352 {
 353         struct task_struct *tsk = current;
 354         struct fpu *fpu = &tsk->thread.fpu;
 355         int fpvalid;
 356
 357         fpvalid = fpu->fpstate_active;
 358         if (fpvalid)
 359                 fpvalid = !fpregs_get(tsk, NULL,
 360                                       0, sizeof(struct user_i387_ia32_struct),
 361                                       ufpu, NULL);
 362
 363         return fpvalid;
 364 }
 365 EXPORT_SYMBOL(dump_fpu);
 366
 367 #endif  /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */