1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
5 #include <linux/export.h>
6 #include <linux/delay.h>
7 #include <linux/errno.h>
8 #include <linux/i8253.h>
9 #include <linux/slab.h>
10 #include <linux/hpet.h>
11 #include <linux/init.h>
12 #include <linux/cpu.h>
16 #include <asm/cpufeature.h>
17 #include <asm/irqdomain.h>
18 #include <asm/fixmap.h>
22 #define HPET_MASK CLOCKSOURCE_MASK(32)
26 #define FSEC_PER_NSEC 1000000L
28 #define HPET_DEV_USED_BIT 2
29 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
30 #define HPET_DEV_VALID 0x8
31 #define HPET_DEV_FSB_CAP 0x1000
32 #define HPET_DEV_PERI_CAP 0x2000
34 #define HPET_MIN_CYCLES 128
35 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
38 * HPET address is set in acpi/boot.c, when an ACPI entry exists
40 unsigned long hpet_address;
41 u8 hpet_blockid; /* OS timer block num */
42 bool hpet_msi_disable;
45 static unsigned int hpet_num_timers;
47 static void __iomem *hpet_virt_address;
50 struct clock_event_device evt;
58 static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
60 return container_of(evtdev, struct hpet_dev, evt);
63 inline unsigned int hpet_readl(unsigned int a)
65 return readl(hpet_virt_address + a);
68 static inline void hpet_writel(unsigned int d, unsigned int a)
70 writel(d, hpet_virt_address + a);
74 #include <asm/pgtable.h>
77 static inline void hpet_set_mapping(void)
79 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
82 static inline void hpet_clear_mapping(void)
84 iounmap(hpet_virt_address);
85 hpet_virt_address = NULL;
89 * HPET command line enable / disable
91 bool boot_hpet_disable;
93 static bool hpet_verbose;
95 static int __init hpet_setup(char *str)
98 char *next = strchr(str, ',');
102 if (!strncmp("disable", str, 7))
103 boot_hpet_disable = true;
104 if (!strncmp("force", str, 5))
105 hpet_force_user = true;
106 if (!strncmp("verbose", str, 7))
112 __setup("hpet=", hpet_setup);
114 static int __init disable_hpet(char *str)
116 boot_hpet_disable = true;
119 __setup("nohpet", disable_hpet);
121 static inline int is_hpet_capable(void)
123 return !boot_hpet_disable && hpet_address;
127 * HPET timer interrupt enable / disable
129 static bool hpet_legacy_int_enabled;
132 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
134 int is_hpet_enabled(void)
136 return is_hpet_capable() && hpet_legacy_int_enabled;
138 EXPORT_SYMBOL_GPL(is_hpet_enabled);
140 static void _hpet_print_config(const char *function, int line)
143 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
144 l = hpet_readl(HPET_ID);
145 h = hpet_readl(HPET_PERIOD);
146 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
147 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
148 l = hpet_readl(HPET_CFG);
149 h = hpet_readl(HPET_STATUS);
150 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
151 l = hpet_readl(HPET_COUNTER);
152 h = hpet_readl(HPET_COUNTER+4);
153 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
155 for (i = 0; i < timers; i++) {
156 l = hpet_readl(HPET_Tn_CFG(i));
157 h = hpet_readl(HPET_Tn_CFG(i)+4);
158 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
160 l = hpet_readl(HPET_Tn_CMP(i));
161 h = hpet_readl(HPET_Tn_CMP(i)+4);
162 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
164 l = hpet_readl(HPET_Tn_ROUTE(i));
165 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
166 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
171 #define hpet_print_config() \
174 _hpet_print_config(__func__, __LINE__); \
178 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
179 * timer 0 and timer 1 in case of RTC emulation.
183 static void hpet_reserve_msi_timers(struct hpet_data *hd);
185 static void hpet_reserve_platform_timers(unsigned int id)
187 struct hpet __iomem *hpet = hpet_virt_address;
188 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
189 unsigned int nrtimers, i;
192 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
194 memset(&hd, 0, sizeof(hd));
195 hd.hd_phys_address = hpet_address;
196 hd.hd_address = hpet;
197 hd.hd_nirqs = nrtimers;
198 hpet_reserve_timer(&hd, 0);
200 #ifdef CONFIG_HPET_EMULATE_RTC
201 hpet_reserve_timer(&hd, 1);
205 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
206 * is wrong for i8259!) not the output IRQ. Many BIOS writers
207 * don't bother configuring *any* comparator interrupts.
209 hd.hd_irq[0] = HPET_LEGACY_8254;
210 hd.hd_irq[1] = HPET_LEGACY_RTC;
212 for (i = 2; i < nrtimers; timer++, i++) {
213 hd.hd_irq[i] = (readl(&timer->hpet_config) &
214 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
217 hpet_reserve_msi_timers(&hd);
223 static void hpet_reserve_platform_timers(unsigned int id) { }
229 static unsigned long hpet_freq;
231 static struct clock_event_device hpet_clockevent;
233 static void hpet_stop_counter(void)
235 u32 cfg = hpet_readl(HPET_CFG);
236 cfg &= ~HPET_CFG_ENABLE;
237 hpet_writel(cfg, HPET_CFG);
240 static void hpet_reset_counter(void)
242 hpet_writel(0, HPET_COUNTER);
243 hpet_writel(0, HPET_COUNTER + 4);
246 static void hpet_start_counter(void)
248 unsigned int cfg = hpet_readl(HPET_CFG);
249 cfg |= HPET_CFG_ENABLE;
250 hpet_writel(cfg, HPET_CFG);
253 static void hpet_restart_counter(void)
256 hpet_reset_counter();
257 hpet_start_counter();
260 static void hpet_resume_device(void)
265 static void hpet_resume_counter(struct clocksource *cs)
267 hpet_resume_device();
268 hpet_restart_counter();
271 static void hpet_enable_legacy_int(void)
273 unsigned int cfg = hpet_readl(HPET_CFG);
275 cfg |= HPET_CFG_LEGACY;
276 hpet_writel(cfg, HPET_CFG);
277 hpet_legacy_int_enabled = true;
280 static void hpet_legacy_clockevent_register(void)
282 /* Start HPET legacy interrupts */
283 hpet_enable_legacy_int();
286 * Start hpet with the boot cpu mask and make it
287 * global after the IO_APIC has been initialized.
289 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
290 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
291 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
292 global_clock_event = &hpet_clockevent;
293 printk(KERN_DEBUG "hpet clockevent registered\n");
296 static int hpet_set_periodic(struct clock_event_device *evt, int timer)
298 unsigned int cfg, cmp, now;
302 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
303 delta >>= evt->shift;
304 now = hpet_readl(HPET_COUNTER);
305 cmp = now + (unsigned int)delta;
306 cfg = hpet_readl(HPET_Tn_CFG(timer));
307 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
309 hpet_writel(cfg, HPET_Tn_CFG(timer));
310 hpet_writel(cmp, HPET_Tn_CMP(timer));
313 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
314 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
315 * bit is automatically cleared after the first write.
316 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
317 * Publication # 24674)
319 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
320 hpet_start_counter();
326 static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
330 cfg = hpet_readl(HPET_Tn_CFG(timer));
331 cfg &= ~HPET_TN_PERIODIC;
332 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
333 hpet_writel(cfg, HPET_Tn_CFG(timer));
338 static int hpet_shutdown(struct clock_event_device *evt, int timer)
342 cfg = hpet_readl(HPET_Tn_CFG(timer));
343 cfg &= ~HPET_TN_ENABLE;
344 hpet_writel(cfg, HPET_Tn_CFG(timer));
349 static int hpet_resume(struct clock_event_device *evt, int timer)
352 hpet_enable_legacy_int();
354 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
356 irq_domain_deactivate_irq(irq_get_irq_data(hdev->irq));
357 irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
358 disable_hardirq(hdev->irq);
359 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
360 enable_irq(hdev->irq);
367 static int hpet_next_event(unsigned long delta,
368 struct clock_event_device *evt, int timer)
373 cnt = hpet_readl(HPET_COUNTER);
375 hpet_writel(cnt, HPET_Tn_CMP(timer));
378 * HPETs are a complete disaster. The compare register is
379 * based on a equal comparison and neither provides a less
380 * than or equal functionality (which would require to take
381 * the wraparound into account) nor a simple count down event
382 * mode. Further the write to the comparator register is
383 * delayed internally up to two HPET clock cycles in certain
384 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
385 * longer delays. We worked around that by reading back the
386 * compare register, but that required another workaround for
387 * ICH9,10 chips where the first readout after write can
388 * return the old stale value. We already had a minimum
389 * programming delta of 5us enforced, but a NMI or SMI hitting
390 * between the counter readout and the comparator write can
391 * move us behind that point easily. Now instead of reading
392 * the compare register back several times, we make the ETIME
393 * decision based on the following: Return ETIME if the
394 * counter value after the write is less than HPET_MIN_CYCLES
395 * away from the event or if the counter is already ahead of
396 * the event. The minimum programming delta for the generic
397 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
399 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
401 return res < HPET_MIN_CYCLES ? -ETIME : 0;
404 static int hpet_legacy_shutdown(struct clock_event_device *evt)
406 return hpet_shutdown(evt, 0);
409 static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
411 return hpet_set_oneshot(evt, 0);
414 static int hpet_legacy_set_periodic(struct clock_event_device *evt)
416 return hpet_set_periodic(evt, 0);
419 static int hpet_legacy_resume(struct clock_event_device *evt)
421 return hpet_resume(evt, 0);
424 static int hpet_legacy_next_event(unsigned long delta,
425 struct clock_event_device *evt)
427 return hpet_next_event(delta, evt, 0);
431 * The hpet clock event device
433 static struct clock_event_device hpet_clockevent = {
435 .features = CLOCK_EVT_FEAT_PERIODIC |
436 CLOCK_EVT_FEAT_ONESHOT,
437 .set_state_periodic = hpet_legacy_set_periodic,
438 .set_state_oneshot = hpet_legacy_set_oneshot,
439 .set_state_shutdown = hpet_legacy_shutdown,
440 .tick_resume = hpet_legacy_resume,
441 .set_next_event = hpet_legacy_next_event,
449 #ifdef CONFIG_PCI_MSI
451 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
452 static struct hpet_dev *hpet_devs;
453 static struct irq_domain *hpet_domain;
455 void hpet_msi_unmask(struct irq_data *data)
457 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
461 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
462 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
463 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
466 void hpet_msi_mask(struct irq_data *data)
468 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
472 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
473 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
474 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
477 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
479 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
480 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
483 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
485 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
486 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
490 static int hpet_msi_shutdown(struct clock_event_device *evt)
492 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
494 return hpet_shutdown(evt, hdev->num);
497 static int hpet_msi_set_oneshot(struct clock_event_device *evt)
499 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
501 return hpet_set_oneshot(evt, hdev->num);
504 static int hpet_msi_set_periodic(struct clock_event_device *evt)
506 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
508 return hpet_set_periodic(evt, hdev->num);
511 static int hpet_msi_resume(struct clock_event_device *evt)
513 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
515 return hpet_resume(evt, hdev->num);
518 static int hpet_msi_next_event(unsigned long delta,
519 struct clock_event_device *evt)
521 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
522 return hpet_next_event(delta, evt, hdev->num);
525 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
527 struct hpet_dev *dev = (struct hpet_dev *)data;
528 struct clock_event_device *hevt = &dev->evt;
530 if (!hevt->event_handler) {
531 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
536 hevt->event_handler(hevt);
540 static int hpet_setup_irq(struct hpet_dev *dev)
543 if (request_irq(dev->irq, hpet_interrupt_handler,
544 IRQF_TIMER | IRQF_NOBALANCING,
548 disable_irq(dev->irq);
549 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
550 enable_irq(dev->irq);
552 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
553 dev->name, dev->irq);
558 /* This should be called in specific @cpu */
559 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
561 struct clock_event_device *evt = &hdev->evt;
563 WARN_ON(cpu != smp_processor_id());
564 if (!(hdev->flags & HPET_DEV_VALID))
568 per_cpu(cpu_hpet_dev, cpu) = hdev;
569 evt->name = hdev->name;
570 hpet_setup_irq(hdev);
571 evt->irq = hdev->irq;
574 evt->features = CLOCK_EVT_FEAT_ONESHOT;
575 if (hdev->flags & HPET_DEV_PERI_CAP) {
576 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
577 evt->set_state_periodic = hpet_msi_set_periodic;
580 evt->set_state_shutdown = hpet_msi_shutdown;
581 evt->set_state_oneshot = hpet_msi_set_oneshot;
582 evt->tick_resume = hpet_msi_resume;
583 evt->set_next_event = hpet_msi_next_event;
584 evt->cpumask = cpumask_of(hdev->cpu);
586 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
591 /* Reserve at least one timer for userspace (/dev/hpet) */
592 #define RESERVE_TIMERS 1
594 #define RESERVE_TIMERS 0
597 static void hpet_msi_capability_lookup(unsigned int start_timer)
600 unsigned int num_timers;
601 unsigned int num_timers_used = 0;
604 if (hpet_msi_disable)
607 if (boot_cpu_has(X86_FEATURE_ARAT))
609 id = hpet_readl(HPET_ID);
611 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
612 num_timers++; /* Value read out starts from 0 */
615 hpet_domain = hpet_create_irq_domain(hpet_blockid);
619 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
623 hpet_num_timers = num_timers;
625 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
626 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
627 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
629 /* Only consider HPET timer with MSI support */
630 if (!(cfg & HPET_TN_FSB_CAP))
634 if (cfg & HPET_TN_PERIODIC_CAP)
635 hdev->flags |= HPET_DEV_PERI_CAP;
636 sprintf(hdev->name, "hpet%d", i);
639 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
644 hdev->flags |= HPET_DEV_FSB_CAP;
645 hdev->flags |= HPET_DEV_VALID;
647 if (num_timers_used == num_possible_cpus())
651 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
652 num_timers, num_timers_used);
656 static void hpet_reserve_msi_timers(struct hpet_data *hd)
663 for (i = 0; i < hpet_num_timers; i++) {
664 struct hpet_dev *hdev = &hpet_devs[i];
666 if (!(hdev->flags & HPET_DEV_VALID))
669 hd->hd_irq[hdev->num] = hdev->irq;
670 hpet_reserve_timer(hd, hdev->num);
675 static struct hpet_dev *hpet_get_unused_timer(void)
682 for (i = 0; i < hpet_num_timers; i++) {
683 struct hpet_dev *hdev = &hpet_devs[i];
685 if (!(hdev->flags & HPET_DEV_VALID))
687 if (test_and_set_bit(HPET_DEV_USED_BIT,
688 (unsigned long *)&hdev->flags))
695 struct hpet_work_struct {
696 struct delayed_work work;
697 struct completion complete;
700 static void hpet_work(struct work_struct *w)
702 struct hpet_dev *hdev;
703 int cpu = smp_processor_id();
704 struct hpet_work_struct *hpet_work;
706 hpet_work = container_of(w, struct hpet_work_struct, work.work);
708 hdev = hpet_get_unused_timer();
710 init_one_hpet_msi_clockevent(hdev, cpu);
712 complete(&hpet_work->complete);
715 static int hpet_cpuhp_online(unsigned int cpu)
717 struct hpet_work_struct work;
719 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
720 init_completion(&work.complete);
721 /* FIXME: add schedule_work_on() */
722 schedule_delayed_work_on(cpu, &work.work, 0);
723 wait_for_completion(&work.complete);
724 destroy_delayed_work_on_stack(&work.work);
728 static int hpet_cpuhp_dead(unsigned int cpu)
730 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
734 free_irq(hdev->irq, hdev);
735 hdev->flags &= ~HPET_DEV_USED;
736 per_cpu(cpu_hpet_dev, cpu) = NULL;
741 static void hpet_msi_capability_lookup(unsigned int start_timer)
747 static void hpet_reserve_msi_timers(struct hpet_data *hd)
753 #define hpet_cpuhp_online NULL
754 #define hpet_cpuhp_dead NULL
759 * Clock source related code
761 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
763 * Reading the HPET counter is a very slow operation. If a large number of
764 * CPUs are trying to access the HPET counter simultaneously, it can cause
765 * massive delay and slow down system performance dramatically. This may
766 * happen when HPET is the default clock source instead of TSC. For a
767 * really large system with hundreds of CPUs, the slowdown may be so
768 * severe that it may actually crash the system because of a NMI watchdog
769 * soft lockup, for example.
771 * If multiple CPUs are trying to access the HPET counter at the same time,
772 * we don't actually need to read the counter multiple times. Instead, the
773 * other CPUs can use the counter value read by the first CPU in the group.
775 * This special feature is only enabled on x86-64 systems. It is unlikely
776 * that 32-bit x86 systems will have enough CPUs to require this feature
777 * with its associated locking overhead. And we also need 64-bit atomic
780 * The lock and the hpet value are stored together and can be read in a
781 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
782 * is 32 bits in size.
786 arch_spinlock_t lock;
792 static union hpet_lock hpet __cacheline_aligned = {
793 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
796 static cycle_t read_hpet(struct clocksource *cs)
799 union hpet_lock old, new;
801 BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
804 * Read HPET directly if in NMI.
807 return (cycle_t)hpet_readl(HPET_COUNTER);
810 * Read the current state of the lock and HPET value atomically.
812 old.lockval = READ_ONCE(hpet.lockval);
814 if (arch_spin_is_locked(&old.lock))
817 local_irq_save(flags);
818 if (arch_spin_trylock(&hpet.lock)) {
819 new.value = hpet_readl(HPET_COUNTER);
821 * Use WRITE_ONCE() to prevent store tearing.
823 WRITE_ONCE(hpet.value, new.value);
824 arch_spin_unlock(&hpet.lock);
825 local_irq_restore(flags);
826 return (cycle_t)new.value;
828 local_irq_restore(flags);
834 * Wait until the HPET value change or the lock is free to indicate
835 * its value is up-to-date.
837 * It is possible that old.value has already contained the latest
838 * HPET value while the lock holder was in the process of releasing
839 * the lock. Checking for lock state change will enable us to return
840 * the value immediately instead of waiting for the next HPET reader
845 new.lockval = READ_ONCE(hpet.lockval);
846 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
848 return (cycle_t)new.value;
854 static cycle_t read_hpet(struct clocksource *cs)
856 return (cycle_t)hpet_readl(HPET_COUNTER);
860 static struct clocksource clocksource_hpet = {
865 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
866 .resume = hpet_resume_counter,
869 static int hpet_clocksource_register(void)
874 /* Start the counter */
875 hpet_restart_counter();
877 /* Verify whether hpet counter works */
878 t1 = hpet_readl(HPET_COUNTER);
882 * We don't know the TSC frequency yet, but waiting for
883 * 200000 TSC cycles is safe:
890 } while ((now - start) < 200000UL);
892 if (t1 == hpet_readl(HPET_COUNTER)) {
894 "HPET counter not counting. HPET disabled\n");
898 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
902 static u32 *hpet_boot_cfg;
905 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
907 int __init hpet_enable(void)
909 u32 hpet_period, cfg, id;
911 unsigned int i, last;
913 if (!is_hpet_capable())
917 if (!hpet_virt_address)
921 * Read the period and check for a sane value:
923 hpet_period = hpet_readl(HPET_PERIOD);
926 * AMD SB700 based systems with spread spectrum enabled use a
927 * SMM based HPET emulation to provide proper frequency
928 * setting. The SMM code is initialized with the first HPET
929 * register access and takes some time to complete. During
930 * this time the config register reads 0xffffffff. We check
931 * for max. 1000 loops whether the config register reads a non
932 * 0xffffffff value to make sure that HPET is up and running
933 * before we go further. A counting loop is safe, as the HPET
934 * access takes thousands of CPU cycles. On non SB700 based
935 * machines this check is only done once and has no side
938 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
941 "HPET config register value = 0xFFFFFFFF. "
947 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
951 * The period is a femto seconds value. Convert it to a
955 do_div(freq, hpet_period);
959 * Read the HPET ID register to retrieve the IRQ routing
960 * information and the number of channels
962 id = hpet_readl(HPET_ID);
965 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
967 #ifdef CONFIG_HPET_EMULATE_RTC
969 * The legacy routing mode needs at least two channels, tick timer
970 * and the rtc emulation channel.
976 cfg = hpet_readl(HPET_CFG);
977 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
980 *hpet_boot_cfg = cfg;
982 pr_warn("HPET initial state will not be saved\n");
983 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
984 hpet_writel(cfg, HPET_CFG);
986 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
989 for (i = 0; i <= last; ++i) {
990 cfg = hpet_readl(HPET_Tn_CFG(i));
992 hpet_boot_cfg[i + 1] = cfg;
993 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
994 hpet_writel(cfg, HPET_Tn_CFG(i));
995 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
996 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
997 | HPET_TN_FSB | HPET_TN_FSB_CAP);
999 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
1002 hpet_print_config();
1004 if (hpet_clocksource_register())
1007 if (id & HPET_ID_LEGSUP) {
1008 hpet_legacy_clockevent_register();
1014 hpet_clear_mapping();
1020 * Needs to be late, as the reserve_timer code calls kalloc !
1022 * Not a problem on i386 as hpet_enable is called from late_time_init,
1023 * but on x86_64 it is necessary !
1025 static __init int hpet_late_init(void)
1029 if (boot_hpet_disable)
1032 if (!hpet_address) {
1033 if (!force_hpet_address)
1036 hpet_address = force_hpet_address;
1040 if (!hpet_virt_address)
1043 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
1044 hpet_msi_capability_lookup(2);
1046 hpet_msi_capability_lookup(0);
1048 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
1049 hpet_print_config();
1051 if (hpet_msi_disable)
1054 if (boot_cpu_has(X86_FEATURE_ARAT))
1057 /* This notifier should be called after workqueue is ready */
1058 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "AP_X86_HPET_ONLINE",
1059 hpet_cpuhp_online, NULL);
1062 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "X86_HPET_DEAD", NULL,
1069 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
1072 fs_initcall(hpet_late_init);
1074 void hpet_disable(void)
1076 if (is_hpet_capable() && hpet_virt_address) {
1077 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
1080 cfg = *hpet_boot_cfg;
1081 else if (hpet_legacy_int_enabled) {
1082 cfg &= ~HPET_CFG_LEGACY;
1083 hpet_legacy_int_enabled = false;
1085 cfg &= ~HPET_CFG_ENABLE;
1086 hpet_writel(cfg, HPET_CFG);
1091 id = hpet_readl(HPET_ID);
1092 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
1094 for (id = 0; id <= last; ++id)
1095 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1097 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1098 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1102 #ifdef CONFIG_HPET_EMULATE_RTC
1104 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1105 * is enabled, we support RTC interrupt functionality in software.
1106 * RTC has 3 kinds of interrupts:
1107 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1109 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1110 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1111 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1112 * (1) and (2) above are implemented using polling at a frequency of
1113 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1114 * overhead. (DEFAULT_RTC_INT_FREQ)
1115 * For (3), we use interrupts at 64Hz or user specified periodic
1116 * frequency, whichever is higher.
1118 #include <linux/mc146818rtc.h>
1119 #include <linux/rtc.h>
1121 #define DEFAULT_RTC_INT_FREQ 64
1122 #define DEFAULT_RTC_SHIFT 6
1123 #define RTC_NUM_INTS 1
1125 static unsigned long hpet_rtc_flags;
1126 static int hpet_prev_update_sec;
1127 static struct rtc_time hpet_alarm_time;
1128 static unsigned long hpet_pie_count;
1129 static u32 hpet_t1_cmp;
1130 static u32 hpet_default_delta;
1131 static u32 hpet_pie_delta;
1132 static unsigned long hpet_pie_limit;
1134 static rtc_irq_handler irq_handler;
1137 * Check that the hpet counter c1 is ahead of the c2
1139 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1141 return (s32)(c2 - c1) < 0;
1145 * Registers a IRQ handler.
1147 int hpet_register_irq_handler(rtc_irq_handler handler)
1149 if (!is_hpet_enabled())
1154 irq_handler = handler;
1158 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1161 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1164 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1166 if (!is_hpet_enabled())
1172 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1175 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1176 * is not supported by all HPET implementations for timer 1.
1178 * hpet_rtc_timer_init() is called when the rtc is initialized.
1180 int hpet_rtc_timer_init(void)
1182 unsigned int cfg, cnt, delta;
1183 unsigned long flags;
1185 if (!is_hpet_enabled())
1188 if (!hpet_default_delta) {
1191 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1192 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1193 hpet_default_delta = clc;
1196 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1197 delta = hpet_default_delta;
1199 delta = hpet_pie_delta;
1201 local_irq_save(flags);
1203 cnt = delta + hpet_readl(HPET_COUNTER);
1204 hpet_writel(cnt, HPET_T1_CMP);
1207 cfg = hpet_readl(HPET_T1_CFG);
1208 cfg &= ~HPET_TN_PERIODIC;
1209 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1210 hpet_writel(cfg, HPET_T1_CFG);
1212 local_irq_restore(flags);
1216 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1218 static void hpet_disable_rtc_channel(void)
1220 u32 cfg = hpet_readl(HPET_T1_CFG);
1221 cfg &= ~HPET_TN_ENABLE;
1222 hpet_writel(cfg, HPET_T1_CFG);
1226 * The functions below are called from rtc driver.
1227 * Return 0 if HPET is not being used.
1228 * Otherwise do the necessary changes and return 1.
1230 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1232 if (!is_hpet_enabled())
1235 hpet_rtc_flags &= ~bit_mask;
1236 if (unlikely(!hpet_rtc_flags))
1237 hpet_disable_rtc_channel();
1241 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1243 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1245 unsigned long oldbits = hpet_rtc_flags;
1247 if (!is_hpet_enabled())
1250 hpet_rtc_flags |= bit_mask;
1252 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1253 hpet_prev_update_sec = -1;
1256 hpet_rtc_timer_init();
1260 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1262 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1265 if (!is_hpet_enabled())
1268 hpet_alarm_time.tm_hour = hrs;
1269 hpet_alarm_time.tm_min = min;
1270 hpet_alarm_time.tm_sec = sec;
1274 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1276 int hpet_set_periodic_freq(unsigned long freq)
1280 if (!is_hpet_enabled())
1283 if (freq <= DEFAULT_RTC_INT_FREQ)
1284 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1286 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1288 clc >>= hpet_clockevent.shift;
1289 hpet_pie_delta = clc;
1294 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1296 int hpet_rtc_dropped_irq(void)
1298 return is_hpet_enabled();
1300 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1302 static void hpet_rtc_timer_reinit(void)
1307 if (unlikely(!hpet_rtc_flags))
1308 hpet_disable_rtc_channel();
1310 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1311 delta = hpet_default_delta;
1313 delta = hpet_pie_delta;
1316 * Increment the comparator value until we are ahead of the
1320 hpet_t1_cmp += delta;
1321 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1323 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1326 if (hpet_rtc_flags & RTC_PIE)
1327 hpet_pie_count += lost_ints;
1328 if (printk_ratelimit())
1329 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1334 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1336 struct rtc_time curr_time;
1337 unsigned long rtc_int_flag = 0;
1339 hpet_rtc_timer_reinit();
1340 memset(&curr_time, 0, sizeof(struct rtc_time));
1342 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1343 mc146818_get_time(&curr_time);
1345 if (hpet_rtc_flags & RTC_UIE &&
1346 curr_time.tm_sec != hpet_prev_update_sec) {
1347 if (hpet_prev_update_sec >= 0)
1348 rtc_int_flag = RTC_UF;
1349 hpet_prev_update_sec = curr_time.tm_sec;
1352 if (hpet_rtc_flags & RTC_PIE &&
1353 ++hpet_pie_count >= hpet_pie_limit) {
1354 rtc_int_flag |= RTC_PF;
1358 if (hpet_rtc_flags & RTC_AIE &&
1359 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1360 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1361 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1362 rtc_int_flag |= RTC_AF;
1365 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1367 irq_handler(rtc_int_flag, dev_id);
1371 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);