arch/x86/kernel/irq.c

   1 /*
   2  * Common interrupt code for 32 and 64 bit
   3  */
   4 #include <linux/cpu.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/kernel_stat.h>
   7 #include <linux/of.h>
   8 #include <linux/seq_file.h>
   9 #include <linux/smp.h>
  10 #include <linux/ftrace.h>
  11 #include <linux/delay.h>
  12 #include <linux/export.h>
  13 #include <linux/irq.h>
  14
  15 #include <asm/apic.h>
  16 #include <asm/io_apic.h>
  17 #include <asm/irq.h>
  18 #include <asm/idle.h>
  19 #include <asm/mce.h>
  20 #include <asm/hw_irq.h>
  21 #include <asm/desc.h>
  22
  23 #define CREATE_TRACE_POINTS
  24 #include <asm/trace/irq_vectors.h>
  25
  26 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
  27 EXPORT_PER_CPU_SYMBOL(irq_stat);
  28
  29 DEFINE_PER_CPU(struct pt_regs *, irq_regs);
  30 EXPORT_PER_CPU_SYMBOL(irq_regs);
  31
  32 atomic_t irq_err_count;
  33
  34 /* Function pointer for generic interrupt vector handling */
  35 void (*x86_platform_ipi_callback)(void) = NULL;
  36
  37 /*
  38  * 'what should we do if we get a hw irq event on an illegal vector'.
  39  * each architecture has to answer this themselves.
  40  */
  41 void ack_bad_irq(unsigned int irq)
  42 {
  43         if (printk_ratelimit())
  44                 pr_err("unexpected IRQ trap at vector %02x\n", irq);
  45
  46         /*
  47          * Currently unexpected vectors happen only on SMP and APIC.
  48          * We _must_ ack these because every local APIC has only N
  49          * irq slots per priority level, and a 'hanging, unacked' IRQ
  50          * holds up an irq slot - in excessive cases (when multiple
  51          * unexpected vectors occur) that might lock up the APIC
  52          * completely.
  53          * But only ack when the APIC is enabled -AK
  54          */
  55         ack_APIC_irq();
  56 }
  57
  58 #define irq_stats(x)            (&per_cpu(irq_stat, x))
  59 /*
  60  * /proc/interrupts printing for arch specific interrupts
  61  */
  62 int arch_show_interrupts(struct seq_file *p, int prec)
  63 {
  64         int j;
  65
  66         seq_printf(p, "%*s: ", prec, "NMI");
  67         for_each_online_cpu(j)
  68                 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
  69         seq_puts(p, "  Non-maskable interrupts\n");
  70 #ifdef CONFIG_X86_LOCAL_APIC
  71         seq_printf(p, "%*s: ", prec, "LOC");
  72         for_each_online_cpu(j)
  73                 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
  74         seq_puts(p, "  Local timer interrupts\n");
  75
  76         seq_printf(p, "%*s: ", prec, "SPU");
  77         for_each_online_cpu(j)
  78                 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
  79         seq_puts(p, "  Spurious interrupts\n");
  80         seq_printf(p, "%*s: ", prec, "PMI");
  81         for_each_online_cpu(j)
  82                 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
  83         seq_puts(p, "  Performance monitoring interrupts\n");
  84         seq_printf(p, "%*s: ", prec, "IWI");
  85         for_each_online_cpu(j)
  86                 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
  87         seq_puts(p, "  IRQ work interrupts\n");
  88         seq_printf(p, "%*s: ", prec, "RTR");
  89         for_each_online_cpu(j)
  90                 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
  91         seq_puts(p, "  APIC ICR read retries\n");
  92 #endif
  93         if (x86_platform_ipi_callback) {
  94                 seq_printf(p, "%*s: ", prec, "PLT");
  95                 for_each_online_cpu(j)
  96                         seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
  97                 seq_puts(p, "  Platform interrupts\n");
  98         }
  99 #ifdef CONFIG_SMP
 100         seq_printf(p, "%*s: ", prec, "RES");
 101         for_each_online_cpu(j)
 102                 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
 103         seq_puts(p, "  Rescheduling interrupts\n");
 104         seq_printf(p, "%*s: ", prec, "CAL");
 105         for_each_online_cpu(j)
 106                 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
 107         seq_puts(p, "  Function call interrupts\n");
 108         seq_printf(p, "%*s: ", prec, "TLB");
 109         for_each_online_cpu(j)
 110                 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
 111         seq_puts(p, "  TLB shootdowns\n");
 112 #endif
 113 #ifdef CONFIG_X86_THERMAL_VECTOR
 114         seq_printf(p, "%*s: ", prec, "TRM");
 115         for_each_online_cpu(j)
 116                 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
 117         seq_puts(p, "  Thermal event interrupts\n");
 118 #endif
 119 #ifdef CONFIG_X86_MCE_THRESHOLD
 120         seq_printf(p, "%*s: ", prec, "THR");
 121         for_each_online_cpu(j)
 122                 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
 123         seq_puts(p, "  Threshold APIC interrupts\n");
 124 #endif
 125 #ifdef CONFIG_X86_MCE_AMD
 126         seq_printf(p, "%*s: ", prec, "DFR");
 127         for_each_online_cpu(j)
 128                 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
 129         seq_puts(p, "  Deferred Error APIC interrupts\n");
 130 #endif
 131 #ifdef CONFIG_X86_MCE
 132         seq_printf(p, "%*s: ", prec, "MCE");
 133         for_each_online_cpu(j)
 134                 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
 135         seq_puts(p, "  Machine check exceptions\n");
 136         seq_printf(p, "%*s: ", prec, "MCP");
 137         for_each_online_cpu(j)
 138                 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
 139         seq_puts(p, "  Machine check polls\n");
 140 #endif
 141 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
 142         if (test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) {
 143                 seq_printf(p, "%*s: ", prec, "HYP");
 144                 for_each_online_cpu(j)
 145                         seq_printf(p, "%10u ",
 146                                    irq_stats(j)->irq_hv_callback_count);
 147                 seq_puts(p, "  Hypervisor callback interrupts\n");
 148         }
 149 #endif
 150         seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
 151 #if defined(CONFIG_X86_IO_APIC)
 152         seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
 153 #endif
 154 #ifdef CONFIG_HAVE_KVM
 155         seq_printf(p, "%*s: ", prec, "PIN");
 156         for_each_online_cpu(j)
 157                 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
 158         seq_puts(p, "  Posted-interrupt notification event\n");
 159
 160         seq_printf(p, "%*s: ", prec, "PIW");
 161         for_each_online_cpu(j)
 162                 seq_printf(p, "%10u ",
 163                            irq_stats(j)->kvm_posted_intr_wakeup_ipis);
 164         seq_puts(p, "  Posted-interrupt wakeup event\n");
 165 #endif
 166         return 0;
 167 }
 168
 169 /*
 170  * /proc/stat helpers
 171  */
 172 u64 arch_irq_stat_cpu(unsigned int cpu)
 173 {
 174         u64 sum = irq_stats(cpu)->__nmi_count;
 175
 176 #ifdef CONFIG_X86_LOCAL_APIC
 177         sum += irq_stats(cpu)->apic_timer_irqs;
 178         sum += irq_stats(cpu)->irq_spurious_count;
 179         sum += irq_stats(cpu)->apic_perf_irqs;
 180         sum += irq_stats(cpu)->apic_irq_work_irqs;
 181         sum += irq_stats(cpu)->icr_read_retry_count;
 182 #endif
 183         if (x86_platform_ipi_callback)
 184                 sum += irq_stats(cpu)->x86_platform_ipis;
 185 #ifdef CONFIG_SMP
 186         sum += irq_stats(cpu)->irq_resched_count;
 187         sum += irq_stats(cpu)->irq_call_count;
 188 #endif
 189 #ifdef CONFIG_X86_THERMAL_VECTOR
 190         sum += irq_stats(cpu)->irq_thermal_count;
 191 #endif
 192 #ifdef CONFIG_X86_MCE_THRESHOLD
 193         sum += irq_stats(cpu)->irq_threshold_count;
 194 #endif
 195 #ifdef CONFIG_X86_MCE
 196         sum += per_cpu(mce_exception_count, cpu);
 197         sum += per_cpu(mce_poll_count, cpu);
 198 #endif
 199         return sum;
 200 }
 201
 202 u64 arch_irq_stat(void)
 203 {
 204         u64 sum = atomic_read(&irq_err_count);
 205         return sum;
 206 }
 207
 208
 209 /*
 210  * do_IRQ handles all normal device IRQ's (the special
 211  * SMP cross-CPU interrupts have their own specific
 212  * handlers).
 213  */
 214 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
 215 {
 216         struct pt_regs *old_regs = set_irq_regs(regs);
 217         struct irq_desc * desc;
 218         /* high bit used in ret_from_ code  */
 219         unsigned vector = ~regs->orig_ax;
 220
 221         /*
 222          * NB: Unlike exception entries, IRQ entries do not reliably
 223          * handle context tracking in the low-level entry code.  This is
 224          * because syscall entries execute briefly with IRQs on before
 225          * updating context tracking state, so we can take an IRQ from
 226          * kernel mode with CONTEXT_USER.  The low-level entry code only
 227          * updates the context if we came from user mode, so we won't
 228          * switch to CONTEXT_KERNEL.  We'll fix that once the syscall
 229          * code is cleaned up enough that we can cleanly defer enabling
 230          * IRQs.
 231          */
 232
 233         entering_irq();
 234
 235         /* entering_irq() tells RCU that we're not quiescent.  Check it. */
 236         RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
 237
 238         desc = __this_cpu_read(vector_irq[vector]);
 239
 240         if (!handle_irq(desc, regs)) {
 241                 ack_APIC_irq();
 242
 243                 if (desc != VECTOR_RETRIGGERED) {
 244                         pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
 245                                              __func__, smp_processor_id(),
 246                                              vector);
 247                 } else {
 248                         __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
 249                 }
 250         }
 251
 252         exiting_irq();
 253
 254         set_irq_regs(old_regs);
 255         return 1;
 256 }
 257
 258 /*
 259  * Handler for X86_PLATFORM_IPI_VECTOR.
 260  */
 261 void __smp_x86_platform_ipi(void)
 262 {
 263         inc_irq_stat(x86_platform_ipis);
 264
 265         if (x86_platform_ipi_callback)
 266                 x86_platform_ipi_callback();
 267 }
 268
 269 __visible void __irq_entry smp_x86_platform_ipi(struct pt_regs *regs)
 270 {
 271         struct pt_regs *old_regs = set_irq_regs(regs);
 272
 273         entering_ack_irq();
 274         __smp_x86_platform_ipi();
 275         exiting_irq();
 276         set_irq_regs(old_regs);
 277 }
 278
 279 #ifdef CONFIG_HAVE_KVM
 280 static void dummy_handler(void) {}
 281 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
 282
 283 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
 284 {
 285         if (handler)
 286                 kvm_posted_intr_wakeup_handler = handler;
 287         else {
 288                 kvm_posted_intr_wakeup_handler = dummy_handler;
 289                 synchronize_rcu();
 290         }
 291 }
 292 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
 293
 294 /*
 295  * Handler for POSTED_INTERRUPT_VECTOR.
 296  */
 297 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
 298 {
 299         struct pt_regs *old_regs = set_irq_regs(regs);
 300
 301         entering_ack_irq();
 302         inc_irq_stat(kvm_posted_intr_ipis);
 303         exiting_irq();
 304         set_irq_regs(old_regs);
 305 }
 306
 307 /*
 308  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
 309  */
 310 __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
 311 {
 312         struct pt_regs *old_regs = set_irq_regs(regs);
 313
 314         entering_ack_irq();
 315         inc_irq_stat(kvm_posted_intr_wakeup_ipis);
 316         kvm_posted_intr_wakeup_handler();
 317         exiting_irq();
 318         set_irq_regs(old_regs);
 319 }
 320 #endif
 321
 322 __visible void __irq_entry smp_trace_x86_platform_ipi(struct pt_regs *regs)
 323 {
 324         struct pt_regs *old_regs = set_irq_regs(regs);
 325
 326         entering_ack_irq();
 327         trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
 328         __smp_x86_platform_ipi();
 329         trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
 330         exiting_irq();
 331         set_irq_regs(old_regs);
 332 }
 333
 334 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
 335
 336 #ifdef CONFIG_HOTPLUG_CPU
 337
 338 /* These two declarations are only used in check_irq_vectors_for_cpu_disable()
 339  * below, which is protected by stop_machine().  Putting them on the stack
 340  * results in a stack frame overflow.  Dynamically allocating could result in a
 341  * failure so declare these two cpumasks as global.
 342  */
 343 static struct cpumask affinity_new, online_new;
 344
 345 /*
 346  * This cpu is going to be removed and its vectors migrated to the remaining
 347  * online cpus.  Check to see if there are enough vectors in the remaining cpus.
 348  * This function is protected by stop_machine().
 349  */
 350 int check_irq_vectors_for_cpu_disable(void)
 351 {
 352         unsigned int this_cpu, vector, this_count, count;
 353         struct irq_desc *desc;
 354         struct irq_data *data;
 355         int cpu;
 356
 357         this_cpu = smp_processor_id();
 358         cpumask_copy(&online_new, cpu_online_mask);
 359         cpumask_clear_cpu(this_cpu, &online_new);
 360
 361         this_count = 0;
 362         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 363                 desc = __this_cpu_read(vector_irq[vector]);
 364                 if (IS_ERR_OR_NULL(desc))
 365                         continue;
 366                 /*
 367                  * Protect against concurrent action removal, affinity
 368                  * changes etc.
 369                  */
 370                 raw_spin_lock(&desc->lock);
 371                 data = irq_desc_get_irq_data(desc);
 372                 cpumask_copy(&affinity_new,
 373                              irq_data_get_affinity_mask(data));
 374                 cpumask_clear_cpu(this_cpu, &affinity_new);
 375
 376                 /* Do not count inactive or per-cpu irqs. */
 377                 if (!irq_desc_has_action(desc) || irqd_is_per_cpu(data)) {
 378                         raw_spin_unlock(&desc->lock);
 379                         continue;
 380                 }
 381
 382                 raw_spin_unlock(&desc->lock);
 383                 /*
 384                  * A single irq may be mapped to multiple cpu's
 385                  * vector_irq[] (for example IOAPIC cluster mode).  In
 386                  * this case we have two possibilities:
 387                  *
 388                  * 1) the resulting affinity mask is empty; that is
 389                  * this the down'd cpu is the last cpu in the irq's
 390                  * affinity mask, or
 391                  *
 392                  * 2) the resulting affinity mask is no longer a
 393                  * subset of the online cpus but the affinity mask is
 394                  * not zero; that is the down'd cpu is the last online
 395                  * cpu in a user set affinity mask.
 396                  */
 397                 if (cpumask_empty(&affinity_new) ||
 398                     !cpumask_subset(&affinity_new, &online_new))
 399                         this_count++;
 400         }
 401
 402         count = 0;
 403         for_each_online_cpu(cpu) {
 404                 if (cpu == this_cpu)
 405                         continue;
 406                 /*
 407                  * We scan from FIRST_EXTERNAL_VECTOR to first system
 408                  * vector. If the vector is marked in the used vectors
 409                  * bitmap or an irq is assigned to it, we don't count
 410                  * it as available.
 411                  *
 412                  * As this is an inaccurate snapshot anyway, we can do
 413                  * this w/o holding vector_lock.
 414                  */
 415                 for (vector = FIRST_EXTERNAL_VECTOR;
 416                      vector < first_system_vector; vector++) {
 417                         if (!test_bit(vector, used_vectors) &&
 418                             IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector]))
 419                             count++;
 420                 }
 421         }
 422
 423         if (count < this_count) {
 424                 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
 425                         this_cpu, this_count, count);
 426                 return -ERANGE;
 427         }
 428         return 0;
 429 }
 430
 431 /* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
 432 void fixup_irqs(void)
 433 {
 434         unsigned int irq, vector;
 435         static int warned;
 436         struct irq_desc *desc;
 437         struct irq_data *data;
 438         struct irq_chip *chip;
 439         int ret;
 440
 441         for_each_irq_desc(irq, desc) {
 442                 int break_affinity = 0;
 443                 int set_affinity = 1;
 444                 const struct cpumask *affinity;
 445
 446                 if (!desc)
 447                         continue;
 448                 if (irq == 2)
 449                         continue;
 450
 451                 /* interrupt's are disabled at this point */
 452                 raw_spin_lock(&desc->lock);
 453
 454                 data = irq_desc_get_irq_data(desc);
 455                 affinity = irq_data_get_affinity_mask(data);
 456                 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
 457                     cpumask_subset(affinity, cpu_online_mask)) {
 458                         raw_spin_unlock(&desc->lock);
 459                         continue;
 460                 }
 461
 462                 /*
 463                  * Complete the irq move. This cpu is going down and for
 464                  * non intr-remapping case, we can't wait till this interrupt
 465                  * arrives at this cpu before completing the irq move.
 466                  */
 467                 irq_force_complete_move(desc);
 468
 469                 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
 470                         break_affinity = 1;
 471                         affinity = cpu_online_mask;
 472                 }
 473
 474                 chip = irq_data_get_irq_chip(data);
 475                 /*
 476                  * The interrupt descriptor might have been cleaned up
 477                  * already, but it is not yet removed from the radix tree
 478                  */
 479                 if (!chip) {
 480                         raw_spin_unlock(&desc->lock);
 481                         continue;
 482                 }
 483
 484                 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
 485                         chip->irq_mask(data);
 486
 487                 if (chip->irq_set_affinity) {
 488                         ret = chip->irq_set_affinity(data, affinity, true);
 489                         if (ret == -ENOSPC)
 490                                 pr_crit("IRQ %d set affinity failed because there are no available vectors.  The device assigned to this IRQ is unstable.\n", irq);
 491                 } else {
 492                         if (!(warned++))
 493                                 set_affinity = 0;
 494                 }
 495
 496                 /*
 497                  * We unmask if the irq was not marked masked by the
 498                  * core code. That respects the lazy irq disable
 499                  * behaviour.
 500                  */
 501                 if (!irqd_can_move_in_process_context(data) &&
 502                     !irqd_irq_masked(data) && chip->irq_unmask)
 503                         chip->irq_unmask(data);
 504
 505                 raw_spin_unlock(&desc->lock);
 506
 507                 if (break_affinity && set_affinity)
 508                         pr_notice("Broke affinity for irq %i\n", irq);
 509                 else if (!set_affinity)
 510                         pr_notice("Cannot set affinity for irq %i\n", irq);
 511         }
 512
 513         /*
 514          * We can remove mdelay() and then send spuriuous interrupts to
 515          * new cpu targets for all the irqs that were handled previously by
 516          * this cpu. While it works, I have seen spurious interrupt messages
 517          * (nothing wrong but still...).
 518          *
 519          * So for now, retain mdelay(1) and check the IRR and then send those
 520          * interrupts to new targets as this cpu is already offlined...
 521          */
 522         mdelay(1);
 523
 524         /*
 525          * We can walk the vector array of this cpu without holding
 526          * vector_lock because the cpu is already marked !online, so
 527          * nothing else will touch it.
 528          */
 529         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 530                 unsigned int irr;
 531
 532                 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
 533                         continue;
 534
 535                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
 536                 if (irr  & (1 << (vector % 32))) {
 537                         desc = __this_cpu_read(vector_irq[vector]);
 538
 539                         raw_spin_lock(&desc->lock);
 540                         data = irq_desc_get_irq_data(desc);
 541                         chip = irq_data_get_irq_chip(data);
 542                         if (chip->irq_retrigger) {
 543                                 chip->irq_retrigger(data);
 544                                 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
 545                         }
 546                         raw_spin_unlock(&desc->lock);
 547                 }
 548                 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
 549                         __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
 550         }
 551 }
 552 #endif