arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #define pr_fmt(fmt) "Calgary: " fmt
  26
  27 #include <linux/kernel.h>
  28 #include <linux/init.h>
  29 #include <linux/types.h>
  30 #include <linux/slab.h>
  31 #include <linux/mm.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/string.h>
  34 #include <linux/crash_dump.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/dma-direct.h>
  37 #include <linux/bitmap.h>
  38 #include <linux/pci_ids.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41 #include <linux/scatterlist.h>
  42 #include <linux/iommu-helper.h>
  43
  44 #include <asm/iommu.h>
  45 #include <asm/calgary.h>
  46 #include <asm/tce.h>
  47 #include <asm/pci-direct.h>
  48 #include <asm/dma.h>
  49 #include <asm/rio.h>
  50 #include <asm/bios_ebda.h>
  51 #include <asm/x86_init.h>
  52 #include <asm/iommu_table.h>
  53
  54 #define CALGARY_MAPPING_ERROR   0
  55
  56 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  57 int use_calgary __read_mostly = 1;
  58 #else
  59 int use_calgary __read_mostly = 0;
  60 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  61
  62 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  63 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  64
  65 /* register offsets inside the host bridge space */
  66 #define CALGARY_CONFIG_REG      0x0108
  67 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  68 #define PHB_PLSSR_OFFSET        0x0120
  69 #define PHB_CONFIG_RW_OFFSET    0x0160
  70 #define PHB_IOBASE_BAR_LOW      0x0170
  71 #define PHB_IOBASE_BAR_HIGH     0x0180
  72 #define PHB_MEM_1_LOW           0x0190
  73 #define PHB_MEM_1_HIGH          0x01A0
  74 #define PHB_IO_ADDR_SIZE        0x01B0
  75 #define PHB_MEM_1_SIZE          0x01C0
  76 #define PHB_MEM_ST_OFFSET       0x01D0
  77 #define PHB_AER_OFFSET          0x0200
  78 #define PHB_CONFIG_0_HIGH       0x0220
  79 #define PHB_CONFIG_0_LOW        0x0230
  80 #define PHB_CONFIG_0_END        0x0240
  81 #define PHB_MEM_2_LOW           0x02B0
  82 #define PHB_MEM_2_HIGH          0x02C0
  83 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  84 #define PHB_MEM_2_SIZE_LOW      0x02E0
  85 #define PHB_DOSHOLE_OFFSET      0x08E0
  86
  87 /* CalIOC2 specific */
  88 #define PHB_SAVIOR_L2           0x0DB0
  89 #define PHB_PAGE_MIG_CTRL       0x0DA8
  90 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  91 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  92
  93 /* PHB_CONFIG_RW */
  94 #define PHB_TCE_ENABLE          0x20000000
  95 #define PHB_SLOT_DISABLE        0x1C000000
  96 #define PHB_DAC_DISABLE         0x01000000
  97 #define PHB_MEM2_ENABLE         0x00400000
  98 #define PHB_MCSR_ENABLE         0x00100000
  99 /* TAR (Table Address Register) */
 100 #define TAR_SW_BITS             0x0000ffffffff800fUL
 101 #define TAR_VALID               0x0000000000000008UL
 102 /* CSR (Channel/DMA Status Register) */
 103 #define CSR_AGENT_MASK          0xffe0ffff
 104 /* CCR (Calgary Configuration Register) */
 105 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
 106 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 107 #define PMR_SOFTSTOP            0x80000000
 108 #define PMR_SOFTSTOPFAULT       0x40000000
 109 #define PMR_HARDSTOP            0x20000000
 110
 111 /*
 112  * The maximum PHB bus number.
 113  * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
 114  * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
 115  * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
 116  * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
 117  */
 118 #define MAX_PHB_BUS_NUM         256
 119
 120 #define PHBS_PER_CALGARY          4
 121
 122 /* register offsets in Calgary's internal register space */
 123 static const unsigned long tar_offsets[] = {
 124         0x0580 /* TAR0 */,
 125         0x0588 /* TAR1 */,
 126         0x0590 /* TAR2 */,
 127         0x0598 /* TAR3 */
 128 };
 129
 130 static const unsigned long split_queue_offsets[] = {
 131         0x4870 /* SPLIT QUEUE 0 */,
 132         0x5870 /* SPLIT QUEUE 1 */,
 133         0x6870 /* SPLIT QUEUE 2 */,
 134         0x7870 /* SPLIT QUEUE 3 */
 135 };
 136
 137 static const unsigned long phb_offsets[] = {
 138         0x8000 /* PHB0 */,
 139         0x9000 /* PHB1 */,
 140         0xA000 /* PHB2 */,
 141         0xB000 /* PHB3 */
 142 };
 143
 144 /* PHB debug registers */
 145
 146 static const unsigned long phb_debug_offsets[] = {
 147         0x4000  /* PHB 0 DEBUG */,
 148         0x5000  /* PHB 1 DEBUG */,
 149         0x6000  /* PHB 2 DEBUG */,
 150         0x7000  /* PHB 3 DEBUG */
 151 };
 152
 153 /*
 154  * STUFF register for each debug PHB,
 155  * byte 1 = start bus number, byte 2 = end bus number
 156  */
 157
 158 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 159
 160 #define EMERGENCY_PAGES 32 /* = 128KB */
 161
 162 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 163 static int translate_empty_slots __read_mostly = 0;
 164 static int calgary_detected __read_mostly = 0;
 165
 166 static struct rio_table_hdr     *rio_table_hdr __initdata;
 167 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 168 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 169
 170 struct calgary_bus_info {
 171         void *tce_space;
 172         unsigned char translation_disabled;
 173         signed char phbid;
 174         void __iomem *bbar;
 175 };
 176
 177 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 178 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 179 static void calgary_dump_error_regs(struct iommu_table *tbl);
 180 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 181 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 182 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 183 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 184 static void get_tce_space_from_tar(void);
 185
 186 static const struct cal_chipset_ops calgary_chip_ops = {
 187         .handle_quirks = calgary_handle_quirks,
 188         .tce_cache_blast = calgary_tce_cache_blast,
 189         .dump_error_regs = calgary_dump_error_regs
 190 };
 191
 192 static const struct cal_chipset_ops calioc2_chip_ops = {
 193         .handle_quirks = calioc2_handle_quirks,
 194         .tce_cache_blast = calioc2_tce_cache_blast,
 195         .dump_error_regs = calioc2_dump_error_regs
 196 };
 197
 198 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 199
 200 static inline int translation_enabled(struct iommu_table *tbl)
 201 {
 202         /* only PHBs with translation enabled have an IOMMU table */
 203         return (tbl != NULL);
 204 }
 205
 206 static void iommu_range_reserve(struct iommu_table *tbl,
 207         unsigned long start_addr, unsigned int npages)
 208 {
 209         unsigned long index;
 210         unsigned long end;
 211         unsigned long flags;
 212
 213         index = start_addr >> PAGE_SHIFT;
 214
 215         /* bail out if we're asked to reserve a region we don't cover */
 216         if (index >= tbl->it_size)
 217                 return;
 218
 219         end = index + npages;
 220         if (end > tbl->it_size) /* don't go off the table */
 221                 end = tbl->it_size;
 222
 223         spin_lock_irqsave(&tbl->it_lock, flags);
 224
 225         bitmap_set(tbl->it_map, index, npages);
 226
 227         spin_unlock_irqrestore(&tbl->it_lock, flags);
 228 }
 229
 230 static unsigned long iommu_range_alloc(struct device *dev,
 231                                        struct iommu_table *tbl,
 232                                        unsigned int npages)
 233 {
 234         unsigned long flags;
 235         unsigned long offset;
 236         unsigned long boundary_size;
 237
 238         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 239                               PAGE_SIZE) >> PAGE_SHIFT;
 240
 241         BUG_ON(npages == 0);
 242
 243         spin_lock_irqsave(&tbl->it_lock, flags);
 244
 245         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 246                                   npages, 0, boundary_size, 0);
 247         if (offset == ~0UL) {
 248                 tbl->chip_ops->tce_cache_blast(tbl);
 249
 250                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 251                                           npages, 0, boundary_size, 0);
 252                 if (offset == ~0UL) {
 253                         pr_warn("IOMMU full\n");
 254                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 255                         if (panic_on_overflow)
 256                                 panic("Calgary: fix the allocator.\n");
 257                         else
 258                                 return CALGARY_MAPPING_ERROR;
 259                 }
 260         }
 261
 262         tbl->it_hint = offset + npages;
 263         BUG_ON(tbl->it_hint > tbl->it_size);
 264
 265         spin_unlock_irqrestore(&tbl->it_lock, flags);
 266
 267         return offset;
 268 }
 269
 270 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 271                               void *vaddr, unsigned int npages, int direction)
 272 {
 273         unsigned long entry;
 274         dma_addr_t ret;
 275
 276         entry = iommu_range_alloc(dev, tbl, npages);
 277
 278         if (unlikely(entry == CALGARY_MAPPING_ERROR)) {
 279                 pr_warn("failed to allocate %u pages in iommu %p\n",
 280                         npages, tbl);
 281                 return CALGARY_MAPPING_ERROR;
 282         }
 283
 284         /* set the return dma address */
 285         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 286
 287         /* put the TCEs in the HW table */
 288         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 289                   direction);
 290         return ret;
 291 }
 292
 293 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 294         unsigned int npages)
 295 {
 296         unsigned long entry;
 297         unsigned long badend;
 298         unsigned long flags;
 299
 300         /* were we called with bad_dma_address? */
 301         badend = CALGARY_MAPPING_ERROR + (EMERGENCY_PAGES * PAGE_SIZE);
 302         if (unlikely(dma_addr < badend)) {
 303                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 304                        "address 0x%Lx\n", dma_addr);
 305                 return;
 306         }
 307
 308         entry = dma_addr >> PAGE_SHIFT;
 309
 310         BUG_ON(entry + npages > tbl->it_size);
 311
 312         tce_free(tbl, entry, npages);
 313
 314         spin_lock_irqsave(&tbl->it_lock, flags);
 315
 316         bitmap_clear(tbl->it_map, entry, npages);
 317
 318         spin_unlock_irqrestore(&tbl->it_lock, flags);
 319 }
 320
 321 static inline struct iommu_table *find_iommu_table(struct device *dev)
 322 {
 323         struct pci_dev *pdev;
 324         struct pci_bus *pbus;
 325         struct iommu_table *tbl;
 326
 327         pdev = to_pci_dev(dev);
 328
 329         /* search up the device tree for an iommu */
 330         pbus = pdev->bus;
 331         do {
 332                 tbl = pci_iommu(pbus);
 333                 if (tbl && tbl->it_busno == pbus->number)
 334                         break;
 335                 tbl = NULL;
 336                 pbus = pbus->parent;
 337         } while (pbus);
 338
 339         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 340
 341         return tbl;
 342 }
 343
 344 static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 345                              int nelems,enum dma_data_direction dir,
 346                              unsigned long attrs)
 347 {
 348         struct iommu_table *tbl = find_iommu_table(dev);
 349         struct scatterlist *s;
 350         int i;
 351
 352         if (!translation_enabled(tbl))
 353                 return;
 354
 355         for_each_sg(sglist, s, nelems, i) {
 356                 unsigned int npages;
 357                 dma_addr_t dma = s->dma_address;
 358                 unsigned int dmalen = s->dma_length;
 359
 360                 if (dmalen == 0)
 361                         break;
 362
 363                 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
 364                 iommu_free(tbl, dma, npages);
 365         }
 366 }
 367
 368 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 369                           int nelems, enum dma_data_direction dir,
 370                           unsigned long attrs)
 371 {
 372         struct iommu_table *tbl = find_iommu_table(dev);
 373         struct scatterlist *s;
 374         unsigned long vaddr;
 375         unsigned int npages;
 376         unsigned long entry;
 377         int i;
 378
 379         for_each_sg(sg, s, nelems, i) {
 380                 BUG_ON(!sg_page(s));
 381
 382                 vaddr = (unsigned long) sg_virt(s);
 383                 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
 384
 385                 entry = iommu_range_alloc(dev, tbl, npages);
 386                 if (entry == CALGARY_MAPPING_ERROR) {
 387                         /* makes sure unmap knows to stop */
 388                         s->dma_length = 0;
 389                         goto error;
 390                 }
 391
 392                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 393
 394                 /* insert into HW table */
 395                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
 396
 397                 s->dma_length = s->length;
 398         }
 399
 400         return nelems;
 401 error:
 402         calgary_unmap_sg(dev, sg, nelems, dir, 0);
 403         for_each_sg(sg, s, nelems, i) {
 404                 sg->dma_address = CALGARY_MAPPING_ERROR;
 405                 sg->dma_length = 0;
 406         }
 407         return 0;
 408 }
 409
 410 static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
 411                                    unsigned long offset, size_t size,
 412                                    enum dma_data_direction dir,
 413                                    unsigned long attrs)
 414 {
 415         void *vaddr = page_address(page) + offset;
 416         unsigned long uaddr;
 417         unsigned int npages;
 418         struct iommu_table *tbl = find_iommu_table(dev);
 419
 420         uaddr = (unsigned long)vaddr;
 421         npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
 422
 423         return iommu_alloc(dev, tbl, vaddr, npages, dir);
 424 }
 425
 426 static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
 427                                size_t size, enum dma_data_direction dir,
 428                                unsigned long attrs)
 429 {
 430         struct iommu_table *tbl = find_iommu_table(dev);
 431         unsigned int npages;
 432
 433         npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
 434         iommu_free(tbl, dma_addr, npages);
 435 }
 436
 437 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 438         dma_addr_t *dma_handle, gfp_t flag, unsigned long attrs)
 439 {
 440         void *ret = NULL;
 441         dma_addr_t mapping;
 442         unsigned int npages, order;
 443         struct iommu_table *tbl = find_iommu_table(dev);
 444
 445         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 446         npages = size >> PAGE_SHIFT;
 447         order = get_order(size);
 448
 449         /* alloc enough pages (and possibly more) */
 450         ret = (void *)__get_free_pages(flag, order);
 451         if (!ret)
 452                 goto error;
 453         memset(ret, 0, size);
 454
 455         /* set up tces to cover the allocated range */
 456         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 457         if (mapping == CALGARY_MAPPING_ERROR)
 458                 goto free;
 459         *dma_handle = mapping;
 460         return ret;
 461 free:
 462         free_pages((unsigned long)ret, get_order(size));
 463         ret = NULL;
 464 error:
 465         return ret;
 466 }
 467
 468 static void calgary_free_coherent(struct device *dev, size_t size,
 469                                   void *vaddr, dma_addr_t dma_handle,
 470                                   unsigned long attrs)
 471 {
 472         unsigned int npages;
 473         struct iommu_table *tbl = find_iommu_table(dev);
 474
 475         size = PAGE_ALIGN(size);
 476         npages = size >> PAGE_SHIFT;
 477
 478         iommu_free(tbl, dma_handle, npages);
 479         free_pages((unsigned long)vaddr, get_order(size));
 480 }
 481
 482 static int calgary_mapping_error(struct device *dev, dma_addr_t dma_addr)
 483 {
 484         return dma_addr == CALGARY_MAPPING_ERROR;
 485 }
 486
 487 static const struct dma_map_ops calgary_dma_ops = {
 488         .alloc = calgary_alloc_coherent,
 489         .free = calgary_free_coherent,
 490         .map_sg = calgary_map_sg,
 491         .unmap_sg = calgary_unmap_sg,
 492         .map_page = calgary_map_page,
 493         .unmap_page = calgary_unmap_page,
 494         .mapping_error = calgary_mapping_error,
 495         .dma_supported = dma_direct_supported,
 496 };
 497
 498 static inline void __iomem * busno_to_bbar(unsigned char num)
 499 {
 500         return bus_info[num].bbar;
 501 }
 502
 503 static inline int busno_to_phbid(unsigned char num)
 504 {
 505         return bus_info[num].phbid;
 506 }
 507
 508 static inline unsigned long split_queue_offset(unsigned char num)
 509 {
 510         size_t idx = busno_to_phbid(num);
 511
 512         return split_queue_offsets[idx];
 513 }
 514
 515 static inline unsigned long tar_offset(unsigned char num)
 516 {
 517         size_t idx = busno_to_phbid(num);
 518
 519         return tar_offsets[idx];
 520 }
 521
 522 static inline unsigned long phb_offset(unsigned char num)
 523 {
 524         size_t idx = busno_to_phbid(num);
 525
 526         return phb_offsets[idx];
 527 }
 528
 529 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 530 {
 531         unsigned long target = ((unsigned long)bar) | offset;
 532         return (void __iomem*)target;
 533 }
 534
 535 static inline int is_calioc2(unsigned short device)
 536 {
 537         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 538 }
 539
 540 static inline int is_calgary(unsigned short device)
 541 {
 542         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 543 }
 544
 545 static inline int is_cal_pci_dev(unsigned short device)
 546 {
 547         return (is_calgary(device) || is_calioc2(device));
 548 }
 549
 550 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 551 {
 552         u64 val;
 553         u32 aer;
 554         int i = 0;
 555         void __iomem *bbar = tbl->bbar;
 556         void __iomem *target;
 557
 558         /* disable arbitration on the bus */
 559         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 560         aer = readl(target);
 561         writel(0, target);
 562
 563         /* read plssr to ensure it got there */
 564         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 565         val = readl(target);
 566
 567         /* poll split queues until all DMA activity is done */
 568         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 569         do {
 570                 val = readq(target);
 571                 i++;
 572         } while ((val & 0xff) != 0xff && i < 100);
 573         if (i == 100)
 574                 pr_warn("PCI bus not quiesced, continuing anyway\n");
 575
 576         /* invalidate TCE cache */
 577         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 578         writeq(tbl->tar_val, target);
 579
 580         /* enable arbitration */
 581         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 582         writel(aer, target);
 583         (void)readl(target); /* flush */
 584 }
 585
 586 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 587 {
 588         void __iomem *bbar = tbl->bbar;
 589         void __iomem *target;
 590         u64 val64;
 591         u32 val;
 592         int i = 0;
 593         int count = 1;
 594         unsigned char bus = tbl->it_busno;
 595
 596 begin:
 597         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 598                "sequence - count %d\n", bus, count);
 599
 600         /* 1. using the Page Migration Control reg set SoftStop */
 601         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 602         val = be32_to_cpu(readl(target));
 603         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 604         val |= PMR_SOFTSTOP;
 605         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 606         writel(cpu_to_be32(val), target);
 607
 608         /* 2. poll split queues until all DMA activity is done */
 609         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 610         target = calgary_reg(bbar, split_queue_offset(bus));
 611         do {
 612                 val64 = readq(target);
 613                 i++;
 614         } while ((val64 & 0xff) != 0xff && i < 100);
 615         if (i == 100)
 616                 pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n");
 617
 618         /* 3. poll Page Migration DEBUG for SoftStopFault */
 619         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 620         val = be32_to_cpu(readl(target));
 621         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 622
 623         /* 4. if SoftStopFault - goto (1) */
 624         if (val & PMR_SOFTSTOPFAULT) {
 625                 if (++count < 100)
 626                         goto begin;
 627                 else {
 628                         pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n");
 629                         return; /* pray for the best */
 630                 }
 631         }
 632
 633         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 634         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 635         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 636         val = be32_to_cpu(readl(target));
 637         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 638         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 639         val = be32_to_cpu(readl(target));
 640         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 641
 642         /* 6. invalidate TCE cache */
 643         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 644         target = calgary_reg(bbar, tar_offset(bus));
 645         writeq(tbl->tar_val, target);
 646
 647         /* 7. Re-read PMCR */
 648         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 649         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 650         val = be32_to_cpu(readl(target));
 651         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 652
 653         /* 8. Remove HardStop */
 654         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 655         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 656         val = 0;
 657         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 658         writel(cpu_to_be32(val), target);
 659         val = be32_to_cpu(readl(target));
 660         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 661 }
 662
 663 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 664         u64 limit)
 665 {
 666         unsigned int numpages;
 667
 668         limit = limit | 0xfffff;
 669         limit++;
 670
 671         numpages = ((limit - start) >> PAGE_SHIFT);
 672         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 673 }
 674
 675 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 676 {
 677         void __iomem *target;
 678         u64 low, high, sizelow;
 679         u64 start, limit;
 680         struct iommu_table *tbl = pci_iommu(dev->bus);
 681         unsigned char busnum = dev->bus->number;
 682         void __iomem *bbar = tbl->bbar;
 683
 684         /* peripheral MEM_1 region */
 685         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 686         low = be32_to_cpu(readl(target));
 687         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 688         high = be32_to_cpu(readl(target));
 689         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 690         sizelow = be32_to_cpu(readl(target));
 691
 692         start = (high << 32) | low;
 693         limit = sizelow;
 694
 695         calgary_reserve_mem_region(dev, start, limit);
 696 }
 697
 698 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 699 {
 700         void __iomem *target;
 701         u32 val32;
 702         u64 low, high, sizelow, sizehigh;
 703         u64 start, limit;
 704         struct iommu_table *tbl = pci_iommu(dev->bus);
 705         unsigned char busnum = dev->bus->number;
 706         void __iomem *bbar = tbl->bbar;
 707
 708         /* is it enabled? */
 709         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 710         val32 = be32_to_cpu(readl(target));
 711         if (!(val32 & PHB_MEM2_ENABLE))
 712                 return;
 713
 714         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 715         low = be32_to_cpu(readl(target));
 716         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 717         high = be32_to_cpu(readl(target));
 718         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 719         sizelow = be32_to_cpu(readl(target));
 720         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 721         sizehigh = be32_to_cpu(readl(target));
 722
 723         start = (high << 32) | low;
 724         limit = (sizehigh << 32) | sizelow;
 725
 726         calgary_reserve_mem_region(dev, start, limit);
 727 }
 728
 729 /*
 730  * some regions of the IO address space do not get translated, so we
 731  * must not give devices IO addresses in those regions. The regions
 732  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 733  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 734  * later.
 735  */
 736 static void __init calgary_reserve_regions(struct pci_dev *dev)
 737 {
 738         unsigned int npages;
 739         u64 start;
 740         struct iommu_table *tbl = pci_iommu(dev->bus);
 741
 742         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 743         iommu_range_reserve(tbl, CALGARY_MAPPING_ERROR, EMERGENCY_PAGES);
 744
 745         /* avoid the BIOS/VGA first 640KB-1MB region */
 746         /* for CalIOC2 - avoid the entire first MB */
 747         if (is_calgary(dev->device)) {
 748                 start = (640 * 1024);
 749                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 750         } else { /* calioc2 */
 751                 start = 0;
 752                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 753         }
 754         iommu_range_reserve(tbl, start, npages);
 755
 756         /* reserve the two PCI peripheral memory regions in IO space */
 757         calgary_reserve_peripheral_mem_1(dev);
 758         calgary_reserve_peripheral_mem_2(dev);
 759 }
 760
 761 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 762 {
 763         u64 val64;
 764         u64 table_phys;
 765         void __iomem *target;
 766         int ret;
 767         struct iommu_table *tbl;
 768
 769         /* build TCE tables for each PHB */
 770         ret = build_tce_table(dev, bbar);
 771         if (ret)
 772                 return ret;
 773
 774         tbl = pci_iommu(dev->bus);
 775         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 776
 777         if (is_kdump_kernel())
 778                 calgary_init_bitmap_from_tce_table(tbl);
 779         else
 780                 tce_free(tbl, 0, tbl->it_size);
 781
 782         if (is_calgary(dev->device))
 783                 tbl->chip_ops = &calgary_chip_ops;
 784         else if (is_calioc2(dev->device))
 785                 tbl->chip_ops = &calioc2_chip_ops;
 786         else
 787                 BUG();
 788
 789         calgary_reserve_regions(dev);
 790
 791         /* set TARs for each PHB */
 792         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 793         val64 = be64_to_cpu(readq(target));
 794
 795         /* zero out all TAR bits under sw control */
 796         val64 &= ~TAR_SW_BITS;
 797         table_phys = (u64)__pa(tbl->it_base);
 798
 799         val64 |= table_phys;
 800
 801         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 802         val64 |= (u64) specified_table_size;
 803
 804         tbl->tar_val = cpu_to_be64(val64);
 805
 806         writeq(tbl->tar_val, target);
 807         readq(target); /* flush */
 808
 809         return 0;
 810 }
 811
 812 static void __init calgary_free_bus(struct pci_dev *dev)
 813 {
 814         u64 val64;
 815         struct iommu_table *tbl = pci_iommu(dev->bus);
 816         void __iomem *target;
 817         unsigned int bitmapsz;
 818
 819         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 820         val64 = be64_to_cpu(readq(target));
 821         val64 &= ~TAR_SW_BITS;
 822         writeq(cpu_to_be64(val64), target);
 823         readq(target); /* flush */
 824
 825         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 826         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 827         tbl->it_map = NULL;
 828
 829         kfree(tbl);
 830
 831         set_pci_iommu(dev->bus, NULL);
 832
 833         /* Can't free bootmem allocated memory after system is up :-( */
 834         bus_info[dev->bus->number].tce_space = NULL;
 835 }
 836
 837 static void calgary_dump_error_regs(struct iommu_table *tbl)
 838 {
 839         void __iomem *bbar = tbl->bbar;
 840         void __iomem *target;
 841         u32 csr, plssr;
 842
 843         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 844         csr = be32_to_cpu(readl(target));
 845
 846         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 847         plssr = be32_to_cpu(readl(target));
 848
 849         /* If no error, the agent ID in the CSR is not valid */
 850         pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n",
 851                  tbl->it_busno, csr, plssr);
 852 }
 853
 854 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 855 {
 856         void __iomem *bbar = tbl->bbar;
 857         u32 csr, csmr, plssr, mck, rcstat;
 858         void __iomem *target;
 859         unsigned long phboff = phb_offset(tbl->it_busno);
 860         unsigned long erroff;
 861         u32 errregs[7];
 862         int i;
 863
 864         /* dump CSR */
 865         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 866         csr = be32_to_cpu(readl(target));
 867         /* dump PLSSR */
 868         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 869         plssr = be32_to_cpu(readl(target));
 870         /* dump CSMR */
 871         target = calgary_reg(bbar, phboff | 0x290);
 872         csmr = be32_to_cpu(readl(target));
 873         /* dump mck */
 874         target = calgary_reg(bbar, phboff | 0x800);
 875         mck = be32_to_cpu(readl(target));
 876
 877         pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno);
 878
 879         pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 880                  csr, plssr, csmr, mck);
 881
 882         /* dump rest of error regs */
 883         pr_emerg("");
 884         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 885                 /* err regs are at 0x810 - 0x870 */
 886                 erroff = (0x810 + (i * 0x10));
 887                 target = calgary_reg(bbar, phboff | erroff);
 888                 errregs[i] = be32_to_cpu(readl(target));
 889                 pr_cont("0x%08x@0x%lx ", errregs[i], erroff);
 890         }
 891         pr_cont("\n");
 892
 893         /* root complex status */
 894         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 895         rcstat = be32_to_cpu(readl(target));
 896         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 897                PHB_ROOT_COMPLEX_STATUS);
 898 }
 899
 900 static void calgary_watchdog(struct timer_list *t)
 901 {
 902         struct iommu_table *tbl = from_timer(tbl, t, watchdog_timer);
 903         void __iomem *bbar = tbl->bbar;
 904         u32 val32;
 905         void __iomem *target;
 906
 907         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 908         val32 = be32_to_cpu(readl(target));
 909
 910         /* If no error, the agent ID in the CSR is not valid */
 911         if (val32 & CSR_AGENT_MASK) {
 912                 tbl->chip_ops->dump_error_regs(tbl);
 913
 914                 /* reset error */
 915                 writel(0, target);
 916
 917                 /* Disable bus that caused the error */
 918                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 919                                      PHB_CONFIG_RW_OFFSET);
 920                 val32 = be32_to_cpu(readl(target));
 921                 val32 |= PHB_SLOT_DISABLE;
 922                 writel(cpu_to_be32(val32), target);
 923                 readl(target); /* flush */
 924         } else {
 925                 /* Reset the timer */
 926                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 927         }
 928 }
 929
 930 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 931         unsigned char busnum, unsigned long timeout)
 932 {
 933         u64 val64;
 934         void __iomem *target;
 935         unsigned int phb_shift = ~0; /* silence gcc */
 936         u64 mask;
 937
 938         switch (busno_to_phbid(busnum)) {
 939         case 0: phb_shift = (63 - 19);
 940                 break;
 941         case 1: phb_shift = (63 - 23);
 942                 break;
 943         case 2: phb_shift = (63 - 27);
 944                 break;
 945         case 3: phb_shift = (63 - 35);
 946                 break;
 947         default:
 948                 BUG_ON(busno_to_phbid(busnum));
 949         }
 950
 951         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 952         val64 = be64_to_cpu(readq(target));
 953
 954         /* zero out this PHB's timer bits */
 955         mask = ~(0xFUL << phb_shift);
 956         val64 &= mask;
 957         val64 |= (timeout << phb_shift);
 958         writeq(cpu_to_be64(val64), target);
 959         readq(target); /* flush */
 960 }
 961
 962 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 963 {
 964         unsigned char busnum = dev->bus->number;
 965         void __iomem *bbar = tbl->bbar;
 966         void __iomem *target;
 967         u32 val;
 968
 969         /*
 970          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
 971          */
 972         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
 973         val = cpu_to_be32(readl(target));
 974         val |= 0x00800000;
 975         writel(cpu_to_be32(val), target);
 976 }
 977
 978 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 979 {
 980         unsigned char busnum = dev->bus->number;
 981
 982         /*
 983          * Give split completion a longer timeout on bus 1 for aic94xx
 984          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
 985          */
 986         if (is_calgary(dev->device) && (busnum == 1))
 987                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
 988                                                      CCR_2SEC_TIMEOUT);
 989 }
 990
 991 static void __init calgary_enable_translation(struct pci_dev *dev)
 992 {
 993         u32 val32;
 994         unsigned char busnum;
 995         void __iomem *target;
 996         void __iomem *bbar;
 997         struct iommu_table *tbl;
 998
 999         busnum = dev->bus->number;
1000         tbl = pci_iommu(dev->bus);
1001         bbar = tbl->bbar;
1002
1003         /* enable TCE in PHB Config Register */
1004         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1005         val32 = be32_to_cpu(readl(target));
1006         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1007
1008         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1009                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1010                "Calgary" : "CalIOC2", busnum);
1011         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1012                "bus.\n");
1013
1014         writel(cpu_to_be32(val32), target);
1015         readl(target); /* flush */
1016
1017         timer_setup(&tbl->watchdog_timer, calgary_watchdog, 0);
1018         mod_timer(&tbl->watchdog_timer, jiffies);
1019 }
1020
1021 static void __init calgary_disable_translation(struct pci_dev *dev)
1022 {
1023         u32 val32;
1024         unsigned char busnum;
1025         void __iomem *target;
1026         void __iomem *bbar;
1027         struct iommu_table *tbl;
1028
1029         busnum = dev->bus->number;
1030         tbl = pci_iommu(dev->bus);
1031         bbar = tbl->bbar;
1032
1033         /* disable TCE in PHB Config Register */
1034         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1035         val32 = be32_to_cpu(readl(target));
1036         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1037
1038         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1039         writel(cpu_to_be32(val32), target);
1040         readl(target); /* flush */
1041
1042         del_timer_sync(&tbl->watchdog_timer);
1043 }
1044
1045 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1046 {
1047         pci_dev_get(dev);
1048         set_pci_iommu(dev->bus, NULL);
1049
1050         /* is the device behind a bridge? */
1051         if (dev->bus->parent)
1052                 dev->bus->parent->self = dev;
1053         else
1054                 dev->bus->self = dev;
1055 }
1056
1057 static int __init calgary_init_one(struct pci_dev *dev)
1058 {
1059         void __iomem *bbar;
1060         struct iommu_table *tbl;
1061         int ret;
1062
1063         bbar = busno_to_bbar(dev->bus->number);
1064         ret = calgary_setup_tar(dev, bbar);
1065         if (ret)
1066                 goto done;
1067
1068         pci_dev_get(dev);
1069
1070         if (dev->bus->parent) {
1071                 if (dev->bus->parent->self)
1072                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1073                                "bus->parent->self!\n", dev);
1074                 dev->bus->parent->self = dev;
1075         } else
1076                 dev->bus->self = dev;
1077
1078         tbl = pci_iommu(dev->bus);
1079         tbl->chip_ops->handle_quirks(tbl, dev);
1080
1081         calgary_enable_translation(dev);
1082
1083         return 0;
1084
1085 done:
1086         return ret;
1087 }
1088
1089 static int __init calgary_locate_bbars(void)
1090 {
1091         int ret;
1092         int rioidx, phb, bus;
1093         void __iomem *bbar;
1094         void __iomem *target;
1095         unsigned long offset;
1096         u8 start_bus, end_bus;
1097         u32 val;
1098
1099         ret = -ENODATA;
1100         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1101                 struct rio_detail *rio = rio_devs[rioidx];
1102
1103                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1104                         continue;
1105
1106                 /* map entire 1MB of Calgary config space */
1107                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1108                 if (!bbar)
1109                         goto error;
1110
1111                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1112                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1113                         target = calgary_reg(bbar, offset);
1114
1115                         val = be32_to_cpu(readl(target));
1116
1117                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1118                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1119
1120                         if (end_bus) {
1121                                 for (bus = start_bus; bus <= end_bus; bus++) {
1122                                         bus_info[bus].bbar = bbar;
1123                                         bus_info[bus].phbid = phb;
1124                                 }
1125                         } else {
1126                                 bus_info[start_bus].bbar = bbar;
1127                                 bus_info[start_bus].phbid = phb;
1128                         }
1129                 }
1130         }
1131
1132         return 0;
1133
1134 error:
1135         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1136         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1137                 if (bus_info[bus].bbar)
1138                         iounmap(bus_info[bus].bbar);
1139
1140         return ret;
1141 }
1142
1143 static int __init calgary_init(void)
1144 {
1145         int ret;
1146         struct pci_dev *dev = NULL;
1147         struct calgary_bus_info *info;
1148
1149         ret = calgary_locate_bbars();
1150         if (ret)
1151                 return ret;
1152
1153         /* Purely for kdump kernel case */
1154         if (is_kdump_kernel())
1155                 get_tce_space_from_tar();
1156
1157         do {
1158                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1159                 if (!dev)
1160                         break;
1161                 if (!is_cal_pci_dev(dev->device))
1162                         continue;
1163
1164                 info = &bus_info[dev->bus->number];
1165                 if (info->translation_disabled) {
1166                         calgary_init_one_nontraslated(dev);
1167                         continue;
1168                 }
1169
1170                 if (!info->tce_space && !translate_empty_slots)
1171                         continue;
1172
1173                 ret = calgary_init_one(dev);
1174                 if (ret)
1175                         goto error;
1176         } while (1);
1177
1178         dev = NULL;
1179         for_each_pci_dev(dev) {
1180                 struct iommu_table *tbl;
1181
1182                 tbl = find_iommu_table(&dev->dev);
1183
1184                 if (translation_enabled(tbl))
1185                         dev->dev.dma_ops = &calgary_dma_ops;
1186         }
1187
1188         return ret;
1189
1190 error:
1191         do {
1192                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1193                 if (!dev)
1194                         break;
1195                 if (!is_cal_pci_dev(dev->device))
1196                         continue;
1197
1198                 info = &bus_info[dev->bus->number];
1199                 if (info->translation_disabled) {
1200                         pci_dev_put(dev);
1201                         continue;
1202                 }
1203                 if (!info->tce_space && !translate_empty_slots)
1204                         continue;
1205
1206                 calgary_disable_translation(dev);
1207                 calgary_free_bus(dev);
1208                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1209                 dev->dev.dma_ops = NULL;
1210         } while (1);
1211
1212         return ret;
1213 }
1214
1215 static inline int __init determine_tce_table_size(void)
1216 {
1217         int ret;
1218
1219         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1220                 return specified_table_size;
1221
1222         if (is_kdump_kernel() && saved_max_pfn) {
1223                 /*
1224                  * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1225                  * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1226                  * larger table size has twice as many entries, so shift the
1227                  * max ram address by 13 to divide by 8K and then look at the
1228                  * order of the result to choose between 0-7.
1229                  */
1230                 ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13);
1231                 if (ret > TCE_TABLE_SIZE_8M)
1232                         ret = TCE_TABLE_SIZE_8M;
1233         } else {
1234                 /*
1235                  * Use 8M by default (suggested by Muli) if it's not
1236                  * kdump kernel and saved_max_pfn isn't set.
1237                  */
1238                 ret = TCE_TABLE_SIZE_8M;
1239         }
1240
1241         return ret;
1242 }
1243
1244 static int __init build_detail_arrays(void)
1245 {
1246         unsigned long ptr;
1247         unsigned numnodes, i;
1248         int scal_detail_size, rio_detail_size;
1249
1250         numnodes = rio_table_hdr->num_scal_dev;
1251         if (numnodes > MAX_NUMNODES){
1252                 printk(KERN_WARNING
1253                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1254                         "but system has %d nodes.\n",
1255                         MAX_NUMNODES, numnodes);
1256                 return -ENODEV;
1257         }
1258
1259         switch (rio_table_hdr->version){
1260         case 2:
1261                 scal_detail_size = 11;
1262                 rio_detail_size = 13;
1263                 break;
1264         case 3:
1265                 scal_detail_size = 12;
1266                 rio_detail_size = 15;
1267                 break;
1268         default:
1269                 printk(KERN_WARNING
1270                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1271                        rio_table_hdr->version);
1272                 return -EPROTO;
1273         }
1274
1275         ptr = ((unsigned long)rio_table_hdr) + 3;
1276         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1277                 scal_devs[i] = (struct scal_detail *)ptr;
1278
1279         for (i = 0; i < rio_table_hdr->num_rio_dev;
1280                     i++, ptr += rio_detail_size)
1281                 rio_devs[i] = (struct rio_detail *)ptr;
1282
1283         return 0;
1284 }
1285
1286 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1287 {
1288         int dev;
1289         u32 val;
1290
1291         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1292                 /*
1293                  * FIXME: properly scan for devices across the
1294                  * PCI-to-PCI bridge on every CalIOC2 port.
1295                  */
1296                 return 1;
1297         }
1298
1299         for (dev = 1; dev < 8; dev++) {
1300                 val = read_pci_config(bus, dev, 0, 0);
1301                 if (val != 0xffffffff)
1302                         break;
1303         }
1304         return (val != 0xffffffff);
1305 }
1306
1307 /*
1308  * calgary_init_bitmap_from_tce_table():
1309  * Function for kdump case. In the second/kdump kernel initialize
1310  * the bitmap based on the tce table entries obtained from first kernel
1311  */
1312 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1313 {
1314         u64 *tp;
1315         unsigned int index;
1316         tp = ((u64 *)tbl->it_base);
1317         for (index = 0 ; index < tbl->it_size; index++) {
1318                 if (*tp != 0x0)
1319                         set_bit(index, tbl->it_map);
1320                 tp++;
1321         }
1322 }
1323
1324 /*
1325  * get_tce_space_from_tar():
1326  * Function for kdump case. Get the tce tables from first kernel
1327  * by reading the contents of the base address register of calgary iommu
1328  */
1329 static void __init get_tce_space_from_tar(void)
1330 {
1331         int bus;
1332         void __iomem *target;
1333         unsigned long tce_space;
1334
1335         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1336                 struct calgary_bus_info *info = &bus_info[bus];
1337                 unsigned short pci_device;
1338                 u32 val;
1339
1340                 val = read_pci_config(bus, 0, 0, 0);
1341                 pci_device = (val & 0xFFFF0000) >> 16;
1342
1343                 if (!is_cal_pci_dev(pci_device))
1344                         continue;
1345                 if (info->translation_disabled)
1346                         continue;
1347
1348                 if (calgary_bus_has_devices(bus, pci_device) ||
1349                                                 translate_empty_slots) {
1350                         target = calgary_reg(bus_info[bus].bbar,
1351                                                 tar_offset(bus));
1352                         tce_space = be64_to_cpu(readq(target));
1353                         tce_space = tce_space & TAR_SW_BITS;
1354
1355                         tce_space = tce_space & (~specified_table_size);
1356                         info->tce_space = (u64 *)__va(tce_space);
1357                 }
1358         }
1359         return;
1360 }
1361
1362 static int __init calgary_iommu_init(void)
1363 {
1364         int ret;
1365
1366         /* ok, we're trying to use Calgary - let's roll */
1367         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1368
1369         ret = calgary_init();
1370         if (ret) {
1371                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1372                        "falling back to no_iommu\n", ret);
1373                 return ret;
1374         }
1375
1376         return 0;
1377 }
1378
1379 int __init detect_calgary(void)
1380 {
1381         int bus;
1382         void *tbl;
1383         int calgary_found = 0;
1384         unsigned long ptr;
1385         unsigned int offset, prev_offset;
1386         int ret;
1387
1388         /*
1389          * if the user specified iommu=off or iommu=soft or we found
1390          * another HW IOMMU already, bail out.
1391          */
1392         if (no_iommu || iommu_detected)
1393                 return -ENODEV;
1394
1395         if (!use_calgary)
1396                 return -ENODEV;
1397
1398         if (!early_pci_allowed())
1399                 return -ENODEV;
1400
1401         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1402
1403         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1404
1405         rio_table_hdr = NULL;
1406         prev_offset = 0;
1407         offset = 0x180;
1408         /*
1409          * The next offset is stored in the 1st word.
1410          * Only parse up until the offset increases:
1411          */
1412         while (offset > prev_offset) {
1413                 /* The block id is stored in the 2nd word */
1414                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1415                         /* set the pointer past the offset & block id */
1416                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1417                         break;
1418                 }
1419                 prev_offset = offset;
1420                 offset = *((unsigned short *)(ptr + offset));
1421         }
1422         if (!rio_table_hdr) {
1423                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1424                        "in EBDA - bailing!\n");
1425                 return -ENODEV;
1426         }
1427
1428         ret = build_detail_arrays();
1429         if (ret) {
1430                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1431                 return -ENOMEM;
1432         }
1433
1434         specified_table_size = determine_tce_table_size();
1435
1436         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1437                 struct calgary_bus_info *info = &bus_info[bus];
1438                 unsigned short pci_device;
1439                 u32 val;
1440
1441                 val = read_pci_config(bus, 0, 0, 0);
1442                 pci_device = (val & 0xFFFF0000) >> 16;
1443
1444                 if (!is_cal_pci_dev(pci_device))
1445                         continue;
1446
1447                 if (info->translation_disabled)
1448                         continue;
1449
1450                 if (calgary_bus_has_devices(bus, pci_device) ||
1451                     translate_empty_slots) {
1452                         /*
1453                          * If it is kdump kernel, find and use tce tables
1454                          * from first kernel, else allocate tce tables here
1455                          */
1456                         if (!is_kdump_kernel()) {
1457                                 tbl = alloc_tce_table();
1458                                 if (!tbl)
1459                                         goto cleanup;
1460                                 info->tce_space = tbl;
1461                         }
1462                         calgary_found = 1;
1463                 }
1464         }
1465
1466         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1467                calgary_found ? "found" : "not found");
1468
1469         if (calgary_found) {
1470                 iommu_detected = 1;
1471                 calgary_detected = 1;
1472                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1473                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1474                        specified_table_size);
1475
1476                 x86_init.iommu.iommu_init = calgary_iommu_init;
1477         }
1478         return calgary_found;
1479
1480 cleanup:
1481         for (--bus; bus >= 0; --bus) {
1482                 struct calgary_bus_info *info = &bus_info[bus];
1483
1484                 if (info->tce_space)
1485                         free_tce_table(info->tce_space);
1486         }
1487         return -ENOMEM;
1488 }
1489
1490 static int __init calgary_parse_options(char *p)
1491 {
1492         unsigned int bridge;
1493         unsigned long val;
1494         size_t len;
1495         ssize_t ret;
1496
1497         while (*p) {
1498                 if (!strncmp(p, "64k", 3))
1499                         specified_table_size = TCE_TABLE_SIZE_64K;
1500                 else if (!strncmp(p, "128k", 4))
1501                         specified_table_size = TCE_TABLE_SIZE_128K;
1502                 else if (!strncmp(p, "256k", 4))
1503                         specified_table_size = TCE_TABLE_SIZE_256K;
1504                 else if (!strncmp(p, "512k", 4))
1505                         specified_table_size = TCE_TABLE_SIZE_512K;
1506                 else if (!strncmp(p, "1M", 2))
1507                         specified_table_size = TCE_TABLE_SIZE_1M;
1508                 else if (!strncmp(p, "2M", 2))
1509                         specified_table_size = TCE_TABLE_SIZE_2M;
1510                 else if (!strncmp(p, "4M", 2))
1511                         specified_table_size = TCE_TABLE_SIZE_4M;
1512                 else if (!strncmp(p, "8M", 2))
1513                         specified_table_size = TCE_TABLE_SIZE_8M;
1514
1515                 len = strlen("translate_empty_slots");
1516                 if (!strncmp(p, "translate_empty_slots", len))
1517                         translate_empty_slots = 1;
1518
1519                 len = strlen("disable");
1520                 if (!strncmp(p, "disable", len)) {
1521                         p += len;
1522                         if (*p == '=')
1523                                 ++p;
1524                         if (*p == '\0')
1525                                 break;
1526                         ret = kstrtoul(p, 0, &val);
1527                         if (ret)
1528                                 break;
1529
1530                         bridge = val;
1531                         if (bridge < MAX_PHB_BUS_NUM) {
1532                                 printk(KERN_INFO "Calgary: disabling "
1533                                        "translation for PHB %#x\n", bridge);
1534                                 bus_info[bridge].translation_disabled = 1;
1535                         }
1536                 }
1537
1538                 p = strpbrk(p, ",");
1539                 if (!p)
1540                         break;
1541
1542                 p++; /* skip ',' */
1543         }
1544         return 1;
1545 }
1546 __setup("calgary=", calgary_parse_options);
1547
1548 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1549 {
1550         struct iommu_table *tbl;
1551         unsigned int npages;
1552         int i;
1553
1554         tbl = pci_iommu(dev->bus);
1555
1556         for (i = 0; i < 4; i++) {
1557                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1558
1559                 /* Don't give out TCEs that map MEM resources */
1560                 if (!(r->flags & IORESOURCE_MEM))
1561                         continue;
1562
1563                 /* 0-based? we reserve the whole 1st MB anyway */
1564                 if (!r->start)
1565                         continue;
1566
1567                 /* cover the whole region */
1568                 npages = resource_size(r) >> PAGE_SHIFT;
1569                 npages++;
1570
1571                 iommu_range_reserve(tbl, r->start, npages);
1572         }
1573 }
1574
1575 static int __init calgary_fixup_tce_spaces(void)
1576 {
1577         struct pci_dev *dev = NULL;
1578         struct calgary_bus_info *info;
1579
1580         if (no_iommu || swiotlb || !calgary_detected)
1581                 return -ENODEV;
1582
1583         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1584
1585         do {
1586                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1587                 if (!dev)
1588                         break;
1589                 if (!is_cal_pci_dev(dev->device))
1590                         continue;
1591
1592                 info = &bus_info[dev->bus->number];
1593                 if (info->translation_disabled)
1594                         continue;
1595
1596                 if (!info->tce_space)
1597                         continue;
1598
1599                 calgary_fixup_one_tce_space(dev);
1600
1601         } while (1);
1602
1603         return 0;
1604 }
1605
1606 /*
1607  * We need to be call after pcibios_assign_resources (fs_initcall level)
1608  * and before device_initcall.
1609  */
1610 rootfs_initcall(calgary_fixup_tce_spaces);
1611
1612 IOMMU_INIT_POST(detect_calgary);