2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
79 #include <asm/qspinlock.h>
80 #include <asm/intel-family.h>
81 #include <asm/cpu_device_id.h>
82 #include <asm/spec-ctrl.h>
83 #include <asm/hw_irq.h>
85 /* representing HT siblings of each logical CPU */
86 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89 /* representing HT and core siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
95 /* Per CPU bogomips and other parameters */
96 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
97 EXPORT_PER_CPU_SYMBOL(cpu_info);
99 /* Logical package management. We might want to allocate that dynamically */
100 unsigned int __max_logical_packages __read_mostly;
101 EXPORT_SYMBOL(__max_logical_packages);
102 static unsigned int logical_packages __read_mostly;
104 /* Maximum number of SMT threads on any online core */
105 int __read_mostly __max_smt_threads = 1;
107 /* Flag to indicate if a complete sched domain rebuild is required */
108 bool x86_topology_update;
110 int arch_update_cpu_topology(void)
112 int retval = x86_topology_update;
114 x86_topology_update = false;
118 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
122 spin_lock_irqsave(&rtc_lock, flags);
123 CMOS_WRITE(0xa, 0xf);
124 spin_unlock_irqrestore(&rtc_lock, flags);
125 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
127 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
131 static inline void smpboot_restore_warm_reset_vector(void)
136 * Paranoid: Set warm reset code and vector here back
139 spin_lock_irqsave(&rtc_lock, flags);
141 spin_unlock_irqrestore(&rtc_lock, flags);
143 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
147 * Report back to the Boot Processor during boot time or to the caller processor
150 static void smp_callin(void)
155 * If waken up by an INIT in an 82489DX configuration
156 * cpu_callout_mask guarantees we don't get here before
157 * an INIT_deassert IPI reaches our local APIC, so it is
158 * now safe to touch our local APIC.
160 cpuid = smp_processor_id();
163 * (This works even if the APIC is not enabled.)
165 phys_id = read_apic_id();
168 * the boot CPU has finished the init stage and is spinning
169 * on callin_map until we finish. We are free to set up this
170 * CPU, first the APIC. (this is probably redundant on most
176 * Save our processor parameters. Note: this information
177 * is needed for clock calibration.
179 smp_store_cpu_info(cpuid);
182 * The topology information must be up to date before
183 * calibrate_delay() and notify_cpu_starting().
185 set_cpu_sibling_map(raw_smp_processor_id());
189 * Update loops_per_jiffy in cpu_data. Previous call to
190 * smp_store_cpu_info() stored a value that is close but not as
191 * accurate as the value just calculated.
194 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
195 pr_debug("Stack at about %p\n", &cpuid);
199 notify_cpu_starting(cpuid);
202 * Allow the master to continue.
204 cpumask_set_cpu(cpuid, cpu_callin_mask);
207 static int cpu0_logical_apicid;
208 static int enable_start_cpu0;
210 * Activate a secondary processor.
212 static void notrace start_secondary(void *unused)
215 * Don't put *anything* except direct CPU state initialization
216 * before cpu_init(), SMP booting is too fragile that we want to
217 * limit the things done here to the most necessary things.
219 if (boot_cpu_has(X86_FEATURE_PCID))
220 __write_cr4(__read_cr4() | X86_CR4_PCIDE);
223 /* switch away from the initial page table */
224 load_cr3(swapper_pg_dir);
226 * Initialize the CR4 shadow before doing anything that could
234 x86_cpuinit.early_percpu_clock_init();
238 enable_start_cpu0 = 0;
240 /* otherwise gcc will move up smp_processor_id before the cpu_init */
243 * Check TSC synchronization with the boot CPU:
245 check_tsc_sync_target();
247 speculative_store_bypass_ht_init();
250 * Lock vector_lock, set CPU online and bring the vector
251 * allocator online. Online must be set with vector_lock held
252 * to prevent a concurrent irq setup/teardown from seeing a
253 * half valid vector space.
256 set_cpu_online(smp_processor_id(), true);
258 unlock_vector_lock();
259 cpu_set_state_online(smp_processor_id());
260 x86_platform.nmi_init();
262 /* enable local interrupts */
265 /* to prevent fake stack check failure in clock setup */
266 boot_init_stack_canary();
268 x86_cpuinit.setup_percpu_clockev();
271 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
274 * Prevent tail call to cpu_startup_entry() because the stack protector
275 * guard has been changed a couple of function calls up, in
276 * boot_init_stack_canary() and must not be checked before tail calling
279 prevent_tail_call_optimization();
283 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
286 bool topology_is_primary_thread(unsigned int cpu)
288 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
292 * topology_smt_supported - Check whether SMT is supported by the CPUs
294 bool topology_smt_supported(void)
296 return smp_num_siblings > 1;
300 * topology_phys_to_logical_pkg - Map a physical package id to a logical
302 * Returns logical package id or -1 if not found
304 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
308 for_each_possible_cpu(cpu) {
309 struct cpuinfo_x86 *c = &cpu_data(cpu);
311 if (c->initialized && c->phys_proc_id == phys_pkg)
312 return c->logical_proc_id;
316 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
319 * topology_update_package_map - Update the physical to logical package map
320 * @pkg: The physical package id as retrieved via CPUID
321 * @cpu: The cpu for which this is updated
323 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
327 /* Already available somewhere? */
328 new = topology_phys_to_logical_pkg(pkg);
332 new = logical_packages++;
334 pr_info("CPU %u Converting physical %u to logical package %u\n",
338 cpu_data(cpu).logical_proc_id = new;
342 void __init smp_store_boot_cpu_info(void)
344 int id = 0; /* CPU 0 */
345 struct cpuinfo_x86 *c = &cpu_data(id);
349 topology_update_package_map(c->phys_proc_id, id);
350 c->initialized = true;
354 * The bootstrap kernel entry code has set these up. Save them for
357 void smp_store_cpu_info(int id)
359 struct cpuinfo_x86 *c = &cpu_data(id);
361 /* Copy boot_cpu_data only on the first bringup */
366 * During boot time, CPU0 has this setup already. Save the info when
367 * bringing up AP or offlined CPU0.
369 identify_secondary_cpu(c);
370 c->initialized = true;
374 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
376 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
378 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
382 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
384 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
386 return !WARN_ONCE(!topology_same_node(c, o),
387 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
388 "[node: %d != %d]. Ignoring dependency.\n",
389 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
392 #define link_mask(mfunc, c1, c2) \
394 cpumask_set_cpu((c1), mfunc(c2)); \
395 cpumask_set_cpu((c2), mfunc(c1)); \
398 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
400 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
401 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
403 if (c->phys_proc_id == o->phys_proc_id &&
404 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
405 if (c->cpu_core_id == o->cpu_core_id)
406 return topology_sane(c, o, "smt");
408 if ((c->cu_id != 0xff) &&
409 (o->cu_id != 0xff) &&
410 (c->cu_id == o->cu_id))
411 return topology_sane(c, o, "smt");
414 } else if (c->phys_proc_id == o->phys_proc_id &&
415 c->cpu_core_id == o->cpu_core_id) {
416 return topology_sane(c, o, "smt");
423 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
425 * These are Intel CPUs that enumerate an LLC that is shared by
426 * multiple NUMA nodes. The LLC on these systems is shared for
427 * off-package data access but private to the NUMA node (half
428 * of the package) for on-package access.
430 * CPUID (the source of the information about the LLC) can only
431 * enumerate the cache as being shared *or* unshared, but not
432 * this particular configuration. The CPU in this case enumerates
433 * the cache to be shared across the entire package (spanning both
437 static const struct x86_cpu_id snc_cpu[] = {
438 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
442 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
444 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
446 /* Do not match if we do not have a valid APICID for cpu: */
447 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
450 /* Do not match if LLC id does not match: */
451 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
455 * Allow the SNC topology without warning. Return of false
456 * means 'c' does not share the LLC of 'o'. This will be
457 * reflected to userspace.
459 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
462 return topology_sane(c, o, "llc");
466 * Unlike the other levels, we do not enforce keeping a
467 * multicore group inside a NUMA node. If this happens, we will
468 * discard the MC level of the topology later.
470 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
472 if (c->phys_proc_id == o->phys_proc_id)
477 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
478 static inline int x86_sched_itmt_flags(void)
480 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
483 #ifdef CONFIG_SCHED_MC
484 static int x86_core_flags(void)
486 return cpu_core_flags() | x86_sched_itmt_flags();
489 #ifdef CONFIG_SCHED_SMT
490 static int x86_smt_flags(void)
492 return cpu_smt_flags() | x86_sched_itmt_flags();
497 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
498 #ifdef CONFIG_SCHED_SMT
499 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
501 #ifdef CONFIG_SCHED_MC
502 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
507 static struct sched_domain_topology_level x86_topology[] = {
508 #ifdef CONFIG_SCHED_SMT
509 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
511 #ifdef CONFIG_SCHED_MC
512 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
514 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
519 * Set if a package/die has multiple NUMA nodes inside.
520 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
521 * Sub-NUMA Clustering have this.
523 static bool x86_has_numa_in_package;
525 void set_cpu_sibling_map(int cpu)
527 bool has_smt = smp_num_siblings > 1;
528 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
529 struct cpuinfo_x86 *c = &cpu_data(cpu);
530 struct cpuinfo_x86 *o;
533 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
536 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
537 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
538 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
543 for_each_cpu(i, cpu_sibling_setup_mask) {
546 if ((i == cpu) || (has_smt && match_smt(c, o)))
547 link_mask(topology_sibling_cpumask, cpu, i);
549 if ((i == cpu) || (has_mp && match_llc(c, o)))
550 link_mask(cpu_llc_shared_mask, cpu, i);
555 * This needs a separate iteration over the cpus because we rely on all
556 * topology_sibling_cpumask links to be set-up.
558 for_each_cpu(i, cpu_sibling_setup_mask) {
561 if ((i == cpu) || (has_mp && match_die(c, o))) {
562 link_mask(topology_core_cpumask, cpu, i);
565 * Does this new cpu bringup a new core?
568 topology_sibling_cpumask(cpu)) == 1) {
570 * for each core in package, increment
571 * the booted_cores for this new cpu
574 topology_sibling_cpumask(i)) == i)
577 * increment the core count for all
578 * the other cpus in this package
581 cpu_data(i).booted_cores++;
582 } else if (i != cpu && !c->booted_cores)
583 c->booted_cores = cpu_data(i).booted_cores;
585 if (match_die(c, o) && !topology_same_node(c, o))
586 x86_has_numa_in_package = true;
589 threads = cpumask_weight(topology_sibling_cpumask(cpu));
590 if (threads > __max_smt_threads)
591 __max_smt_threads = threads;
594 /* maps the cpu to the sched domain representing multi-core */
595 const struct cpumask *cpu_coregroup_mask(int cpu)
597 return cpu_llc_shared_mask(cpu);
600 static void impress_friends(void)
603 unsigned long bogosum = 0;
605 * Allow the user to impress friends.
607 pr_debug("Before bogomips\n");
608 for_each_possible_cpu(cpu)
609 if (cpumask_test_cpu(cpu, cpu_callout_mask))
610 bogosum += cpu_data(cpu).loops_per_jiffy;
611 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
614 (bogosum/(5000/HZ))%100);
616 pr_debug("Before bogocount - setting activated=1\n");
619 void __inquire_remote_apic(int apicid)
621 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
622 const char * const names[] = { "ID", "VERSION", "SPIV" };
626 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
628 for (i = 0; i < ARRAY_SIZE(regs); i++) {
629 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
634 status = safe_apic_wait_icr_idle();
636 pr_cont("a previous APIC delivery may have failed\n");
638 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
643 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
644 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
647 case APIC_ICR_RR_VALID:
648 status = apic_read(APIC_RRR);
649 pr_cont("%08x\n", status);
658 * The Multiprocessor Specification 1.4 (1997) example code suggests
659 * that there should be a 10ms delay between the BSP asserting INIT
660 * and de-asserting INIT, when starting a remote processor.
661 * But that slows boot and resume on modern processors, which include
662 * many cores and don't require that delay.
664 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
665 * Modern processor families are quirked to remove the delay entirely.
667 #define UDELAY_10MS_DEFAULT 10000
669 static unsigned int init_udelay = UINT_MAX;
671 static int __init cpu_init_udelay(char *str)
673 get_option(&str, &init_udelay);
677 early_param("cpu_init_udelay", cpu_init_udelay);
679 static void __init smp_quirk_init_udelay(void)
681 /* if cmdline changed it from default, leave it alone */
682 if (init_udelay != UINT_MAX)
685 /* if modern processor, use no delay */
686 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
687 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
691 /* else, use legacy delay */
692 init_udelay = UDELAY_10MS_DEFAULT;
696 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
697 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
698 * won't ... remember to clear down the APIC, etc later.
701 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
703 unsigned long send_status, accept_status = 0;
707 /* Boot on the stack */
708 /* Kick the second */
709 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
711 pr_debug("Waiting for send to finish...\n");
712 send_status = safe_apic_wait_icr_idle();
715 * Give the other CPU some time to accept the IPI.
718 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
719 maxlvt = lapic_get_maxlvt();
720 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
721 apic_write(APIC_ESR, 0);
722 accept_status = (apic_read(APIC_ESR) & 0xEF);
724 pr_debug("NMI sent\n");
727 pr_err("APIC never delivered???\n");
729 pr_err("APIC delivery error (%lx)\n", accept_status);
731 return (send_status | accept_status);
735 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
737 unsigned long send_status = 0, accept_status = 0;
738 int maxlvt, num_starts, j;
740 maxlvt = lapic_get_maxlvt();
743 * Be paranoid about clearing APIC errors.
745 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
746 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
747 apic_write(APIC_ESR, 0);
751 pr_debug("Asserting INIT\n");
754 * Turn INIT on target chip
759 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
762 pr_debug("Waiting for send to finish...\n");
763 send_status = safe_apic_wait_icr_idle();
767 pr_debug("Deasserting INIT\n");
771 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
773 pr_debug("Waiting for send to finish...\n");
774 send_status = safe_apic_wait_icr_idle();
779 * Should we send STARTUP IPIs ?
781 * Determine this based on the APIC version.
782 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
784 if (APIC_INTEGRATED(boot_cpu_apic_version))
790 * Run STARTUP IPI loop.
792 pr_debug("#startup loops: %d\n", num_starts);
794 for (j = 1; j <= num_starts; j++) {
795 pr_debug("Sending STARTUP #%d\n", j);
796 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
797 apic_write(APIC_ESR, 0);
799 pr_debug("After apic_write\n");
806 /* Boot on the stack */
807 /* Kick the second */
808 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
812 * Give the other CPU some time to accept the IPI.
814 if (init_udelay == 0)
819 pr_debug("Startup point 1\n");
821 pr_debug("Waiting for send to finish...\n");
822 send_status = safe_apic_wait_icr_idle();
825 * Give the other CPU some time to accept the IPI.
827 if (init_udelay == 0)
832 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
833 apic_write(APIC_ESR, 0);
834 accept_status = (apic_read(APIC_ESR) & 0xEF);
835 if (send_status || accept_status)
838 pr_debug("After Startup\n");
841 pr_err("APIC never delivered???\n");
843 pr_err("APIC delivery error (%lx)\n", accept_status);
845 return (send_status | accept_status);
848 /* reduce the number of lines printed when booting a large cpu count system */
849 static void announce_cpu(int cpu, int apicid)
851 static int current_node = -1;
852 int node = early_cpu_to_node(cpu);
853 static int width, node_width;
856 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
859 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
862 printk(KERN_INFO "x86: Booting SMP configuration:\n");
864 if (system_state < SYSTEM_RUNNING) {
865 if (node != current_node) {
866 if (current_node > (-1))
870 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
871 node_width - num_digits(node), " ", node);
874 /* Add padding for the BSP */
876 pr_cont("%*s", width + 1, " ");
878 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
881 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
885 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
889 cpu = smp_processor_id();
890 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
897 * Wake up AP by INIT, INIT, STARTUP sequence.
899 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
900 * boot-strap code which is not a desired behavior for waking up BSP. To
901 * void the boot-strap code, wake up CPU0 by NMI instead.
903 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
904 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
905 * We'll change this code in the future to wake up hard offlined CPU0 if
906 * real platform and request are available.
909 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
910 int *cpu0_nmi_registered)
918 * Wake up AP by INIT, INIT, STARTUP sequence.
921 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
926 * Wake up BSP by nmi.
928 * Register a NMI handler to help wake up CPU0.
930 boot_error = register_nmi_handler(NMI_LOCAL,
931 wakeup_cpu0_nmi, 0, "wake_cpu0");
934 enable_start_cpu0 = 1;
935 *cpu0_nmi_registered = 1;
936 if (apic->dest_logical == APIC_DEST_LOGICAL)
937 id = cpu0_logical_apicid;
940 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
949 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
951 /* Just in case we booted with a single CPU. */
952 alternatives_enable_smp();
954 per_cpu(current_task, cpu) = idle;
957 /* Stack for startup_32 can be just as for start_secondary onwards */
959 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
961 initial_gs = per_cpu_offset(cpu);
966 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
967 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
968 * Returns zero if CPU booted OK, else error code from
969 * ->wakeup_secondary_cpu.
971 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
972 int *cpu0_nmi_registered)
974 volatile u32 *trampoline_status =
975 (volatile u32 *) __va(real_mode_header->trampoline_status);
976 /* start_ip had better be page-aligned! */
977 unsigned long start_ip = real_mode_header->trampoline_start;
979 unsigned long boot_error = 0;
980 unsigned long timeout;
982 idle->thread.sp = (unsigned long)task_pt_regs(idle);
983 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
984 initial_code = (unsigned long)start_secondary;
985 initial_stack = idle->thread.sp;
987 /* Enable the espfix hack for this CPU */
990 /* So we see what's up */
991 announce_cpu(cpu, apicid);
994 * This grunge runs the startup process for
995 * the targeted processor.
998 if (x86_platform.legacy.warm_reset) {
1000 pr_debug("Setting warm reset code and vector.\n");
1002 smpboot_setup_warm_reset_vector(start_ip);
1004 * Be paranoid about clearing APIC errors.
1006 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1007 apic_write(APIC_ESR, 0);
1008 apic_read(APIC_ESR);
1013 * AP might wait on cpu_callout_mask in cpu_init() with
1014 * cpu_initialized_mask set if previous attempt to online
1015 * it timed-out. Clear cpu_initialized_mask so that after
1016 * INIT/SIPI it could start with a clean state.
1018 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1022 * Wake up a CPU in difference cases:
1023 * - Use the method in the APIC driver if it's defined
1025 * - Use an INIT boot APIC message for APs or NMI for BSP.
1027 if (apic->wakeup_secondary_cpu)
1028 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1030 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1031 cpu0_nmi_registered);
1035 * Wait 10s total for first sign of life from AP
1038 timeout = jiffies + 10*HZ;
1039 while (time_before(jiffies, timeout)) {
1040 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1042 * Tell AP to proceed with initialization
1044 cpumask_set_cpu(cpu, cpu_callout_mask);
1054 * Wait till AP completes initial initialization
1056 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1058 * Allow other tasks to run while we wait for the
1059 * AP to come online. This also gives a chance
1060 * for the MTRR work(triggered by the AP coming online)
1061 * to be completed in the stop machine context.
1067 /* mark "stuck" area as not stuck */
1068 *trampoline_status = 0;
1070 if (x86_platform.legacy.warm_reset) {
1072 * Cleanup possible dangling ends...
1074 smpboot_restore_warm_reset_vector();
1080 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1082 int apicid = apic->cpu_present_to_apicid(cpu);
1083 int cpu0_nmi_registered = 0;
1084 unsigned long flags;
1087 lockdep_assert_irqs_enabled();
1089 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1091 if (apicid == BAD_APICID ||
1092 !physid_isset(apicid, phys_cpu_present_map) ||
1093 !apic->apic_id_valid(apicid)) {
1094 pr_err("%s: bad cpu %d\n", __func__, cpu);
1099 * Already booted CPU?
1101 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1102 pr_debug("do_boot_cpu %d Already started\n", cpu);
1107 * Save current MTRR state in case it was changed since early boot
1108 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1112 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1113 err = cpu_check_up_prepare(cpu);
1114 if (err && err != -EBUSY)
1117 /* the FPU context is blank, nobody can own it */
1118 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1120 common_cpu_up(cpu, tidle);
1122 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1124 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1130 * Check TSC synchronization with the AP (keep irqs disabled
1133 local_irq_save(flags);
1134 check_tsc_sync_source(cpu);
1135 local_irq_restore(flags);
1137 while (!cpu_online(cpu)) {
1139 touch_nmi_watchdog();
1144 * Clean up the nmi handler. Do this after the callin and callout sync
1145 * to avoid impact of possible long unregister time.
1147 if (cpu0_nmi_registered)
1148 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1154 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1156 void arch_disable_smp_support(void)
1158 disable_ioapic_support();
1162 * Fall back to non SMP mode after errors.
1164 * RED-PEN audit/test this more. I bet there is more state messed up here.
1166 static __init void disable_smp(void)
1168 pr_info("SMP disabled\n");
1170 disable_ioapic_support();
1172 init_cpu_present(cpumask_of(0));
1173 init_cpu_possible(cpumask_of(0));
1175 if (smp_found_config)
1176 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1178 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1179 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1180 cpumask_set_cpu(0, topology_core_cpumask(0));
1184 * Various sanity checks.
1186 static void __init smp_sanity_check(void)
1190 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1191 if (def_to_bigsmp && nr_cpu_ids > 8) {
1195 pr_warn("More than 8 CPUs detected - skipping them\n"
1196 "Use CONFIG_X86_BIGSMP\n");
1199 for_each_present_cpu(cpu) {
1201 set_cpu_present(cpu, false);
1206 for_each_possible_cpu(cpu) {
1208 set_cpu_possible(cpu, false);
1216 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1217 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1218 hard_smp_processor_id());
1220 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1224 * Should not be necessary because the MP table should list the boot
1225 * CPU too, but we do it for the sake of robustness anyway.
1227 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1228 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1229 boot_cpu_physical_apicid);
1230 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1235 static void __init smp_cpu_index_default(void)
1238 struct cpuinfo_x86 *c;
1240 for_each_possible_cpu(i) {
1242 /* mark all to hotplug */
1243 c->cpu_index = nr_cpu_ids;
1247 static void __init smp_get_logical_apicid(void)
1250 cpu0_logical_apicid = apic_read(APIC_LDR);
1252 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1256 * Prepare for SMP bootup.
1257 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1258 * for common interface support.
1260 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1264 smp_cpu_index_default();
1267 * Setup boot CPU information
1269 smp_store_boot_cpu_info(); /* Final full version of the data */
1270 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1273 for_each_possible_cpu(i) {
1274 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1275 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1276 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1280 * Set 'default' x86 topology, this matches default_topology() in that
1281 * it has NUMA nodes as a topology level. See also
1282 * native_smp_cpus_done().
1284 * Must be done before set_cpus_sibling_map() is ran.
1286 set_sched_topology(x86_topology);
1288 set_cpu_sibling_map(0);
1292 switch (apic_intr_mode) {
1294 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1297 case APIC_SYMMETRIC_IO_NO_ROUTING:
1299 /* Setup local timer */
1300 x86_init.timers.setup_percpu_clockev();
1302 case APIC_VIRTUAL_WIRE:
1303 case APIC_SYMMETRIC_IO:
1307 /* Setup local timer */
1308 x86_init.timers.setup_percpu_clockev();
1310 smp_get_logical_apicid();
1313 print_cpu_info(&cpu_data(0));
1315 native_pv_lock_init();
1319 set_mtrr_aps_delayed_init();
1321 smp_quirk_init_udelay();
1323 speculative_store_bypass_ht_init();
1326 void arch_enable_nonboot_cpus_begin(void)
1328 set_mtrr_aps_delayed_init();
1331 void arch_enable_nonboot_cpus_end(void)
1337 * Early setup to make printk work.
1339 void __init native_smp_prepare_boot_cpu(void)
1341 int me = smp_processor_id();
1342 switch_to_new_gdt(me);
1343 /* already set me in cpu_online_mask in boot_cpu_init() */
1344 cpumask_set_cpu(me, cpu_callout_mask);
1345 cpu_set_state_online(me);
1348 void __init calculate_max_logical_packages(void)
1353 * Today neither Intel nor AMD support heterogenous systems so
1354 * extrapolate the boot cpu's data to all packages.
1356 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1357 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1358 pr_info("Max logical packages: %u\n", __max_logical_packages);
1361 void __init native_smp_cpus_done(unsigned int max_cpus)
1363 pr_debug("Boot done\n");
1365 calculate_max_logical_packages();
1367 if (x86_has_numa_in_package)
1368 set_sched_topology(x86_numa_in_package_topology);
1375 static int __initdata setup_possible_cpus = -1;
1376 static int __init _setup_possible_cpus(char *str)
1378 get_option(&str, &setup_possible_cpus);
1381 early_param("possible_cpus", _setup_possible_cpus);
1385 * cpu_possible_mask should be static, it cannot change as cpu's
1386 * are onlined, or offlined. The reason is per-cpu data-structures
1387 * are allocated by some modules at init time, and dont expect to
1388 * do this dynamically on cpu arrival/departure.
1389 * cpu_present_mask on the other hand can change dynamically.
1390 * In case when cpu_hotplug is not compiled, then we resort to current
1391 * behaviour, which is cpu_possible == cpu_present.
1394 * Three ways to find out the number of additional hotplug CPUs:
1395 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1396 * - The user can overwrite it with possible_cpus=NUM
1397 * - Otherwise don't reserve additional CPUs.
1398 * We do this because additional CPUs waste a lot of memory.
1401 __init void prefill_possible_map(void)
1405 /* No boot processor was found in mptable or ACPI MADT */
1406 if (!num_processors) {
1407 if (boot_cpu_has(X86_FEATURE_APIC)) {
1408 int apicid = boot_cpu_physical_apicid;
1409 int cpu = hard_smp_processor_id();
1411 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1413 /* Make sure boot cpu is enumerated */
1414 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1415 apic->apic_id_valid(apicid))
1416 generic_processor_info(apicid, boot_cpu_apic_version);
1419 if (!num_processors)
1423 i = setup_max_cpus ?: 1;
1424 if (setup_possible_cpus == -1) {
1425 possible = num_processors;
1426 #ifdef CONFIG_HOTPLUG_CPU
1428 possible += disabled_cpus;
1434 possible = setup_possible_cpus;
1436 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1438 /* nr_cpu_ids could be reduced via nr_cpus= */
1439 if (possible > nr_cpu_ids) {
1440 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1441 possible, nr_cpu_ids);
1442 possible = nr_cpu_ids;
1445 #ifdef CONFIG_HOTPLUG_CPU
1446 if (!setup_max_cpus)
1449 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1450 possible, setup_max_cpus);
1454 nr_cpu_ids = possible;
1456 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1457 possible, max_t(int, possible - num_processors, 0));
1459 reset_cpu_possible_mask();
1461 for (i = 0; i < possible; i++)
1462 set_cpu_possible(i, true);
1465 #ifdef CONFIG_HOTPLUG_CPU
1467 /* Recompute SMT state for all CPUs on offline */
1468 static void recompute_smt_state(void)
1470 int max_threads, cpu;
1473 for_each_online_cpu (cpu) {
1474 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1476 if (threads > max_threads)
1477 max_threads = threads;
1479 __max_smt_threads = max_threads;
1482 static void remove_siblinginfo(int cpu)
1485 struct cpuinfo_x86 *c = &cpu_data(cpu);
1487 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1488 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1490 * last thread sibling in this cpu core going down
1492 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1493 cpu_data(sibling).booted_cores--;
1496 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1497 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1498 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1499 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1500 cpumask_clear(cpu_llc_shared_mask(cpu));
1501 cpumask_clear(topology_sibling_cpumask(cpu));
1502 cpumask_clear(topology_core_cpumask(cpu));
1504 c->booted_cores = 0;
1505 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1506 recompute_smt_state();
1509 static void remove_cpu_from_maps(int cpu)
1511 set_cpu_online(cpu, false);
1512 cpumask_clear_cpu(cpu, cpu_callout_mask);
1513 cpumask_clear_cpu(cpu, cpu_callin_mask);
1514 /* was set by cpu_init() */
1515 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1516 numa_remove_cpu(cpu);
1519 void cpu_disable_common(void)
1521 int cpu = smp_processor_id();
1523 remove_siblinginfo(cpu);
1525 /* It's now safe to remove this processor from the online map */
1527 remove_cpu_from_maps(cpu);
1528 unlock_vector_lock();
1533 int native_cpu_disable(void)
1537 ret = lapic_can_unplug_cpu();
1542 cpu_disable_common();
1547 int common_cpu_die(unsigned int cpu)
1551 /* We don't do anything here: idle task is faking death itself. */
1553 /* They ack this in play_dead() by setting CPU_DEAD */
1554 if (cpu_wait_death(cpu, 5)) {
1555 if (system_state == SYSTEM_RUNNING)
1556 pr_info("CPU %u is now offline\n", cpu);
1558 pr_err("CPU %u didn't die...\n", cpu);
1565 void native_cpu_die(unsigned int cpu)
1567 common_cpu_die(cpu);
1570 void play_dead_common(void)
1575 (void)cpu_report_death();
1578 * With physical CPU hotplug, we should halt the cpu
1580 local_irq_disable();
1583 static bool wakeup_cpu0(void)
1585 if (smp_processor_id() == 0 && enable_start_cpu0)
1592 * We need to flush the caches before going to sleep, lest we have
1593 * dirty data in our caches when we come back up.
1595 static inline void mwait_play_dead(void)
1597 unsigned int eax, ebx, ecx, edx;
1598 unsigned int highest_cstate = 0;
1599 unsigned int highest_subcstate = 0;
1603 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1605 if (!this_cpu_has(X86_FEATURE_MWAIT))
1607 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1609 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1612 eax = CPUID_MWAIT_LEAF;
1614 native_cpuid(&eax, &ebx, &ecx, &edx);
1617 * eax will be 0 if EDX enumeration is not valid.
1618 * Initialized below to cstate, sub_cstate value when EDX is valid.
1620 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1623 edx >>= MWAIT_SUBSTATE_SIZE;
1624 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1625 if (edx & MWAIT_SUBSTATE_MASK) {
1627 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1630 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1631 (highest_subcstate - 1);
1635 * This should be a memory location in a cache line which is
1636 * unlikely to be touched by other processors. The actual
1637 * content is immaterial as it is not actually modified in any way.
1639 mwait_ptr = ¤t_thread_info()->flags;
1645 * The CLFLUSH is a workaround for erratum AAI65 for
1646 * the Xeon 7400 series. It's not clear it is actually
1647 * needed, but it should be harmless in either case.
1648 * The WBINVD is insufficient due to the spurious-wakeup
1649 * case where we return around the loop.
1654 __monitor(mwait_ptr, 0, 0);
1658 * If NMI wants to wake up CPU0, start CPU0.
1665 void hlt_play_dead(void)
1667 if (__this_cpu_read(cpu_info.x86) >= 4)
1673 * If NMI wants to wake up CPU0, start CPU0.
1680 void native_play_dead(void)
1683 tboot_shutdown(TB_SHUTDOWN_WFS);
1685 mwait_play_dead(); /* Only returns on failure */
1686 if (cpuidle_play_dead())
1690 #else /* ... !CONFIG_HOTPLUG_CPU */
1691 int native_cpu_disable(void)
1696 void native_cpu_die(unsigned int cpu)
1698 /* We said "no" in __cpu_disable */
1702 void native_play_dead(void)