arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...) do {} while (0)
  59
  60 /* 14 is the version for Xeon and Pentium 8.4.8*/
  61 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  62 #define LAPIC_MMIO_LENGTH               (1 << 12)
  63 /* followed define is not in apicdef.h */
  64 #define APIC_SHORT_MASK                 0xc0000
  65 #define APIC_DEST_NOSHORT               0x0
  66 #define APIC_DEST_MASK                  0x800
  67 #define MAX_APIC_VECTOR                 256
  68 #define APIC_VECTORS_PER_REG            32
  69
  70 #define APIC_BROADCAST                  0xFF
  71 #define X2APIC_BROADCAST                0xFFFFFFFFul
  72
  73 static inline int apic_test_vector(int vec, void *bitmap)
  74 {
  75         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  76 }
  77
  78 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  79 {
  80         struct kvm_lapic *apic = vcpu->arch.apic;
  81
  82         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  83                 apic_test_vector(vector, apic->regs + APIC_IRR);
  84 }
  85
  86 static inline void apic_clear_vector(int vec, void *bitmap)
  87 {
  88         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  92 {
  93         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
  97 {
  98         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 struct static_key_deferred apic_hw_disabled __read_mostly;
 102 struct static_key_deferred apic_sw_disabled __read_mostly;
 103
 104 static inline int apic_enabled(struct kvm_lapic *apic)
 105 {
 106         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 107 }
 108
 109 #define LVT_MASK        \
 110         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 111
 112 #define LINT_MASK       \
 113         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 114          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 115
 116 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 117 {
 118         return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 119 }
 120
 121 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
 122 {
 123         return apic->vcpu->vcpu_id;
 124 }
 125
 126 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 127                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 128         switch (map->mode) {
 129         case KVM_APIC_MODE_X2APIC: {
 130                 u32 offset = (dest_id >> 16) * 16;
 131                 u32 max_apic_id = map->max_apic_id;
 132
 133                 if (offset <= max_apic_id) {
 134                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 135
 136                         offset = array_index_nospec(offset, map->max_apic_id + 1);
 137                         *cluster = &map->phys_map[offset];
 138                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 139                 } else {
 140                         *mask = 0;
 141                 }
 142
 143                 return true;
 144                 }
 145         case KVM_APIC_MODE_XAPIC_FLAT:
 146                 *cluster = map->xapic_flat_map;
 147                 *mask = dest_id & 0xff;
 148                 return true;
 149         case KVM_APIC_MODE_XAPIC_CLUSTER:
 150                 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
 151                 *mask = dest_id & 0xf;
 152                 return true;
 153         default:
 154                 /* Not optimized. */
 155                 return false;
 156         }
 157 }
 158
 159 static void kvm_apic_map_free(struct rcu_head *rcu)
 160 {
 161         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 162
 163         kvfree(map);
 164 }
 165
 166 static void recalculate_apic_map(struct kvm *kvm)
 167 {
 168         struct kvm_apic_map *new, *old = NULL;
 169         struct kvm_vcpu *vcpu;
 170         int i;
 171         u32 max_id = 255; /* enough space for any xAPIC ID */
 172
 173         mutex_lock(&kvm->arch.apic_map_lock);
 174
 175         kvm_for_each_vcpu(i, vcpu, kvm)
 176                 if (kvm_apic_present(vcpu))
 177                         max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
 178
 179         new = kvzalloc(sizeof(struct kvm_apic_map) +
 180                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL);
 181
 182         if (!new)
 183                 goto out;
 184
 185         new->max_apic_id = max_id;
 186
 187         kvm_for_each_vcpu(i, vcpu, kvm) {
 188                 struct kvm_lapic *apic = vcpu->arch.apic;
 189                 struct kvm_lapic **cluster;
 190                 u16 mask;
 191                 u32 ldr;
 192                 u8 xapic_id;
 193                 u32 x2apic_id;
 194
 195                 if (!kvm_apic_present(vcpu))
 196                         continue;
 197
 198                 xapic_id = kvm_xapic_id(apic);
 199                 x2apic_id = kvm_x2apic_id(apic);
 200
 201                 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
 202                 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
 203                                 x2apic_id <= new->max_apic_id)
 204                         new->phys_map[x2apic_id] = apic;
 205                 /*
 206                  * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
 207                  * prevent them from masking VCPUs with APIC ID <= 0xff.
 208                  */
 209                 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
 210                         new->phys_map[xapic_id] = apic;
 211
 212                 if (!kvm_apic_sw_enabled(apic))
 213                         continue;
 214
 215                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 216
 217                 if (apic_x2apic_mode(apic)) {
 218                         new->mode |= KVM_APIC_MODE_X2APIC;
 219                 } else if (ldr) {
 220                         ldr = GET_APIC_LOGICAL_ID(ldr);
 221                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 222                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 223                         else
 224                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 225                 }
 226
 227                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 228                         continue;
 229
 230                 if (mask)
 231                         cluster[ffs(mask) - 1] = apic;
 232         }
 233 out:
 234         old = rcu_dereference_protected(kvm->arch.apic_map,
 235                         lockdep_is_held(&kvm->arch.apic_map_lock));
 236         rcu_assign_pointer(kvm->arch.apic_map, new);
 237         mutex_unlock(&kvm->arch.apic_map_lock);
 238
 239         if (old)
 240                 call_rcu(&old->rcu, kvm_apic_map_free);
 241
 242         kvm_make_scan_ioapic_request(kvm);
 243 }
 244
 245 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 246 {
 247         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 248
 249         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 250
 251         if (enabled != apic->sw_enabled) {
 252                 apic->sw_enabled = enabled;
 253                 if (enabled) {
 254                         static_key_slow_dec_deferred(&apic_sw_disabled);
 255                         recalculate_apic_map(apic->vcpu->kvm);
 256                 } else
 257                         static_key_slow_inc(&apic_sw_disabled.key);
 258
 259                 recalculate_apic_map(apic->vcpu->kvm);
 260         }
 261 }
 262
 263 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 264 {
 265         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 266         recalculate_apic_map(apic->vcpu->kvm);
 267 }
 268
 269 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 270 {
 271         kvm_lapic_set_reg(apic, APIC_LDR, id);
 272         recalculate_apic_map(apic->vcpu->kvm);
 273 }
 274
 275 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
 276 {
 277         return ((id >> 4) << 16) | (1 << (id & 0xf));
 278 }
 279
 280 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 281 {
 282         u32 ldr = kvm_apic_calc_x2apic_ldr(id);
 283
 284         WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
 285
 286         kvm_lapic_set_reg(apic, APIC_ID, id);
 287         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 288         recalculate_apic_map(apic->vcpu->kvm);
 289 }
 290
 291 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 292 {
 293         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 294 }
 295
 296 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 297 {
 298         return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 299 }
 300
 301 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 302 {
 303         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 304 }
 305
 306 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 307 {
 308         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 309 }
 310
 311 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 312 {
 313         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 314 }
 315
 316 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 317 {
 318         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 319 }
 320
 321 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 322 {
 323         struct kvm_lapic *apic = vcpu->arch.apic;
 324         struct kvm_cpuid_entry2 *feat;
 325         u32 v = APIC_VERSION;
 326
 327         if (!lapic_in_kernel(vcpu))
 328                 return;
 329
 330         /*
 331          * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
 332          * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
 333          * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
 334          * version first and level-triggered interrupts never get EOIed in
 335          * IOAPIC.
 336          */
 337         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 338         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
 339             !ioapic_in_kernel(vcpu->kvm))
 340                 v |= APIC_LVR_DIRECTED_EOI;
 341         kvm_lapic_set_reg(apic, APIC_LVR, v);
 342 }
 343
 344 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 345         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 346         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 347         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 348         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 349         LVT_MASK                /* LVTERR */
 350 };
 351
 352 static int find_highest_vector(void *bitmap)
 353 {
 354         int vec;
 355         u32 *reg;
 356
 357         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 358              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 359                 reg = bitmap + REG_POS(vec);
 360                 if (*reg)
 361                         return __fls(*reg) + vec;
 362         }
 363
 364         return -1;
 365 }
 366
 367 static u8 count_vectors(void *bitmap)
 368 {
 369         int vec;
 370         u32 *reg;
 371         u8 count = 0;
 372
 373         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 374                 reg = bitmap + REG_POS(vec);
 375                 count += hweight32(*reg);
 376         }
 377
 378         return count;
 379 }
 380
 381 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
 382 {
 383         u32 i, vec;
 384         u32 pir_val, irr_val, prev_irr_val;
 385         int max_updated_irr;
 386
 387         max_updated_irr = -1;
 388         *max_irr = -1;
 389
 390         for (i = vec = 0; i <= 7; i++, vec += 32) {
 391                 pir_val = READ_ONCE(pir[i]);
 392                 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
 393                 if (pir_val) {
 394                         prev_irr_val = irr_val;
 395                         irr_val |= xchg(&pir[i], 0);
 396                         *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
 397                         if (prev_irr_val != irr_val) {
 398                                 max_updated_irr =
 399                                         __fls(irr_val ^ prev_irr_val) + vec;
 400                         }
 401                 }
 402                 if (irr_val)
 403                         *max_irr = __fls(irr_val) + vec;
 404         }
 405
 406         return ((max_updated_irr != -1) &&
 407                 (max_updated_irr == *max_irr));
 408 }
 409 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 410
 411 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
 412 {
 413         struct kvm_lapic *apic = vcpu->arch.apic;
 414
 415         return __kvm_apic_update_irr(pir, apic->regs, max_irr);
 416 }
 417 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 418
 419 static inline int apic_search_irr(struct kvm_lapic *apic)
 420 {
 421         return find_highest_vector(apic->regs + APIC_IRR);
 422 }
 423
 424 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 425 {
 426         int result;
 427
 428         /*
 429          * Note that irr_pending is just a hint. It will be always
 430          * true with virtual interrupt delivery enabled.
 431          */
 432         if (!apic->irr_pending)
 433                 return -1;
 434
 435         result = apic_search_irr(apic);
 436         ASSERT(result == -1 || result >= 16);
 437
 438         return result;
 439 }
 440
 441 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 442 {
 443         struct kvm_vcpu *vcpu;
 444
 445         vcpu = apic->vcpu;
 446
 447         if (unlikely(vcpu->arch.apicv_active)) {
 448                 /* need to update RVI */
 449                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 450                 kvm_x86_ops->hwapic_irr_update(vcpu,
 451                                 apic_find_highest_irr(apic));
 452         } else {
 453                 apic->irr_pending = false;
 454                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 455                 if (apic_search_irr(apic) != -1)
 456                         apic->irr_pending = true;
 457         }
 458 }
 459
 460 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 461 {
 462         struct kvm_vcpu *vcpu;
 463
 464         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 465                 return;
 466
 467         vcpu = apic->vcpu;
 468
 469         /*
 470          * With APIC virtualization enabled, all caching is disabled
 471          * because the processor can modify ISR under the hood.  Instead
 472          * just set SVI.
 473          */
 474         if (unlikely(vcpu->arch.apicv_active))
 475                 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
 476         else {
 477                 ++apic->isr_count;
 478                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 479                 /*
 480                  * ISR (in service register) bit is set when injecting an interrupt.
 481                  * The highest vector is injected. Thus the latest bit set matches
 482                  * the highest bit in ISR.
 483                  */
 484                 apic->highest_isr_cache = vec;
 485         }
 486 }
 487
 488 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 489 {
 490         int result;
 491
 492         /*
 493          * Note that isr_count is always 1, and highest_isr_cache
 494          * is always -1, with APIC virtualization enabled.
 495          */
 496         if (!apic->isr_count)
 497                 return -1;
 498         if (likely(apic->highest_isr_cache != -1))
 499                 return apic->highest_isr_cache;
 500
 501         result = find_highest_vector(apic->regs + APIC_ISR);
 502         ASSERT(result == -1 || result >= 16);
 503
 504         return result;
 505 }
 506
 507 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 508 {
 509         struct kvm_vcpu *vcpu;
 510         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 511                 return;
 512
 513         vcpu = apic->vcpu;
 514
 515         /*
 516          * We do get here for APIC virtualization enabled if the guest
 517          * uses the Hyper-V APIC enlightenment.  In this case we may need
 518          * to trigger a new interrupt delivery by writing the SVI field;
 519          * on the other hand isr_count and highest_isr_cache are unused
 520          * and must be left alone.
 521          */
 522         if (unlikely(vcpu->arch.apicv_active))
 523                 kvm_x86_ops->hwapic_isr_update(vcpu,
 524                                                apic_find_highest_isr(apic));
 525         else {
 526                 --apic->isr_count;
 527                 BUG_ON(apic->isr_count < 0);
 528                 apic->highest_isr_cache = -1;
 529         }
 530 }
 531
 532 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 533 {
 534         /* This may race with setting of irr in __apic_accept_irq() and
 535          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 536          * will cause vmexit immediately and the value will be recalculated
 537          * on the next vmentry.
 538          */
 539         return apic_find_highest_irr(vcpu->arch.apic);
 540 }
 541 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 542
 543 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 544                              int vector, int level, int trig_mode,
 545                              struct dest_map *dest_map);
 546
 547 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 548                      struct dest_map *dest_map)
 549 {
 550         struct kvm_lapic *apic = vcpu->arch.apic;
 551
 552         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 553                         irq->level, irq->trig_mode, dest_map);
 554 }
 555
 556 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
 557                     unsigned long ipi_bitmap_high, u32 min,
 558                     unsigned long icr, int op_64_bit)
 559 {
 560         int i;
 561         struct kvm_apic_map *map;
 562         struct kvm_vcpu *vcpu;
 563         struct kvm_lapic_irq irq = {0};
 564         int cluster_size = op_64_bit ? 64 : 32;
 565         int count = 0;
 566
 567         irq.vector = icr & APIC_VECTOR_MASK;
 568         irq.delivery_mode = icr & APIC_MODE_MASK;
 569         irq.level = (icr & APIC_INT_ASSERT) != 0;
 570         irq.trig_mode = icr & APIC_INT_LEVELTRIG;
 571
 572         if (icr & APIC_DEST_MASK)
 573                 return -KVM_EINVAL;
 574         if (icr & APIC_SHORT_MASK)
 575                 return -KVM_EINVAL;
 576
 577         rcu_read_lock();
 578         map = rcu_dereference(kvm->arch.apic_map);
 579
 580         if (unlikely(!map)) {
 581                 count = -EOPNOTSUPP;
 582                 goto out;
 583         }
 584
 585         if (min > map->max_apic_id)
 586                 goto out;
 587         /* Bits above cluster_size are masked in the caller.  */
 588         for_each_set_bit(i, &ipi_bitmap_low,
 589                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 590                 if (map->phys_map[min + i]) {
 591                         vcpu = map->phys_map[min + i]->vcpu;
 592                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 593                 }
 594         }
 595
 596         min += cluster_size;
 597
 598         if (min > map->max_apic_id)
 599                 goto out;
 600
 601         for_each_set_bit(i, &ipi_bitmap_high,
 602                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 603                 if (map->phys_map[min + i]) {
 604                         vcpu = map->phys_map[min + i]->vcpu;
 605                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 606                 }
 607         }
 608
 609 out:
 610         rcu_read_unlock();
 611         return count;
 612 }
 613
 614 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 615 {
 616
 617         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 618                                       sizeof(val));
 619 }
 620
 621 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 622 {
 623
 624         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 625                                       sizeof(*val));
 626 }
 627
 628 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 629 {
 630         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 631 }
 632
 633 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 634 {
 635         u8 val;
 636         if (pv_eoi_get_user(vcpu, &val) < 0) {
 637                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 638                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 639                 return false;
 640         }
 641         return val & 0x1;
 642 }
 643
 644 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 645 {
 646         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 647                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 648                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 649                 return;
 650         }
 651         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 652 }
 653
 654 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 655 {
 656         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 657                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 658                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 659                 return;
 660         }
 661         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 662 }
 663
 664 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
 665 {
 666         int highest_irr;
 667         if (apic->vcpu->arch.apicv_active)
 668                 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 669         else
 670                 highest_irr = apic_find_highest_irr(apic);
 671         if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
 672                 return -1;
 673         return highest_irr;
 674 }
 675
 676 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
 677 {
 678         u32 tpr, isrv, ppr, old_ppr;
 679         int isr;
 680
 681         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 682         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 683         isr = apic_find_highest_isr(apic);
 684         isrv = (isr != -1) ? isr : 0;
 685
 686         if ((tpr & 0xf0) >= (isrv & 0xf0))
 687                 ppr = tpr & 0xff;
 688         else
 689                 ppr = isrv & 0xf0;
 690
 691         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 692                    apic, ppr, isr, isrv);
 693
 694         *new_ppr = ppr;
 695         if (old_ppr != ppr)
 696                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 697
 698         return ppr < old_ppr;
 699 }
 700
 701 static void apic_update_ppr(struct kvm_lapic *apic)
 702 {
 703         u32 ppr;
 704
 705         if (__apic_update_ppr(apic, &ppr) &&
 706             apic_has_interrupt_for_ppr(apic, ppr) != -1)
 707                 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 708 }
 709
 710 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
 711 {
 712         apic_update_ppr(vcpu->arch.apic);
 713 }
 714 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
 715
 716 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 717 {
 718         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 719         apic_update_ppr(apic);
 720 }
 721
 722 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 723 {
 724         return mda == (apic_x2apic_mode(apic) ?
 725                         X2APIC_BROADCAST : APIC_BROADCAST);
 726 }
 727
 728 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 729 {
 730         if (kvm_apic_broadcast(apic, mda))
 731                 return true;
 732
 733         if (apic_x2apic_mode(apic))
 734                 return mda == kvm_x2apic_id(apic);
 735
 736         /*
 737          * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
 738          * it were in x2APIC mode.  Hotplugged VCPUs start in xAPIC mode and
 739          * this allows unique addressing of VCPUs with APIC ID over 0xff.
 740          * The 0xff condition is needed because writeable xAPIC ID.
 741          */
 742         if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
 743                 return true;
 744
 745         return mda == kvm_xapic_id(apic);
 746 }
 747
 748 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 749 {
 750         u32 logical_id;
 751
 752         if (kvm_apic_broadcast(apic, mda))
 753                 return true;
 754
 755         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 756
 757         if (apic_x2apic_mode(apic))
 758                 return ((logical_id >> 16) == (mda >> 16))
 759                        && (logical_id & mda & 0xffff) != 0;
 760
 761         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 762
 763         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 764         case APIC_DFR_FLAT:
 765                 return (logical_id & mda) != 0;
 766         case APIC_DFR_CLUSTER:
 767                 return ((logical_id >> 4) == (mda >> 4))
 768                        && (logical_id & mda & 0xf) != 0;
 769         default:
 770                 apic_debug("Bad DFR vcpu %d: %08x\n",
 771                            apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
 772                 return false;
 773         }
 774 }
 775
 776 /* The KVM local APIC implementation has two quirks:
 777  *
 778  *  - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
 779  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
 780  *    KVM doesn't do that aliasing.
 781  *
 782  *  - in-kernel IOAPIC messages have to be delivered directly to
 783  *    x2APIC, because the kernel does not support interrupt remapping.
 784  *    In order to support broadcast without interrupt remapping, x2APIC
 785  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 786  *    to X2APIC_BROADCAST.
 787  *
 788  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 789  * important when userspace wants to use x2APIC-format MSIs, because
 790  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 791  */
 792 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 793                 struct kvm_lapic *source, struct kvm_lapic *target)
 794 {
 795         bool ipi = source != NULL;
 796
 797         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 798             !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
 799                 return X2APIC_BROADCAST;
 800
 801         return dest_id;
 802 }
 803
 804 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 805                            int short_hand, unsigned int dest, int dest_mode)
 806 {
 807         struct kvm_lapic *target = vcpu->arch.apic;
 808         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 809
 810         apic_debug("target %p, source %p, dest 0x%x, "
 811                    "dest_mode 0x%x, short_hand 0x%x\n",
 812                    target, source, dest, dest_mode, short_hand);
 813
 814         ASSERT(target);
 815         switch (short_hand) {
 816         case APIC_DEST_NOSHORT:
 817                 if (dest_mode == APIC_DEST_PHYSICAL)
 818                         return kvm_apic_match_physical_addr(target, mda);
 819                 else
 820                         return kvm_apic_match_logical_addr(target, mda);
 821         case APIC_DEST_SELF:
 822                 return target == source;
 823         case APIC_DEST_ALLINC:
 824                 return true;
 825         case APIC_DEST_ALLBUT:
 826                 return target != source;
 827         default:
 828                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 829                            short_hand);
 830                 return false;
 831         }
 832 }
 833 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 834
 835 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 836                        const unsigned long *bitmap, u32 bitmap_size)
 837 {
 838         u32 mod;
 839         int i, idx = -1;
 840
 841         mod = vector % dest_vcpus;
 842
 843         for (i = 0; i <= mod; i++) {
 844                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 845                 BUG_ON(idx == bitmap_size);
 846         }
 847
 848         return idx;
 849 }
 850
 851 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 852 {
 853         if (!kvm->arch.disabled_lapic_found) {
 854                 kvm->arch.disabled_lapic_found = true;
 855                 printk(KERN_INFO
 856                        "Disabled LAPIC found during irq injection\n");
 857         }
 858 }
 859
 860 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 861                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 862 {
 863         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 864                 if ((irq->dest_id == APIC_BROADCAST &&
 865                                 map->mode != KVM_APIC_MODE_X2APIC))
 866                         return true;
 867                 if (irq->dest_id == X2APIC_BROADCAST)
 868                         return true;
 869         } else {
 870                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 871                 if (irq->dest_id == (x2apic_ipi ?
 872                                      X2APIC_BROADCAST : APIC_BROADCAST))
 873                         return true;
 874         }
 875
 876         return false;
 877 }
 878
 879 /* Return true if the interrupt can be handled by using *bitmap as index mask
 880  * for valid destinations in *dst array.
 881  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 882  * Note: we may have zero kvm_lapic destinations when we return true, which
 883  * means that the interrupt should be dropped.  In this case, *bitmap would be
 884  * zero and *dst undefined.
 885  */
 886 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 887                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 888                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 889                 unsigned long *bitmap)
 890 {
 891         int i, lowest;
 892
 893         if (irq->shorthand == APIC_DEST_SELF && src) {
 894                 *dst = src;
 895                 *bitmap = 1;
 896                 return true;
 897         } else if (irq->shorthand)
 898                 return false;
 899
 900         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 901                 return false;
 902
 903         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 904                 if (irq->dest_id > map->max_apic_id) {
 905                         *bitmap = 0;
 906                 } else {
 907                         u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
 908                         *dst = &map->phys_map[dest_id];
 909                         *bitmap = 1;
 910                 }
 911                 return true;
 912         }
 913
 914         *bitmap = 0;
 915         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 916                                 (u16 *)bitmap))
 917                 return false;
 918
 919         if (!kvm_lowest_prio_delivery(irq))
 920                 return true;
 921
 922         if (!kvm_vector_hashing_enabled()) {
 923                 lowest = -1;
 924                 for_each_set_bit(i, bitmap, 16) {
 925                         if (!(*dst)[i])
 926                                 continue;
 927                         if (lowest < 0)
 928                                 lowest = i;
 929                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 930                                                 (*dst)[lowest]->vcpu) < 0)
 931                                 lowest = i;
 932                 }
 933         } else {
 934                 if (!*bitmap)
 935                         return true;
 936
 937                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 938                                 bitmap, 16);
 939
 940                 if (!(*dst)[lowest]) {
 941                         kvm_apic_disabled_lapic_found(kvm);
 942                         *bitmap = 0;
 943                         return true;
 944                 }
 945         }
 946
 947         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 948
 949         return true;
 950 }
 951
 952 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 953                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 954 {
 955         struct kvm_apic_map *map;
 956         unsigned long bitmap;
 957         struct kvm_lapic **dst = NULL;
 958         int i;
 959         bool ret;
 960
 961         *r = -1;
 962
 963         if (irq->shorthand == APIC_DEST_SELF) {
 964                 if (KVM_BUG_ON(!src, kvm)) {
 965                         *r = 0;
 966                         return true;
 967                 }
 968                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 969                 return true;
 970         }
 971
 972         rcu_read_lock();
 973         map = rcu_dereference(kvm->arch.apic_map);
 974
 975         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 976         if (ret)
 977                 for_each_set_bit(i, &bitmap, 16) {
 978                         if (!dst[i])
 979                                 continue;
 980                         if (*r < 0)
 981                                 *r = 0;
 982                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 983                 }
 984
 985         rcu_read_unlock();
 986         return ret;
 987 }
 988
 989 /*
 990  * This routine tries to handler interrupts in posted mode, here is how
 991  * it deals with different cases:
 992  * - For single-destination interrupts, handle it in posted mode
 993  * - Else if vector hashing is enabled and it is a lowest-priority
 994  *   interrupt, handle it in posted mode and use the following mechanism
 995  *   to find the destinaiton vCPU.
 996  *      1. For lowest-priority interrupts, store all the possible
 997  *         destination vCPUs in an array.
 998  *      2. Use "guest vector % max number of destination vCPUs" to find
 999  *         the right destination vCPU in the array for the lowest-priority
1000  *         interrupt.
1001  * - Otherwise, use remapped mode to inject the interrupt.
1002  */
1003 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
1004                         struct kvm_vcpu **dest_vcpu)
1005 {
1006         struct kvm_apic_map *map;
1007         unsigned long bitmap;
1008         struct kvm_lapic **dst = NULL;
1009         bool ret = false;
1010
1011         if (irq->shorthand)
1012                 return false;
1013
1014         rcu_read_lock();
1015         map = rcu_dereference(kvm->arch.apic_map);
1016
1017         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1018                         hweight16(bitmap) == 1) {
1019                 unsigned long i = find_first_bit(&bitmap, 16);
1020
1021                 if (dst[i]) {
1022                         *dest_vcpu = dst[i]->vcpu;
1023                         ret = true;
1024                 }
1025         }
1026
1027         rcu_read_unlock();
1028         return ret;
1029 }
1030
1031 /*
1032  * Add a pending IRQ into lapic.
1033  * Return 1 if successfully added and 0 if discarded.
1034  */
1035 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1036                              int vector, int level, int trig_mode,
1037                              struct dest_map *dest_map)
1038 {
1039         int result = 0;
1040         struct kvm_vcpu *vcpu = apic->vcpu;
1041
1042         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1043                                   trig_mode, vector);
1044         switch (delivery_mode) {
1045         case APIC_DM_LOWEST:
1046                 vcpu->arch.apic_arb_prio++;
1047         case APIC_DM_FIXED:
1048                 if (unlikely(trig_mode && !level))
1049                         break;
1050
1051                 /* FIXME add logic for vcpu on reset */
1052                 if (unlikely(!apic_enabled(apic)))
1053                         break;
1054
1055                 result = 1;
1056
1057                 if (dest_map) {
1058                         __set_bit(vcpu->vcpu_id, dest_map->map);
1059                         dest_map->vectors[vcpu->vcpu_id] = vector;
1060                 }
1061
1062                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1063                         if (trig_mode)
1064                                 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
1065                         else
1066                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
1067                 }
1068
1069                 if (kvm_x86_ops->deliver_posted_interrupt(vcpu, vector)) {
1070                         kvm_lapic_set_irr(vector, apic);
1071                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1072                         kvm_vcpu_kick(vcpu);
1073                 }
1074                 break;
1075
1076         case APIC_DM_REMRD:
1077                 result = 1;
1078                 vcpu->arch.pv.pv_unhalted = 1;
1079                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1080                 kvm_vcpu_kick(vcpu);
1081                 break;
1082
1083         case APIC_DM_SMI:
1084                 result = 1;
1085                 kvm_make_request(KVM_REQ_SMI, vcpu);
1086                 kvm_vcpu_kick(vcpu);
1087                 break;
1088
1089         case APIC_DM_NMI:
1090                 result = 1;
1091                 kvm_inject_nmi(vcpu);
1092                 kvm_vcpu_kick(vcpu);
1093                 break;
1094
1095         case APIC_DM_INIT:
1096                 if (!trig_mode || level) {
1097                         result = 1;
1098                         /* assumes that there are only KVM_APIC_INIT/SIPI */
1099                         apic->pending_events = (1UL << KVM_APIC_INIT);
1100                         /* make sure pending_events is visible before sending
1101                          * the request */
1102                         smp_wmb();
1103                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1104                         kvm_vcpu_kick(vcpu);
1105                 } else {
1106                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1107                                    vcpu->vcpu_id);
1108                 }
1109                 break;
1110
1111         case APIC_DM_STARTUP:
1112                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1113                            vcpu->vcpu_id, vector);
1114                 result = 1;
1115                 apic->sipi_vector = vector;
1116                 /* make sure sipi_vector is visible for the receiver */
1117                 smp_wmb();
1118                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1119                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1120                 kvm_vcpu_kick(vcpu);
1121                 break;
1122
1123         case APIC_DM_EXTINT:
1124                 /*
1125                  * Should only be called by kvm_apic_local_deliver() with LVT0,
1126                  * before NMI watchdog was enabled. Already handled by
1127                  * kvm_apic_accept_pic_intr().
1128                  */
1129                 break;
1130
1131         default:
1132                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1133                        delivery_mode);
1134                 break;
1135         }
1136         return result;
1137 }
1138
1139 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1140 {
1141         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1142 }
1143
1144 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1145 {
1146         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1147 }
1148
1149 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1150 {
1151         int trigger_mode;
1152
1153         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1154         if (!kvm_ioapic_handles_vector(apic, vector))
1155                 return;
1156
1157         /* Request a KVM exit to inform the userspace IOAPIC. */
1158         if (irqchip_split(apic->vcpu->kvm)) {
1159                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1160                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1161                 return;
1162         }
1163
1164         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1165                 trigger_mode = IOAPIC_LEVEL_TRIG;
1166         else
1167                 trigger_mode = IOAPIC_EDGE_TRIG;
1168
1169         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1170 }
1171
1172 static int apic_set_eoi(struct kvm_lapic *apic)
1173 {
1174         int vector = apic_find_highest_isr(apic);
1175
1176         trace_kvm_eoi(apic, vector);
1177
1178         /*
1179          * Not every write EOI will has corresponding ISR,
1180          * one example is when Kernel check timer on setup_IO_APIC
1181          */
1182         if (vector == -1)
1183                 return vector;
1184
1185         apic_clear_isr(vector, apic);
1186         apic_update_ppr(apic);
1187
1188         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1189                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1190
1191         kvm_ioapic_send_eoi(apic, vector);
1192         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1193         return vector;
1194 }
1195
1196 /*
1197  * this interface assumes a trap-like exit, which has already finished
1198  * desired side effect including vISR and vPPR update.
1199  */
1200 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1201 {
1202         struct kvm_lapic *apic = vcpu->arch.apic;
1203
1204         trace_kvm_eoi(apic, vector);
1205
1206         kvm_ioapic_send_eoi(apic, vector);
1207         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1208 }
1209 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1210
1211 static void apic_send_ipi(struct kvm_lapic *apic)
1212 {
1213         u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1214         u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1215         struct kvm_lapic_irq irq;
1216
1217         irq.vector = icr_low & APIC_VECTOR_MASK;
1218         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1219         irq.dest_mode = icr_low & APIC_DEST_MASK;
1220         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1221         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1222         irq.shorthand = icr_low & APIC_SHORT_MASK;
1223         irq.msi_redir_hint = false;
1224         if (apic_x2apic_mode(apic))
1225                 irq.dest_id = icr_high;
1226         else
1227                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1228
1229         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1230
1231         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1232                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1233                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1234                    "msi_redir_hint 0x%x\n",
1235                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1236                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1237                    irq.vector, irq.msi_redir_hint);
1238
1239         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1240 }
1241
1242 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1243 {
1244         ktime_t remaining, now;
1245         s64 ns;
1246         u32 tmcct;
1247
1248         ASSERT(apic != NULL);
1249
1250         /* if initial count is 0, current count should also be 0 */
1251         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1252                 apic->lapic_timer.period == 0)
1253                 return 0;
1254
1255         now = ktime_get();
1256         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1257         if (ktime_to_ns(remaining) < 0)
1258                 remaining = 0;
1259
1260         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1261         tmcct = div64_u64(ns,
1262                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1263
1264         return tmcct;
1265 }
1266
1267 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1268 {
1269         struct kvm_vcpu *vcpu = apic->vcpu;
1270         struct kvm_run *run = vcpu->run;
1271
1272         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1273         run->tpr_access.rip = kvm_rip_read(vcpu);
1274         run->tpr_access.is_write = write;
1275 }
1276
1277 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1278 {
1279         if (apic->vcpu->arch.tpr_access_reporting)
1280                 __report_tpr_access(apic, write);
1281 }
1282
1283 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1284 {
1285         u32 val = 0;
1286
1287         if (offset >= LAPIC_MMIO_LENGTH)
1288                 return 0;
1289
1290         switch (offset) {
1291         case APIC_ARBPRI:
1292                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1293                 break;
1294
1295         case APIC_TMCCT:        /* Timer CCR */
1296                 if (apic_lvtt_tscdeadline(apic))
1297                         return 0;
1298
1299                 val = apic_get_tmcct(apic);
1300                 break;
1301         case APIC_PROCPRI:
1302                 apic_update_ppr(apic);
1303                 val = kvm_lapic_get_reg(apic, offset);
1304                 break;
1305         case APIC_TASKPRI:
1306                 report_tpr_access(apic, false);
1307                 /* fall thru */
1308         default:
1309                 val = kvm_lapic_get_reg(apic, offset);
1310                 break;
1311         }
1312
1313         return val;
1314 }
1315
1316 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1317 {
1318         return container_of(dev, struct kvm_lapic, dev);
1319 }
1320
1321 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1322                 void *data)
1323 {
1324         unsigned char alignment = offset & 0xf;
1325         u32 result;
1326         /* this bitmask has a bit cleared for each reserved register */
1327         static const u64 rmask = 0x43ff01ffffffe70cULL;
1328
1329         if ((alignment + len) > 4) {
1330                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1331                            offset, len);
1332                 return 1;
1333         }
1334
1335         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1336                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1337                            offset);
1338                 return 1;
1339         }
1340
1341         result = __apic_read(apic, offset & ~0xf);
1342
1343         trace_kvm_apic_read(offset, result);
1344
1345         switch (len) {
1346         case 1:
1347         case 2:
1348         case 4:
1349                 memcpy(data, (char *)&result + alignment, len);
1350                 break;
1351         default:
1352                 printk(KERN_ERR "Local APIC read with len = %x, "
1353                        "should be 1,2, or 4 instead\n", len);
1354                 break;
1355         }
1356         return 0;
1357 }
1358 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1359
1360 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1361 {
1362         return addr >= apic->base_address &&
1363                 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1364 }
1365
1366 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1367                            gpa_t address, int len, void *data)
1368 {
1369         struct kvm_lapic *apic = to_lapic(this);
1370         u32 offset = address - apic->base_address;
1371
1372         if (!apic_mmio_in_range(apic, address))
1373                 return -EOPNOTSUPP;
1374
1375         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1376                 if (!kvm_check_has_quirk(vcpu->kvm,
1377                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1378                         return -EOPNOTSUPP;
1379
1380                 memset(data, 0xff, len);
1381                 return 0;
1382         }
1383
1384         kvm_lapic_reg_read(apic, offset, len, data);
1385
1386         return 0;
1387 }
1388
1389 static void update_divide_count(struct kvm_lapic *apic)
1390 {
1391         u32 tmp1, tmp2, tdcr;
1392
1393         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1394         tmp1 = tdcr & 0xf;
1395         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1396         apic->divide_count = 0x1 << (tmp2 & 0x7);
1397
1398         apic_debug("timer divide count is 0x%x\n",
1399                                    apic->divide_count);
1400 }
1401
1402 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1403 {
1404         /*
1405          * Do not allow the guest to program periodic timers with small
1406          * interval, since the hrtimers are not throttled by the host
1407          * scheduler.
1408          */
1409         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1410                 s64 min_period = min_timer_period_us * 1000LL;
1411
1412                 if (apic->lapic_timer.period < min_period) {
1413                         pr_info_ratelimited(
1414                             "kvm: vcpu %i: requested %lld ns "
1415                             "lapic timer period limited to %lld ns\n",
1416                             apic->vcpu->vcpu_id,
1417                             apic->lapic_timer.period, min_period);
1418                         apic->lapic_timer.period = min_period;
1419                 }
1420         }
1421 }
1422
1423 static void apic_update_lvtt(struct kvm_lapic *apic)
1424 {
1425         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1426                         apic->lapic_timer.timer_mode_mask;
1427
1428         if (apic->lapic_timer.timer_mode != timer_mode) {
1429                 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1430                                 APIC_LVT_TIMER_TSCDEADLINE)) {
1431                         hrtimer_cancel(&apic->lapic_timer.timer);
1432                         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1433                         apic->lapic_timer.period = 0;
1434                         apic->lapic_timer.tscdeadline = 0;
1435                 }
1436                 apic->lapic_timer.timer_mode = timer_mode;
1437                 limit_periodic_timer_frequency(apic);
1438         }
1439 }
1440
1441 static void apic_timer_expired(struct kvm_lapic *apic)
1442 {
1443         struct kvm_vcpu *vcpu = apic->vcpu;
1444         struct swait_queue_head *q = &vcpu->wq;
1445         struct kvm_timer *ktimer = &apic->lapic_timer;
1446
1447         if (atomic_read(&apic->lapic_timer.pending))
1448                 return;
1449
1450         atomic_inc(&apic->lapic_timer.pending);
1451         kvm_set_pending_timer(vcpu);
1452
1453         /*
1454          * For x86, the atomic_inc() is serialized, thus
1455          * using swait_active() is safe.
1456          */
1457         if (swait_active(q))
1458                 swake_up_one(q);
1459
1460         if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1461                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1462 }
1463
1464 /*
1465  * On APICv, this test will cause a busy wait
1466  * during a higher-priority task.
1467  */
1468
1469 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1470 {
1471         struct kvm_lapic *apic = vcpu->arch.apic;
1472         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1473
1474         if (kvm_apic_hw_enabled(apic)) {
1475                 int vec = reg & APIC_VECTOR_MASK;
1476                 void *bitmap = apic->regs + APIC_ISR;
1477
1478                 if (vcpu->arch.apicv_active)
1479                         bitmap = apic->regs + APIC_IRR;
1480
1481                 if (apic_test_vector(vec, bitmap))
1482                         return true;
1483         }
1484         return false;
1485 }
1486
1487 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1488 {
1489         struct kvm_lapic *apic = vcpu->arch.apic;
1490         u64 guest_tsc, tsc_deadline;
1491
1492         if (!lapic_in_kernel(vcpu))
1493                 return;
1494
1495         if (apic->lapic_timer.expired_tscdeadline == 0)
1496                 return;
1497
1498         if (!lapic_timer_int_injected(vcpu))
1499                 return;
1500
1501         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1502         apic->lapic_timer.expired_tscdeadline = 0;
1503         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1504         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1505
1506         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1507         if (guest_tsc < tsc_deadline)
1508                 __delay(min(tsc_deadline - guest_tsc,
1509                         nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1510 }
1511
1512 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1513 {
1514         u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1515         u64 ns = 0;
1516         ktime_t expire;
1517         struct kvm_vcpu *vcpu = apic->vcpu;
1518         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1519         unsigned long flags;
1520         ktime_t now;
1521
1522         if (unlikely(!tscdeadline || !this_tsc_khz))
1523                 return;
1524
1525         local_irq_save(flags);
1526
1527         now = ktime_get();
1528         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1529         if (likely(tscdeadline > guest_tsc)) {
1530                 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1531                 do_div(ns, this_tsc_khz);
1532                 expire = ktime_add_ns(now, ns);
1533                 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1534                 hrtimer_start(&apic->lapic_timer.timer,
1535                                 expire, HRTIMER_MODE_ABS_PINNED);
1536         } else
1537                 apic_timer_expired(apic);
1538
1539         local_irq_restore(flags);
1540 }
1541
1542 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1543 {
1544         ktime_t now, remaining;
1545         u64 ns_remaining_old, ns_remaining_new;
1546
1547         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1548                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1549         limit_periodic_timer_frequency(apic);
1550
1551         now = ktime_get();
1552         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1553         if (ktime_to_ns(remaining) < 0)
1554                 remaining = 0;
1555
1556         ns_remaining_old = ktime_to_ns(remaining);
1557         ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1558                                            apic->divide_count, old_divisor);
1559
1560         apic->lapic_timer.tscdeadline +=
1561                 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1562                 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1563         apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1564 }
1565
1566 static bool set_target_expiration(struct kvm_lapic *apic)
1567 {
1568         ktime_t now;
1569         u64 tscl = rdtsc();
1570
1571         now = ktime_get();
1572         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1573                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1574
1575         if (!apic->lapic_timer.period) {
1576                 apic->lapic_timer.tscdeadline = 0;
1577                 return false;
1578         }
1579
1580         limit_periodic_timer_frequency(apic);
1581
1582         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1583                    PRIx64 ", "
1584                    "timer initial count 0x%x, period %lldns, "
1585                    "expire @ 0x%016" PRIx64 ".\n", __func__,
1586                    APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1587                    kvm_lapic_get_reg(apic, APIC_TMICT),
1588                    apic->lapic_timer.period,
1589                    ktime_to_ns(ktime_add_ns(now,
1590                                 apic->lapic_timer.period)));
1591
1592         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1593                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1594         apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1595
1596         return true;
1597 }
1598
1599 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1600 {
1601         ktime_t now = ktime_get();
1602         u64 tscl = rdtsc();
1603         ktime_t delta;
1604
1605         /*
1606          * Synchronize both deadlines to the same time source or
1607          * differences in the periods (caused by differences in the
1608          * underlying clocks or numerical approximation errors) will
1609          * cause the two to drift apart over time as the errors
1610          * accumulate.
1611          */
1612         apic->lapic_timer.target_expiration =
1613                 ktime_add_ns(apic->lapic_timer.target_expiration,
1614                                 apic->lapic_timer.period);
1615         delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1616         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1617                 nsec_to_cycles(apic->vcpu, delta);
1618 }
1619
1620 static void start_sw_period(struct kvm_lapic *apic)
1621 {
1622         if (!apic->lapic_timer.period)
1623                 return;
1624
1625         if (ktime_after(ktime_get(),
1626                         apic->lapic_timer.target_expiration)) {
1627                 apic_timer_expired(apic);
1628
1629                 if (apic_lvtt_oneshot(apic))
1630                         return;
1631
1632                 advance_periodic_target_expiration(apic);
1633         }
1634
1635         hrtimer_start(&apic->lapic_timer.timer,
1636                 apic->lapic_timer.target_expiration,
1637                 HRTIMER_MODE_ABS_PINNED);
1638 }
1639
1640 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1641 {
1642         if (!lapic_in_kernel(vcpu))
1643                 return false;
1644
1645         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1646 }
1647 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1648
1649 static void cancel_hv_timer(struct kvm_lapic *apic)
1650 {
1651         WARN_ON(preemptible());
1652         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1653         kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1654         apic->lapic_timer.hv_timer_in_use = false;
1655 }
1656
1657 static bool start_hv_timer(struct kvm_lapic *apic)
1658 {
1659         struct kvm_timer *ktimer = &apic->lapic_timer;
1660         int r;
1661
1662         WARN_ON(preemptible());
1663         if (!kvm_x86_ops->set_hv_timer)
1664                 return false;
1665
1666         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1667                 return false;
1668
1669         if (!ktimer->tscdeadline)
1670                 return false;
1671
1672         r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline);
1673         if (r < 0)
1674                 return false;
1675
1676         ktimer->hv_timer_in_use = true;
1677         hrtimer_cancel(&ktimer->timer);
1678
1679         /*
1680          * Also recheck ktimer->pending, in case the sw timer triggered in
1681          * the window.  For periodic timer, leave the hv timer running for
1682          * simplicity, and the deadline will be recomputed on the next vmexit.
1683          */
1684         if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) {
1685                 if (r)
1686                         apic_timer_expired(apic);
1687                 return false;
1688         }
1689
1690         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true);
1691         return true;
1692 }
1693
1694 static void start_sw_timer(struct kvm_lapic *apic)
1695 {
1696         struct kvm_timer *ktimer = &apic->lapic_timer;
1697
1698         WARN_ON(preemptible());
1699         if (apic->lapic_timer.hv_timer_in_use)
1700                 cancel_hv_timer(apic);
1701         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1702                 return;
1703
1704         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1705                 start_sw_period(apic);
1706         else if (apic_lvtt_tscdeadline(apic))
1707                 start_sw_tscdeadline(apic);
1708         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1709 }
1710
1711 static void restart_apic_timer(struct kvm_lapic *apic)
1712 {
1713         preempt_disable();
1714         if (!start_hv_timer(apic))
1715                 start_sw_timer(apic);
1716         preempt_enable();
1717 }
1718
1719 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1720 {
1721         struct kvm_lapic *apic = vcpu->arch.apic;
1722
1723         preempt_disable();
1724         /* If the preempt notifier has already run, it also called apic_timer_expired */
1725         if (!apic->lapic_timer.hv_timer_in_use)
1726                 goto out;
1727         WARN_ON(swait_active(&vcpu->wq));
1728         cancel_hv_timer(apic);
1729         apic_timer_expired(apic);
1730
1731         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1732                 advance_periodic_target_expiration(apic);
1733                 restart_apic_timer(apic);
1734         }
1735 out:
1736         preempt_enable();
1737 }
1738 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1739
1740 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1741 {
1742         restart_apic_timer(vcpu->arch.apic);
1743 }
1744 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1745
1746 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1747 {
1748         struct kvm_lapic *apic = vcpu->arch.apic;
1749
1750         preempt_disable();
1751         /* Possibly the TSC deadline timer is not enabled yet */
1752         if (apic->lapic_timer.hv_timer_in_use)
1753                 start_sw_timer(apic);
1754         preempt_enable();
1755 }
1756 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1757
1758 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1759 {
1760         struct kvm_lapic *apic = vcpu->arch.apic;
1761
1762         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1763         restart_apic_timer(apic);
1764 }
1765
1766 static void start_apic_timer(struct kvm_lapic *apic)
1767 {
1768         atomic_set(&apic->lapic_timer.pending, 0);
1769
1770         if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1771             && !set_target_expiration(apic))
1772                 return;
1773
1774         restart_apic_timer(apic);
1775 }
1776
1777 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1778 {
1779         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1780
1781         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1782                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1783                 if (lvt0_in_nmi_mode) {
1784                         apic_debug("Receive NMI setting on APIC_LVT0 "
1785                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1786                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1787                 } else
1788                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1789         }
1790 }
1791
1792 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1793 {
1794         int ret = 0;
1795
1796         trace_kvm_apic_write(reg, val);
1797
1798         switch (reg) {
1799         case APIC_ID:           /* Local APIC ID */
1800                 if (!apic_x2apic_mode(apic))
1801                         kvm_apic_set_xapic_id(apic, val >> 24);
1802                 else
1803                         ret = 1;
1804                 break;
1805
1806         case APIC_TASKPRI:
1807                 report_tpr_access(apic, true);
1808                 apic_set_tpr(apic, val & 0xff);
1809                 break;
1810
1811         case APIC_EOI:
1812                 apic_set_eoi(apic);
1813                 break;
1814
1815         case APIC_LDR:
1816                 if (!apic_x2apic_mode(apic))
1817                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1818                 else
1819                         ret = 1;
1820                 break;
1821
1822         case APIC_DFR:
1823                 if (!apic_x2apic_mode(apic)) {
1824                         kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1825                         recalculate_apic_map(apic->vcpu->kvm);
1826                 } else
1827                         ret = 1;
1828                 break;
1829
1830         case APIC_SPIV: {
1831                 u32 mask = 0x3ff;
1832                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1833                         mask |= APIC_SPIV_DIRECTED_EOI;
1834                 apic_set_spiv(apic, val & mask);
1835                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1836                         int i;
1837                         u32 lvt_val;
1838
1839                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1840                                 lvt_val = kvm_lapic_get_reg(apic,
1841                                                        APIC_LVTT + 0x10 * i);
1842                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1843                                              lvt_val | APIC_LVT_MASKED);
1844                         }
1845                         apic_update_lvtt(apic);
1846                         atomic_set(&apic->lapic_timer.pending, 0);
1847
1848                 }
1849                 break;
1850         }
1851         case APIC_ICR:
1852                 /* No delay here, so we always clear the pending bit */
1853                 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1854                 apic_send_ipi(apic);
1855                 break;
1856
1857         case APIC_ICR2:
1858                 if (!apic_x2apic_mode(apic))
1859                         val &= 0xff000000;
1860                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1861                 break;
1862
1863         case APIC_LVT0:
1864                 apic_manage_nmi_watchdog(apic, val);
1865         case APIC_LVTTHMR:
1866         case APIC_LVTPC:
1867         case APIC_LVT1:
1868         case APIC_LVTERR: {
1869                 /* TODO: Check vector */
1870                 size_t size;
1871                 u32 index;
1872
1873                 if (!kvm_apic_sw_enabled(apic))
1874                         val |= APIC_LVT_MASKED;
1875                 size = ARRAY_SIZE(apic_lvt_mask);
1876                 index = array_index_nospec(
1877                                 (reg - APIC_LVTT) >> 4, size);
1878                 val &= apic_lvt_mask[index];
1879                 kvm_lapic_set_reg(apic, reg, val);
1880                 break;
1881         }
1882
1883         case APIC_LVTT:
1884                 if (!kvm_apic_sw_enabled(apic))
1885                         val |= APIC_LVT_MASKED;
1886                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1887                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1888                 apic_update_lvtt(apic);
1889                 break;
1890
1891         case APIC_TMICT:
1892                 if (apic_lvtt_tscdeadline(apic))
1893                         break;
1894
1895                 hrtimer_cancel(&apic->lapic_timer.timer);
1896                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1897                 start_apic_timer(apic);
1898                 break;
1899
1900         case APIC_TDCR: {
1901                 uint32_t old_divisor = apic->divide_count;
1902
1903                 if (val & 4)
1904                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1905                 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1906                 update_divide_count(apic);
1907                 if (apic->divide_count != old_divisor &&
1908                                 apic->lapic_timer.period) {
1909                         hrtimer_cancel(&apic->lapic_timer.timer);
1910                         update_target_expiration(apic, old_divisor);
1911                         restart_apic_timer(apic);
1912                 }
1913                 break;
1914         }
1915         case APIC_ESR:
1916                 if (apic_x2apic_mode(apic) && val != 0) {
1917                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1918                         ret = 1;
1919                 }
1920                 break;
1921
1922         case APIC_SELF_IPI:
1923                 if (apic_x2apic_mode(apic)) {
1924                         kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1925                 } else
1926                         ret = 1;
1927                 break;
1928         default:
1929                 ret = 1;
1930                 break;
1931         }
1932         if (ret)
1933                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1934         return ret;
1935 }
1936 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1937
1938 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1939                             gpa_t address, int len, const void *data)
1940 {
1941         struct kvm_lapic *apic = to_lapic(this);
1942         unsigned int offset = address - apic->base_address;
1943         u32 val;
1944
1945         if (!apic_mmio_in_range(apic, address))
1946                 return -EOPNOTSUPP;
1947
1948         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1949                 if (!kvm_check_has_quirk(vcpu->kvm,
1950                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1951                         return -EOPNOTSUPP;
1952
1953                 return 0;
1954         }
1955
1956         /*
1957          * APIC register must be aligned on 128-bits boundary.
1958          * 32/64/128 bits registers must be accessed thru 32 bits.
1959          * Refer SDM 8.4.1
1960          */
1961         if (len != 4 || (offset & 0xf)) {
1962                 /* Don't shout loud, $infamous_os would cause only noise. */
1963                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1964                 return 0;
1965         }
1966
1967         val = *(u32*)data;
1968
1969         /* too common printing */
1970         if (offset != APIC_EOI)
1971                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1972                            "0x%x\n", __func__, offset, len, val);
1973
1974         kvm_lapic_reg_write(apic, offset & 0xff0, val);
1975
1976         return 0;
1977 }
1978
1979 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1980 {
1981         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1982 }
1983 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1984
1985 /* emulate APIC access in a trap manner */
1986 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1987 {
1988         u32 val = 0;
1989
1990         /* hw has done the conditional check and inst decode */
1991         offset &= 0xff0;
1992
1993         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1994
1995         /* TODO: optimize to just emulate side effect w/o one more write */
1996         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1997 }
1998 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1999
2000 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2001 {
2002         struct kvm_lapic *apic = vcpu->arch.apic;
2003
2004         if (!vcpu->arch.apic)
2005                 return;
2006
2007         hrtimer_cancel(&apic->lapic_timer.timer);
2008
2009         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2010                 static_key_slow_dec_deferred(&apic_hw_disabled);
2011
2012         if (!apic->sw_enabled)
2013                 static_key_slow_dec_deferred(&apic_sw_disabled);
2014
2015         if (apic->regs)
2016                 free_page((unsigned long)apic->regs);
2017
2018         kfree(apic);
2019 }
2020
2021 /*
2022  *----------------------------------------------------------------------
2023  * LAPIC interface
2024  *----------------------------------------------------------------------
2025  */
2026 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2027 {
2028         struct kvm_lapic *apic = vcpu->arch.apic;
2029
2030         if (!lapic_in_kernel(vcpu) ||
2031                 !apic_lvtt_tscdeadline(apic))
2032                 return 0;
2033
2034         return apic->lapic_timer.tscdeadline;
2035 }
2036
2037 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2038 {
2039         struct kvm_lapic *apic = vcpu->arch.apic;
2040
2041         if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
2042                         apic_lvtt_period(apic))
2043                 return;
2044
2045         hrtimer_cancel(&apic->lapic_timer.timer);
2046         apic->lapic_timer.tscdeadline = data;
2047         start_apic_timer(apic);
2048 }
2049
2050 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2051 {
2052         apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4);
2053 }
2054
2055 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2056 {
2057         u64 tpr;
2058
2059         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2060
2061         return (tpr & 0xf0) >> 4;
2062 }
2063
2064 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2065 {
2066         u64 old_value = vcpu->arch.apic_base;
2067         struct kvm_lapic *apic = vcpu->arch.apic;
2068
2069         if (!apic)
2070                 value |= MSR_IA32_APICBASE_BSP;
2071
2072         vcpu->arch.apic_base = value;
2073
2074         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2075                 kvm_update_cpuid(vcpu);
2076
2077         if (!apic)
2078                 return;
2079
2080         /* update jump label if enable bit changes */
2081         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2082                 if (value & MSR_IA32_APICBASE_ENABLE) {
2083                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2084                         static_key_slow_dec_deferred(&apic_hw_disabled);
2085                 } else {
2086                         static_key_slow_inc(&apic_hw_disabled.key);
2087                         recalculate_apic_map(vcpu->kvm);
2088                 }
2089         }
2090
2091         if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2092                 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2093
2094         if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2095                 kvm_x86_ops->set_virtual_apic_mode(vcpu);
2096
2097         apic->base_address = apic->vcpu->arch.apic_base &
2098                              MSR_IA32_APICBASE_BASE;
2099
2100         if ((value & MSR_IA32_APICBASE_ENABLE) &&
2101              apic->base_address != APIC_DEFAULT_PHYS_BASE)
2102                 pr_warn_once("APIC base relocation is unsupported by KVM");
2103
2104         /* with FSB delivery interrupt, we can restart APIC functionality */
2105         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
2106                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
2107
2108 }
2109
2110 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2111 {
2112         struct kvm_lapic *apic = vcpu->arch.apic;
2113         int i;
2114
2115         if (!apic)
2116                 return;
2117
2118         apic_debug("%s\n", __func__);
2119
2120         /* Stop the timer in case it's a reset to an active apic */
2121         hrtimer_cancel(&apic->lapic_timer.timer);
2122
2123         if (!init_event) {
2124                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2125                                          MSR_IA32_APICBASE_ENABLE);
2126                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2127         }
2128         kvm_apic_set_version(apic->vcpu);
2129
2130         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2131                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2132         apic_update_lvtt(apic);
2133         if (kvm_vcpu_is_reset_bsp(vcpu) &&
2134             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2135                 kvm_lapic_set_reg(apic, APIC_LVT0,
2136                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2137         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2138
2139         kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2140         apic_set_spiv(apic, 0xff);
2141         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2142         if (!apic_x2apic_mode(apic))
2143                 kvm_apic_set_ldr(apic, 0);
2144         kvm_lapic_set_reg(apic, APIC_ESR, 0);
2145         kvm_lapic_set_reg(apic, APIC_ICR, 0);
2146         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2147         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2148         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2149         for (i = 0; i < 8; i++) {
2150                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2151                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2152                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2153         }
2154         apic->irr_pending = vcpu->arch.apicv_active;
2155         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2156         apic->highest_isr_cache = -1;
2157         update_divide_count(apic);
2158         atomic_set(&apic->lapic_timer.pending, 0);
2159         if (kvm_vcpu_is_bsp(vcpu))
2160                 kvm_lapic_set_base(vcpu,
2161                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2162         vcpu->arch.pv_eoi.msr_val = 0;
2163         apic_update_ppr(apic);
2164         if (vcpu->arch.apicv_active) {
2165                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2166                 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2167                 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2168         }
2169
2170         vcpu->arch.apic_arb_prio = 0;
2171         vcpu->arch.apic_attention = 0;
2172
2173         apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
2174                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
2175                    vcpu, kvm_lapic_get_reg(apic, APIC_ID),
2176                    vcpu->arch.apic_base, apic->base_address);
2177 }
2178
2179 /*
2180  *----------------------------------------------------------------------
2181  * timer interface
2182  *----------------------------------------------------------------------
2183  */
2184
2185 static bool lapic_is_periodic(struct kvm_lapic *apic)
2186 {
2187         return apic_lvtt_period(apic);
2188 }
2189
2190 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2191 {
2192         struct kvm_lapic *apic = vcpu->arch.apic;
2193
2194         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2195                 return atomic_read(&apic->lapic_timer.pending);
2196
2197         return 0;
2198 }
2199
2200 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2201 {
2202         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2203         int vector, mode, trig_mode;
2204
2205         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2206                 vector = reg & APIC_VECTOR_MASK;
2207                 mode = reg & APIC_MODE_MASK;
2208                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2209                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2210                                         NULL);
2211         }
2212         return 0;
2213 }
2214
2215 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2216 {
2217         struct kvm_lapic *apic = vcpu->arch.apic;
2218
2219         if (apic)
2220                 kvm_apic_local_deliver(apic, APIC_LVT0);
2221 }
2222
2223 static const struct kvm_io_device_ops apic_mmio_ops = {
2224         .read     = apic_mmio_read,
2225         .write    = apic_mmio_write,
2226 };
2227
2228 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2229 {
2230         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2231         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2232
2233         apic_timer_expired(apic);
2234
2235         if (lapic_is_periodic(apic)) {
2236                 advance_periodic_target_expiration(apic);
2237                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2238                 return HRTIMER_RESTART;
2239         } else
2240                 return HRTIMER_NORESTART;
2241 }
2242
2243 int kvm_create_lapic(struct kvm_vcpu *vcpu)
2244 {
2245         struct kvm_lapic *apic;
2246
2247         ASSERT(vcpu != NULL);
2248         apic_debug("apic_init %d\n", vcpu->vcpu_id);
2249
2250         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2251         if (!apic)
2252                 goto nomem;
2253
2254         vcpu->arch.apic = apic;
2255
2256         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2257         if (!apic->regs) {
2258                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2259                        vcpu->vcpu_id);
2260                 goto nomem_free_apic;
2261         }
2262         apic->vcpu = vcpu;
2263
2264         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2265                      HRTIMER_MODE_ABS_PINNED);
2266         apic->lapic_timer.timer.function = apic_timer_fn;
2267
2268         /*
2269          * APIC is created enabled. This will prevent kvm_lapic_set_base from
2270          * thinking that APIC satet has changed.
2271          */
2272         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2273         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2274         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2275
2276         return 0;
2277 nomem_free_apic:
2278         kfree(apic);
2279 nomem:
2280         return -ENOMEM;
2281 }
2282
2283 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2284 {
2285         struct kvm_lapic *apic = vcpu->arch.apic;
2286         u32 ppr;
2287
2288         if (!kvm_apic_present(vcpu))
2289                 return -1;
2290
2291         __apic_update_ppr(apic, &ppr);
2292         return apic_has_interrupt_for_ppr(apic, ppr);
2293 }
2294
2295 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2296 {
2297         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2298         int r = 0;
2299
2300         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2301                 r = 1;
2302         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2303             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2304                 r = 1;
2305         return r;
2306 }
2307
2308 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2309 {
2310         struct kvm_lapic *apic = vcpu->arch.apic;
2311
2312         if (atomic_read(&apic->lapic_timer.pending) > 0) {
2313                 kvm_apic_local_deliver(apic, APIC_LVTT);
2314                 if (apic_lvtt_tscdeadline(apic))
2315                         apic->lapic_timer.tscdeadline = 0;
2316                 if (apic_lvtt_oneshot(apic)) {
2317                         apic->lapic_timer.tscdeadline = 0;
2318                         apic->lapic_timer.target_expiration = 0;
2319                 }
2320                 atomic_set(&apic->lapic_timer.pending, 0);
2321         }
2322 }
2323
2324 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2325 {
2326         int vector = kvm_apic_has_interrupt(vcpu);
2327         struct kvm_lapic *apic = vcpu->arch.apic;
2328         u32 ppr;
2329
2330         if (vector == -1)
2331                 return -1;
2332
2333         /*
2334          * We get here even with APIC virtualization enabled, if doing
2335          * nested virtualization and L1 runs with the "acknowledge interrupt
2336          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2337          * because the process would deliver it through the IDT.
2338          */
2339
2340         apic_clear_irr(vector, apic);
2341         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2342                 /*
2343                  * For auto-EOI interrupts, there might be another pending
2344                  * interrupt above PPR, so check whether to raise another
2345                  * KVM_REQ_EVENT.
2346                  */
2347                 apic_update_ppr(apic);
2348         } else {
2349                 /*
2350                  * For normal interrupts, PPR has been raised and there cannot
2351                  * be a higher-priority pending interrupt---except if there was
2352                  * a concurrent interrupt injection, but that would have
2353                  * triggered KVM_REQ_EVENT already.
2354                  */
2355                 apic_set_isr(vector, apic);
2356                 __apic_update_ppr(apic, &ppr);
2357         }
2358
2359         return vector;
2360 }
2361
2362 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2363                 struct kvm_lapic_state *s, bool set)
2364 {
2365         if (apic_x2apic_mode(vcpu->arch.apic)) {
2366                 u32 *id = (u32 *)(s->regs + APIC_ID);
2367                 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2368
2369                 if (vcpu->kvm->arch.x2apic_format) {
2370                         if (*id != vcpu->vcpu_id)
2371                                 return -EINVAL;
2372                 } else {
2373                         if (set)
2374                                 *id >>= 24;
2375                         else
2376                                 *id <<= 24;
2377                 }
2378
2379                 /* In x2APIC mode, the LDR is fixed and based on the id */
2380                 if (set)
2381                         *ldr = kvm_apic_calc_x2apic_ldr(*id);
2382         }
2383
2384         return 0;
2385 }
2386
2387 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2388 {
2389         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2390         return kvm_apic_state_fixup(vcpu, s, false);
2391 }
2392
2393 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2394 {
2395         struct kvm_lapic *apic = vcpu->arch.apic;
2396         int r;
2397
2398
2399         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2400         /* set SPIV separately to get count of SW disabled APICs right */
2401         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2402
2403         r = kvm_apic_state_fixup(vcpu, s, true);
2404         if (r)
2405                 return r;
2406         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2407
2408         recalculate_apic_map(vcpu->kvm);
2409         kvm_apic_set_version(vcpu);
2410
2411         apic_update_ppr(apic);
2412         hrtimer_cancel(&apic->lapic_timer.timer);
2413         apic_update_lvtt(apic);
2414         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2415         update_divide_count(apic);
2416         start_apic_timer(apic);
2417         apic->irr_pending = true;
2418         apic->isr_count = vcpu->arch.apicv_active ?
2419                                 1 : count_vectors(apic->regs + APIC_ISR);
2420         apic->highest_isr_cache = -1;
2421         if (vcpu->arch.apicv_active) {
2422                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2423                 kvm_x86_ops->hwapic_irr_update(vcpu,
2424                                 apic_find_highest_irr(apic));
2425                 kvm_x86_ops->hwapic_isr_update(vcpu,
2426                                 apic_find_highest_isr(apic));
2427         }
2428         kvm_make_request(KVM_REQ_EVENT, vcpu);
2429         if (ioapic_in_kernel(vcpu->kvm))
2430                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2431
2432         vcpu->arch.apic_arb_prio = 0;
2433
2434         return 0;
2435 }
2436
2437 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2438 {
2439         struct hrtimer *timer;
2440
2441         if (!lapic_in_kernel(vcpu))
2442                 return;
2443
2444         timer = &vcpu->arch.apic->lapic_timer.timer;
2445         if (hrtimer_cancel(timer))
2446                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2447 }
2448
2449 /*
2450  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2451  *
2452  * Detect whether guest triggered PV EOI since the
2453  * last entry. If yes, set EOI on guests's behalf.
2454  * Clear PV EOI in guest memory in any case.
2455  */
2456 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2457                                         struct kvm_lapic *apic)
2458 {
2459         bool pending;
2460         int vector;
2461         /*
2462          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2463          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2464          *
2465          * KVM_APIC_PV_EOI_PENDING is unset:
2466          *      -> host disabled PV EOI.
2467          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2468          *      -> host enabled PV EOI, guest did not execute EOI yet.
2469          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2470          *      -> host enabled PV EOI, guest executed EOI.
2471          */
2472         BUG_ON(!pv_eoi_enabled(vcpu));
2473         pending = pv_eoi_get_pending(vcpu);
2474         /*
2475          * Clear pending bit in any case: it will be set again on vmentry.
2476          * While this might not be ideal from performance point of view,
2477          * this makes sure pv eoi is only enabled when we know it's safe.
2478          */
2479         pv_eoi_clr_pending(vcpu);
2480         if (pending)
2481                 return;
2482         vector = apic_set_eoi(apic);
2483         trace_kvm_pv_eoi(apic, vector);
2484 }
2485
2486 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2487 {
2488         u32 data;
2489
2490         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2491                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2492
2493         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2494                 return;
2495
2496         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2497                                   sizeof(u32)))
2498                 return;
2499
2500         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2501 }
2502
2503 /*
2504  * apic_sync_pv_eoi_to_guest - called before vmentry
2505  *
2506  * Detect whether it's safe to enable PV EOI and
2507  * if yes do so.
2508  */
2509 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2510                                         struct kvm_lapic *apic)
2511 {
2512         if (!pv_eoi_enabled(vcpu) ||
2513             /* IRR set or many bits in ISR: could be nested. */
2514             apic->irr_pending ||
2515             /* Cache not set: could be safe but we don't bother. */
2516             apic->highest_isr_cache == -1 ||
2517             /* Need EOI to update ioapic. */
2518             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2519                 /*
2520                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2521                  * so we need not do anything here.
2522                  */
2523                 return;
2524         }
2525
2526         pv_eoi_set_pending(apic->vcpu);
2527 }
2528
2529 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2530 {
2531         u32 data, tpr;
2532         int max_irr, max_isr;
2533         struct kvm_lapic *apic = vcpu->arch.apic;
2534
2535         apic_sync_pv_eoi_to_guest(vcpu, apic);
2536
2537         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2538                 return;
2539
2540         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2541         max_irr = apic_find_highest_irr(apic);
2542         if (max_irr < 0)
2543                 max_irr = 0;
2544         max_isr = apic_find_highest_isr(apic);
2545         if (max_isr < 0)
2546                 max_isr = 0;
2547         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2548
2549         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2550                                 sizeof(u32));
2551 }
2552
2553 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2554 {
2555         if (vapic_addr) {
2556                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2557                                         &vcpu->arch.apic->vapic_cache,
2558                                         vapic_addr, sizeof(u32)))
2559                         return -EINVAL;
2560                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2561         } else {
2562                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2563         }
2564
2565         vcpu->arch.apic->vapic_addr = vapic_addr;
2566         return 0;
2567 }
2568
2569 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2570 {
2571         struct kvm_lapic *apic = vcpu->arch.apic;
2572         u32 reg = (msr - APIC_BASE_MSR) << 4;
2573
2574         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2575                 return 1;
2576
2577         if (reg == APIC_ICR2)
2578                 return 1;
2579
2580         /* if this is ICR write vector before command */
2581         if (reg == APIC_ICR)
2582                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2583         return kvm_lapic_reg_write(apic, reg, (u32)data);
2584 }
2585
2586 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2587 {
2588         struct kvm_lapic *apic = vcpu->arch.apic;
2589         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2590
2591         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2592                 return 1;
2593
2594         if (reg == APIC_DFR || reg == APIC_ICR2) {
2595                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2596                            reg);
2597                 return 1;
2598         }
2599
2600         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2601                 return 1;
2602         if (reg == APIC_ICR)
2603                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2604
2605         *data = (((u64)high) << 32) | low;
2606
2607         return 0;
2608 }
2609
2610 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2611 {
2612         struct kvm_lapic *apic = vcpu->arch.apic;
2613
2614         if (!lapic_in_kernel(vcpu))
2615                 return 1;
2616
2617         /* if this is ICR write vector before command */
2618         if (reg == APIC_ICR)
2619                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2620         return kvm_lapic_reg_write(apic, reg, (u32)data);
2621 }
2622
2623 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2624 {
2625         struct kvm_lapic *apic = vcpu->arch.apic;
2626         u32 low, high = 0;
2627
2628         if (!lapic_in_kernel(vcpu))
2629                 return 1;
2630
2631         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2632                 return 1;
2633         if (reg == APIC_ICR)
2634                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2635
2636         *data = (((u64)high) << 32) | low;
2637
2638         return 0;
2639 }
2640
2641 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2642 {
2643         u64 addr = data & ~KVM_MSR_ENABLED;
2644         struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2645         unsigned long new_len;
2646
2647         if (!IS_ALIGNED(addr, 4))
2648                 return 1;
2649
2650         vcpu->arch.pv_eoi.msr_val = data;
2651         if (!pv_eoi_enabled(vcpu))
2652                 return 0;
2653
2654         if (addr == ghc->gpa && len <= ghc->len)
2655                 new_len = ghc->len;
2656         else
2657                 new_len = len;
2658
2659         return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2660 }
2661
2662 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2663 {
2664         struct kvm_lapic *apic = vcpu->arch.apic;
2665         u8 sipi_vector;
2666         unsigned long pe;
2667
2668         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2669                 return;
2670
2671         /*
2672          * INITs are latched while in SMM.  Because an SMM CPU cannot
2673          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2674          * and delay processing of INIT until the next RSM.
2675          */
2676         if (is_smm(vcpu)) {
2677                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2678                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2679                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2680                 return;
2681         }
2682
2683         pe = xchg(&apic->pending_events, 0);
2684         if (test_bit(KVM_APIC_INIT, &pe)) {
2685                 kvm_vcpu_reset(vcpu, true);
2686                 if (kvm_vcpu_is_bsp(apic->vcpu))
2687                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2688                 else
2689                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2690         }
2691         if (test_bit(KVM_APIC_SIPI, &pe) &&
2692             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2693                 /* evaluate pending_events before reading the vector */
2694                 smp_rmb();
2695                 sipi_vector = apic->sipi_vector;
2696                 apic_debug("vcpu %d received sipi with vector # %x\n",
2697                          vcpu->vcpu_id, sipi_vector);
2698                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2699                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2700         }
2701 }
2702
2703 void kvm_lapic_init(void)
2704 {
2705         /* do not patch jump label more than once per second */
2706         jump_label_rate_limit(&apic_hw_disabled, HZ);
2707         jump_label_rate_limit(&apic_sw_disabled, HZ);
2708 }
2709
2710 void kvm_lapic_exit(void)
2711 {
2712         static_key_deferred_flush(&apic_hw_disabled);
2713         static_key_deferred_flush(&apic_sw_disabled);
2714 }