2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40 #include <linux/psp-sev.h>
41 #include <linux/file.h>
42 #include <linux/pagemap.h>
43 #include <linux/swap.h>
46 #include <asm/perf_event.h>
47 #include <asm/tlbflush.h>
49 #include <asm/debugreg.h>
50 #include <asm/kvm_para.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/spec-ctrl.h>
53 #include <asm/cpu_device_id.h>
55 #include <asm/virtext.h>
58 #define __ex(x) __kvm_handle_fault_on_reboot(x)
60 MODULE_AUTHOR("Qumranet");
61 MODULE_LICENSE("GPL");
63 static const struct x86_cpu_id svm_cpu_id[] = {
64 X86_FEATURE_MATCH(X86_FEATURE_SVM),
67 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
69 #define IOPM_ALLOC_ORDER 2
70 #define MSRPM_ALLOC_ORDER 1
72 #define SEG_TYPE_LDT 2
73 #define SEG_TYPE_BUSY_TSS16 3
75 #define SVM_FEATURE_NPT (1 << 0)
76 #define SVM_FEATURE_LBRV (1 << 1)
77 #define SVM_FEATURE_SVML (1 << 2)
78 #define SVM_FEATURE_NRIP (1 << 3)
79 #define SVM_FEATURE_TSC_RATE (1 << 4)
80 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
81 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
82 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
83 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
85 #define SVM_AVIC_DOORBELL 0xc001011b
87 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
88 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
89 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
91 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
93 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
94 #define TSC_RATIO_MIN 0x0000000000000001ULL
95 #define TSC_RATIO_MAX 0x000000ffffffffffULL
97 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
100 * 0xff is broadcast, so the max index allowed for physical APIC ID
101 * table is 0xfe. APIC IDs above 0xff are reserved.
103 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
105 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
106 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
107 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
109 /* AVIC GATAG is encoded using VM and VCPU IDs */
110 #define AVIC_VCPU_ID_BITS 8
111 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
113 #define AVIC_VM_ID_BITS 24
114 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
115 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
117 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
118 (y & AVIC_VCPU_ID_MASK))
119 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
120 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
122 static bool erratum_383_found __read_mostly;
124 static const u32 host_save_user_msrs[] = {
126 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
129 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
133 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
135 struct kvm_sev_info {
136 bool active; /* SEV enabled guest */
137 unsigned int asid; /* ASID used for this guest */
138 unsigned int handle; /* SEV firmware handle */
139 int fd; /* SEV device fd */
140 unsigned long pages_locked; /* Number of pages locked */
141 struct list_head regions_list; /* List of registered regions */
147 /* Struct members for AVIC */
150 struct page *avic_logical_id_table_page;
151 struct page *avic_physical_id_table_page;
152 struct hlist_node hnode;
154 struct kvm_sev_info sev_info;
159 struct nested_state {
165 /* These are the merged vectors */
168 /* gpa pointers to the real vectors */
172 /* A VMEXIT is required but not yet emulated */
175 /* cache for intercepts of the guest */
178 u32 intercept_exceptions;
181 /* Nested Paging related state */
185 #define MSRPM_OFFSETS 16
186 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
189 * Set osvw_len to higher value when updated Revision Guides
190 * are published and we know what the new status bits are
192 static uint64_t osvw_len = 4, osvw_status;
195 struct kvm_vcpu vcpu;
197 unsigned long vmcb_pa;
198 struct svm_cpu_data *svm_data;
199 uint64_t asid_generation;
200 uint64_t sysenter_esp;
201 uint64_t sysenter_eip;
208 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
218 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
219 * translated into the appropriate L2_CFG bits on the host to
220 * perform speculative control.
228 struct nested_state nested;
231 u64 nmi_singlestep_guest_rflags;
233 unsigned int3_injected;
234 unsigned long int3_rip;
236 /* cached guest cpuid flags for faster access */
237 bool nrips_enabled : 1;
240 struct page *avic_backing_page;
241 u64 *avic_physical_id_cache;
242 bool avic_is_running;
245 * Per-vcpu list of struct amd_svm_iommu_ir:
246 * This is used mainly to store interrupt remapping information used
247 * when update the vcpu affinity. This avoids the need to scan for
248 * IRTE and try to match ga_tag in the IOMMU driver.
250 struct list_head ir_list;
251 spinlock_t ir_list_lock;
253 /* which host CPU was used for running this vcpu */
254 unsigned int last_cpu;
258 * This is a wrapper of struct amd_iommu_ir_data.
260 struct amd_svm_iommu_ir {
261 struct list_head node; /* Used by SVM for per-vcpu ir_list */
262 void *data; /* Storing pointer to struct amd_ir_data */
265 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
266 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
268 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
269 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
270 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
271 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
273 static DEFINE_PER_CPU(u64, current_tsc_ratio);
274 #define TSC_RATIO_DEFAULT 0x0100000000ULL
276 #define MSR_INVALID 0xffffffffU
278 static const struct svm_direct_access_msrs {
279 u32 index; /* Index of the MSR */
280 bool always; /* True if intercept is always on */
281 } direct_access_msrs[] = {
282 { .index = MSR_STAR, .always = true },
283 { .index = MSR_IA32_SYSENTER_CS, .always = true },
285 { .index = MSR_GS_BASE, .always = true },
286 { .index = MSR_FS_BASE, .always = true },
287 { .index = MSR_KERNEL_GS_BASE, .always = true },
288 { .index = MSR_LSTAR, .always = true },
289 { .index = MSR_CSTAR, .always = true },
290 { .index = MSR_SYSCALL_MASK, .always = true },
292 { .index = MSR_IA32_SPEC_CTRL, .always = false },
293 { .index = MSR_IA32_PRED_CMD, .always = false },
294 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
295 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
296 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
297 { .index = MSR_IA32_LASTINTTOIP, .always = false },
298 { .index = MSR_INVALID, .always = false },
301 /* enable NPT for AMD64 and X86 with PAE */
302 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
303 static bool npt_enabled = true;
305 static bool npt_enabled;
309 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
310 * pause_filter_count: On processors that support Pause filtering(indicated
311 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
312 * count value. On VMRUN this value is loaded into an internal counter.
313 * Each time a pause instruction is executed, this counter is decremented
314 * until it reaches zero at which time a #VMEXIT is generated if pause
315 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
316 * Intercept Filtering for more details.
317 * This also indicate if ple logic enabled.
319 * pause_filter_thresh: In addition, some processor families support advanced
320 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
321 * the amount of time a guest is allowed to execute in a pause loop.
322 * In this mode, a 16-bit pause filter threshold field is added in the
323 * VMCB. The threshold value is a cycle count that is used to reset the
324 * pause counter. As with simple pause filtering, VMRUN loads the pause
325 * count value from VMCB into an internal counter. Then, on each pause
326 * instruction the hardware checks the elapsed number of cycles since
327 * the most recent pause instruction against the pause filter threshold.
328 * If the elapsed cycle count is greater than the pause filter threshold,
329 * then the internal pause count is reloaded from the VMCB and execution
330 * continues. If the elapsed cycle count is less than the pause filter
331 * threshold, then the internal pause count is decremented. If the count
332 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
333 * triggered. If advanced pause filtering is supported and pause filter
334 * threshold field is set to zero, the filter will operate in the simpler,
338 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
339 module_param(pause_filter_thresh, ushort, 0444);
341 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
342 module_param(pause_filter_count, ushort, 0444);
344 /* Default doubles per-vcpu window every exit. */
345 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
346 module_param(pause_filter_count_grow, ushort, 0444);
348 /* Default resets per-vcpu window every exit to pause_filter_count. */
349 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
350 module_param(pause_filter_count_shrink, ushort, 0444);
352 /* Default is to compute the maximum so we can never overflow. */
353 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
354 module_param(pause_filter_count_max, ushort, 0444);
356 /* allow nested paging (virtualized MMU) for all guests */
357 static int npt = true;
358 module_param(npt, int, S_IRUGO);
360 /* allow nested virtualization in KVM/SVM */
361 static int nested = true;
362 module_param(nested, int, S_IRUGO);
364 /* enable / disable AVIC */
366 #ifdef CONFIG_X86_LOCAL_APIC
367 module_param(avic, int, S_IRUGO);
370 /* enable/disable Virtual VMLOAD VMSAVE */
371 static int vls = true;
372 module_param(vls, int, 0444);
374 /* enable/disable Virtual GIF */
375 static int vgif = true;
376 module_param(vgif, int, 0444);
378 /* enable/disable SEV support */
379 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
380 module_param(sev, int, 0444);
382 static u8 rsm_ins_bytes[] = "\x0f\xaa";
384 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
385 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
386 static void svm_complete_interrupts(struct vcpu_svm *svm);
388 static int nested_svm_exit_handled(struct vcpu_svm *svm);
389 static int nested_svm_intercept(struct vcpu_svm *svm);
390 static int nested_svm_vmexit(struct vcpu_svm *svm);
391 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
392 bool has_error_code, u32 error_code);
395 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
396 pause filter count */
397 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
398 VMCB_ASID, /* ASID */
399 VMCB_INTR, /* int_ctl, int_vector */
400 VMCB_NPT, /* npt_en, nCR3, gPAT */
401 VMCB_CR, /* CR0, CR3, CR4, EFER */
402 VMCB_DR, /* DR6, DR7 */
403 VMCB_DT, /* GDT, IDT */
404 VMCB_SEG, /* CS, DS, SS, ES, CPL */
405 VMCB_CR2, /* CR2 only */
406 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
407 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
408 * AVIC PHYSICAL_TABLE pointer,
409 * AVIC LOGICAL_TABLE pointer
414 /* TPR and CR2 are always written before VMRUN */
415 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
417 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
419 static unsigned int max_sev_asid;
420 static unsigned int min_sev_asid;
421 static unsigned long *sev_asid_bitmap;
422 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
425 struct list_head list;
426 unsigned long npages;
433 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
435 return container_of(kvm, struct kvm_svm, kvm);
438 static inline bool svm_sev_enabled(void)
440 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
443 static inline bool sev_guest(struct kvm *kvm)
445 #ifdef CONFIG_KVM_AMD_SEV
446 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
454 static inline int sev_get_asid(struct kvm *kvm)
456 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
461 static inline void mark_all_dirty(struct vmcb *vmcb)
463 vmcb->control.clean = 0;
466 static inline void mark_all_clean(struct vmcb *vmcb)
468 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
469 & ~VMCB_ALWAYS_DIRTY_MASK;
472 static inline void mark_dirty(struct vmcb *vmcb, int bit)
474 vmcb->control.clean &= ~(1 << bit);
477 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
479 return container_of(vcpu, struct vcpu_svm, vcpu);
482 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
484 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
485 mark_dirty(svm->vmcb, VMCB_AVIC);
488 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
490 struct vcpu_svm *svm = to_svm(vcpu);
491 u64 *entry = svm->avic_physical_id_cache;
496 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
499 static void recalc_intercepts(struct vcpu_svm *svm)
501 struct vmcb_control_area *c, *h;
502 struct nested_state *g;
504 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
506 if (!is_guest_mode(&svm->vcpu))
509 c = &svm->vmcb->control;
510 h = &svm->nested.hsave->control;
513 c->intercept_cr = h->intercept_cr | g->intercept_cr;
514 c->intercept_dr = h->intercept_dr | g->intercept_dr;
515 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
516 c->intercept = h->intercept | g->intercept;
518 c->intercept |= (1ULL << INTERCEPT_VMLOAD);
519 c->intercept |= (1ULL << INTERCEPT_VMSAVE);
522 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
524 if (is_guest_mode(&svm->vcpu))
525 return svm->nested.hsave;
530 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
532 struct vmcb *vmcb = get_host_vmcb(svm);
534 vmcb->control.intercept_cr |= (1U << bit);
536 recalc_intercepts(svm);
539 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
541 struct vmcb *vmcb = get_host_vmcb(svm);
543 vmcb->control.intercept_cr &= ~(1U << bit);
545 recalc_intercepts(svm);
548 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
550 struct vmcb *vmcb = get_host_vmcb(svm);
552 return vmcb->control.intercept_cr & (1U << bit);
555 static inline void set_dr_intercepts(struct vcpu_svm *svm)
557 struct vmcb *vmcb = get_host_vmcb(svm);
559 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
560 | (1 << INTERCEPT_DR1_READ)
561 | (1 << INTERCEPT_DR2_READ)
562 | (1 << INTERCEPT_DR3_READ)
563 | (1 << INTERCEPT_DR4_READ)
564 | (1 << INTERCEPT_DR5_READ)
565 | (1 << INTERCEPT_DR6_READ)
566 | (1 << INTERCEPT_DR7_READ)
567 | (1 << INTERCEPT_DR0_WRITE)
568 | (1 << INTERCEPT_DR1_WRITE)
569 | (1 << INTERCEPT_DR2_WRITE)
570 | (1 << INTERCEPT_DR3_WRITE)
571 | (1 << INTERCEPT_DR4_WRITE)
572 | (1 << INTERCEPT_DR5_WRITE)
573 | (1 << INTERCEPT_DR6_WRITE)
574 | (1 << INTERCEPT_DR7_WRITE);
576 recalc_intercepts(svm);
579 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
581 struct vmcb *vmcb = get_host_vmcb(svm);
583 vmcb->control.intercept_dr = 0;
585 recalc_intercepts(svm);
588 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
590 struct vmcb *vmcb = get_host_vmcb(svm);
592 vmcb->control.intercept_exceptions |= (1U << bit);
594 recalc_intercepts(svm);
597 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
599 struct vmcb *vmcb = get_host_vmcb(svm);
601 vmcb->control.intercept_exceptions &= ~(1U << bit);
603 recalc_intercepts(svm);
606 static inline void set_intercept(struct vcpu_svm *svm, int bit)
608 struct vmcb *vmcb = get_host_vmcb(svm);
610 vmcb->control.intercept |= (1ULL << bit);
612 recalc_intercepts(svm);
615 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
617 struct vmcb *vmcb = get_host_vmcb(svm);
619 vmcb->control.intercept &= ~(1ULL << bit);
621 recalc_intercepts(svm);
624 static inline bool vgif_enabled(struct vcpu_svm *svm)
626 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
629 static inline void enable_gif(struct vcpu_svm *svm)
631 if (vgif_enabled(svm))
632 svm->vmcb->control.int_ctl |= V_GIF_MASK;
634 svm->vcpu.arch.hflags |= HF_GIF_MASK;
637 static inline void disable_gif(struct vcpu_svm *svm)
639 if (vgif_enabled(svm))
640 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
642 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
645 static inline bool gif_set(struct vcpu_svm *svm)
647 if (vgif_enabled(svm))
648 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
650 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
653 static unsigned long iopm_base;
655 struct kvm_ldttss_desc {
658 unsigned base1:8, type:5, dpl:2, p:1;
659 unsigned limit1:4, zero0:3, g:1, base2:8;
662 } __attribute__((packed));
664 struct svm_cpu_data {
671 struct kvm_ldttss_desc *tss_desc;
673 struct page *save_area;
674 struct vmcb *current_vmcb;
676 /* index = sev_asid, value = vmcb pointer */
677 struct vmcb **sev_vmcbs;
680 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
682 struct svm_init_data {
687 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
689 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
690 #define MSRS_RANGE_SIZE 2048
691 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
693 static u32 svm_msrpm_offset(u32 msr)
698 for (i = 0; i < NUM_MSR_MAPS; i++) {
699 if (msr < msrpm_ranges[i] ||
700 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
703 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
704 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
706 /* Now we have the u8 offset - but need the u32 offset */
710 /* MSR not in any range */
714 #define MAX_INST_SIZE 15
716 static inline void clgi(void)
718 asm volatile (__ex(SVM_CLGI));
721 static inline void stgi(void)
723 asm volatile (__ex(SVM_STGI));
726 static inline void invlpga(unsigned long addr, u32 asid)
728 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
731 static int get_npt_level(struct kvm_vcpu *vcpu)
734 return PT64_ROOT_4LEVEL;
736 return PT32E_ROOT_LEVEL;
740 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
742 vcpu->arch.efer = efer;
745 /* Shadow paging assumes NX to be available. */
748 if (!(efer & EFER_LMA))
752 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
753 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
756 static int is_external_interrupt(u32 info)
758 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
759 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
762 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
764 struct vcpu_svm *svm = to_svm(vcpu);
767 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
768 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
772 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
774 struct vcpu_svm *svm = to_svm(vcpu);
777 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
779 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
783 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
785 struct vcpu_svm *svm = to_svm(vcpu);
787 if (svm->vmcb->control.next_rip != 0) {
788 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
789 svm->next_rip = svm->vmcb->control.next_rip;
792 if (!svm->next_rip) {
793 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
795 printk(KERN_DEBUG "%s: NOP\n", __func__);
798 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
799 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
800 __func__, kvm_rip_read(vcpu), svm->next_rip);
802 kvm_rip_write(vcpu, svm->next_rip);
803 svm_set_interrupt_shadow(vcpu, 0);
806 static void svm_queue_exception(struct kvm_vcpu *vcpu)
808 struct vcpu_svm *svm = to_svm(vcpu);
809 unsigned nr = vcpu->arch.exception.nr;
810 bool has_error_code = vcpu->arch.exception.has_error_code;
811 bool reinject = vcpu->arch.exception.injected;
812 u32 error_code = vcpu->arch.exception.error_code;
815 * If we are within a nested VM we'd better #VMEXIT and let the guest
816 * handle the exception
819 nested_svm_check_exception(svm, nr, has_error_code, error_code))
822 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
823 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
826 * For guest debugging where we have to reinject #BP if some
827 * INT3 is guest-owned:
828 * Emulate nRIP by moving RIP forward. Will fail if injection
829 * raises a fault that is not intercepted. Still better than
830 * failing in all cases.
832 skip_emulated_instruction(&svm->vcpu);
833 rip = kvm_rip_read(&svm->vcpu);
834 svm->int3_rip = rip + svm->vmcb->save.cs.base;
835 svm->int3_injected = rip - old_rip;
838 svm->vmcb->control.event_inj = nr
840 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
841 | SVM_EVTINJ_TYPE_EXEPT;
842 svm->vmcb->control.event_inj_err = error_code;
845 static void svm_init_erratum_383(void)
851 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
854 /* Use _safe variants to not break nested virtualization */
855 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
861 low = lower_32_bits(val);
862 high = upper_32_bits(val);
864 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
866 erratum_383_found = true;
869 static void svm_init_osvw(struct kvm_vcpu *vcpu)
872 * Guests should see errata 400 and 415 as fixed (assuming that
873 * HLT and IO instructions are intercepted).
875 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
876 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
879 * By increasing VCPU's osvw.length to 3 we are telling the guest that
880 * all osvw.status bits inside that length, including bit 0 (which is
881 * reserved for erratum 298), are valid. However, if host processor's
882 * osvw_len is 0 then osvw_status[0] carries no information. We need to
883 * be conservative here and therefore we tell the guest that erratum 298
884 * is present (because we really don't know).
886 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
887 vcpu->arch.osvw.status |= 1;
890 static int has_svm(void)
894 if (!cpu_has_svm(&msg)) {
895 printk(KERN_INFO "has_svm: %s\n", msg);
900 pr_info("KVM is unsupported when running as an SEV guest\n");
907 static void svm_hardware_disable(void)
909 /* Make sure we clean up behind us */
910 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
911 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
915 amd_pmu_disable_virt();
918 static int svm_hardware_enable(void)
921 struct svm_cpu_data *sd;
923 struct desc_struct *gdt;
924 int me = raw_smp_processor_id();
926 rdmsrl(MSR_EFER, efer);
927 if (efer & EFER_SVME)
931 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
934 sd = per_cpu(svm_data, me);
936 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
940 sd->asid_generation = 1;
941 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
942 sd->next_asid = sd->max_asid + 1;
943 sd->min_asid = max_sev_asid + 1;
945 gdt = get_current_gdt_rw();
946 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
948 wrmsrl(MSR_EFER, efer | EFER_SVME);
950 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
952 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
953 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
954 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
961 * Note that it is possible to have a system with mixed processor
962 * revisions and therefore different OSVW bits. If bits are not the same
963 * on different processors then choose the worst case (i.e. if erratum
964 * is present on one processor and not on another then assume that the
965 * erratum is present everywhere).
967 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
968 uint64_t len, status = 0;
971 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
973 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
977 osvw_status = osvw_len = 0;
981 osvw_status |= status;
982 osvw_status &= (1ULL << osvw_len) - 1;
985 osvw_status = osvw_len = 0;
987 svm_init_erratum_383();
989 amd_pmu_enable_virt();
994 static void svm_cpu_uninit(int cpu)
996 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
1001 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
1002 kfree(sd->sev_vmcbs);
1003 __free_page(sd->save_area);
1007 static int svm_cpu_init(int cpu)
1009 struct svm_cpu_data *sd;
1011 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1015 sd->save_area = alloc_page(GFP_KERNEL);
1019 if (svm_sev_enabled()) {
1020 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1024 goto free_save_area;
1027 per_cpu(svm_data, cpu) = sd;
1032 __free_page(sd->save_area);
1039 static bool valid_msr_intercept(u32 index)
1043 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1044 if (direct_access_msrs[i].index == index)
1050 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1057 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1058 to_svm(vcpu)->msrpm;
1060 offset = svm_msrpm_offset(msr);
1061 bit_write = 2 * (msr & 0x0f) + 1;
1062 tmp = msrpm[offset];
1064 BUG_ON(offset == MSR_INVALID);
1066 return !!test_bit(bit_write, &tmp);
1069 static void set_msr_interception(u32 *msrpm, unsigned msr,
1070 int read, int write)
1072 u8 bit_read, bit_write;
1077 * If this warning triggers extend the direct_access_msrs list at the
1078 * beginning of the file
1080 WARN_ON(!valid_msr_intercept(msr));
1082 offset = svm_msrpm_offset(msr);
1083 bit_read = 2 * (msr & 0x0f);
1084 bit_write = 2 * (msr & 0x0f) + 1;
1085 tmp = msrpm[offset];
1087 BUG_ON(offset == MSR_INVALID);
1089 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1090 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1092 msrpm[offset] = tmp;
1095 static void svm_vcpu_init_msrpm(u32 *msrpm)
1099 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1101 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1102 if (!direct_access_msrs[i].always)
1105 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1109 static void add_msr_offset(u32 offset)
1113 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1115 /* Offset already in list? */
1116 if (msrpm_offsets[i] == offset)
1119 /* Slot used by another offset? */
1120 if (msrpm_offsets[i] != MSR_INVALID)
1123 /* Add offset to list */
1124 msrpm_offsets[i] = offset;
1130 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1131 * increase MSRPM_OFFSETS in this case.
1136 static void init_msrpm_offsets(void)
1140 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1142 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1145 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1146 BUG_ON(offset == MSR_INVALID);
1148 add_msr_offset(offset);
1152 static void svm_enable_lbrv(struct vcpu_svm *svm)
1154 u32 *msrpm = svm->msrpm;
1156 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1157 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1158 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1159 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1160 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1163 static void svm_disable_lbrv(struct vcpu_svm *svm)
1165 u32 *msrpm = svm->msrpm;
1167 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1168 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1169 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1170 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1171 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1174 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1176 svm->nmi_singlestep = false;
1178 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1179 /* Clear our flags if they were not set by the guest */
1180 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1181 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1182 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1183 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1188 * This hash table is used to map VM_ID to a struct kvm_svm,
1189 * when handling AMD IOMMU GALOG notification to schedule in
1190 * a particular vCPU.
1192 #define SVM_VM_DATA_HASH_BITS 8
1193 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1194 static u32 next_vm_id = 0;
1195 static bool next_vm_id_wrapped = 0;
1196 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1199 * This function is called from IOMMU driver to notify
1200 * SVM to schedule in a particular vCPU of a particular VM.
1202 static int avic_ga_log_notifier(u32 ga_tag)
1204 unsigned long flags;
1205 struct kvm_svm *kvm_svm;
1206 struct kvm_vcpu *vcpu = NULL;
1207 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1208 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1210 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1212 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1213 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1214 if (kvm_svm->avic_vm_id != vm_id)
1216 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1219 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1222 * At this point, the IOMMU should have already set the pending
1223 * bit in the vAPIC backing page. So, we just need to schedule
1227 kvm_vcpu_wake_up(vcpu);
1232 static __init int sev_hardware_setup(void)
1234 struct sev_user_data_status *status;
1237 /* Maximum number of encrypted guests supported simultaneously */
1238 max_sev_asid = cpuid_ecx(0x8000001F);
1243 /* Minimum ASID value that should be used for SEV guest */
1244 min_sev_asid = cpuid_edx(0x8000001F);
1246 /* Initialize SEV ASID bitmap */
1247 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1248 if (!sev_asid_bitmap)
1251 status = kmalloc(sizeof(*status), GFP_KERNEL);
1256 * Check SEV platform status.
1258 * PLATFORM_STATUS can be called in any state, if we failed to query
1259 * the PLATFORM status then either PSP firmware does not support SEV
1260 * feature or SEV firmware is dead.
1262 rc = sev_platform_status(status, NULL);
1266 pr_info("SEV supported\n");
1273 static void grow_ple_window(struct kvm_vcpu *vcpu)
1275 struct vcpu_svm *svm = to_svm(vcpu);
1276 struct vmcb_control_area *control = &svm->vmcb->control;
1277 int old = control->pause_filter_count;
1279 control->pause_filter_count = __grow_ple_window(old,
1281 pause_filter_count_grow,
1282 pause_filter_count_max);
1284 if (control->pause_filter_count != old)
1285 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1287 trace_kvm_ple_window_grow(vcpu->vcpu_id,
1288 control->pause_filter_count, old);
1291 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1293 struct vcpu_svm *svm = to_svm(vcpu);
1294 struct vmcb_control_area *control = &svm->vmcb->control;
1295 int old = control->pause_filter_count;
1297 control->pause_filter_count =
1298 __shrink_ple_window(old,
1300 pause_filter_count_shrink,
1301 pause_filter_count);
1302 if (control->pause_filter_count != old)
1303 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1305 trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1306 control->pause_filter_count, old);
1310 * The default MMIO mask is a single bit (excluding the present bit),
1311 * which could conflict with the memory encryption bit. Check for
1312 * memory encryption support and override the default MMIO mask if
1313 * memory encryption is enabled.
1315 static __init void svm_adjust_mmio_mask(void)
1317 unsigned int enc_bit, mask_bit;
1320 /* If there is no memory encryption support, use existing mask */
1321 if (cpuid_eax(0x80000000) < 0x8000001f)
1324 /* If memory encryption is not enabled, use existing mask */
1325 rdmsrl(MSR_K8_SYSCFG, msr);
1326 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
1329 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
1330 mask_bit = boot_cpu_data.x86_phys_bits;
1332 /* Increment the mask bit if it is the same as the encryption bit */
1333 if (enc_bit == mask_bit)
1337 * If the mask bit location is below 52, then some bits above the
1338 * physical addressing limit will always be reserved, so use the
1339 * rsvd_bits() function to generate the mask. This mask, along with
1340 * the present bit, will be used to generate a page fault with
1343 * If the mask bit location is 52 (or above), then clear the mask.
1345 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
1347 kvm_mmu_set_mmio_spte_mask(mask, mask);
1350 static __init int svm_hardware_setup(void)
1353 struct page *iopm_pages;
1357 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1362 iopm_va = page_address(iopm_pages);
1363 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1364 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1366 init_msrpm_offsets();
1368 if (boot_cpu_has(X86_FEATURE_NX))
1369 kvm_enable_efer_bits(EFER_NX);
1371 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1372 kvm_enable_efer_bits(EFER_FFXSR);
1374 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1375 kvm_has_tsc_control = true;
1376 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1377 kvm_tsc_scaling_ratio_frac_bits = 32;
1380 /* Check for pause filtering support */
1381 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1382 pause_filter_count = 0;
1383 pause_filter_thresh = 0;
1384 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1385 pause_filter_thresh = 0;
1389 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1390 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1394 if (boot_cpu_has(X86_FEATURE_SEV) &&
1395 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1396 r = sev_hardware_setup();
1404 svm_adjust_mmio_mask();
1406 for_each_possible_cpu(cpu) {
1407 r = svm_cpu_init(cpu);
1412 if (!boot_cpu_has(X86_FEATURE_NPT))
1413 npt_enabled = false;
1415 if (npt_enabled && !npt) {
1416 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1417 npt_enabled = false;
1421 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1428 !boot_cpu_has(X86_FEATURE_AVIC) ||
1429 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1432 pr_info("AVIC enabled\n");
1434 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1440 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1441 !IS_ENABLED(CONFIG_X86_64)) {
1444 pr_info("Virtual VMLOAD VMSAVE supported\n");
1448 vgif = false; /* Disabled for CVE-2021-3653 */
1453 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1458 static __exit void svm_hardware_unsetup(void)
1462 if (svm_sev_enabled())
1463 bitmap_free(sev_asid_bitmap);
1465 for_each_possible_cpu(cpu)
1466 svm_cpu_uninit(cpu);
1468 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1472 static void init_seg(struct vmcb_seg *seg)
1475 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1476 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1477 seg->limit = 0xffff;
1481 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1484 seg->attrib = SVM_SELECTOR_P_MASK | type;
1485 seg->limit = 0xffff;
1489 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1491 struct vcpu_svm *svm = to_svm(vcpu);
1493 if (is_guest_mode(vcpu))
1494 return svm->nested.hsave->control.tsc_offset;
1496 return vcpu->arch.tsc_offset;
1499 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1501 struct vcpu_svm *svm = to_svm(vcpu);
1502 u64 g_tsc_offset = 0;
1504 if (is_guest_mode(vcpu)) {
1505 /* Write L1's TSC offset. */
1506 g_tsc_offset = svm->vmcb->control.tsc_offset -
1507 svm->nested.hsave->control.tsc_offset;
1508 svm->nested.hsave->control.tsc_offset = offset;
1510 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1511 svm->vmcb->control.tsc_offset,
1514 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1516 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1517 return svm->vmcb->control.tsc_offset;
1520 static void avic_init_vmcb(struct vcpu_svm *svm)
1522 struct vmcb *vmcb = svm->vmcb;
1523 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1524 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1525 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1526 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1528 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1529 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1530 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1531 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1532 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1535 static void init_vmcb(struct vcpu_svm *svm)
1537 struct vmcb_control_area *control = &svm->vmcb->control;
1538 struct vmcb_save_area *save = &svm->vmcb->save;
1540 svm->vcpu.arch.hflags = 0;
1542 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1543 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1544 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1545 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1546 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1547 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1548 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1549 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1551 set_dr_intercepts(svm);
1553 set_exception_intercept(svm, PF_VECTOR);
1554 set_exception_intercept(svm, UD_VECTOR);
1555 set_exception_intercept(svm, MC_VECTOR);
1556 set_exception_intercept(svm, AC_VECTOR);
1557 set_exception_intercept(svm, DB_VECTOR);
1559 * Guest access to VMware backdoor ports could legitimately
1560 * trigger #GP because of TSS I/O permission bitmap.
1561 * We intercept those #GP and allow access to them anyway
1564 if (enable_vmware_backdoor)
1565 set_exception_intercept(svm, GP_VECTOR);
1567 set_intercept(svm, INTERCEPT_INTR);
1568 set_intercept(svm, INTERCEPT_NMI);
1569 set_intercept(svm, INTERCEPT_SMI);
1570 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1571 set_intercept(svm, INTERCEPT_RDPMC);
1572 set_intercept(svm, INTERCEPT_CPUID);
1573 set_intercept(svm, INTERCEPT_INVD);
1574 set_intercept(svm, INTERCEPT_INVLPG);
1575 set_intercept(svm, INTERCEPT_INVLPGA);
1576 set_intercept(svm, INTERCEPT_IOIO_PROT);
1577 set_intercept(svm, INTERCEPT_MSR_PROT);
1578 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1579 set_intercept(svm, INTERCEPT_SHUTDOWN);
1580 set_intercept(svm, INTERCEPT_VMRUN);
1581 set_intercept(svm, INTERCEPT_VMMCALL);
1582 set_intercept(svm, INTERCEPT_VMLOAD);
1583 set_intercept(svm, INTERCEPT_VMSAVE);
1584 set_intercept(svm, INTERCEPT_STGI);
1585 set_intercept(svm, INTERCEPT_CLGI);
1586 set_intercept(svm, INTERCEPT_SKINIT);
1587 set_intercept(svm, INTERCEPT_WBINVD);
1588 set_intercept(svm, INTERCEPT_XSETBV);
1589 set_intercept(svm, INTERCEPT_RSM);
1591 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1592 set_intercept(svm, INTERCEPT_MONITOR);
1593 set_intercept(svm, INTERCEPT_MWAIT);
1596 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1597 set_intercept(svm, INTERCEPT_HLT);
1599 control->iopm_base_pa = __sme_set(iopm_base);
1600 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1601 control->int_ctl = V_INTR_MASKING_MASK;
1603 init_seg(&save->es);
1604 init_seg(&save->ss);
1605 init_seg(&save->ds);
1606 init_seg(&save->fs);
1607 init_seg(&save->gs);
1609 save->cs.selector = 0xf000;
1610 save->cs.base = 0xffff0000;
1611 /* Executable/Readable Code Segment */
1612 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1613 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1614 save->cs.limit = 0xffff;
1616 save->gdtr.limit = 0xffff;
1617 save->idtr.limit = 0xffff;
1619 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1620 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1622 svm_set_efer(&svm->vcpu, 0);
1623 save->dr6 = 0xffff0ff0;
1624 kvm_set_rflags(&svm->vcpu, 2);
1625 save->rip = 0x0000fff0;
1626 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1629 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1630 * It also updates the guest-visible cr0 value.
1632 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1633 kvm_mmu_reset_context(&svm->vcpu);
1635 save->cr4 = X86_CR4_PAE;
1639 /* Setup VMCB for Nested Paging */
1640 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1641 clr_intercept(svm, INTERCEPT_INVLPG);
1642 clr_exception_intercept(svm, PF_VECTOR);
1643 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1644 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1645 save->g_pat = svm->vcpu.arch.pat;
1649 svm->asid_generation = 0;
1651 svm->nested.vmcb = 0;
1652 svm->vcpu.arch.hflags = 0;
1654 if (pause_filter_count) {
1655 control->pause_filter_count = pause_filter_count;
1656 if (pause_filter_thresh)
1657 control->pause_filter_thresh = pause_filter_thresh;
1658 set_intercept(svm, INTERCEPT_PAUSE);
1660 clr_intercept(svm, INTERCEPT_PAUSE);
1663 if (kvm_vcpu_apicv_active(&svm->vcpu))
1664 avic_init_vmcb(svm);
1667 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1668 * in VMCB and clear intercepts to avoid #VMEXIT.
1671 clr_intercept(svm, INTERCEPT_VMLOAD);
1672 clr_intercept(svm, INTERCEPT_VMSAVE);
1673 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1677 clr_intercept(svm, INTERCEPT_STGI);
1678 clr_intercept(svm, INTERCEPT_CLGI);
1679 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1682 if (sev_guest(svm->vcpu.kvm)) {
1683 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1684 clr_exception_intercept(svm, UD_VECTOR);
1687 mark_all_dirty(svm->vmcb);
1693 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1696 u64 *avic_physical_id_table;
1697 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1699 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1702 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1704 return &avic_physical_id_table[index];
1709 * AVIC hardware walks the nested page table to check permissions,
1710 * but does not use the SPA address specified in the leaf page
1711 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1712 * field of the VMCB. Therefore, we set up the
1713 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1715 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1717 struct kvm *kvm = vcpu->kvm;
1720 mutex_lock(&kvm->slots_lock);
1721 if (kvm->arch.apic_access_page_done)
1724 ret = __x86_set_memory_region(kvm,
1725 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1726 APIC_DEFAULT_PHYS_BASE,
1731 kvm->arch.apic_access_page_done = true;
1733 mutex_unlock(&kvm->slots_lock);
1737 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1740 u64 *entry, new_entry;
1741 int id = vcpu->vcpu_id;
1742 struct vcpu_svm *svm = to_svm(vcpu);
1744 ret = avic_init_access_page(vcpu);
1748 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1751 if (!svm->vcpu.arch.apic->regs)
1754 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1756 /* Setting AVIC backing page address in the phy APIC ID table */
1757 entry = avic_get_physical_id_entry(vcpu, id);
1761 new_entry = READ_ONCE(*entry);
1762 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1763 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1764 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1765 WRITE_ONCE(*entry, new_entry);
1767 svm->avic_physical_id_cache = entry;
1772 static void __sev_asid_free(int asid)
1774 struct svm_cpu_data *sd;
1778 clear_bit(pos, sev_asid_bitmap);
1780 for_each_possible_cpu(cpu) {
1781 sd = per_cpu(svm_data, cpu);
1782 sd->sev_vmcbs[asid] = NULL;
1786 static void sev_asid_free(struct kvm *kvm)
1788 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1790 __sev_asid_free(sev->asid);
1793 static void sev_decommission(unsigned int handle)
1795 struct sev_data_decommission *decommission;
1800 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1804 decommission->handle = handle;
1805 sev_guest_decommission(decommission, NULL);
1807 kfree(decommission);
1810 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1812 struct sev_data_deactivate *data;
1817 data = kzalloc(sizeof(*data), GFP_KERNEL);
1821 /* deactivate handle */
1822 data->handle = handle;
1823 sev_guest_deactivate(data, NULL);
1825 wbinvd_on_all_cpus();
1826 sev_guest_df_flush(NULL);
1829 sev_decommission(handle);
1832 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1833 unsigned long ulen, unsigned long *n,
1836 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1837 unsigned long npages, npinned, size;
1838 unsigned long locked, lock_limit;
1839 struct page **pages;
1840 unsigned long first, last;
1842 lockdep_assert_held(&kvm->lock);
1844 if (ulen == 0 || uaddr + ulen < uaddr)
1847 /* Calculate number of pages. */
1848 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1849 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1850 npages = (last - first + 1);
1852 locked = sev->pages_locked + npages;
1853 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1854 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1855 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1859 /* Avoid using vmalloc for smaller buffers. */
1860 size = npages * sizeof(struct page *);
1861 if (size > PAGE_SIZE)
1862 pages = vmalloc(size);
1864 pages = kmalloc(size, GFP_KERNEL);
1869 /* Pin the user virtual address. */
1870 npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1871 if (npinned != npages) {
1872 pr_err("SEV: Failure locking %lu pages.\n", npages);
1877 sev->pages_locked = locked;
1883 release_pages(pages, npinned);
1889 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1890 unsigned long npages)
1892 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1894 release_pages(pages, npages);
1896 sev->pages_locked -= npages;
1899 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1901 uint8_t *page_virtual;
1904 if (npages == 0 || pages == NULL)
1907 for (i = 0; i < npages; i++) {
1908 page_virtual = kmap_atomic(pages[i]);
1909 clflush_cache_range(page_virtual, PAGE_SIZE);
1910 kunmap_atomic(page_virtual);
1914 static void __unregister_enc_region_locked(struct kvm *kvm,
1915 struct enc_region *region)
1918 * The guest may change the memory encryption attribute from C=0 -> C=1
1919 * or vice versa for this memory range. Lets make sure caches are
1920 * flushed to ensure that guest data gets written into memory with
1923 sev_clflush_pages(region->pages, region->npages);
1925 sev_unpin_memory(kvm, region->pages, region->npages);
1926 list_del(®ion->list);
1930 static struct kvm *svm_vm_alloc(void)
1932 struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1937 return &kvm_svm->kvm;
1940 static void svm_vm_free(struct kvm *kvm)
1942 vfree(to_kvm_svm(kvm));
1945 static void sev_vm_destroy(struct kvm *kvm)
1947 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1948 struct list_head *head = &sev->regions_list;
1949 struct list_head *pos, *q;
1951 if (!sev_guest(kvm))
1954 mutex_lock(&kvm->lock);
1957 * if userspace was terminated before unregistering the memory regions
1958 * then lets unpin all the registered memory.
1960 if (!list_empty(head)) {
1961 list_for_each_safe(pos, q, head) {
1962 __unregister_enc_region_locked(kvm,
1963 list_entry(pos, struct enc_region, list));
1968 mutex_unlock(&kvm->lock);
1970 sev_unbind_asid(kvm, sev->handle);
1974 static void avic_vm_destroy(struct kvm *kvm)
1976 unsigned long flags;
1977 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1982 if (kvm_svm->avic_logical_id_table_page)
1983 __free_page(kvm_svm->avic_logical_id_table_page);
1984 if (kvm_svm->avic_physical_id_table_page)
1985 __free_page(kvm_svm->avic_physical_id_table_page);
1987 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1988 hash_del(&kvm_svm->hnode);
1989 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1992 static void svm_vm_destroy(struct kvm *kvm)
1994 avic_vm_destroy(kvm);
1995 sev_vm_destroy(kvm);
1998 static int avic_vm_init(struct kvm *kvm)
2000 unsigned long flags;
2002 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
2004 struct page *p_page;
2005 struct page *l_page;
2011 /* Allocating physical APIC ID table (4KB) */
2012 p_page = alloc_page(GFP_KERNEL);
2016 kvm_svm->avic_physical_id_table_page = p_page;
2017 clear_page(page_address(p_page));
2019 /* Allocating logical APIC ID table (4KB) */
2020 l_page = alloc_page(GFP_KERNEL);
2024 kvm_svm->avic_logical_id_table_page = l_page;
2025 clear_page(page_address(l_page));
2027 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
2029 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
2030 if (vm_id == 0) { /* id is 1-based, zero is not okay */
2031 next_vm_id_wrapped = 1;
2034 /* Is it still in use? Only possible if wrapped at least once */
2035 if (next_vm_id_wrapped) {
2036 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
2037 if (k2->avic_vm_id == vm_id)
2041 kvm_svm->avic_vm_id = vm_id;
2042 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
2043 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
2048 avic_vm_destroy(kvm);
2053 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
2056 unsigned long flags;
2057 struct amd_svm_iommu_ir *ir;
2058 struct vcpu_svm *svm = to_svm(vcpu);
2060 if (!kvm_arch_has_assigned_device(vcpu->kvm))
2064 * Here, we go through the per-vcpu ir_list to update all existing
2065 * interrupt remapping table entry targeting this vcpu.
2067 spin_lock_irqsave(&svm->ir_list_lock, flags);
2069 if (list_empty(&svm->ir_list))
2072 list_for_each_entry(ir, &svm->ir_list, node) {
2073 ret = amd_iommu_update_ga(cpu, r, ir->data);
2078 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2082 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2085 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2086 int h_physical_id = kvm_cpu_get_apicid(cpu);
2087 struct vcpu_svm *svm = to_svm(vcpu);
2089 if (!kvm_vcpu_apicv_active(vcpu))
2093 * Since the host physical APIC id is 8 bits,
2094 * we can support host APIC ID upto 255.
2096 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2099 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2100 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2102 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2103 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2105 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2106 if (svm->avic_is_running)
2107 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2109 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2110 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2111 svm->avic_is_running);
2114 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2117 struct vcpu_svm *svm = to_svm(vcpu);
2119 if (!kvm_vcpu_apicv_active(vcpu))
2122 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2123 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2124 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2126 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2127 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2131 * This function is called during VCPU halt/unhalt.
2133 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2135 struct vcpu_svm *svm = to_svm(vcpu);
2137 svm->avic_is_running = is_run;
2139 avic_vcpu_load(vcpu, vcpu->cpu);
2141 avic_vcpu_put(vcpu);
2144 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2146 struct vcpu_svm *svm = to_svm(vcpu);
2150 vcpu->arch.microcode_version = 0x01000065;
2152 svm->virt_spec_ctrl = 0;
2155 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2156 MSR_IA32_APICBASE_ENABLE;
2157 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2158 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2162 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2163 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2165 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2166 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2169 static int avic_init_vcpu(struct vcpu_svm *svm)
2173 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2176 ret = avic_init_backing_page(&svm->vcpu);
2180 INIT_LIST_HEAD(&svm->ir_list);
2181 spin_lock_init(&svm->ir_list_lock);
2186 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2188 struct vcpu_svm *svm;
2190 struct page *msrpm_pages;
2191 struct page *hsave_page;
2192 struct page *nested_msrpm_pages;
2195 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2201 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2206 page = alloc_page(GFP_KERNEL);
2210 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2214 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2215 if (!nested_msrpm_pages)
2218 hsave_page = alloc_page(GFP_KERNEL);
2222 err = avic_init_vcpu(svm);
2226 /* We initialize this flag to true to make sure that the is_running
2227 * bit would be set the first time the vcpu is loaded.
2229 svm->avic_is_running = true;
2231 svm->nested.hsave = page_address(hsave_page);
2233 svm->msrpm = page_address(msrpm_pages);
2234 svm_vcpu_init_msrpm(svm->msrpm);
2236 svm->nested.msrpm = page_address(nested_msrpm_pages);
2237 svm_vcpu_init_msrpm(svm->nested.msrpm);
2239 svm->vmcb = page_address(page);
2240 clear_page(svm->vmcb);
2241 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2242 svm->asid_generation = 0;
2245 svm_init_osvw(&svm->vcpu);
2250 __free_page(hsave_page);
2252 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2254 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2258 kvm_vcpu_uninit(&svm->vcpu);
2260 kmem_cache_free(kvm_vcpu_cache, svm);
2262 return ERR_PTR(err);
2265 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2269 for_each_online_cpu(i)
2270 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2273 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2275 struct vcpu_svm *svm = to_svm(vcpu);
2278 * The vmcb page can be recycled, causing a false negative in
2279 * svm_vcpu_load(). So, ensure that no logical CPU has this
2280 * vmcb page recorded as its current vmcb.
2282 svm_clear_current_vmcb(svm->vmcb);
2284 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2285 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2286 __free_page(virt_to_page(svm->nested.hsave));
2287 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2288 kvm_vcpu_uninit(vcpu);
2289 kmem_cache_free(kvm_vcpu_cache, svm);
2292 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2294 struct vcpu_svm *svm = to_svm(vcpu);
2295 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2298 if (unlikely(cpu != vcpu->cpu)) {
2299 svm->asid_generation = 0;
2300 mark_all_dirty(svm->vmcb);
2303 #ifdef CONFIG_X86_64
2304 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2306 savesegment(fs, svm->host.fs);
2307 savesegment(gs, svm->host.gs);
2308 svm->host.ldt = kvm_read_ldt();
2310 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2311 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2313 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2314 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2315 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2316 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2317 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2320 /* This assumes that the kernel never uses MSR_TSC_AUX */
2321 if (static_cpu_has(X86_FEATURE_RDTSCP))
2322 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2324 if (sd->current_vmcb != svm->vmcb) {
2325 sd->current_vmcb = svm->vmcb;
2326 indirect_branch_prediction_barrier();
2328 avic_vcpu_load(vcpu, cpu);
2331 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2333 struct vcpu_svm *svm = to_svm(vcpu);
2336 avic_vcpu_put(vcpu);
2338 ++vcpu->stat.host_state_reload;
2339 kvm_load_ldt(svm->host.ldt);
2340 #ifdef CONFIG_X86_64
2341 loadsegment(fs, svm->host.fs);
2342 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2343 load_gs_index(svm->host.gs);
2345 #ifdef CONFIG_X86_32_LAZY_GS
2346 loadsegment(gs, svm->host.gs);
2349 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2350 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2353 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2355 avic_set_running(vcpu, false);
2358 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2360 avic_set_running(vcpu, true);
2363 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2365 struct vcpu_svm *svm = to_svm(vcpu);
2366 unsigned long rflags = svm->vmcb->save.rflags;
2368 if (svm->nmi_singlestep) {
2369 /* Hide our flags if they were not set by the guest */
2370 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2371 rflags &= ~X86_EFLAGS_TF;
2372 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2373 rflags &= ~X86_EFLAGS_RF;
2378 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2380 if (to_svm(vcpu)->nmi_singlestep)
2381 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2384 * Any change of EFLAGS.VM is accompanied by a reload of SS
2385 * (caused by either a task switch or an inter-privilege IRET),
2386 * so we do not need to update the CPL here.
2388 to_svm(vcpu)->vmcb->save.rflags = rflags;
2391 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2394 case VCPU_EXREG_PDPTR:
2395 BUG_ON(!npt_enabled);
2396 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2403 static void svm_set_vintr(struct vcpu_svm *svm)
2405 set_intercept(svm, INTERCEPT_VINTR);
2408 static void svm_clear_vintr(struct vcpu_svm *svm)
2410 clr_intercept(svm, INTERCEPT_VINTR);
2413 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2415 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2418 case VCPU_SREG_CS: return &save->cs;
2419 case VCPU_SREG_DS: return &save->ds;
2420 case VCPU_SREG_ES: return &save->es;
2421 case VCPU_SREG_FS: return &save->fs;
2422 case VCPU_SREG_GS: return &save->gs;
2423 case VCPU_SREG_SS: return &save->ss;
2424 case VCPU_SREG_TR: return &save->tr;
2425 case VCPU_SREG_LDTR: return &save->ldtr;
2431 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2433 struct vmcb_seg *s = svm_seg(vcpu, seg);
2438 static void svm_get_segment(struct kvm_vcpu *vcpu,
2439 struct kvm_segment *var, int seg)
2441 struct vmcb_seg *s = svm_seg(vcpu, seg);
2443 var->base = s->base;
2444 var->limit = s->limit;
2445 var->selector = s->selector;
2446 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2447 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2448 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2449 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2450 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2451 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2452 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2455 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2456 * However, the SVM spec states that the G bit is not observed by the
2457 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2458 * So let's synthesize a legal G bit for all segments, this helps
2459 * running KVM nested. It also helps cross-vendor migration, because
2460 * Intel's vmentry has a check on the 'G' bit.
2462 var->g = s->limit > 0xfffff;
2465 * AMD's VMCB does not have an explicit unusable field, so emulate it
2466 * for cross vendor migration purposes by "not present"
2468 var->unusable = !var->present;
2473 * Work around a bug where the busy flag in the tr selector
2483 * The accessed bit must always be set in the segment
2484 * descriptor cache, although it can be cleared in the
2485 * descriptor, the cached bit always remains at 1. Since
2486 * Intel has a check on this, set it here to support
2487 * cross-vendor migration.
2494 * On AMD CPUs sometimes the DB bit in the segment
2495 * descriptor is left as 1, although the whole segment has
2496 * been made unusable. Clear it here to pass an Intel VMX
2497 * entry check when cross vendor migrating.
2501 /* This is symmetric with svm_set_segment() */
2502 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2507 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2509 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2514 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2516 struct vcpu_svm *svm = to_svm(vcpu);
2518 dt->size = svm->vmcb->save.idtr.limit;
2519 dt->address = svm->vmcb->save.idtr.base;
2522 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2524 struct vcpu_svm *svm = to_svm(vcpu);
2526 svm->vmcb->save.idtr.limit = dt->size;
2527 svm->vmcb->save.idtr.base = dt->address ;
2528 mark_dirty(svm->vmcb, VMCB_DT);
2531 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2533 struct vcpu_svm *svm = to_svm(vcpu);
2535 dt->size = svm->vmcb->save.gdtr.limit;
2536 dt->address = svm->vmcb->save.gdtr.base;
2539 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2541 struct vcpu_svm *svm = to_svm(vcpu);
2543 svm->vmcb->save.gdtr.limit = dt->size;
2544 svm->vmcb->save.gdtr.base = dt->address ;
2545 mark_dirty(svm->vmcb, VMCB_DT);
2548 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2552 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2556 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2560 static void update_cr0_intercept(struct vcpu_svm *svm)
2562 ulong gcr0 = svm->vcpu.arch.cr0;
2563 u64 *hcr0 = &svm->vmcb->save.cr0;
2565 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2566 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2568 mark_dirty(svm->vmcb, VMCB_CR);
2570 if (gcr0 == *hcr0) {
2571 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2572 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2574 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2575 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2579 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2581 struct vcpu_svm *svm = to_svm(vcpu);
2583 #ifdef CONFIG_X86_64
2584 if (vcpu->arch.efer & EFER_LME) {
2585 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2586 vcpu->arch.efer |= EFER_LMA;
2587 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2590 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2591 vcpu->arch.efer &= ~EFER_LMA;
2592 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2596 vcpu->arch.cr0 = cr0;
2599 cr0 |= X86_CR0_PG | X86_CR0_WP;
2602 * re-enable caching here because the QEMU bios
2603 * does not do it - this results in some delay at
2606 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2607 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2608 svm->vmcb->save.cr0 = cr0;
2609 mark_dirty(svm->vmcb, VMCB_CR);
2610 update_cr0_intercept(svm);
2613 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2615 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2616 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2618 if (cr4 & X86_CR4_VMXE)
2621 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2622 svm_flush_tlb(vcpu, true);
2624 vcpu->arch.cr4 = cr4;
2627 cr4 |= host_cr4_mce;
2628 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2629 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2633 static void svm_set_segment(struct kvm_vcpu *vcpu,
2634 struct kvm_segment *var, int seg)
2636 struct vcpu_svm *svm = to_svm(vcpu);
2637 struct vmcb_seg *s = svm_seg(vcpu, seg);
2639 s->base = var->base;
2640 s->limit = var->limit;
2641 s->selector = var->selector;
2642 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2643 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2644 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2645 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2646 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2647 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2648 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2649 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2652 * This is always accurate, except if SYSRET returned to a segment
2653 * with SS.DPL != 3. Intel does not have this quirk, and always
2654 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2655 * would entail passing the CPL to userspace and back.
2657 if (seg == VCPU_SREG_SS)
2658 /* This is symmetric with svm_get_segment() */
2659 svm->vmcb->save.cpl = (var->dpl & 3);
2661 mark_dirty(svm->vmcb, VMCB_SEG);
2664 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2666 struct vcpu_svm *svm = to_svm(vcpu);
2668 clr_exception_intercept(svm, BP_VECTOR);
2670 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2671 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2672 set_exception_intercept(svm, BP_VECTOR);
2674 vcpu->guest_debug = 0;
2677 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2679 if (sd->next_asid > sd->max_asid) {
2680 ++sd->asid_generation;
2681 sd->next_asid = sd->min_asid;
2682 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2685 svm->asid_generation = sd->asid_generation;
2686 svm->vmcb->control.asid = sd->next_asid++;
2688 mark_dirty(svm->vmcb, VMCB_ASID);
2691 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2693 return to_svm(vcpu)->vmcb->save.dr6;
2696 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2698 struct vcpu_svm *svm = to_svm(vcpu);
2700 svm->vmcb->save.dr6 = value;
2701 mark_dirty(svm->vmcb, VMCB_DR);
2704 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2706 struct vcpu_svm *svm = to_svm(vcpu);
2708 get_debugreg(vcpu->arch.db[0], 0);
2709 get_debugreg(vcpu->arch.db[1], 1);
2710 get_debugreg(vcpu->arch.db[2], 2);
2711 get_debugreg(vcpu->arch.db[3], 3);
2712 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2713 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2715 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2716 set_dr_intercepts(svm);
2719 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2721 struct vcpu_svm *svm = to_svm(vcpu);
2723 svm->vmcb->save.dr7 = value;
2724 mark_dirty(svm->vmcb, VMCB_DR);
2727 static int pf_interception(struct vcpu_svm *svm)
2729 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2730 u64 error_code = svm->vmcb->control.exit_info_1;
2732 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2733 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2734 svm->vmcb->control.insn_bytes : NULL,
2735 svm->vmcb->control.insn_len);
2738 static int npf_interception(struct vcpu_svm *svm)
2740 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2741 u64 error_code = svm->vmcb->control.exit_info_1;
2743 trace_kvm_page_fault(fault_address, error_code);
2744 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2745 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2746 svm->vmcb->control.insn_bytes : NULL,
2747 svm->vmcb->control.insn_len);
2750 static int db_interception(struct vcpu_svm *svm)
2752 struct kvm_run *kvm_run = svm->vcpu.run;
2753 struct kvm_vcpu *vcpu = &svm->vcpu;
2755 if (!(svm->vcpu.guest_debug &
2756 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2757 !svm->nmi_singlestep) {
2758 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2762 if (svm->nmi_singlestep) {
2763 disable_nmi_singlestep(svm);
2764 /* Make sure we check for pending NMIs upon entry */
2765 kvm_make_request(KVM_REQ_EVENT, vcpu);
2768 if (svm->vcpu.guest_debug &
2769 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2770 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2771 kvm_run->debug.arch.pc =
2772 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2773 kvm_run->debug.arch.exception = DB_VECTOR;
2780 static int bp_interception(struct vcpu_svm *svm)
2782 struct kvm_run *kvm_run = svm->vcpu.run;
2784 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2785 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2786 kvm_run->debug.arch.exception = BP_VECTOR;
2790 static int ud_interception(struct vcpu_svm *svm)
2792 return handle_ud(&svm->vcpu);
2795 static int ac_interception(struct vcpu_svm *svm)
2797 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2801 static int gp_interception(struct vcpu_svm *svm)
2803 struct kvm_vcpu *vcpu = &svm->vcpu;
2804 u32 error_code = svm->vmcb->control.exit_info_1;
2807 WARN_ON_ONCE(!enable_vmware_backdoor);
2809 er = kvm_emulate_instruction(vcpu,
2810 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2811 if (er == EMULATE_USER_EXIT)
2813 else if (er != EMULATE_DONE)
2814 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2818 static bool is_erratum_383(void)
2823 if (!erratum_383_found)
2826 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2830 /* Bit 62 may or may not be set for this mce */
2831 value &= ~(1ULL << 62);
2833 if (value != 0xb600000000010015ULL)
2836 /* Clear MCi_STATUS registers */
2837 for (i = 0; i < 6; ++i)
2838 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2840 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2844 value &= ~(1ULL << 2);
2845 low = lower_32_bits(value);
2846 high = upper_32_bits(value);
2848 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2851 /* Flush tlb to evict multi-match entries */
2857 static void svm_handle_mce(struct vcpu_svm *svm)
2859 if (is_erratum_383()) {
2861 * Erratum 383 triggered. Guest state is corrupt so kill the
2864 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2866 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2872 * On an #MC intercept the MCE handler is not called automatically in
2873 * the host. So do it by hand here.
2877 /* not sure if we ever come back to this point */
2882 static int mc_interception(struct vcpu_svm *svm)
2887 static int shutdown_interception(struct vcpu_svm *svm)
2889 struct kvm_run *kvm_run = svm->vcpu.run;
2892 * VMCB is undefined after a SHUTDOWN intercept
2893 * so reinitialize it.
2895 clear_page(svm->vmcb);
2898 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2902 static int io_interception(struct vcpu_svm *svm)
2904 struct kvm_vcpu *vcpu = &svm->vcpu;
2905 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2906 int size, in, string;
2909 ++svm->vcpu.stat.io_exits;
2910 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2911 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2913 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2915 port = io_info >> 16;
2916 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2917 svm->next_rip = svm->vmcb->control.exit_info_2;
2919 return kvm_fast_pio(&svm->vcpu, size, port, in);
2922 static int nmi_interception(struct vcpu_svm *svm)
2927 static int intr_interception(struct vcpu_svm *svm)
2929 ++svm->vcpu.stat.irq_exits;
2933 static int nop_on_interception(struct vcpu_svm *svm)
2938 static int halt_interception(struct vcpu_svm *svm)
2940 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2941 return kvm_emulate_halt(&svm->vcpu);
2944 static int vmmcall_interception(struct vcpu_svm *svm)
2946 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2947 return kvm_emulate_hypercall(&svm->vcpu);
2950 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2952 struct vcpu_svm *svm = to_svm(vcpu);
2954 return svm->nested.nested_cr3;
2957 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2959 struct vcpu_svm *svm = to_svm(vcpu);
2960 u64 cr3 = svm->nested.nested_cr3;
2964 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2965 offset_in_page(cr3) + index * 8, 8);
2971 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2974 struct vcpu_svm *svm = to_svm(vcpu);
2976 svm->vmcb->control.nested_cr3 = __sme_set(root);
2977 mark_dirty(svm->vmcb, VMCB_NPT);
2980 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2981 struct x86_exception *fault)
2983 struct vcpu_svm *svm = to_svm(vcpu);
2985 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2987 * TODO: track the cause of the nested page fault, and
2988 * correctly fill in the high bits of exit_info_1.
2990 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2991 svm->vmcb->control.exit_code_hi = 0;
2992 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2993 svm->vmcb->control.exit_info_2 = fault->address;
2996 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2997 svm->vmcb->control.exit_info_1 |= fault->error_code;
3000 * The present bit is always zero for page structure faults on real
3003 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
3004 svm->vmcb->control.exit_info_1 &= ~1;
3006 nested_svm_vmexit(svm);
3009 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
3011 WARN_ON(mmu_is_nested(vcpu));
3012 kvm_init_shadow_mmu(vcpu);
3013 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
3014 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
3015 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
3016 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
3017 vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
3018 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
3019 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
3022 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
3024 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
3027 static int nested_svm_check_permissions(struct vcpu_svm *svm)
3029 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
3030 !is_paging(&svm->vcpu)) {
3031 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3035 if (svm->vmcb->save.cpl) {
3036 kvm_inject_gp(&svm->vcpu, 0);
3043 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
3044 bool has_error_code, u32 error_code)
3048 if (!is_guest_mode(&svm->vcpu))
3051 vmexit = nested_svm_intercept(svm);
3052 if (vmexit != NESTED_EXIT_DONE)
3055 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3056 svm->vmcb->control.exit_code_hi = 0;
3057 svm->vmcb->control.exit_info_1 = error_code;
3060 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
3061 * The fix is to add the ancillary datum (CR2 or DR6) to structs
3062 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
3063 * written only when inject_pending_event runs (DR6 would written here
3064 * too). This should be conditional on a new capability---if the
3065 * capability is disabled, kvm_multiple_exception would write the
3066 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
3068 if (svm->vcpu.arch.exception.nested_apf)
3069 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3071 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3073 svm->nested.exit_required = true;
3077 /* This function returns true if it is save to enable the irq window */
3078 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3080 if (!is_guest_mode(&svm->vcpu))
3083 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3086 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3090 * if vmexit was already requested (by intercepted exception
3091 * for instance) do not overwrite it with "external interrupt"
3094 if (svm->nested.exit_required)
3097 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3098 svm->vmcb->control.exit_info_1 = 0;
3099 svm->vmcb->control.exit_info_2 = 0;
3101 if (svm->nested.intercept & 1ULL) {
3103 * The #vmexit can't be emulated here directly because this
3104 * code path runs with irqs and preemption disabled. A
3105 * #vmexit emulation might sleep. Only signal request for
3108 svm->nested.exit_required = true;
3109 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3116 /* This function returns true if it is save to enable the nmi window */
3117 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3119 if (!is_guest_mode(&svm->vcpu))
3122 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3125 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3126 svm->nested.exit_required = true;
3131 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3137 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3138 if (is_error_page(page))
3146 kvm_inject_gp(&svm->vcpu, 0);
3151 static void nested_svm_unmap(struct page *page)
3154 kvm_release_page_dirty(page);
3157 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3159 unsigned port, size, iopm_len;
3164 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3165 return NESTED_EXIT_HOST;
3167 port = svm->vmcb->control.exit_info_1 >> 16;
3168 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3169 SVM_IOIO_SIZE_SHIFT;
3170 gpa = svm->nested.vmcb_iopm + (port / 8);
3171 start_bit = port % 8;
3172 iopm_len = (start_bit + size > 8) ? 2 : 1;
3173 mask = (0xf >> (4 - size)) << start_bit;
3176 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3177 return NESTED_EXIT_DONE;
3179 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3182 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3184 u32 offset, msr, value;
3187 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3188 return NESTED_EXIT_HOST;
3190 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3191 offset = svm_msrpm_offset(msr);
3192 write = svm->vmcb->control.exit_info_1 & 1;
3193 mask = 1 << ((2 * (msr & 0xf)) + write);
3195 if (offset == MSR_INVALID)
3196 return NESTED_EXIT_DONE;
3198 /* Offset is in 32 bit units but need in 8 bit units */
3201 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3202 return NESTED_EXIT_DONE;
3204 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3207 /* DB exceptions for our internal use must not cause vmexit */
3208 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3212 /* if we're not singlestepping, it's not ours */
3213 if (!svm->nmi_singlestep)
3214 return NESTED_EXIT_DONE;
3216 /* if it's not a singlestep exception, it's not ours */
3217 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3218 return NESTED_EXIT_DONE;
3219 if (!(dr6 & DR6_BS))
3220 return NESTED_EXIT_DONE;
3222 /* if the guest is singlestepping, it should get the vmexit */
3223 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3224 disable_nmi_singlestep(svm);
3225 return NESTED_EXIT_DONE;
3228 /* it's ours, the nested hypervisor must not see this one */
3229 return NESTED_EXIT_HOST;
3232 static int nested_svm_exit_special(struct vcpu_svm *svm)
3234 u32 exit_code = svm->vmcb->control.exit_code;
3236 switch (exit_code) {
3239 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3240 return NESTED_EXIT_HOST;
3242 /* For now we are always handling NPFs when using them */
3244 return NESTED_EXIT_HOST;
3246 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3247 /* Trap async PF even if not shadowing */
3248 if (!npt_enabled || svm->vcpu.arch.apf.host_apf_reason)
3249 return NESTED_EXIT_HOST;
3255 return NESTED_EXIT_CONTINUE;
3259 * If this function returns true, this #vmexit was already handled
3261 static int nested_svm_intercept(struct vcpu_svm *svm)
3263 u32 exit_code = svm->vmcb->control.exit_code;
3264 int vmexit = NESTED_EXIT_HOST;
3266 switch (exit_code) {
3268 vmexit = nested_svm_exit_handled_msr(svm);
3271 vmexit = nested_svm_intercept_ioio(svm);
3273 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3274 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3275 if (svm->nested.intercept_cr & bit)
3276 vmexit = NESTED_EXIT_DONE;
3279 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3280 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3281 if (svm->nested.intercept_dr & bit)
3282 vmexit = NESTED_EXIT_DONE;
3285 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3286 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3287 if (svm->nested.intercept_exceptions & excp_bits) {
3288 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3289 vmexit = nested_svm_intercept_db(svm);
3291 vmexit = NESTED_EXIT_DONE;
3293 /* async page fault always cause vmexit */
3294 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3295 svm->vcpu.arch.exception.nested_apf != 0)
3296 vmexit = NESTED_EXIT_DONE;
3299 case SVM_EXIT_ERR: {
3300 vmexit = NESTED_EXIT_DONE;
3304 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3305 if (svm->nested.intercept & exit_bits)
3306 vmexit = NESTED_EXIT_DONE;
3313 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3317 vmexit = nested_svm_intercept(svm);
3319 if (vmexit == NESTED_EXIT_DONE)
3320 nested_svm_vmexit(svm);
3325 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3327 struct vmcb_control_area *dst = &dst_vmcb->control;
3328 struct vmcb_control_area *from = &from_vmcb->control;
3330 dst->intercept_cr = from->intercept_cr;
3331 dst->intercept_dr = from->intercept_dr;
3332 dst->intercept_exceptions = from->intercept_exceptions;
3333 dst->intercept = from->intercept;
3334 dst->iopm_base_pa = from->iopm_base_pa;
3335 dst->msrpm_base_pa = from->msrpm_base_pa;
3336 dst->tsc_offset = from->tsc_offset;
3337 /* asid not copied, it is handled manually for svm->vmcb. */
3338 dst->tlb_ctl = from->tlb_ctl;
3339 dst->int_ctl = from->int_ctl;
3340 dst->int_vector = from->int_vector;
3341 dst->int_state = from->int_state;
3342 dst->exit_code = from->exit_code;
3343 dst->exit_code_hi = from->exit_code_hi;
3344 dst->exit_info_1 = from->exit_info_1;
3345 dst->exit_info_2 = from->exit_info_2;
3346 dst->exit_int_info = from->exit_int_info;
3347 dst->exit_int_info_err = from->exit_int_info_err;
3348 dst->nested_ctl = from->nested_ctl;
3349 dst->event_inj = from->event_inj;
3350 dst->event_inj_err = from->event_inj_err;
3351 dst->nested_cr3 = from->nested_cr3;
3352 dst->virt_ext = from->virt_ext;
3355 static int nested_svm_vmexit(struct vcpu_svm *svm)
3357 struct vmcb *nested_vmcb;
3358 struct vmcb *hsave = svm->nested.hsave;
3359 struct vmcb *vmcb = svm->vmcb;
3362 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3363 vmcb->control.exit_info_1,
3364 vmcb->control.exit_info_2,
3365 vmcb->control.exit_int_info,
3366 vmcb->control.exit_int_info_err,
3369 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3373 /* Exit Guest-Mode */
3374 leave_guest_mode(&svm->vcpu);
3375 svm->nested.vmcb = 0;
3377 /* Give the current vmcb to the guest */
3380 nested_vmcb->save.es = vmcb->save.es;
3381 nested_vmcb->save.cs = vmcb->save.cs;
3382 nested_vmcb->save.ss = vmcb->save.ss;
3383 nested_vmcb->save.ds = vmcb->save.ds;
3384 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3385 nested_vmcb->save.idtr = vmcb->save.idtr;
3386 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3387 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3388 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3389 nested_vmcb->save.cr2 = vmcb->save.cr2;
3390 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3391 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3392 nested_vmcb->save.rip = vmcb->save.rip;
3393 nested_vmcb->save.rsp = vmcb->save.rsp;
3394 nested_vmcb->save.rax = vmcb->save.rax;
3395 nested_vmcb->save.dr7 = vmcb->save.dr7;
3396 nested_vmcb->save.dr6 = vmcb->save.dr6;
3397 nested_vmcb->save.cpl = vmcb->save.cpl;
3399 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3400 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3401 nested_vmcb->control.int_state = vmcb->control.int_state;
3402 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3403 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3404 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3405 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3406 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3407 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3409 if (svm->nrips_enabled)
3410 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3413 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3414 * to make sure that we do not lose injected events. So check event_inj
3415 * here and copy it to exit_int_info if it is valid.
3416 * Exit_int_info and event_inj can't be both valid because the case
3417 * below only happens on a VMRUN instruction intercept which has
3418 * no valid exit_int_info set.
3420 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3421 struct vmcb_control_area *nc = &nested_vmcb->control;
3423 nc->exit_int_info = vmcb->control.event_inj;
3424 nc->exit_int_info_err = vmcb->control.event_inj_err;
3427 nested_vmcb->control.tlb_ctl = 0;
3428 nested_vmcb->control.event_inj = 0;
3429 nested_vmcb->control.event_inj_err = 0;
3431 /* We always set V_INTR_MASKING and remember the old value in hflags */
3432 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3433 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3435 /* Restore the original control entries */
3436 copy_vmcb_control_area(vmcb, hsave);
3438 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3439 kvm_clear_exception_queue(&svm->vcpu);
3440 kvm_clear_interrupt_queue(&svm->vcpu);
3442 svm->nested.nested_cr3 = 0;
3444 /* Restore selected save entries */
3445 svm->vmcb->save.es = hsave->save.es;
3446 svm->vmcb->save.cs = hsave->save.cs;
3447 svm->vmcb->save.ss = hsave->save.ss;
3448 svm->vmcb->save.ds = hsave->save.ds;
3449 svm->vmcb->save.gdtr = hsave->save.gdtr;
3450 svm->vmcb->save.idtr = hsave->save.idtr;
3451 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3452 svm_set_efer(&svm->vcpu, hsave->save.efer);
3453 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3454 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3456 svm->vmcb->save.cr3 = hsave->save.cr3;
3457 svm->vcpu.arch.cr3 = hsave->save.cr3;
3459 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3461 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3462 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3463 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3464 svm->vmcb->save.dr7 = 0;
3465 svm->vmcb->save.cpl = 0;
3466 svm->vmcb->control.exit_int_info = 0;
3468 mark_all_dirty(svm->vmcb);
3470 nested_svm_unmap(page);
3472 nested_svm_uninit_mmu_context(&svm->vcpu);
3473 kvm_mmu_reset_context(&svm->vcpu);
3474 kvm_mmu_load(&svm->vcpu);
3477 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3478 * doesn't end up in L1.
3480 svm->vcpu.arch.nmi_injected = false;
3481 kvm_clear_exception_queue(&svm->vcpu);
3482 kvm_clear_interrupt_queue(&svm->vcpu);
3487 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3490 * This function merges the msr permission bitmaps of kvm and the
3491 * nested vmcb. It is optimized in that it only merges the parts where
3492 * the kvm msr permission bitmap may contain zero bits
3496 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3499 for (i = 0; i < MSRPM_OFFSETS; i++) {
3503 if (msrpm_offsets[i] == 0xffffffff)
3506 p = msrpm_offsets[i];
3507 offset = svm->nested.vmcb_msrpm + (p * 4);
3509 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3512 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3515 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3520 static bool nested_vmcb_checks(struct vmcb *vmcb)
3522 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3525 if (vmcb->control.asid == 0)
3528 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3535 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3536 struct vmcb *nested_vmcb, struct page *page)
3538 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3539 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3541 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3543 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3544 kvm_mmu_unload(&svm->vcpu);
3545 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3546 nested_svm_init_mmu_context(&svm->vcpu);
3549 /* Load the nested guest state */
3550 svm->vmcb->save.es = nested_vmcb->save.es;
3551 svm->vmcb->save.cs = nested_vmcb->save.cs;
3552 svm->vmcb->save.ss = nested_vmcb->save.ss;
3553 svm->vmcb->save.ds = nested_vmcb->save.ds;
3554 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3555 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3556 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3557 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3558 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3559 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3561 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3562 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3564 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3566 /* Guest paging mode is active - reset mmu */
3567 kvm_mmu_reset_context(&svm->vcpu);
3569 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3570 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3571 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3572 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3574 /* In case we don't even reach vcpu_run, the fields are not updated */
3575 svm->vmcb->save.rax = nested_vmcb->save.rax;
3576 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3577 svm->vmcb->save.rip = nested_vmcb->save.rip;
3578 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3579 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3580 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3582 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3583 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3585 /* cache intercepts */
3586 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3587 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3588 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3589 svm->nested.intercept = nested_vmcb->control.intercept;
3591 svm_flush_tlb(&svm->vcpu, true);
3593 svm->vmcb->control.int_ctl &=
3594 V_INTR_MASKING_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK;
3596 svm->vmcb->control.int_ctl |= nested_vmcb->control.int_ctl &
3597 (V_TPR_MASK | V_IRQ_INJECTION_BITS_MASK);
3599 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3600 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3602 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3604 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3605 /* We only want the cr8 intercept bits of the guest */
3606 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3607 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3610 /* We don't want to see VMMCALLs from a nested guest */
3611 clr_intercept(svm, INTERCEPT_VMMCALL);
3613 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3614 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3616 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3617 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3618 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3619 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3620 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3622 nested_svm_unmap(page);
3624 /* Enter Guest-Mode */
3625 enter_guest_mode(&svm->vcpu);
3628 * Merge guest and host intercepts - must be called with vcpu in
3629 * guest-mode to take affect here
3631 recalc_intercepts(svm);
3633 svm->nested.vmcb = vmcb_gpa;
3637 mark_all_dirty(svm->vmcb);
3640 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3642 struct vmcb *nested_vmcb;
3643 struct vmcb *hsave = svm->nested.hsave;
3644 struct vmcb *vmcb = svm->vmcb;
3648 vmcb_gpa = svm->vmcb->save.rax;
3650 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3654 if (!nested_vmcb_checks(nested_vmcb)) {
3655 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3656 nested_vmcb->control.exit_code_hi = 0;
3657 nested_vmcb->control.exit_info_1 = 0;
3658 nested_vmcb->control.exit_info_2 = 0;
3660 nested_svm_unmap(page);
3665 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3666 nested_vmcb->save.rip,
3667 nested_vmcb->control.int_ctl,
3668 nested_vmcb->control.event_inj,
3669 nested_vmcb->control.nested_ctl);
3671 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3672 nested_vmcb->control.intercept_cr >> 16,
3673 nested_vmcb->control.intercept_exceptions,
3674 nested_vmcb->control.intercept);
3676 /* Clear internal status */
3677 kvm_clear_exception_queue(&svm->vcpu);
3678 kvm_clear_interrupt_queue(&svm->vcpu);
3681 * Save the old vmcb, so we don't need to pick what we save, but can
3682 * restore everything when a VMEXIT occurs
3684 hsave->save.es = vmcb->save.es;
3685 hsave->save.cs = vmcb->save.cs;
3686 hsave->save.ss = vmcb->save.ss;
3687 hsave->save.ds = vmcb->save.ds;
3688 hsave->save.gdtr = vmcb->save.gdtr;
3689 hsave->save.idtr = vmcb->save.idtr;
3690 hsave->save.efer = svm->vcpu.arch.efer;
3691 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3692 hsave->save.cr4 = svm->vcpu.arch.cr4;
3693 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3694 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3695 hsave->save.rsp = vmcb->save.rsp;
3696 hsave->save.rax = vmcb->save.rax;
3698 hsave->save.cr3 = vmcb->save.cr3;
3700 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3702 copy_vmcb_control_area(hsave, vmcb);
3704 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3709 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3711 to_vmcb->save.fs = from_vmcb->save.fs;
3712 to_vmcb->save.gs = from_vmcb->save.gs;
3713 to_vmcb->save.tr = from_vmcb->save.tr;
3714 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3715 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3716 to_vmcb->save.star = from_vmcb->save.star;
3717 to_vmcb->save.lstar = from_vmcb->save.lstar;
3718 to_vmcb->save.cstar = from_vmcb->save.cstar;
3719 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3720 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3721 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3722 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3725 static int vmload_interception(struct vcpu_svm *svm)
3727 struct vmcb *nested_vmcb;
3731 if (nested_svm_check_permissions(svm))
3734 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3738 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3739 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3741 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3742 nested_svm_unmap(page);
3747 static int vmsave_interception(struct vcpu_svm *svm)
3749 struct vmcb *nested_vmcb;
3753 if (nested_svm_check_permissions(svm))
3756 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3760 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3761 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3763 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3764 nested_svm_unmap(page);
3769 static int vmrun_interception(struct vcpu_svm *svm)
3771 if (nested_svm_check_permissions(svm))
3774 /* Save rip after vmrun instruction */
3775 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3777 if (!nested_svm_vmrun(svm))
3780 if (!nested_svm_vmrun_msrpm(svm))
3787 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3788 svm->vmcb->control.exit_code_hi = 0;
3789 svm->vmcb->control.exit_info_1 = 0;
3790 svm->vmcb->control.exit_info_2 = 0;
3792 nested_svm_vmexit(svm);
3797 static int stgi_interception(struct vcpu_svm *svm)
3801 if (nested_svm_check_permissions(svm))
3805 * If VGIF is enabled, the STGI intercept is only added to
3806 * detect the opening of the SMI/NMI window; remove it now.
3808 if (vgif_enabled(svm))
3809 clr_intercept(svm, INTERCEPT_STGI);
3811 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3812 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3813 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3820 static int clgi_interception(struct vcpu_svm *svm)
3824 if (nested_svm_check_permissions(svm))
3827 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3828 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3832 /* After a CLGI no interrupts should come */
3833 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3834 svm_clear_vintr(svm);
3835 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3836 mark_dirty(svm->vmcb, VMCB_INTR);
3842 static int invlpga_interception(struct vcpu_svm *svm)
3844 struct kvm_vcpu *vcpu = &svm->vcpu;
3846 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3847 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3849 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3850 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3852 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3853 return kvm_skip_emulated_instruction(&svm->vcpu);
3856 static int skinit_interception(struct vcpu_svm *svm)
3858 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3860 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3864 static int wbinvd_interception(struct vcpu_svm *svm)
3866 return kvm_emulate_wbinvd(&svm->vcpu);
3869 static int xsetbv_interception(struct vcpu_svm *svm)
3871 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3872 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3874 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3875 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3876 return kvm_skip_emulated_instruction(&svm->vcpu);
3882 static int task_switch_interception(struct vcpu_svm *svm)
3886 int int_type = svm->vmcb->control.exit_int_info &
3887 SVM_EXITINTINFO_TYPE_MASK;
3888 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3890 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3892 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3893 bool has_error_code = false;
3896 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3898 if (svm->vmcb->control.exit_info_2 &
3899 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3900 reason = TASK_SWITCH_IRET;
3901 else if (svm->vmcb->control.exit_info_2 &
3902 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3903 reason = TASK_SWITCH_JMP;
3905 reason = TASK_SWITCH_GATE;
3907 reason = TASK_SWITCH_CALL;
3909 if (reason == TASK_SWITCH_GATE) {
3911 case SVM_EXITINTINFO_TYPE_NMI:
3912 svm->vcpu.arch.nmi_injected = false;
3914 case SVM_EXITINTINFO_TYPE_EXEPT:
3915 if (svm->vmcb->control.exit_info_2 &
3916 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3917 has_error_code = true;
3919 (u32)svm->vmcb->control.exit_info_2;
3921 kvm_clear_exception_queue(&svm->vcpu);
3923 case SVM_EXITINTINFO_TYPE_INTR:
3924 kvm_clear_interrupt_queue(&svm->vcpu);
3931 if (reason != TASK_SWITCH_GATE ||
3932 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3933 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3934 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3935 skip_emulated_instruction(&svm->vcpu);
3937 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3940 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3941 has_error_code, error_code) == EMULATE_FAIL) {
3942 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3943 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3944 svm->vcpu.run->internal.ndata = 0;
3950 static int cpuid_interception(struct vcpu_svm *svm)
3952 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3953 return kvm_emulate_cpuid(&svm->vcpu);
3956 static int iret_interception(struct vcpu_svm *svm)
3958 ++svm->vcpu.stat.nmi_window_exits;
3959 clr_intercept(svm, INTERCEPT_IRET);
3960 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3961 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3962 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3966 static int invd_interception(struct vcpu_svm *svm)
3968 /* Treat an INVD instruction as a NOP and just skip it. */
3969 return kvm_skip_emulated_instruction(&svm->vcpu);
3972 static int invlpg_interception(struct vcpu_svm *svm)
3974 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3975 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3977 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3978 return kvm_skip_emulated_instruction(&svm->vcpu);
3981 static int emulate_on_interception(struct vcpu_svm *svm)
3983 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3986 static int rsm_interception(struct vcpu_svm *svm)
3988 return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3989 rsm_ins_bytes, 2) == EMULATE_DONE;
3992 static int rdpmc_interception(struct vcpu_svm *svm)
3996 if (!static_cpu_has(X86_FEATURE_NRIPS))
3997 return emulate_on_interception(svm);
3999 err = kvm_rdpmc(&svm->vcpu);
4000 return kvm_complete_insn_gp(&svm->vcpu, err);
4003 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
4006 unsigned long cr0 = svm->vcpu.arch.cr0;
4010 intercept = svm->nested.intercept;
4012 if (!is_guest_mode(&svm->vcpu) ||
4013 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
4016 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
4017 val &= ~SVM_CR0_SELECTIVE_MASK;
4020 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4021 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
4027 #define CR_VALID (1ULL << 63)
4029 static int cr_interception(struct vcpu_svm *svm)
4035 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
4036 return emulate_on_interception(svm);
4038 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
4039 return emulate_on_interception(svm);
4041 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4042 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
4043 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
4045 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
4048 if (cr >= 16) { /* mov to cr */
4050 val = kvm_register_readl(&svm->vcpu, reg);
4053 if (!check_selective_cr0_intercepted(svm, val))
4054 err = kvm_set_cr0(&svm->vcpu, val);
4060 err = kvm_set_cr3(&svm->vcpu, val);
4063 err = kvm_set_cr4(&svm->vcpu, val);
4066 err = kvm_set_cr8(&svm->vcpu, val);
4069 WARN(1, "unhandled write to CR%d", cr);
4070 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4073 } else { /* mov from cr */
4076 val = kvm_read_cr0(&svm->vcpu);
4079 val = svm->vcpu.arch.cr2;
4082 val = kvm_read_cr3(&svm->vcpu);
4085 val = kvm_read_cr4(&svm->vcpu);
4088 val = kvm_get_cr8(&svm->vcpu);
4091 WARN(1, "unhandled read from CR%d", cr);
4092 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4095 kvm_register_writel(&svm->vcpu, reg, val);
4097 return kvm_complete_insn_gp(&svm->vcpu, err);
4100 static int dr_interception(struct vcpu_svm *svm)
4105 if (svm->vcpu.guest_debug == 0) {
4107 * No more DR vmexits; force a reload of the debug registers
4108 * and reenter on this instruction. The next vmexit will
4109 * retrieve the full state of the debug registers.
4111 clr_dr_intercepts(svm);
4112 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4116 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4117 return emulate_on_interception(svm);
4119 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4120 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4122 if (dr >= 16) { /* mov to DRn */
4123 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4125 val = kvm_register_readl(&svm->vcpu, reg);
4126 kvm_set_dr(&svm->vcpu, dr - 16, val);
4128 if (!kvm_require_dr(&svm->vcpu, dr))
4130 kvm_get_dr(&svm->vcpu, dr, &val);
4131 kvm_register_writel(&svm->vcpu, reg, val);
4134 return kvm_skip_emulated_instruction(&svm->vcpu);
4137 static int cr8_write_interception(struct vcpu_svm *svm)
4139 struct kvm_run *kvm_run = svm->vcpu.run;
4142 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4143 /* instruction emulation calls kvm_set_cr8() */
4144 r = cr_interception(svm);
4145 if (lapic_in_kernel(&svm->vcpu))
4147 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4149 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4153 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4157 switch (msr->index) {
4158 case MSR_AMD64_DE_CFG:
4159 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
4160 msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE;
4169 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4171 struct vcpu_svm *svm = to_svm(vcpu);
4173 switch (msr_info->index) {
4175 msr_info->data = svm->vmcb->save.star;
4177 #ifdef CONFIG_X86_64
4179 msr_info->data = svm->vmcb->save.lstar;
4182 msr_info->data = svm->vmcb->save.cstar;
4184 case MSR_KERNEL_GS_BASE:
4185 msr_info->data = svm->vmcb->save.kernel_gs_base;
4187 case MSR_SYSCALL_MASK:
4188 msr_info->data = svm->vmcb->save.sfmask;
4191 case MSR_IA32_SYSENTER_CS:
4192 msr_info->data = svm->vmcb->save.sysenter_cs;
4194 case MSR_IA32_SYSENTER_EIP:
4195 msr_info->data = svm->sysenter_eip;
4197 case MSR_IA32_SYSENTER_ESP:
4198 msr_info->data = svm->sysenter_esp;
4201 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4203 msr_info->data = svm->tsc_aux;
4206 * Nobody will change the following 5 values in the VMCB so we can
4207 * safely return them on rdmsr. They will always be 0 until LBRV is
4210 case MSR_IA32_DEBUGCTLMSR:
4211 msr_info->data = svm->vmcb->save.dbgctl;
4213 case MSR_IA32_LASTBRANCHFROMIP:
4214 msr_info->data = svm->vmcb->save.br_from;
4216 case MSR_IA32_LASTBRANCHTOIP:
4217 msr_info->data = svm->vmcb->save.br_to;
4219 case MSR_IA32_LASTINTFROMIP:
4220 msr_info->data = svm->vmcb->save.last_excp_from;
4222 case MSR_IA32_LASTINTTOIP:
4223 msr_info->data = svm->vmcb->save.last_excp_to;
4225 case MSR_VM_HSAVE_PA:
4226 msr_info->data = svm->nested.hsave_msr;
4229 msr_info->data = svm->nested.vm_cr_msr;
4231 case MSR_IA32_SPEC_CTRL:
4232 if (!msr_info->host_initiated &&
4233 !guest_has_spec_ctrl_msr(vcpu))
4236 msr_info->data = svm->spec_ctrl;
4238 case MSR_AMD64_VIRT_SPEC_CTRL:
4239 if (!msr_info->host_initiated &&
4240 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4243 msr_info->data = svm->virt_spec_ctrl;
4245 case MSR_F15H_IC_CFG: {
4249 family = guest_cpuid_family(vcpu);
4250 model = guest_cpuid_model(vcpu);
4252 if (family < 0 || model < 0)
4253 return kvm_get_msr_common(vcpu, msr_info);
4257 if (family == 0x15 &&
4258 (model >= 0x2 && model < 0x20))
4259 msr_info->data = 0x1E;
4262 case MSR_AMD64_DE_CFG:
4263 msr_info->data = svm->msr_decfg;
4266 return kvm_get_msr_common(vcpu, msr_info);
4271 static int rdmsr_interception(struct vcpu_svm *svm)
4273 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4274 struct msr_data msr_info;
4276 msr_info.index = ecx;
4277 msr_info.host_initiated = false;
4278 if (svm_get_msr(&svm->vcpu, &msr_info)) {
4279 trace_kvm_msr_read_ex(ecx);
4280 kvm_inject_gp(&svm->vcpu, 0);
4283 trace_kvm_msr_read(ecx, msr_info.data);
4285 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4286 msr_info.data & 0xffffffff);
4287 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4288 msr_info.data >> 32);
4289 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4290 return kvm_skip_emulated_instruction(&svm->vcpu);
4294 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4296 struct vcpu_svm *svm = to_svm(vcpu);
4297 int svm_dis, chg_mask;
4299 if (data & ~SVM_VM_CR_VALID_MASK)
4302 chg_mask = SVM_VM_CR_VALID_MASK;
4304 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4305 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4307 svm->nested.vm_cr_msr &= ~chg_mask;
4308 svm->nested.vm_cr_msr |= (data & chg_mask);
4310 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4312 /* check for svm_disable while efer.svme is set */
4313 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4319 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4321 struct vcpu_svm *svm = to_svm(vcpu);
4323 u32 ecx = msr->index;
4324 u64 data = msr->data;
4326 case MSR_IA32_CR_PAT:
4327 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4329 vcpu->arch.pat = data;
4330 svm->vmcb->save.g_pat = data;
4331 mark_dirty(svm->vmcb, VMCB_NPT);
4333 case MSR_IA32_SPEC_CTRL:
4334 if (!msr->host_initiated &&
4335 !guest_has_spec_ctrl_msr(vcpu))
4338 /* The STIBP bit doesn't fault even if it's not advertised */
4339 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4342 svm->spec_ctrl = data;
4349 * When it's written (to non-zero) for the first time, pass
4353 * The handling of the MSR bitmap for L2 guests is done in
4354 * nested_svm_vmrun_msrpm.
4355 * We update the L1 MSR bit as well since it will end up
4356 * touching the MSR anyway now.
4358 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4360 case MSR_IA32_PRED_CMD:
4361 if (!msr->host_initiated &&
4362 !guest_has_pred_cmd_msr(vcpu))
4365 if (data & ~PRED_CMD_IBPB)
4370 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4371 if (is_guest_mode(vcpu))
4373 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4375 case MSR_AMD64_VIRT_SPEC_CTRL:
4376 if (!msr->host_initiated &&
4377 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4380 if (data & ~SPEC_CTRL_SSBD)
4383 svm->virt_spec_ctrl = data;
4386 svm->vmcb->save.star = data;
4388 #ifdef CONFIG_X86_64
4390 svm->vmcb->save.lstar = data;
4393 svm->vmcb->save.cstar = data;
4395 case MSR_KERNEL_GS_BASE:
4396 svm->vmcb->save.kernel_gs_base = data;
4398 case MSR_SYSCALL_MASK:
4399 svm->vmcb->save.sfmask = data;
4402 case MSR_IA32_SYSENTER_CS:
4403 svm->vmcb->save.sysenter_cs = data;
4405 case MSR_IA32_SYSENTER_EIP:
4406 svm->sysenter_eip = data;
4407 svm->vmcb->save.sysenter_eip = data;
4409 case MSR_IA32_SYSENTER_ESP:
4410 svm->sysenter_esp = data;
4411 svm->vmcb->save.sysenter_esp = data;
4414 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4418 * This is rare, so we update the MSR here instead of using
4419 * direct_access_msrs. Doing that would require a rdmsr in
4422 svm->tsc_aux = data;
4423 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4425 case MSR_IA32_DEBUGCTLMSR:
4426 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4427 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4431 if (data & DEBUGCTL_RESERVED_BITS)
4434 svm->vmcb->save.dbgctl = data;
4435 mark_dirty(svm->vmcb, VMCB_LBR);
4436 if (data & (1ULL<<0))
4437 svm_enable_lbrv(svm);
4439 svm_disable_lbrv(svm);
4441 case MSR_VM_HSAVE_PA:
4442 svm->nested.hsave_msr = data;
4445 return svm_set_vm_cr(vcpu, data);
4447 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4449 case MSR_AMD64_DE_CFG: {
4450 struct kvm_msr_entry msr_entry;
4452 msr_entry.index = msr->index;
4453 if (svm_get_msr_feature(&msr_entry))
4456 /* Check the supported bits */
4457 if (data & ~msr_entry.data)
4460 /* Don't allow the guest to change a bit, #GP */
4461 if (!msr->host_initiated && (data ^ msr_entry.data))
4464 svm->msr_decfg = data;
4467 case MSR_IA32_APICBASE:
4468 if (kvm_vcpu_apicv_active(vcpu))
4469 avic_update_vapic_bar(to_svm(vcpu), data);
4470 /* Follow through */
4472 return kvm_set_msr_common(vcpu, msr);
4477 static int wrmsr_interception(struct vcpu_svm *svm)
4479 struct msr_data msr;
4480 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4481 u64 data = kvm_read_edx_eax(&svm->vcpu);
4485 msr.host_initiated = false;
4487 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4488 if (kvm_set_msr(&svm->vcpu, &msr)) {
4489 trace_kvm_msr_write_ex(ecx, data);
4490 kvm_inject_gp(&svm->vcpu, 0);
4493 trace_kvm_msr_write(ecx, data);
4494 return kvm_skip_emulated_instruction(&svm->vcpu);
4498 static int msr_interception(struct vcpu_svm *svm)
4500 if (svm->vmcb->control.exit_info_1)
4501 return wrmsr_interception(svm);
4503 return rdmsr_interception(svm);
4506 static int interrupt_window_interception(struct vcpu_svm *svm)
4508 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4509 svm_clear_vintr(svm);
4510 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4511 mark_dirty(svm->vmcb, VMCB_INTR);
4512 ++svm->vcpu.stat.irq_window_exits;
4516 static int pause_interception(struct vcpu_svm *svm)
4518 struct kvm_vcpu *vcpu = &svm->vcpu;
4519 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4521 if (pause_filter_thresh)
4522 grow_ple_window(vcpu);
4524 kvm_vcpu_on_spin(vcpu, in_kernel);
4528 static int nop_interception(struct vcpu_svm *svm)
4530 return kvm_skip_emulated_instruction(&(svm->vcpu));
4533 static int monitor_interception(struct vcpu_svm *svm)
4535 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4536 return nop_interception(svm);
4539 static int mwait_interception(struct vcpu_svm *svm)
4541 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4542 return nop_interception(svm);
4545 enum avic_ipi_failure_cause {
4546 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4547 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4548 AVIC_IPI_FAILURE_INVALID_TARGET,
4549 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4552 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4554 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4555 u32 icrl = svm->vmcb->control.exit_info_1;
4556 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4557 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4558 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4560 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4563 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4565 * AVIC hardware handles the generation of
4566 * IPIs when the specified Message Type is Fixed
4567 * (also known as fixed delivery mode) and
4568 * the Trigger Mode is edge-triggered. The hardware
4569 * also supports self and broadcast delivery modes
4570 * specified via the Destination Shorthand(DSH)
4571 * field of the ICRL. Logical and physical APIC ID
4572 * formats are supported. All other IPI types cause
4573 * a #VMEXIT, which needs to emulated.
4575 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4576 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4578 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4580 struct kvm_vcpu *vcpu;
4581 struct kvm *kvm = svm->vcpu.kvm;
4582 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4585 * At this point, we expect that the AVIC HW has already
4586 * set the appropriate IRR bits on the valid target
4587 * vcpus. So, we just need to kick the appropriate vcpu.
4589 kvm_for_each_vcpu(i, vcpu, kvm) {
4590 bool m = kvm_apic_match_dest(vcpu, apic,
4591 icrl & KVM_APIC_SHORT_MASK,
4592 GET_APIC_DEST_FIELD(icrh),
4593 icrl & KVM_APIC_DEST_MASK);
4595 if (m && !avic_vcpu_is_running(vcpu))
4596 kvm_vcpu_wake_up(vcpu);
4600 case AVIC_IPI_FAILURE_INVALID_TARGET:
4602 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4603 WARN_ONCE(1, "Invalid backing page\n");
4606 pr_err("Unknown IPI interception\n");
4612 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4614 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4616 u32 *logical_apic_id_table;
4617 int dlid = GET_APIC_LOGICAL_ID(ldr);
4622 if (flat) { /* flat */
4623 index = ffs(dlid) - 1;
4626 } else { /* cluster */
4627 int cluster = (dlid & 0xf0) >> 4;
4628 int apic = ffs(dlid & 0x0f) - 1;
4630 if ((apic < 0) || (apic > 7) ||
4633 index = (cluster << 2) + apic;
4636 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4638 return &logical_apic_id_table[index];
4641 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4645 u32 *entry, new_entry;
4647 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4648 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4652 new_entry = READ_ONCE(*entry);
4653 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4654 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4656 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4658 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4659 WRITE_ONCE(*entry, new_entry);
4664 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4667 struct vcpu_svm *svm = to_svm(vcpu);
4668 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4673 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4674 if (ret && svm->ldr_reg) {
4675 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4683 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4686 struct vcpu_svm *svm = to_svm(vcpu);
4687 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4688 u32 id = (apic_id_reg >> 24) & 0xff;
4690 if (vcpu->vcpu_id == id)
4693 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4694 new = avic_get_physical_id_entry(vcpu, id);
4698 /* We need to move physical_id_entry to new offset */
4701 to_svm(vcpu)->avic_physical_id_cache = new;
4704 * Also update the guest physical APIC ID in the logical
4705 * APIC ID table entry if already setup the LDR.
4708 avic_handle_ldr_update(vcpu);
4713 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4715 struct vcpu_svm *svm = to_svm(vcpu);
4716 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4717 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4718 u32 mod = (dfr >> 28) & 0xf;
4721 * We assume that all local APICs are using the same type.
4722 * If this changes, we need to flush the AVIC logical
4725 if (kvm_svm->ldr_mode == mod)
4728 clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4729 kvm_svm->ldr_mode = mod;
4732 avic_handle_ldr_update(vcpu);
4736 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4738 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4739 u32 offset = svm->vmcb->control.exit_info_1 &
4740 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4744 if (avic_handle_apic_id_update(&svm->vcpu))
4748 if (avic_handle_ldr_update(&svm->vcpu))
4752 avic_handle_dfr_update(&svm->vcpu);
4758 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4763 static bool is_avic_unaccelerated_access_trap(u32 offset)
4792 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4795 u32 offset = svm->vmcb->control.exit_info_1 &
4796 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4797 u32 vector = svm->vmcb->control.exit_info_2 &
4798 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4799 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4800 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4801 bool trap = is_avic_unaccelerated_access_trap(offset);
4803 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4804 trap, write, vector);
4807 WARN_ONCE(!write, "svm: Handling trap read.\n");
4808 ret = avic_unaccel_trap_write(svm);
4810 /* Handling Fault */
4811 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4817 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4818 [SVM_EXIT_READ_CR0] = cr_interception,
4819 [SVM_EXIT_READ_CR3] = cr_interception,
4820 [SVM_EXIT_READ_CR4] = cr_interception,
4821 [SVM_EXIT_READ_CR8] = cr_interception,
4822 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4823 [SVM_EXIT_WRITE_CR0] = cr_interception,
4824 [SVM_EXIT_WRITE_CR3] = cr_interception,
4825 [SVM_EXIT_WRITE_CR4] = cr_interception,
4826 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4827 [SVM_EXIT_READ_DR0] = dr_interception,
4828 [SVM_EXIT_READ_DR1] = dr_interception,
4829 [SVM_EXIT_READ_DR2] = dr_interception,
4830 [SVM_EXIT_READ_DR3] = dr_interception,
4831 [SVM_EXIT_READ_DR4] = dr_interception,
4832 [SVM_EXIT_READ_DR5] = dr_interception,
4833 [SVM_EXIT_READ_DR6] = dr_interception,
4834 [SVM_EXIT_READ_DR7] = dr_interception,
4835 [SVM_EXIT_WRITE_DR0] = dr_interception,
4836 [SVM_EXIT_WRITE_DR1] = dr_interception,
4837 [SVM_EXIT_WRITE_DR2] = dr_interception,
4838 [SVM_EXIT_WRITE_DR3] = dr_interception,
4839 [SVM_EXIT_WRITE_DR4] = dr_interception,
4840 [SVM_EXIT_WRITE_DR5] = dr_interception,
4841 [SVM_EXIT_WRITE_DR6] = dr_interception,
4842 [SVM_EXIT_WRITE_DR7] = dr_interception,
4843 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4844 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4845 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4846 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4847 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4848 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4849 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4850 [SVM_EXIT_INTR] = intr_interception,
4851 [SVM_EXIT_NMI] = nmi_interception,
4852 [SVM_EXIT_SMI] = nop_on_interception,
4853 [SVM_EXIT_INIT] = nop_on_interception,
4854 [SVM_EXIT_VINTR] = interrupt_window_interception,
4855 [SVM_EXIT_RDPMC] = rdpmc_interception,
4856 [SVM_EXIT_CPUID] = cpuid_interception,
4857 [SVM_EXIT_IRET] = iret_interception,
4858 [SVM_EXIT_INVD] = invd_interception,
4859 [SVM_EXIT_PAUSE] = pause_interception,
4860 [SVM_EXIT_HLT] = halt_interception,
4861 [SVM_EXIT_INVLPG] = invlpg_interception,
4862 [SVM_EXIT_INVLPGA] = invlpga_interception,
4863 [SVM_EXIT_IOIO] = io_interception,
4864 [SVM_EXIT_MSR] = msr_interception,
4865 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4866 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4867 [SVM_EXIT_VMRUN] = vmrun_interception,
4868 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4869 [SVM_EXIT_VMLOAD] = vmload_interception,
4870 [SVM_EXIT_VMSAVE] = vmsave_interception,
4871 [SVM_EXIT_STGI] = stgi_interception,
4872 [SVM_EXIT_CLGI] = clgi_interception,
4873 [SVM_EXIT_SKINIT] = skinit_interception,
4874 [SVM_EXIT_WBINVD] = wbinvd_interception,
4875 [SVM_EXIT_MONITOR] = monitor_interception,
4876 [SVM_EXIT_MWAIT] = mwait_interception,
4877 [SVM_EXIT_XSETBV] = xsetbv_interception,
4878 [SVM_EXIT_NPF] = npf_interception,
4879 [SVM_EXIT_RSM] = rsm_interception,
4880 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4881 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4884 static void dump_vmcb(struct kvm_vcpu *vcpu)
4886 struct vcpu_svm *svm = to_svm(vcpu);
4887 struct vmcb_control_area *control = &svm->vmcb->control;
4888 struct vmcb_save_area *save = &svm->vmcb->save;
4890 pr_err("VMCB Control Area:\n");
4891 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4892 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4893 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4894 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4895 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4896 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4897 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4898 pr_err("%-20s%d\n", "pause filter threshold:",
4899 control->pause_filter_thresh);
4900 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4901 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4902 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4903 pr_err("%-20s%d\n", "asid:", control->asid);
4904 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4905 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4906 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4907 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4908 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4909 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4910 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4911 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4912 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4913 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4914 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4915 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4916 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4917 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4918 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4919 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4920 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4921 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4922 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4923 pr_err("VMCB State Save Area:\n");
4924 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4926 save->es.selector, save->es.attrib,
4927 save->es.limit, save->es.base);
4928 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4930 save->cs.selector, save->cs.attrib,
4931 save->cs.limit, save->cs.base);
4932 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4934 save->ss.selector, save->ss.attrib,
4935 save->ss.limit, save->ss.base);
4936 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4938 save->ds.selector, save->ds.attrib,
4939 save->ds.limit, save->ds.base);
4940 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4942 save->fs.selector, save->fs.attrib,
4943 save->fs.limit, save->fs.base);
4944 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4946 save->gs.selector, save->gs.attrib,
4947 save->gs.limit, save->gs.base);
4948 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4950 save->gdtr.selector, save->gdtr.attrib,
4951 save->gdtr.limit, save->gdtr.base);
4952 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4954 save->ldtr.selector, save->ldtr.attrib,
4955 save->ldtr.limit, save->ldtr.base);
4956 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4958 save->idtr.selector, save->idtr.attrib,
4959 save->idtr.limit, save->idtr.base);
4960 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4962 save->tr.selector, save->tr.attrib,
4963 save->tr.limit, save->tr.base);
4964 pr_err("cpl: %d efer: %016llx\n",
4965 save->cpl, save->efer);
4966 pr_err("%-15s %016llx %-13s %016llx\n",
4967 "cr0:", save->cr0, "cr2:", save->cr2);
4968 pr_err("%-15s %016llx %-13s %016llx\n",
4969 "cr3:", save->cr3, "cr4:", save->cr4);
4970 pr_err("%-15s %016llx %-13s %016llx\n",
4971 "dr6:", save->dr6, "dr7:", save->dr7);
4972 pr_err("%-15s %016llx %-13s %016llx\n",
4973 "rip:", save->rip, "rflags:", save->rflags);
4974 pr_err("%-15s %016llx %-13s %016llx\n",
4975 "rsp:", save->rsp, "rax:", save->rax);
4976 pr_err("%-15s %016llx %-13s %016llx\n",
4977 "star:", save->star, "lstar:", save->lstar);
4978 pr_err("%-15s %016llx %-13s %016llx\n",
4979 "cstar:", save->cstar, "sfmask:", save->sfmask);
4980 pr_err("%-15s %016llx %-13s %016llx\n",
4981 "kernel_gs_base:", save->kernel_gs_base,
4982 "sysenter_cs:", save->sysenter_cs);
4983 pr_err("%-15s %016llx %-13s %016llx\n",
4984 "sysenter_esp:", save->sysenter_esp,
4985 "sysenter_eip:", save->sysenter_eip);
4986 pr_err("%-15s %016llx %-13s %016llx\n",
4987 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4988 pr_err("%-15s %016llx %-13s %016llx\n",
4989 "br_from:", save->br_from, "br_to:", save->br_to);
4990 pr_err("%-15s %016llx %-13s %016llx\n",
4991 "excp_from:", save->last_excp_from,
4992 "excp_to:", save->last_excp_to);
4995 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4997 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4999 *info1 = control->exit_info_1;
5000 *info2 = control->exit_info_2;
5003 static int handle_exit(struct kvm_vcpu *vcpu)
5005 struct vcpu_svm *svm = to_svm(vcpu);
5006 struct kvm_run *kvm_run = vcpu->run;
5007 u32 exit_code = svm->vmcb->control.exit_code;
5009 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
5011 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
5012 vcpu->arch.cr0 = svm->vmcb->save.cr0;
5014 vcpu->arch.cr3 = svm->vmcb->save.cr3;
5016 if (unlikely(svm->nested.exit_required)) {
5017 nested_svm_vmexit(svm);
5018 svm->nested.exit_required = false;
5023 if (is_guest_mode(vcpu)) {
5026 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
5027 svm->vmcb->control.exit_info_1,
5028 svm->vmcb->control.exit_info_2,
5029 svm->vmcb->control.exit_int_info,
5030 svm->vmcb->control.exit_int_info_err,
5033 vmexit = nested_svm_exit_special(svm);
5035 if (vmexit == NESTED_EXIT_CONTINUE)
5036 vmexit = nested_svm_exit_handled(svm);
5038 if (vmexit == NESTED_EXIT_DONE)
5042 svm_complete_interrupts(svm);
5044 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
5045 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5046 kvm_run->fail_entry.hardware_entry_failure_reason
5047 = svm->vmcb->control.exit_code;
5048 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
5053 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
5054 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
5055 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
5056 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
5057 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
5059 __func__, svm->vmcb->control.exit_int_info,
5062 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
5063 || !svm_exit_handlers[exit_code]) {
5064 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
5065 kvm_queue_exception(vcpu, UD_VECTOR);
5069 return svm_exit_handlers[exit_code](svm);
5072 static void reload_tss(struct kvm_vcpu *vcpu)
5074 int cpu = raw_smp_processor_id();
5076 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5077 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5081 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5083 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5084 int asid = sev_get_asid(svm->vcpu.kvm);
5086 /* Assign the asid allocated with this SEV guest */
5087 svm->vmcb->control.asid = asid;
5092 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5093 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5095 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5096 svm->last_cpu == cpu)
5099 svm->last_cpu = cpu;
5100 sd->sev_vmcbs[asid] = svm->vmcb;
5101 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5102 mark_dirty(svm->vmcb, VMCB_ASID);
5105 static void pre_svm_run(struct vcpu_svm *svm)
5107 int cpu = raw_smp_processor_id();
5109 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5111 if (sev_guest(svm->vcpu.kvm))
5112 return pre_sev_run(svm, cpu);
5114 /* FIXME: handle wraparound of asid_generation */
5115 if (svm->asid_generation != sd->asid_generation)
5119 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5121 struct vcpu_svm *svm = to_svm(vcpu);
5123 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5124 vcpu->arch.hflags |= HF_NMI_MASK;
5125 set_intercept(svm, INTERCEPT_IRET);
5126 ++vcpu->stat.nmi_injections;
5129 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5131 struct vmcb_control_area *control;
5133 /* The following fields are ignored when AVIC is enabled */
5134 control = &svm->vmcb->control;
5135 control->int_vector = irq;
5136 control->int_ctl &= ~V_INTR_PRIO_MASK;
5137 control->int_ctl |= V_IRQ_MASK |
5138 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5139 mark_dirty(svm->vmcb, VMCB_INTR);
5142 static void svm_set_irq(struct kvm_vcpu *vcpu)
5144 struct vcpu_svm *svm = to_svm(vcpu);
5146 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5147 ++vcpu->stat.irq_injections;
5149 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5150 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5153 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5155 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5158 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5160 struct vcpu_svm *svm = to_svm(vcpu);
5162 if (svm_nested_virtualize_tpr(vcpu) ||
5163 kvm_vcpu_apicv_active(vcpu))
5166 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5172 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5175 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5180 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5182 return avic && irqchip_split(vcpu->kvm);
5185 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5189 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5193 /* Note: Currently only used by Hyper-V. */
5194 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5196 struct vcpu_svm *svm = to_svm(vcpu);
5197 struct vmcb *vmcb = svm->vmcb;
5199 if (!kvm_vcpu_apicv_active(&svm->vcpu))
5202 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5203 mark_dirty(vmcb, VMCB_INTR);
5206 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5211 static int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5213 if (!vcpu->arch.apicv_active)
5216 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5217 smp_mb__after_atomic();
5219 if (avic_vcpu_is_running(vcpu))
5220 wrmsrl(SVM_AVIC_DOORBELL,
5221 kvm_cpu_get_apicid(vcpu->cpu));
5223 kvm_vcpu_wake_up(vcpu);
5228 static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
5233 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5235 unsigned long flags;
5236 struct amd_svm_iommu_ir *cur;
5238 spin_lock_irqsave(&svm->ir_list_lock, flags);
5239 list_for_each_entry(cur, &svm->ir_list, node) {
5240 if (cur->data != pi->ir_data)
5242 list_del(&cur->node);
5246 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5249 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5252 unsigned long flags;
5253 struct amd_svm_iommu_ir *ir;
5256 * In some cases, the existing irte is updaed and re-set,
5257 * so we need to check here if it's already been * added
5260 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5261 struct kvm *kvm = svm->vcpu.kvm;
5262 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5263 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5264 struct vcpu_svm *prev_svm;
5271 prev_svm = to_svm(prev_vcpu);
5272 svm_ir_list_del(prev_svm, pi);
5276 * Allocating new amd_iommu_pi_data, which will get
5277 * add to the per-vcpu ir_list.
5279 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5284 ir->data = pi->ir_data;
5286 spin_lock_irqsave(&svm->ir_list_lock, flags);
5287 list_add(&ir->node, &svm->ir_list);
5288 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5295 * The HW cannot support posting multicast/broadcast
5296 * interrupts to a vCPU. So, we still use legacy interrupt
5297 * remapping for these kind of interrupts.
5299 * For lowest-priority interrupts, we only support
5300 * those with single CPU as the destination, e.g. user
5301 * configures the interrupts via /proc/irq or uses
5302 * irqbalance to make the interrupts single-CPU.
5305 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5306 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5308 struct kvm_lapic_irq irq;
5309 struct kvm_vcpu *vcpu = NULL;
5311 kvm_set_msi_irq(kvm, e, &irq);
5313 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5314 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5315 __func__, irq.vector);
5319 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5321 *svm = to_svm(vcpu);
5322 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5323 vcpu_info->vector = irq.vector;
5329 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5332 * @host_irq: host irq of the interrupt
5333 * @guest_irq: gsi of the interrupt
5334 * @set: set or unset PI
5335 * returns 0 on success, < 0 on failure
5337 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5338 uint32_t guest_irq, bool set)
5340 struct kvm_kernel_irq_routing_entry *e;
5341 struct kvm_irq_routing_table *irq_rt;
5342 int idx, ret = -EINVAL;
5344 if (!kvm_arch_has_assigned_device(kvm) ||
5345 !irq_remapping_cap(IRQ_POSTING_CAP))
5348 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5349 __func__, host_irq, guest_irq, set);
5351 idx = srcu_read_lock(&kvm->irq_srcu);
5352 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5353 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5355 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5356 struct vcpu_data vcpu_info;
5357 struct vcpu_svm *svm = NULL;
5359 if (e->type != KVM_IRQ_ROUTING_MSI)
5363 * Here, we setup with legacy mode in the following cases:
5364 * 1. When cannot target interrupt to a specific vcpu.
5365 * 2. Unsetting posted interrupt.
5366 * 3. APIC virtialization is disabled for the vcpu.
5368 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5369 kvm_vcpu_apicv_active(&svm->vcpu)) {
5370 struct amd_iommu_pi_data pi;
5372 /* Try to enable guest_mode in IRTE */
5373 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5375 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5377 pi.is_guest_mode = true;
5378 pi.vcpu_data = &vcpu_info;
5379 ret = irq_set_vcpu_affinity(host_irq, &pi);
5382 * Here, we successfully setting up vcpu affinity in
5383 * IOMMU guest mode. Now, we need to store the posted
5384 * interrupt information in a per-vcpu ir_list so that
5385 * we can reference to them directly when we update vcpu
5386 * scheduling information in IOMMU irte.
5388 if (!ret && pi.is_guest_mode)
5389 svm_ir_list_add(svm, &pi);
5391 /* Use legacy mode in IRTE */
5392 struct amd_iommu_pi_data pi;
5395 * Here, pi is used to:
5396 * - Tell IOMMU to use legacy mode for this interrupt.
5397 * - Retrieve ga_tag of prior interrupt remapping data.
5400 pi.is_guest_mode = false;
5401 ret = irq_set_vcpu_affinity(host_irq, &pi);
5404 * Check if the posted interrupt was previously
5405 * setup with the guest_mode by checking if the ga_tag
5406 * was cached. If so, we need to clean up the per-vcpu
5409 if (!ret && pi.prev_ga_tag) {
5410 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5411 struct kvm_vcpu *vcpu;
5413 vcpu = kvm_get_vcpu_by_id(kvm, id);
5415 svm_ir_list_del(to_svm(vcpu), &pi);
5420 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5421 e->gsi, vcpu_info.vector,
5422 vcpu_info.pi_desc_addr, set);
5426 pr_err("%s: failed to update PI IRTE\n", __func__);
5433 srcu_read_unlock(&kvm->irq_srcu, idx);
5437 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5439 struct vcpu_svm *svm = to_svm(vcpu);
5440 struct vmcb *vmcb = svm->vmcb;
5442 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5443 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5444 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5449 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5451 struct vcpu_svm *svm = to_svm(vcpu);
5453 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5456 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5458 struct vcpu_svm *svm = to_svm(vcpu);
5461 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5462 set_intercept(svm, INTERCEPT_IRET);
5464 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5465 clr_intercept(svm, INTERCEPT_IRET);
5469 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5471 struct vcpu_svm *svm = to_svm(vcpu);
5472 struct vmcb *vmcb = svm->vmcb;
5475 if (!gif_set(svm) ||
5476 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5479 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5481 if (is_guest_mode(vcpu))
5482 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5487 static void enable_irq_window(struct kvm_vcpu *vcpu)
5489 struct vcpu_svm *svm = to_svm(vcpu);
5491 if (kvm_vcpu_apicv_active(vcpu))
5495 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5496 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5497 * get that intercept, this function will be called again though and
5498 * we'll get the vintr intercept. However, if the vGIF feature is
5499 * enabled, the STGI interception will not occur. Enable the irq
5500 * window under the assumption that the hardware will set the GIF.
5502 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5504 svm_inject_irq(svm, 0x0);
5508 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5510 struct vcpu_svm *svm = to_svm(vcpu);
5512 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5514 return; /* IRET will cause a vm exit */
5516 if (!gif_set(svm)) {
5517 if (vgif_enabled(svm))
5518 set_intercept(svm, INTERCEPT_STGI);
5519 return; /* STGI will cause a vm exit */
5522 if (svm->nested.exit_required)
5523 return; /* we're not going to run the guest yet */
5526 * Something prevents NMI from been injected. Single step over possible
5527 * problem (IRET or exception injection or interrupt shadow)
5529 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5530 svm->nmi_singlestep = true;
5531 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5534 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5539 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5544 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5546 struct vcpu_svm *svm = to_svm(vcpu);
5548 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5549 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5551 svm->asid_generation--;
5554 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5556 struct vcpu_svm *svm = to_svm(vcpu);
5558 invlpga(gva, svm->vmcb->control.asid);
5561 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5565 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5567 struct vcpu_svm *svm = to_svm(vcpu);
5569 if (svm_nested_virtualize_tpr(vcpu))
5572 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5573 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5574 kvm_set_cr8(vcpu, cr8);
5578 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5580 struct vcpu_svm *svm = to_svm(vcpu);
5583 if (svm_nested_virtualize_tpr(vcpu) ||
5584 kvm_vcpu_apicv_active(vcpu))
5587 cr8 = kvm_get_cr8(vcpu);
5588 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5589 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5592 static void svm_complete_interrupts(struct vcpu_svm *svm)
5596 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5597 unsigned int3_injected = svm->int3_injected;
5599 svm->int3_injected = 0;
5602 * If we've made progress since setting HF_IRET_MASK, we've
5603 * executed an IRET and can allow NMI injection.
5605 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5606 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5607 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5608 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5611 svm->vcpu.arch.nmi_injected = false;
5612 kvm_clear_exception_queue(&svm->vcpu);
5613 kvm_clear_interrupt_queue(&svm->vcpu);
5615 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5618 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5620 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5621 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5624 case SVM_EXITINTINFO_TYPE_NMI:
5625 svm->vcpu.arch.nmi_injected = true;
5627 case SVM_EXITINTINFO_TYPE_EXEPT:
5629 * In case of software exceptions, do not reinject the vector,
5630 * but re-execute the instruction instead. Rewind RIP first
5631 * if we emulated INT3 before.
5633 if (kvm_exception_is_soft(vector)) {
5634 if (vector == BP_VECTOR && int3_injected &&
5635 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5636 kvm_rip_write(&svm->vcpu,
5637 kvm_rip_read(&svm->vcpu) -
5641 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5642 u32 err = svm->vmcb->control.exit_int_info_err;
5643 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5646 kvm_requeue_exception(&svm->vcpu, vector);
5648 case SVM_EXITINTINFO_TYPE_INTR:
5649 kvm_queue_interrupt(&svm->vcpu, vector, false);
5656 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5658 struct vcpu_svm *svm = to_svm(vcpu);
5659 struct vmcb_control_area *control = &svm->vmcb->control;
5661 control->exit_int_info = control->event_inj;
5662 control->exit_int_info_err = control->event_inj_err;
5663 control->event_inj = 0;
5664 svm_complete_interrupts(svm);
5667 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5669 struct vcpu_svm *svm = to_svm(vcpu);
5671 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5672 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5673 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5676 * A vmexit emulation is required before the vcpu can be executed
5679 if (unlikely(svm->nested.exit_required))
5683 * Disable singlestep if we're injecting an interrupt/exception.
5684 * We don't want our modified rflags to be pushed on the stack where
5685 * we might not be able to easily reset them if we disabled NMI
5688 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5690 * Event injection happens before external interrupts cause a
5691 * vmexit and interrupts are disabled here, so smp_send_reschedule
5692 * is enough to force an immediate vmexit.
5694 disable_nmi_singlestep(svm);
5695 smp_send_reschedule(vcpu->cpu);
5700 sync_lapic_to_cr8(vcpu);
5702 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5705 kvm_load_guest_xcr0(vcpu);
5708 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5709 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5710 * is no need to worry about the conditional branch over the wrmsr
5711 * being speculatively taken.
5713 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5718 "push %%" _ASM_BP "; \n\t"
5719 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5720 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5721 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5722 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5723 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5724 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5725 #ifdef CONFIG_X86_64
5726 "mov %c[r8](%[svm]), %%r8 \n\t"
5727 "mov %c[r9](%[svm]), %%r9 \n\t"
5728 "mov %c[r10](%[svm]), %%r10 \n\t"
5729 "mov %c[r11](%[svm]), %%r11 \n\t"
5730 "mov %c[r12](%[svm]), %%r12 \n\t"
5731 "mov %c[r13](%[svm]), %%r13 \n\t"
5732 "mov %c[r14](%[svm]), %%r14 \n\t"
5733 "mov %c[r15](%[svm]), %%r15 \n\t"
5736 /* Enter guest mode */
5737 "push %%" _ASM_AX " \n\t"
5738 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5739 __ex(SVM_VMLOAD) "\n\t"
5740 __ex(SVM_VMRUN) "\n\t"
5741 __ex(SVM_VMSAVE) "\n\t"
5742 "pop %%" _ASM_AX " \n\t"
5744 /* Save guest registers, load host registers */
5745 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5746 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5747 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5748 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5749 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5750 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5751 #ifdef CONFIG_X86_64
5752 "mov %%r8, %c[r8](%[svm]) \n\t"
5753 "mov %%r9, %c[r9](%[svm]) \n\t"
5754 "mov %%r10, %c[r10](%[svm]) \n\t"
5755 "mov %%r11, %c[r11](%[svm]) \n\t"
5756 "mov %%r12, %c[r12](%[svm]) \n\t"
5757 "mov %%r13, %c[r13](%[svm]) \n\t"
5758 "mov %%r14, %c[r14](%[svm]) \n\t"
5759 "mov %%r15, %c[r15](%[svm]) \n\t"
5762 * Clear host registers marked as clobbered to prevent
5765 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
5766 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
5767 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
5768 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
5769 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
5770 #ifdef CONFIG_X86_64
5771 "xor %%r8, %%r8 \n\t"
5772 "xor %%r9, %%r9 \n\t"
5773 "xor %%r10, %%r10 \n\t"
5774 "xor %%r11, %%r11 \n\t"
5775 "xor %%r12, %%r12 \n\t"
5776 "xor %%r13, %%r13 \n\t"
5777 "xor %%r14, %%r14 \n\t"
5778 "xor %%r15, %%r15 \n\t"
5783 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5784 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5785 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5786 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5787 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5788 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5789 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5790 #ifdef CONFIG_X86_64
5791 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5792 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5793 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5794 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5795 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5796 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5797 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5798 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5801 #ifdef CONFIG_X86_64
5802 , "rbx", "rcx", "rdx", "rsi", "rdi"
5803 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5805 , "ebx", "ecx", "edx", "esi", "edi"
5809 /* Eliminate branch target predictions from guest mode */
5812 #ifdef CONFIG_X86_64
5813 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5815 loadsegment(fs, svm->host.fs);
5816 #ifndef CONFIG_X86_32_LAZY_GS
5817 loadsegment(gs, svm->host.gs);
5822 * We do not use IBRS in the kernel. If this vCPU has used the
5823 * SPEC_CTRL MSR it may have left it on; save the value and
5824 * turn it off. This is much more efficient than blindly adding
5825 * it to the atomic save/restore list. Especially as the former
5826 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5828 * For non-nested case:
5829 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5833 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5836 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5837 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5841 local_irq_disable();
5843 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5845 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5846 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5847 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5848 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5850 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5851 kvm_before_interrupt(&svm->vcpu);
5853 kvm_put_guest_xcr0(vcpu);
5856 /* Any pending NMI will happen here */
5858 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5859 kvm_after_interrupt(&svm->vcpu);
5861 sync_cr8_to_lapic(vcpu);
5865 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5867 /* if exit due to PF check for async PF */
5868 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5869 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5872 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5873 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5877 * We need to handle MC intercepts here before the vcpu has a chance to
5878 * change the physical cpu
5880 if (unlikely(svm->vmcb->control.exit_code ==
5881 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5882 svm_handle_mce(svm);
5884 mark_all_clean(svm->vmcb);
5886 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5888 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5890 struct vcpu_svm *svm = to_svm(vcpu);
5892 svm->vmcb->save.cr3 = __sme_set(root);
5893 mark_dirty(svm->vmcb, VMCB_CR);
5896 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5898 struct vcpu_svm *svm = to_svm(vcpu);
5900 svm->vmcb->control.nested_cr3 = __sme_set(root);
5901 mark_dirty(svm->vmcb, VMCB_NPT);
5903 /* Also sync guest cr3 here in case we live migrate */
5904 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5905 mark_dirty(svm->vmcb, VMCB_CR);
5908 static int is_disabled(void)
5912 rdmsrl(MSR_VM_CR, vm_cr);
5913 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5920 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5923 * Patch in the VMMCALL instruction:
5925 hypercall[0] = 0x0f;
5926 hypercall[1] = 0x01;
5927 hypercall[2] = 0xd9;
5930 static void svm_check_processor_compat(void *rtn)
5935 static bool svm_cpu_has_accelerated_tpr(void)
5940 static bool svm_has_emulated_msr(int index)
5943 case MSR_IA32_MCG_EXT_CTL:
5952 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5957 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5959 struct vcpu_svm *svm = to_svm(vcpu);
5961 /* Update nrips enabled cache */
5962 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5964 if (!kvm_vcpu_apicv_active(vcpu))
5967 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5970 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5975 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5979 entry->ecx |= (1 << 2); /* Set SVM bit */
5982 entry->eax = 1; /* SVM revision 1 */
5983 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5984 ASID emulation to nested SVM */
5985 entry->ecx = 0; /* Reserved */
5986 entry->edx = 0; /* Per default do not support any
5987 additional features */
5989 /* Support next_rip if host supports it */
5990 if (boot_cpu_has(X86_FEATURE_NRIPS))
5991 entry->edx |= SVM_FEATURE_NRIP;
5993 /* Support NPT for the guest if enabled */
5995 entry->edx |= SVM_FEATURE_NPT;
5999 /* Support memory encryption cpuid if host supports it */
6000 if (boot_cpu_has(X86_FEATURE_SEV))
6001 cpuid(0x8000001f, &entry->eax, &entry->ebx,
6002 &entry->ecx, &entry->edx);
6007 static int svm_get_lpage_level(void)
6009 return PT_PDPE_LEVEL;
6012 static bool svm_rdtscp_supported(void)
6014 return boot_cpu_has(X86_FEATURE_RDTSCP);
6017 static bool svm_invpcid_supported(void)
6022 static bool svm_mpx_supported(void)
6027 static bool svm_xsaves_supported(void)
6032 static bool svm_umip_emulated(void)
6037 static bool svm_has_wbinvd_exit(void)
6042 #define PRE_EX(exit) { .exit_code = (exit), \
6043 .stage = X86_ICPT_PRE_EXCEPT, }
6044 #define POST_EX(exit) { .exit_code = (exit), \
6045 .stage = X86_ICPT_POST_EXCEPT, }
6046 #define POST_MEM(exit) { .exit_code = (exit), \
6047 .stage = X86_ICPT_POST_MEMACCESS, }
6049 static const struct __x86_intercept {
6051 enum x86_intercept_stage stage;
6052 } x86_intercept_map[] = {
6053 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
6054 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
6055 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
6056 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
6057 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
6058 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
6059 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
6060 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
6061 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
6062 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
6063 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
6064 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
6065 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
6066 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
6067 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
6068 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
6069 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
6070 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
6071 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
6072 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
6073 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
6074 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
6075 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
6076 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
6077 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
6078 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
6079 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
6080 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
6081 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
6082 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
6083 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
6084 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
6085 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
6086 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
6087 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
6088 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
6089 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
6090 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
6091 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
6092 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
6093 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
6094 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
6095 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
6096 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
6097 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
6098 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
6105 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6106 struct x86_instruction_info *info,
6107 enum x86_intercept_stage stage)
6109 struct vcpu_svm *svm = to_svm(vcpu);
6110 int vmexit, ret = X86EMUL_CONTINUE;
6111 struct __x86_intercept icpt_info;
6112 struct vmcb *vmcb = svm->vmcb;
6114 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6117 icpt_info = x86_intercept_map[info->intercept];
6119 if (stage != icpt_info.stage)
6122 switch (icpt_info.exit_code) {
6123 case SVM_EXIT_READ_CR0:
6124 if (info->intercept == x86_intercept_cr_read)
6125 icpt_info.exit_code += info->modrm_reg;
6127 case SVM_EXIT_WRITE_CR0: {
6128 unsigned long cr0, val;
6131 if (info->intercept == x86_intercept_cr_write)
6132 icpt_info.exit_code += info->modrm_reg;
6134 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6135 info->intercept == x86_intercept_clts)
6138 intercept = svm->nested.intercept;
6140 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6143 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6144 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6146 if (info->intercept == x86_intercept_lmsw) {
6149 /* lmsw can't clear PE - catch this here */
6150 if (cr0 & X86_CR0_PE)
6155 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6159 case SVM_EXIT_READ_DR0:
6160 case SVM_EXIT_WRITE_DR0:
6161 icpt_info.exit_code += info->modrm_reg;
6164 if (info->intercept == x86_intercept_wrmsr)
6165 vmcb->control.exit_info_1 = 1;
6167 vmcb->control.exit_info_1 = 0;
6169 case SVM_EXIT_PAUSE:
6171 * We get this for NOP only, but pause
6172 * is rep not, check this here
6174 if (info->rep_prefix != REPE_PREFIX)
6177 case SVM_EXIT_IOIO: {
6181 if (info->intercept == x86_intercept_in ||
6182 info->intercept == x86_intercept_ins) {
6183 exit_info = ((info->src_val & 0xffff) << 16) |
6185 bytes = info->dst_bytes;
6187 exit_info = (info->dst_val & 0xffff) << 16;
6188 bytes = info->src_bytes;
6191 if (info->intercept == x86_intercept_outs ||
6192 info->intercept == x86_intercept_ins)
6193 exit_info |= SVM_IOIO_STR_MASK;
6195 if (info->rep_prefix)
6196 exit_info |= SVM_IOIO_REP_MASK;
6198 bytes = min(bytes, 4u);
6200 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6202 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6204 vmcb->control.exit_info_1 = exit_info;
6205 vmcb->control.exit_info_2 = info->next_rip;
6213 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6214 if (static_cpu_has(X86_FEATURE_NRIPS))
6215 vmcb->control.next_rip = info->next_rip;
6216 vmcb->control.exit_code = icpt_info.exit_code;
6217 vmexit = nested_svm_exit_handled(svm);
6219 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6226 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6230 * We must have an instruction with interrupts enabled, so
6231 * the timer interrupt isn't delayed by the interrupt shadow.
6234 local_irq_disable();
6237 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6239 if (pause_filter_thresh)
6240 shrink_ple_window(vcpu);
6243 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6245 if (avic_handle_apic_id_update(vcpu) != 0)
6247 if (avic_handle_dfr_update(vcpu) != 0)
6249 avic_handle_ldr_update(vcpu);
6252 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6254 /* [63:9] are reserved. */
6255 vcpu->arch.mcg_cap &= 0x1ff;
6258 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6260 struct vcpu_svm *svm = to_svm(vcpu);
6262 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6266 if (is_guest_mode(&svm->vcpu) &&
6267 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6268 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6269 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6270 svm->nested.exit_required = true;
6277 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6279 struct vcpu_svm *svm = to_svm(vcpu);
6282 if (is_guest_mode(vcpu)) {
6283 /* FED8h - SVM Guest */
6284 put_smstate(u64, smstate, 0x7ed8, 1);
6285 /* FEE0h - SVM Guest VMCB Physical Address */
6286 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6288 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6289 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6290 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6292 ret = nested_svm_vmexit(svm);
6299 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6301 struct vcpu_svm *svm = to_svm(vcpu);
6302 struct vmcb *nested_vmcb;
6310 ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6311 sizeof(svm_state_save));
6315 if (svm_state_save.guest) {
6316 vcpu->arch.hflags &= ~HF_SMM_MASK;
6317 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6319 enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6322 vcpu->arch.hflags |= HF_SMM_MASK;
6327 static int enable_smi_window(struct kvm_vcpu *vcpu)
6329 struct vcpu_svm *svm = to_svm(vcpu);
6331 if (!gif_set(svm)) {
6332 if (vgif_enabled(svm))
6333 set_intercept(svm, INTERCEPT_STGI);
6334 /* STGI will cause a vm exit */
6340 static int sev_asid_new(void)
6345 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6347 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6348 if (pos >= max_sev_asid)
6351 set_bit(pos, sev_asid_bitmap);
6355 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6357 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6361 if (unlikely(sev->active))
6364 asid = sev_asid_new();
6368 ret = sev_platform_init(&argp->error);
6374 INIT_LIST_HEAD(&sev->regions_list);
6379 __sev_asid_free(asid);
6383 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6385 struct sev_data_activate *data;
6386 int asid = sev_get_asid(kvm);
6389 wbinvd_on_all_cpus();
6391 ret = sev_guest_df_flush(error);
6395 data = kzalloc(sizeof(*data), GFP_KERNEL);
6399 /* activate ASID on the given handle */
6400 data->handle = handle;
6402 ret = sev_guest_activate(data, error);
6408 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6417 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6423 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6425 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6427 return __sev_issue_cmd(sev->fd, id, data, error);
6430 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6432 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6433 struct sev_data_launch_start *start;
6434 struct kvm_sev_launch_start params;
6435 void *dh_blob, *session_blob;
6436 int *error = &argp->error;
6439 if (!sev_guest(kvm))
6442 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6445 start = kzalloc(sizeof(*start), GFP_KERNEL);
6450 if (params.dh_uaddr) {
6451 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6452 if (IS_ERR(dh_blob)) {
6453 ret = PTR_ERR(dh_blob);
6457 start->dh_cert_address = __sme_set(__pa(dh_blob));
6458 start->dh_cert_len = params.dh_len;
6461 session_blob = NULL;
6462 if (params.session_uaddr) {
6463 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6464 if (IS_ERR(session_blob)) {
6465 ret = PTR_ERR(session_blob);
6469 start->session_address = __sme_set(__pa(session_blob));
6470 start->session_len = params.session_len;
6473 start->handle = params.handle;
6474 start->policy = params.policy;
6476 /* create memory encryption context */
6477 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6479 goto e_free_session;
6481 /* Bind ASID to this guest */
6482 ret = sev_bind_asid(kvm, start->handle, error);
6484 sev_decommission(start->handle);
6485 goto e_free_session;
6488 /* return handle to userspace */
6489 params.handle = start->handle;
6490 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6491 sev_unbind_asid(kvm, start->handle);
6493 goto e_free_session;
6496 sev->handle = start->handle;
6497 sev->fd = argp->sev_fd;
6500 kfree(session_blob);
6508 static unsigned long get_num_contig_pages(unsigned long idx,
6509 struct page **inpages, unsigned long npages)
6511 unsigned long paddr, next_paddr;
6512 unsigned long i = idx + 1, pages = 1;
6514 /* find the number of contiguous pages starting from idx */
6515 paddr = __sme_page_pa(inpages[idx]);
6516 while (i < npages) {
6517 next_paddr = __sme_page_pa(inpages[i++]);
6518 if ((paddr + PAGE_SIZE) == next_paddr) {
6529 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6531 unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6532 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6533 struct kvm_sev_launch_update_data params;
6534 struct sev_data_launch_update_data *data;
6535 struct page **inpages;
6538 if (!sev_guest(kvm))
6541 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6544 data = kzalloc(sizeof(*data), GFP_KERNEL);
6548 vaddr = params.uaddr;
6550 vaddr_end = vaddr + size;
6552 /* Lock the user memory. */
6553 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6560 * The LAUNCH_UPDATE command will perform in-place encryption of the
6561 * memory content (i.e it will write the same memory region with C=1).
6562 * It's possible that the cache may contain the data with C=0, i.e.,
6563 * unencrypted so invalidate it first.
6565 sev_clflush_pages(inpages, npages);
6567 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6571 * If the user buffer is not page-aligned, calculate the offset
6574 offset = vaddr & (PAGE_SIZE - 1);
6576 /* Calculate the number of pages that can be encrypted in one go. */
6577 pages = get_num_contig_pages(i, inpages, npages);
6579 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6581 data->handle = sev->handle;
6583 data->address = __sme_page_pa(inpages[i]) + offset;
6584 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6589 next_vaddr = vaddr + len;
6593 /* content of memory is updated, mark pages dirty */
6594 for (i = 0; i < npages; i++) {
6595 set_page_dirty_lock(inpages[i]);
6596 mark_page_accessed(inpages[i]);
6598 /* unlock the user pages */
6599 sev_unpin_memory(kvm, inpages, npages);
6605 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6607 void __user *measure = (void __user *)(uintptr_t)argp->data;
6608 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6609 struct sev_data_launch_measure *data;
6610 struct kvm_sev_launch_measure params;
6611 void __user *p = NULL;
6615 if (!sev_guest(kvm))
6618 if (copy_from_user(¶ms, measure, sizeof(params)))
6621 data = kzalloc(sizeof(*data), GFP_KERNEL);
6625 /* User wants to query the blob length */
6629 p = (void __user *)(uintptr_t)params.uaddr;
6631 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6637 blob = kmalloc(params.len, GFP_KERNEL);
6641 data->address = __psp_pa(blob);
6642 data->len = params.len;
6646 data->handle = sev->handle;
6647 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6650 * If we query the session length, FW responded with expected data.
6659 if (copy_to_user(p, blob, params.len))
6664 params.len = data->len;
6665 if (copy_to_user(measure, ¶ms, sizeof(params)))
6674 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6676 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6677 struct sev_data_launch_finish *data;
6680 if (!sev_guest(kvm))
6683 data = kzalloc(sizeof(*data), GFP_KERNEL);
6687 data->handle = sev->handle;
6688 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6694 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6696 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6697 struct kvm_sev_guest_status params;
6698 struct sev_data_guest_status *data;
6701 if (!sev_guest(kvm))
6704 data = kzalloc(sizeof(*data), GFP_KERNEL);
6708 data->handle = sev->handle;
6709 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6713 params.policy = data->policy;
6714 params.state = data->state;
6715 params.handle = data->handle;
6717 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6724 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6725 unsigned long dst, int size,
6726 int *error, bool enc)
6728 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6729 struct sev_data_dbg *data;
6732 data = kzalloc(sizeof(*data), GFP_KERNEL);
6736 data->handle = sev->handle;
6737 data->dst_addr = dst;
6738 data->src_addr = src;
6741 ret = sev_issue_cmd(kvm,
6742 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6748 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6749 unsigned long dst_paddr, int sz, int *err)
6754 * Its safe to read more than we are asked, caller should ensure that
6755 * destination has enough space.
6757 src_paddr = round_down(src_paddr, 16);
6758 offset = src_paddr & 15;
6759 sz = round_up(sz + offset, 16);
6761 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6764 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6765 unsigned long __user dst_uaddr,
6766 unsigned long dst_paddr,
6769 struct page *tpage = NULL;
6772 /* if inputs are not 16-byte then use intermediate buffer */
6773 if (!IS_ALIGNED(dst_paddr, 16) ||
6774 !IS_ALIGNED(paddr, 16) ||
6775 !IS_ALIGNED(size, 16)) {
6776 tpage = (void *)alloc_page(GFP_KERNEL);
6780 dst_paddr = __sme_page_pa(tpage);
6783 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6788 offset = paddr & 15;
6789 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6790 page_address(tpage) + offset, size))
6801 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6802 unsigned long __user vaddr,
6803 unsigned long dst_paddr,
6804 unsigned long __user dst_vaddr,
6805 int size, int *error)
6807 struct page *src_tpage = NULL;
6808 struct page *dst_tpage = NULL;
6809 int ret, len = size;
6811 /* If source buffer is not aligned then use an intermediate buffer */
6812 if (!IS_ALIGNED(vaddr, 16)) {
6813 src_tpage = alloc_page(GFP_KERNEL);
6817 if (copy_from_user(page_address(src_tpage),
6818 (void __user *)(uintptr_t)vaddr, size)) {
6819 __free_page(src_tpage);
6823 paddr = __sme_page_pa(src_tpage);
6827 * If destination buffer or length is not aligned then do read-modify-write:
6828 * - decrypt destination in an intermediate buffer
6829 * - copy the source buffer in an intermediate buffer
6830 * - use the intermediate buffer as source buffer
6832 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6835 dst_tpage = alloc_page(GFP_KERNEL);
6841 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6842 __sme_page_pa(dst_tpage), size, error);
6847 * If source is kernel buffer then use memcpy() otherwise
6850 dst_offset = dst_paddr & 15;
6853 memcpy(page_address(dst_tpage) + dst_offset,
6854 page_address(src_tpage), size);
6856 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6857 (void __user *)(uintptr_t)vaddr, size)) {
6863 paddr = __sme_page_pa(dst_tpage);
6864 dst_paddr = round_down(dst_paddr, 16);
6865 len = round_up(size, 16);
6868 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6872 __free_page(src_tpage);
6874 __free_page(dst_tpage);
6878 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6880 unsigned long vaddr, vaddr_end, next_vaddr;
6881 unsigned long dst_vaddr;
6882 struct page **src_p, **dst_p;
6883 struct kvm_sev_dbg debug;
6888 if (!sev_guest(kvm))
6891 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6894 if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6896 if (!debug.dst_uaddr)
6899 vaddr = debug.src_uaddr;
6901 vaddr_end = vaddr + size;
6902 dst_vaddr = debug.dst_uaddr;
6904 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6905 int len, s_off, d_off;
6907 /* lock userspace source and destination page */
6908 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6912 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6914 sev_unpin_memory(kvm, src_p, n);
6919 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6920 * memory content (i.e it will write the same memory region with C=1).
6921 * It's possible that the cache may contain the data with C=0, i.e.,
6922 * unencrypted so invalidate it first.
6924 sev_clflush_pages(src_p, 1);
6925 sev_clflush_pages(dst_p, 1);
6928 * Since user buffer may not be page aligned, calculate the
6929 * offset within the page.
6931 s_off = vaddr & ~PAGE_MASK;
6932 d_off = dst_vaddr & ~PAGE_MASK;
6933 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6936 ret = __sev_dbg_decrypt_user(kvm,
6937 __sme_page_pa(src_p[0]) + s_off,
6939 __sme_page_pa(dst_p[0]) + d_off,
6942 ret = __sev_dbg_encrypt_user(kvm,
6943 __sme_page_pa(src_p[0]) + s_off,
6945 __sme_page_pa(dst_p[0]) + d_off,
6949 sev_unpin_memory(kvm, src_p, n);
6950 sev_unpin_memory(kvm, dst_p, n);
6955 next_vaddr = vaddr + len;
6956 dst_vaddr = dst_vaddr + len;
6963 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6965 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6966 struct sev_data_launch_secret *data;
6967 struct kvm_sev_launch_secret params;
6968 struct page **pages;
6973 if (!sev_guest(kvm))
6976 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6979 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6984 * The secret must be copied into contiguous memory region, lets verify
6985 * that userspace memory pages are contiguous before we issue command.
6987 if (get_num_contig_pages(0, pages, n) != n) {
6989 goto e_unpin_memory;
6993 data = kzalloc(sizeof(*data), GFP_KERNEL);
6995 goto e_unpin_memory;
6997 offset = params.guest_uaddr & (PAGE_SIZE - 1);
6998 data->guest_address = __sme_page_pa(pages[0]) + offset;
6999 data->guest_len = params.guest_len;
7001 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
7003 ret = PTR_ERR(blob);
7007 data->trans_address = __psp_pa(blob);
7008 data->trans_len = params.trans_len;
7010 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
7015 data->hdr_address = __psp_pa(hdr);
7016 data->hdr_len = params.hdr_len;
7018 data->handle = sev->handle;
7019 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
7028 sev_unpin_memory(kvm, pages, n);
7032 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
7034 struct kvm_sev_cmd sev_cmd;
7037 if (!svm_sev_enabled())
7040 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
7043 mutex_lock(&kvm->lock);
7045 switch (sev_cmd.id) {
7047 r = sev_guest_init(kvm, &sev_cmd);
7049 case KVM_SEV_LAUNCH_START:
7050 r = sev_launch_start(kvm, &sev_cmd);
7052 case KVM_SEV_LAUNCH_UPDATE_DATA:
7053 r = sev_launch_update_data(kvm, &sev_cmd);
7055 case KVM_SEV_LAUNCH_MEASURE:
7056 r = sev_launch_measure(kvm, &sev_cmd);
7058 case KVM_SEV_LAUNCH_FINISH:
7059 r = sev_launch_finish(kvm, &sev_cmd);
7061 case KVM_SEV_GUEST_STATUS:
7062 r = sev_guest_status(kvm, &sev_cmd);
7064 case KVM_SEV_DBG_DECRYPT:
7065 r = sev_dbg_crypt(kvm, &sev_cmd, true);
7067 case KVM_SEV_DBG_ENCRYPT:
7068 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7070 case KVM_SEV_LAUNCH_SECRET:
7071 r = sev_launch_secret(kvm, &sev_cmd);
7078 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7082 mutex_unlock(&kvm->lock);
7086 static int svm_register_enc_region(struct kvm *kvm,
7087 struct kvm_enc_region *range)
7089 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7090 struct enc_region *region;
7093 if (!sev_guest(kvm))
7096 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7099 region = kzalloc(sizeof(*region), GFP_KERNEL);
7103 mutex_lock(&kvm->lock);
7104 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
7105 if (!region->pages) {
7107 mutex_unlock(&kvm->lock);
7111 region->uaddr = range->addr;
7112 region->size = range->size;
7114 list_add_tail(®ion->list, &sev->regions_list);
7115 mutex_unlock(&kvm->lock);
7118 * The guest may change the memory encryption attribute from C=0 -> C=1
7119 * or vice versa for this memory range. Lets make sure caches are
7120 * flushed to ensure that guest data gets written into memory with
7123 sev_clflush_pages(region->pages, region->npages);
7132 static struct enc_region *
7133 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7135 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7136 struct list_head *head = &sev->regions_list;
7137 struct enc_region *i;
7139 list_for_each_entry(i, head, list) {
7140 if (i->uaddr == range->addr &&
7141 i->size == range->size)
7149 static int svm_unregister_enc_region(struct kvm *kvm,
7150 struct kvm_enc_region *range)
7152 struct enc_region *region;
7155 mutex_lock(&kvm->lock);
7157 if (!sev_guest(kvm)) {
7162 region = find_enc_region(kvm, range);
7168 __unregister_enc_region_locked(kvm, region);
7170 mutex_unlock(&kvm->lock);
7174 mutex_unlock(&kvm->lock);
7178 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7179 .cpu_has_kvm_support = has_svm,
7180 .disabled_by_bios = is_disabled,
7181 .hardware_setup = svm_hardware_setup,
7182 .hardware_unsetup = svm_hardware_unsetup,
7183 .check_processor_compatibility = svm_check_processor_compat,
7184 .hardware_enable = svm_hardware_enable,
7185 .hardware_disable = svm_hardware_disable,
7186 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7187 .has_emulated_msr = svm_has_emulated_msr,
7189 .vcpu_create = svm_create_vcpu,
7190 .vcpu_free = svm_free_vcpu,
7191 .vcpu_reset = svm_vcpu_reset,
7193 .vm_alloc = svm_vm_alloc,
7194 .vm_free = svm_vm_free,
7195 .vm_init = avic_vm_init,
7196 .vm_destroy = svm_vm_destroy,
7198 .prepare_guest_switch = svm_prepare_guest_switch,
7199 .vcpu_load = svm_vcpu_load,
7200 .vcpu_put = svm_vcpu_put,
7201 .vcpu_blocking = svm_vcpu_blocking,
7202 .vcpu_unblocking = svm_vcpu_unblocking,
7204 .update_bp_intercept = update_bp_intercept,
7205 .get_msr_feature = svm_get_msr_feature,
7206 .get_msr = svm_get_msr,
7207 .set_msr = svm_set_msr,
7208 .get_segment_base = svm_get_segment_base,
7209 .get_segment = svm_get_segment,
7210 .set_segment = svm_set_segment,
7211 .get_cpl = svm_get_cpl,
7212 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7213 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7214 .decache_cr3 = svm_decache_cr3,
7215 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7216 .set_cr0 = svm_set_cr0,
7217 .set_cr3 = svm_set_cr3,
7218 .set_cr4 = svm_set_cr4,
7219 .set_efer = svm_set_efer,
7220 .get_idt = svm_get_idt,
7221 .set_idt = svm_set_idt,
7222 .get_gdt = svm_get_gdt,
7223 .set_gdt = svm_set_gdt,
7224 .get_dr6 = svm_get_dr6,
7225 .set_dr6 = svm_set_dr6,
7226 .set_dr7 = svm_set_dr7,
7227 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7228 .cache_reg = svm_cache_reg,
7229 .get_rflags = svm_get_rflags,
7230 .set_rflags = svm_set_rflags,
7232 .tlb_flush = svm_flush_tlb,
7233 .tlb_flush_gva = svm_flush_tlb_gva,
7235 .run = svm_vcpu_run,
7236 .handle_exit = handle_exit,
7237 .skip_emulated_instruction = skip_emulated_instruction,
7238 .set_interrupt_shadow = svm_set_interrupt_shadow,
7239 .get_interrupt_shadow = svm_get_interrupt_shadow,
7240 .patch_hypercall = svm_patch_hypercall,
7241 .set_irq = svm_set_irq,
7242 .set_nmi = svm_inject_nmi,
7243 .queue_exception = svm_queue_exception,
7244 .cancel_injection = svm_cancel_injection,
7245 .interrupt_allowed = svm_interrupt_allowed,
7246 .nmi_allowed = svm_nmi_allowed,
7247 .get_nmi_mask = svm_get_nmi_mask,
7248 .set_nmi_mask = svm_set_nmi_mask,
7249 .enable_nmi_window = enable_nmi_window,
7250 .enable_irq_window = enable_irq_window,
7251 .update_cr8_intercept = update_cr8_intercept,
7252 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7253 .get_enable_apicv = svm_get_enable_apicv,
7254 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7255 .load_eoi_exitmap = svm_load_eoi_exitmap,
7256 .hwapic_irr_update = svm_hwapic_irr_update,
7257 .hwapic_isr_update = svm_hwapic_isr_update,
7258 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7259 .apicv_post_state_restore = avic_post_state_restore,
7261 .set_tss_addr = svm_set_tss_addr,
7262 .set_identity_map_addr = svm_set_identity_map_addr,
7263 .get_tdp_level = get_npt_level,
7264 .get_mt_mask = svm_get_mt_mask,
7266 .get_exit_info = svm_get_exit_info,
7268 .get_lpage_level = svm_get_lpage_level,
7270 .cpuid_update = svm_cpuid_update,
7272 .rdtscp_supported = svm_rdtscp_supported,
7273 .invpcid_supported = svm_invpcid_supported,
7274 .mpx_supported = svm_mpx_supported,
7275 .xsaves_supported = svm_xsaves_supported,
7276 .umip_emulated = svm_umip_emulated,
7278 .set_supported_cpuid = svm_set_supported_cpuid,
7280 .has_wbinvd_exit = svm_has_wbinvd_exit,
7282 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7283 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7285 .set_tdp_cr3 = set_tdp_cr3,
7287 .check_intercept = svm_check_intercept,
7288 .handle_external_intr = svm_handle_external_intr,
7290 .request_immediate_exit = __kvm_request_immediate_exit,
7292 .sched_in = svm_sched_in,
7294 .pmu_ops = &amd_pmu_ops,
7295 .deliver_posted_interrupt = svm_deliver_avic_intr,
7296 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
7297 .update_pi_irte = svm_update_pi_irte,
7298 .setup_mce = svm_setup_mce,
7300 .smi_allowed = svm_smi_allowed,
7301 .pre_enter_smm = svm_pre_enter_smm,
7302 .pre_leave_smm = svm_pre_leave_smm,
7303 .enable_smi_window = enable_smi_window,
7305 .mem_enc_op = svm_mem_enc_op,
7306 .mem_enc_reg_region = svm_register_enc_region,
7307 .mem_enc_unreg_region = svm_unregister_enc_region,
7310 static int __init svm_init(void)
7312 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7313 __alignof__(struct vcpu_svm), THIS_MODULE);
7316 static void __exit svm_exit(void)
7321 module_init(svm_init)
7322 module_exit(svm_exit)