2 #include <linux/initrd.h>
3 #include <linux/ioport.h>
4 #include <linux/swap.h>
5 #include <linux/memblock.h>
6 #include <linux/bootmem.h> /* for max_low_pfn */
7 #include <linux/swapfile.h>
8 #include <linux/swapops.h>
9 #include <linux/kmemleak.h>
11 #include <asm/set_memory.h>
12 #include <asm/cpu_device_id.h>
13 #include <asm/e820/api.h>
16 #include <asm/page_types.h>
17 #include <asm/sections.h>
18 #include <asm/setup.h>
19 #include <asm/tlbflush.h>
21 #include <asm/proto.h>
22 #include <asm/dma.h> /* for MAX_DMA_PFN */
23 #include <asm/microcode.h>
24 #include <asm/kaslr.h>
25 #include <asm/hypervisor.h>
26 #include <asm/cpufeature.h>
30 * We need to define the tracepoints somewhere, and tlb.c
31 * is only compied when SMP=y.
33 #define CREATE_TRACE_POINTS
34 #include <trace/events/tlb.h>
36 #include "mm_internal.h"
39 * Tables translating between page_cache_type_t and pte encoding.
41 * The default values are defined statically as minimal supported mode;
42 * WC and WT fall back to UC-. pat_init() updates these values to support
43 * more cache modes, WC and WT, when it is safe to do so. See pat_init()
44 * for the details. Note, __early_ioremap() used during early boot-time
45 * takes pgprot_t (pte encoding) and does not use these tables.
47 * Index into __cachemode2pte_tbl[] is the cachemode.
49 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
50 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
52 uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
53 [_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
54 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
55 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
56 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
57 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
58 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
60 EXPORT_SYMBOL(__cachemode2pte_tbl);
62 uint8_t __pte2cachemode_tbl[8] = {
63 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
64 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
65 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
66 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC,
67 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
68 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
69 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
70 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
72 EXPORT_SYMBOL(__pte2cachemode_tbl);
74 static unsigned long __initdata pgt_buf_start;
75 static unsigned long __initdata pgt_buf_end;
76 static unsigned long __initdata pgt_buf_top;
78 static unsigned long min_pfn_mapped;
80 static bool __initdata can_use_brk_pgt = true;
83 * Pages returned are already directly mapped.
85 * Changing that is likely to break Xen, see commit:
87 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve
89 * for detailed information.
91 __ref void *alloc_low_pages(unsigned int num)
99 order = get_order((unsigned long)num << PAGE_SHIFT);
100 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
103 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) {
104 unsigned long ret = 0;
106 if (min_pfn_mapped < max_pfn_mapped) {
107 ret = memblock_find_in_range(
108 min_pfn_mapped << PAGE_SHIFT,
109 max_pfn_mapped << PAGE_SHIFT,
110 PAGE_SIZE * num , PAGE_SIZE);
113 memblock_reserve(ret, PAGE_SIZE * num);
114 else if (can_use_brk_pgt)
115 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE));
118 panic("alloc_low_pages: can not alloc memory");
120 pfn = ret >> PAGE_SHIFT;
126 for (i = 0; i < num; i++) {
129 adr = __va((pfn + i) << PAGE_SHIFT);
133 return __va(pfn << PAGE_SHIFT);
137 * By default need 3 4k for initial PMD_SIZE, 3 4k for 0-ISA_END_ADDRESS.
138 * With KASLR memory randomization, depending on the machine e820 memory
139 * and the PUD alignment. We may need twice more pages when KASLR memory
140 * randomization is enabled.
142 #ifndef CONFIG_RANDOMIZE_MEMORY
143 #define INIT_PGD_PAGE_COUNT 6
145 #define INIT_PGD_PAGE_COUNT 12
147 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE)
148 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE);
149 void __init early_alloc_pgt_buf(void)
151 unsigned long tables = INIT_PGT_BUF_SIZE;
154 base = __pa(extend_brk(tables, PAGE_SIZE));
156 pgt_buf_start = base >> PAGE_SHIFT;
157 pgt_buf_end = pgt_buf_start;
158 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT);
163 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES);
168 unsigned page_size_mask;
171 static int page_size_mask;
173 static void __init probe_page_size_mask(void)
176 * For pagealloc debugging, identity mapping will use small pages.
177 * This will simplify cpa(), which otherwise needs to support splitting
178 * large pages into small in interrupt context, etc.
180 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
181 page_size_mask |= 1 << PG_LEVEL_2M;
185 /* Enable PSE if available */
186 if (boot_cpu_has(X86_FEATURE_PSE))
187 cr4_set_bits_and_update_boot(X86_CR4_PSE);
189 /* Enable PGE if available */
190 __supported_pte_mask &= ~_PAGE_GLOBAL;
191 if (boot_cpu_has(X86_FEATURE_PGE)) {
192 cr4_set_bits_and_update_boot(X86_CR4_PGE);
193 __supported_pte_mask |= _PAGE_GLOBAL;
196 /* By the default is everything supported: */
197 __default_kernel_pte_mask = __supported_pte_mask;
198 /* Except when with PTI where the kernel is mostly non-Global: */
199 if (cpu_feature_enabled(X86_FEATURE_PTI))
200 __default_kernel_pte_mask &= ~_PAGE_GLOBAL;
202 /* Enable 1 GB linear kernel mappings if available: */
203 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) {
204 printk(KERN_INFO "Using GB pages for direct mapping\n");
205 page_size_mask |= 1 << PG_LEVEL_1G;
211 #define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \
216 * INVLPG may not properly flush Global entries
217 * on these CPUs when PCIDs are enabled.
219 static const struct x86_cpu_id invlpg_miss_ids[] = {
220 INTEL_MATCH(INTEL_FAM6_ALDERLAKE ),
221 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ),
222 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ),
223 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ),
224 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P),
225 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S),
229 static void setup_pcid(void)
231 if (!IS_ENABLED(CONFIG_X86_64))
234 if (!boot_cpu_has(X86_FEATURE_PCID))
237 if (x86_match_cpu(invlpg_miss_ids)) {
238 pr_info("Incomplete global flushes, disabling PCID");
239 setup_clear_cpu_cap(X86_FEATURE_PCID);
243 if (boot_cpu_has(X86_FEATURE_PGE)) {
245 * This can't be cr4_set_bits_and_update_boot() -- the
246 * trampoline code can't handle CR4.PCIDE and it wouldn't
247 * do any good anyway. Despite the name,
248 * cr4_set_bits_and_update_boot() doesn't actually cause
249 * the bits in question to remain set all the way through
250 * the secondary boot asm.
252 * Instead, we brute-force it and set CR4.PCIDE manually in
255 cr4_set_bits(X86_CR4_PCIDE);
258 * INVPCID's single-context modes (2/3) only work if we set
259 * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable
260 * on systems that have X86_CR4_PCIDE clear, or that have
261 * no INVPCID support at all.
263 if (boot_cpu_has(X86_FEATURE_INVPCID))
264 setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE);
267 * flush_tlb_all(), as currently implemented, won't work if
268 * PCID is on but PGE is not. Since that combination
269 * doesn't exist on real hardware, there's no reason to try
270 * to fully support it, but it's polite to avoid corrupting
271 * data if we're on an improperly configured VM.
273 setup_clear_cpu_cap(X86_FEATURE_PCID);
278 #define NR_RANGE_MR 3
279 #else /* CONFIG_X86_64 */
280 #define NR_RANGE_MR 5
283 static int __meminit save_mr(struct map_range *mr, int nr_range,
284 unsigned long start_pfn, unsigned long end_pfn,
285 unsigned long page_size_mask)
287 if (start_pfn < end_pfn) {
288 if (nr_range >= NR_RANGE_MR)
289 panic("run out of range for init_memory_mapping\n");
290 mr[nr_range].start = start_pfn<<PAGE_SHIFT;
291 mr[nr_range].end = end_pfn<<PAGE_SHIFT;
292 mr[nr_range].page_size_mask = page_size_mask;
300 * adjust the page_size_mask for small range to go with
301 * big page size instead small one if nearby are ram too.
303 static void __ref adjust_range_page_size_mask(struct map_range *mr,
308 for (i = 0; i < nr_range; i++) {
309 if ((page_size_mask & (1<<PG_LEVEL_2M)) &&
310 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) {
311 unsigned long start = round_down(mr[i].start, PMD_SIZE);
312 unsigned long end = round_up(mr[i].end, PMD_SIZE);
315 if ((end >> PAGE_SHIFT) > max_low_pfn)
319 if (memblock_is_region_memory(start, end - start))
320 mr[i].page_size_mask |= 1<<PG_LEVEL_2M;
322 if ((page_size_mask & (1<<PG_LEVEL_1G)) &&
323 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) {
324 unsigned long start = round_down(mr[i].start, PUD_SIZE);
325 unsigned long end = round_up(mr[i].end, PUD_SIZE);
327 if (memblock_is_region_memory(start, end - start))
328 mr[i].page_size_mask |= 1<<PG_LEVEL_1G;
333 static const char *page_size_string(struct map_range *mr)
335 static const char str_1g[] = "1G";
336 static const char str_2m[] = "2M";
337 static const char str_4m[] = "4M";
338 static const char str_4k[] = "4k";
340 if (mr->page_size_mask & (1<<PG_LEVEL_1G))
343 * 32-bit without PAE has a 4M large page size.
344 * PG_LEVEL_2M is misnamed, but we can at least
345 * print out the right size in the string.
347 if (IS_ENABLED(CONFIG_X86_32) &&
348 !IS_ENABLED(CONFIG_X86_PAE) &&
349 mr->page_size_mask & (1<<PG_LEVEL_2M))
352 if (mr->page_size_mask & (1<<PG_LEVEL_2M))
358 static int __meminit split_mem_range(struct map_range *mr, int nr_range,
362 unsigned long start_pfn, end_pfn, limit_pfn;
366 limit_pfn = PFN_DOWN(end);
368 /* head if not big page alignment ? */
369 pfn = start_pfn = PFN_DOWN(start);
372 * Don't use a large page for the first 2/4MB of memory
373 * because there are often fixed size MTRRs in there
374 * and overlapping MTRRs into large pages can cause
378 end_pfn = PFN_DOWN(PMD_SIZE);
380 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
381 #else /* CONFIG_X86_64 */
382 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
384 if (end_pfn > limit_pfn)
386 if (start_pfn < end_pfn) {
387 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
391 /* big page (2M) range */
392 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
394 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
395 #else /* CONFIG_X86_64 */
396 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
397 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE)))
398 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
401 if (start_pfn < end_pfn) {
402 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
403 page_size_mask & (1<<PG_LEVEL_2M));
408 /* big page (1G) range */
409 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
410 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE));
411 if (start_pfn < end_pfn) {
412 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
414 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
418 /* tail is not big page (1G) alignment */
419 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
420 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
421 if (start_pfn < end_pfn) {
422 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
423 page_size_mask & (1<<PG_LEVEL_2M));
428 /* tail is not big page (2M) alignment */
431 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
434 adjust_range_page_size_mask(mr, nr_range);
436 /* try to merge same page size and continuous */
437 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
438 unsigned long old_start;
439 if (mr[i].end != mr[i+1].start ||
440 mr[i].page_size_mask != mr[i+1].page_size_mask)
443 old_start = mr[i].start;
444 memmove(&mr[i], &mr[i+1],
445 (nr_range - 1 - i) * sizeof(struct map_range));
446 mr[i--].start = old_start;
450 for (i = 0; i < nr_range; i++)
451 pr_debug(" [mem %#010lx-%#010lx] page %s\n",
452 mr[i].start, mr[i].end - 1,
453 page_size_string(&mr[i]));
458 struct range pfn_mapped[E820_MAX_ENTRIES];
461 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn)
463 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES,
464 nr_pfn_mapped, start_pfn, end_pfn);
465 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES);
467 max_pfn_mapped = max(max_pfn_mapped, end_pfn);
469 if (start_pfn < (1UL<<(32-PAGE_SHIFT)))
470 max_low_pfn_mapped = max(max_low_pfn_mapped,
471 min(end_pfn, 1UL<<(32-PAGE_SHIFT)));
474 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn)
478 for (i = 0; i < nr_pfn_mapped; i++)
479 if ((start_pfn >= pfn_mapped[i].start) &&
480 (end_pfn <= pfn_mapped[i].end))
487 * Setup the direct mapping of the physical memory at PAGE_OFFSET.
488 * This runs before bootmem is initialized and gets pages directly from
489 * the physical memory. To access them they are temporarily mapped.
491 unsigned long __ref init_memory_mapping(unsigned long start,
494 struct map_range mr[NR_RANGE_MR];
495 unsigned long ret = 0;
498 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n",
501 memset(mr, 0, sizeof(mr));
502 nr_range = split_mem_range(mr, 0, start, end);
504 for (i = 0; i < nr_range; i++)
505 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end,
506 mr[i].page_size_mask);
508 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT);
510 return ret >> PAGE_SHIFT;
514 * We need to iterate through the E820 memory map and create direct mappings
515 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply
516 * create direct mappings for all pfns from [0 to max_low_pfn) and
517 * [4GB to max_pfn) because of possible memory holes in high addresses
518 * that cannot be marked as UC by fixed/variable range MTRRs.
519 * Depending on the alignment of E820 ranges, this may possibly result
520 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables.
522 * init_mem_mapping() calls init_range_memory_mapping() with big range.
523 * That range would have hole in the middle or ends, and only ram parts
524 * will be mapped in init_range_memory_mapping().
526 static unsigned long __init init_range_memory_mapping(
527 unsigned long r_start,
530 unsigned long start_pfn, end_pfn;
531 unsigned long mapped_ram_size = 0;
534 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
535 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end);
536 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end);
541 * if it is overlapping with brk pgt, we need to
542 * alloc pgt buf from memblock instead.
544 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >=
545 min(end, (u64)pgt_buf_top<<PAGE_SHIFT);
546 init_memory_mapping(start, end);
547 mapped_ram_size += end - start;
548 can_use_brk_pgt = true;
551 return mapped_ram_size;
554 static unsigned long __init get_new_step_size(unsigned long step_size)
557 * Initial mapped size is PMD_SIZE (2M).
558 * We can not set step_size to be PUD_SIZE (1G) yet.
559 * In worse case, when we cross the 1G boundary, and
560 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k)
561 * to map 1G range with PTE. Hence we use one less than the
562 * difference of page table level shifts.
564 * Don't need to worry about overflow in the top-down case, on 32bit,
565 * when step_size is 0, round_down() returns 0 for start, and that
566 * turns it into 0x100000000ULL.
567 * In the bottom-up case, round_up(x, 0) returns 0 though too, which
568 * needs to be taken into consideration by the code below.
570 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1);
574 * memory_map_top_down - Map [map_start, map_end) top down
575 * @map_start: start address of the target memory range
576 * @map_end: end address of the target memory range
578 * This function will setup direct mapping for memory range
579 * [map_start, map_end) in top-down. That said, the page tables
580 * will be allocated at the end of the memory, and we map the
581 * memory in top-down.
583 static void __init memory_map_top_down(unsigned long map_start,
584 unsigned long map_end)
586 unsigned long real_end, start, last_start;
587 unsigned long step_size;
589 unsigned long mapped_ram_size = 0;
591 /* xen has big range in reserved near end of ram, skip it at first.*/
592 addr = memblock_find_in_range(map_start, map_end, PMD_SIZE, PMD_SIZE);
593 real_end = addr + PMD_SIZE;
595 /* step_size need to be small so pgt_buf from BRK could cover it */
596 step_size = PMD_SIZE;
597 max_pfn_mapped = 0; /* will get exact value next */
598 min_pfn_mapped = real_end >> PAGE_SHIFT;
599 last_start = start = real_end;
602 * We start from the top (end of memory) and go to the bottom.
603 * The memblock_find_in_range() gets us a block of RAM from the
604 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
607 while (last_start > map_start) {
608 if (last_start > step_size) {
609 start = round_down(last_start - 1, step_size);
610 if (start < map_start)
614 mapped_ram_size += init_range_memory_mapping(start,
617 min_pfn_mapped = last_start >> PAGE_SHIFT;
618 if (mapped_ram_size >= step_size)
619 step_size = get_new_step_size(step_size);
622 if (real_end < map_end)
623 init_range_memory_mapping(real_end, map_end);
627 * memory_map_bottom_up - Map [map_start, map_end) bottom up
628 * @map_start: start address of the target memory range
629 * @map_end: end address of the target memory range
631 * This function will setup direct mapping for memory range
632 * [map_start, map_end) in bottom-up. Since we have limited the
633 * bottom-up allocation above the kernel, the page tables will
634 * be allocated just above the kernel and we map the memory
635 * in [map_start, map_end) in bottom-up.
637 static void __init memory_map_bottom_up(unsigned long map_start,
638 unsigned long map_end)
640 unsigned long next, start;
641 unsigned long mapped_ram_size = 0;
642 /* step_size need to be small so pgt_buf from BRK could cover it */
643 unsigned long step_size = PMD_SIZE;
646 min_pfn_mapped = start >> PAGE_SHIFT;
649 * We start from the bottom (@map_start) and go to the top (@map_end).
650 * The memblock_find_in_range() gets us a block of RAM from the
651 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
654 while (start < map_end) {
655 if (step_size && map_end - start > step_size) {
656 next = round_up(start + 1, step_size);
663 mapped_ram_size += init_range_memory_mapping(start, next);
666 if (mapped_ram_size >= step_size)
667 step_size = get_new_step_size(step_size);
671 void __init init_mem_mapping(void)
675 pti_check_boottime_disable();
676 probe_page_size_mask();
680 end = max_pfn << PAGE_SHIFT;
682 end = max_low_pfn << PAGE_SHIFT;
685 /* the ISA range is always mapped regardless of memory holes */
686 init_memory_mapping(0, ISA_END_ADDRESS);
688 /* Init the trampoline, possibly with KASLR memory offset */
692 * If the allocation is in bottom-up direction, we setup direct mapping
693 * in bottom-up, otherwise we setup direct mapping in top-down.
695 if (memblock_bottom_up()) {
696 unsigned long kernel_end = __pa_symbol(_end);
699 * we need two separate calls here. This is because we want to
700 * allocate page tables above the kernel. So we first map
701 * [kernel_end, end) to make memory above the kernel be mapped
702 * as soon as possible. And then use page tables allocated above
703 * the kernel to map [ISA_END_ADDRESS, kernel_end).
705 memory_map_bottom_up(kernel_end, end);
706 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end);
708 memory_map_top_down(ISA_END_ADDRESS, end);
712 if (max_pfn > max_low_pfn) {
713 /* can we preseve max_low_pfn ?*/
714 max_low_pfn = max_pfn;
717 early_ioremap_page_table_range_init();
720 load_cr3(swapper_pg_dir);
723 x86_init.hyper.init_mem_mapping();
725 early_memtest(0, max_pfn_mapped << PAGE_SHIFT);
729 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
730 * is valid. The argument is a physical page number.
732 * On x86, access has to be given to the first megabyte of RAM because that
733 * area traditionally contains BIOS code and data regions used by X, dosemu,
734 * and similar apps. Since they map the entire memory range, the whole range
735 * must be allowed (for mapping), but any areas that would otherwise be
736 * disallowed are flagged as being "zero filled" instead of rejected.
737 * Access has to be given to non-kernel-ram areas as well, these contain the
738 * PCI mmio resources as well as potential bios/acpi data regions.
740 int devmem_is_allowed(unsigned long pagenr)
742 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE,
743 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
744 != REGION_DISJOINT) {
746 * For disallowed memory regions in the low 1MB range,
747 * request that the page be shown as all zeros.
756 * This must follow RAM test, since System RAM is considered a
757 * restricted resource under CONFIG_STRICT_IOMEM.
759 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) {
760 /* Low 1MB bypasses iomem restrictions. */
770 void free_init_pages(char *what, unsigned long begin, unsigned long end)
772 unsigned long begin_aligned, end_aligned;
774 /* Make sure boundaries are page aligned */
775 begin_aligned = PAGE_ALIGN(begin);
776 end_aligned = end & PAGE_MASK;
778 if (WARN_ON(begin_aligned != begin || end_aligned != end)) {
779 begin = begin_aligned;
787 * If debugging page accesses then do not free this memory but
788 * mark them not present - any buggy init-section access will
789 * create a kernel page fault:
791 if (debug_pagealloc_enabled()) {
792 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n",
795 * Inform kmemleak about the hole in the memory since the
796 * corresponding pages will be unmapped.
798 kmemleak_free_part((void *)begin, end - begin);
799 set_memory_np(begin, (end - begin) >> PAGE_SHIFT);
802 * We just marked the kernel text read only above, now that
803 * we are going to free part of that, we need to make that
804 * writeable and non-executable first.
806 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT);
807 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT);
809 free_reserved_area((void *)begin, (void *)end,
810 POISON_FREE_INITMEM, what);
815 * begin/end can be in the direct map or the "high kernel mapping"
816 * used for the kernel image only. free_init_pages() will do the
817 * right thing for either kind of address.
819 void free_kernel_image_pages(void *begin, void *end)
821 unsigned long begin_ul = (unsigned long)begin;
822 unsigned long end_ul = (unsigned long)end;
823 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT;
826 free_init_pages("unused kernel image", begin_ul, end_ul);
829 * PTI maps some of the kernel into userspace. For performance,
830 * this includes some kernel areas that do not contain secrets.
831 * Those areas might be adjacent to the parts of the kernel image
832 * being freed, which may contain secrets. Remove the "high kernel
833 * image mapping" for these freed areas, ensuring they are not even
834 * potentially vulnerable to Meltdown regardless of the specific
835 * optimizations PTI is currently using.
837 * The "noalias" prevents unmapping the direct map alias which is
838 * needed to access the freed pages.
840 * This is only valid for 64bit kernels. 32bit has only one mapping
841 * which can't be treated in this way for obvious reasons.
843 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI))
844 set_memory_np_noalias(begin_ul, len_pages);
847 void __weak mem_encrypt_free_decrypted_mem(void) { }
849 void __ref free_initmem(void)
851 e820__reallocate_tables();
853 mem_encrypt_free_decrypted_mem();
855 free_kernel_image_pages(&__init_begin, &__init_end);
858 #ifdef CONFIG_BLK_DEV_INITRD
859 void __init free_initrd_mem(unsigned long start, unsigned long end)
862 * end could be not aligned, and We can not align that,
863 * decompresser could be confused by aligned initrd_end
864 * We already reserve the end partial page before in
865 * - i386_start_kernel()
866 * - x86_64_start_kernel()
867 * - relocate_initrd()
868 * So here We can do PAGE_ALIGN() safely to get partial page to be freed
870 free_init_pages("initrd", start, PAGE_ALIGN(end));
875 * Calculate the precise size of the DMA zone (first 16 MB of RAM),
876 * and pass it to the MM layer - to help it set zone watermarks more
879 * Done on 64-bit systems only for the time being, although 32-bit systems
880 * might benefit from this as well.
882 void __init memblock_find_dma_reserve(void)
885 u64 nr_pages = 0, nr_free_pages = 0;
886 unsigned long start_pfn, end_pfn;
887 phys_addr_t start_addr, end_addr;
892 * Iterate over all memory ranges (free and reserved ones alike),
893 * to calculate the total number of pages in the first 16 MB of RAM:
896 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
897 start_pfn = min(start_pfn, MAX_DMA_PFN);
898 end_pfn = min(end_pfn, MAX_DMA_PFN);
900 nr_pages += end_pfn - start_pfn;
904 * Iterate over free memory ranges to calculate the number of free
905 * pages in the DMA zone, while not counting potential partial
906 * pages at the beginning or the end of the range:
909 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) {
910 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN);
911 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN);
913 if (start_pfn < end_pfn)
914 nr_free_pages += end_pfn - start_pfn;
917 set_dma_reserve(nr_pages - nr_free_pages);
921 void __init zone_sizes_init(void)
923 unsigned long max_zone_pfns[MAX_NR_ZONES];
925 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
927 #ifdef CONFIG_ZONE_DMA
928 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn);
930 #ifdef CONFIG_ZONE_DMA32
931 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn);
933 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
934 #ifdef CONFIG_HIGHMEM
935 max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
938 free_area_init_nodes(max_zone_pfns);
941 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = {
942 .loaded_mm = &init_mm,
944 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */
946 EXPORT_PER_CPU_SYMBOL(cpu_tlbstate);
948 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
950 /* entry 0 MUST be WB (hardwired to speed up translations) */
951 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB);
953 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry);
954 __pte2cachemode_tbl[entry] = cache;
958 unsigned long max_swapfile_size(void)
962 pages = generic_max_swapfile_size();
964 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) {
965 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */
966 unsigned long long l1tf_limit = l1tf_pfn_limit();
968 * We encode swap offsets also with 3 bits below those for pfn
969 * which makes the usable limit higher.
971 #if CONFIG_PGTABLE_LEVELS > 2
972 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT;
974 pages = min_t(unsigned long long, l1tf_limit, pages);