arch/xtensa/boot/dts/xtfpga.dtsi

   1 / {
   2         compatible = "cdns,xtensa-xtfpga";
   3         #address-cells = <1>;
   4         #size-cells = <1>;
   5         interrupt-parent = <&pic>;
   6
   7         chosen {
   8                 bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
   9         };
  10
  11         memory@0 {
  12                 device_type = "memory";
  13                 reg = <0x00000000 0x06000000>;
  14         };
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 cpu@0 {
  20                         compatible = "cdns,xtensa-cpu";
  21                         reg = <0>;
  22                         clocks = <&osc>;
  23                 };
  24         };
  25
  26         pic: pic {
  27                 compatible = "cdns,xtensa-pic";
  28                 /* one cell: internal irq number,
  29                  * two cells: second cell == 0: internal irq number
  30                  *            second cell == 1: external irq number
  31                  */
  32                 #interrupt-cells = <2>;
  33                 interrupt-controller;
  34         };
  35
  36         clocks {
  37                 clk54: clk54 {
  38                         #clock-cells = <0>;
  39                         compatible = "fixed-clock";
  40                         clock-frequency = <54000000>;
  41                 };
  42         };
  43
  44         soc {
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 compatible = "simple-bus";
  48                 ranges = <0x00000000 0xf0000000 0x10000000>;
  49
  50                 osc: main-oscillator {
  51                         #clock-cells = <0>;
  52                         compatible = "cdns,xtfpga-clock";
  53                         reg = <0x0d020004 0x4>;
  54                 };
  55
  56                 serial0: serial@0d050020 {
  57                         device_type = "serial";
  58                         compatible = "ns16550a";
  59                         no-loopback-test;
  60                         reg = <0x0d050020 0x20>;
  61                         reg-shift = <2>;
  62                         reg-io-width = <4>;
  63                         native-endian;
  64                         interrupts = <0 1>; /* external irq 0 */
  65                         clocks = <&osc>;
  66                 };
  67
  68                 enet0: ethoc@0d030000 {
  69                         compatible = "opencores,ethoc";
  70                         reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
  71                         native-endian;
  72                         interrupts = <1 1>; /* external irq 1 */
  73                         local-mac-address = [00 50 c2 13 6f 00];
  74                         clocks = <&osc>;
  75                 };
  76
  77                 i2s0: xtfpga-i2s@0d080000 {
  78                         #sound-dai-cells = <0>;
  79                         compatible = "cdns,xtfpga-i2s";
  80                         reg = <0x0d080000 0x40>;
  81                         interrupts = <2 1>; /* external irq 2 */
  82                         clocks = <&cdce706 4>;
  83                 };
  84
  85                 i2c0: i2c-master@0d090000 {
  86                         compatible = "opencores,i2c-ocores";
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         reg = <0x0d090000 0x20>;
  90                         reg-shift = <2>;
  91                         reg-io-width = <4>;
  92                         native-endian;
  93                         interrupts = <4 1>;
  94                         clocks = <&osc>;
  95
  96                         cdce706: clock-synth@69 {
  97                                 compatible = "ti,cdce706";
  98                                 #clock-cells = <1>;
  99                                 reg = <0x69>;
 100                                 clocks = <&clk54>;
 101                                 clock-names = "clk_in0";
 102                         };
 103                 };
 104
 105                 spi0: spi-master@0d0a0000 {
 106                         compatible = "cdns,xtfpga-spi";
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109                         reg = <0x0d0a0000 0xc>;
 110
 111                         tlv320aic23: sound-codec@0 {
 112                                 #sound-dai-cells = <0>;
 113                                 compatible = "tlv320aic23";
 114                                 reg = <0>;
 115                                 spi-max-frequency = <12500000>;
 116                         };
 117                 };
 118         };
 119
 120         sound {
 121                 compatible = "simple-audio-card";
 122                 simple-audio-card,format = "i2s";
 123                 simple-audio-card,mclk-fs = <256>;
 124
 125                 simple-audio-card,cpu {
 126                         sound-dai = <&i2s0>;
 127                 };
 128
 129                 simple-audio-card,codec {
 130                         sound-dai = <&tlv320aic23>;
 131                         simple-audio-card,bitclock-master = <0>;
 132                         simple-audio-card,frame-master = <0>;
 133                         clocks = <&cdce706 4>;
 134                 };
 135         };
 136 };