drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/mutex.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/platform_data/clk-lpss.h>
  21 #include <linux/platform_data/x86/pmc_atom.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/pwm.h>
  25 #include <linux/delay.h>
  26
  27 #include "internal.h"
  28
  29 ACPI_MODULE_NAME("acpi_lpss");
  30
  31 #ifdef CONFIG_X86_INTEL_LPSS
  32
  33 #include <asm/cpu_device_id.h>
  34 #include <asm/intel-family.h>
  35 #include <asm/iosf_mbi.h>
  36
  37 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  38
  39 #define LPSS_CLK_SIZE   0x04
  40 #define LPSS_LTR_SIZE   0x18
  41
  42 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  43 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  44 #define LPSS_RESETS                     0x04
  45 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  46 #define LPSS_RESETS_RESET_APB           BIT(1)
  47 #define LPSS_GENERAL                    0x08
  48 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  49 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  50 #define LPSS_SW_LTR                     0x10
  51 #define LPSS_AUTO_LTR                   0x14
  52 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  53 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  54 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  55 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  56 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  57 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  58 #define LPSS_LTR_MAX_VAL                0x3FF
  59 #define LPSS_TX_INT                     0x20
  60 #define LPSS_TX_INT_MASK                BIT(1)
  61
  62 #define LPSS_PRV_REG_COUNT              9
  63
  64 /* LPSS Flags */
  65 #define LPSS_CLK                        BIT(0)
  66 #define LPSS_CLK_GATE                   BIT(1)
  67 #define LPSS_CLK_DIVIDER                BIT(2)
  68 #define LPSS_LTR                        BIT(3)
  69 #define LPSS_SAVE_CTX                   BIT(4)
  70 #define LPSS_NO_D3_DELAY                BIT(5)
  71
  72 /* Crystal Cove PMIC shares same ACPI ID between different platforms */
  73 #define BYT_CRC_HRV                     2
  74 #define CHT_CRC_HRV                     3
  75
  76 struct lpss_private_data;
  77
  78 struct lpss_device_desc {
  79         unsigned int flags;
  80         const char *clk_con_id;
  81         unsigned int prv_offset;
  82         size_t prv_size_override;
  83         struct property_entry *properties;
  84         void (*setup)(struct lpss_private_data *pdata);
  85 };
  86
  87 static const struct lpss_device_desc lpss_dma_desc = {
  88         .flags = LPSS_CLK,
  89 };
  90
  91 struct lpss_private_data {
  92         struct acpi_device *adev;
  93         void __iomem *mmio_base;
  94         resource_size_t mmio_size;
  95         unsigned int fixed_clk_rate;
  96         struct clk *clk;
  97         const struct lpss_device_desc *dev_desc;
  98         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  99 };
 100
 101 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
 102 static u32 pmc_atom_d3_mask = 0xfe000ffe;
 103
 104 /* LPSS run time quirks */
 105 static unsigned int lpss_quirks;
 106
 107 /*
 108  * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
 109  *
 110  * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
 111  * it can be powered off automatically whenever the last LPSS device goes down.
 112  * In case of no power any access to the DMA controller will hang the system.
 113  * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
 114  * well as on ASuS T100TA transformer.
 115  *
 116  * This quirk overrides power state of entire LPSS island to keep DMA powered
 117  * on whenever we have at least one other device in use.
 118  */
 119 #define LPSS_QUIRK_ALWAYS_POWER_ON      BIT(0)
 120
 121 /* UART Component Parameter Register */
 122 #define LPSS_UART_CPR                   0xF4
 123 #define LPSS_UART_CPR_AFCE              BIT(4)
 124
 125 static void lpss_uart_setup(struct lpss_private_data *pdata)
 126 {
 127         unsigned int offset;
 128         u32 val;
 129
 130         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
 131         val = readl(pdata->mmio_base + offset);
 132         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
 133
 134         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 135         if (!(val & LPSS_UART_CPR_AFCE)) {
 136                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 137                 val = readl(pdata->mmio_base + offset);
 138                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 139                 writel(val, pdata->mmio_base + offset);
 140         }
 141 }
 142
 143 static void lpss_deassert_reset(struct lpss_private_data *pdata)
 144 {
 145         unsigned int offset;
 146         u32 val;
 147
 148         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 149         val = readl(pdata->mmio_base + offset);
 150         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 151         writel(val, pdata->mmio_base + offset);
 152 }
 153
 154 /*
 155  * BYT PWM used for backlight control by the i915 driver on systems without
 156  * the Crystal Cove PMIC.
 157  */
 158 static struct pwm_lookup byt_pwm_lookup[] = {
 159         PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
 160                                "pwm_backlight", 0, PWM_POLARITY_NORMAL,
 161                                "pwm-lpss-platform"),
 162 };
 163
 164 static void byt_pwm_setup(struct lpss_private_data *pdata)
 165 {
 166         struct acpi_device *adev = pdata->adev;
 167
 168         /* Only call pwm_add_table for the first PWM controller */
 169         if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
 170                 return;
 171
 172         if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
 173                 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
 174 }
 175
 176 #define LPSS_I2C_ENABLE                 0x6c
 177
 178 static void byt_i2c_setup(struct lpss_private_data *pdata)
 179 {
 180         const char *uid_str = acpi_device_uid(pdata->adev);
 181         acpi_handle handle = pdata->adev->handle;
 182         unsigned long long shared_host = 0;
 183         acpi_status status;
 184         long uid = 0;
 185
 186         /* Expected to always be true, but better safe then sorry */
 187         if (uid_str)
 188                 uid = simple_strtol(uid_str, NULL, 10);
 189
 190         /* Detect I2C bus shared with PUNIT and ignore its d3 status */
 191         status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
 192         if (ACPI_SUCCESS(status) && shared_host && uid)
 193                 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
 194
 195         lpss_deassert_reset(pdata);
 196
 197         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 198                 pdata->fixed_clk_rate = 133000000;
 199
 200         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
 201 }
 202
 203 /* BSW PWM used for backlight control by the i915 driver */
 204 static struct pwm_lookup bsw_pwm_lookup[] = {
 205         PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
 206                                "pwm_backlight", 0, PWM_POLARITY_NORMAL,
 207                                "pwm-lpss-platform"),
 208 };
 209
 210 static void bsw_pwm_setup(struct lpss_private_data *pdata)
 211 {
 212         struct acpi_device *adev = pdata->adev;
 213
 214         /* Only call pwm_add_table for the first PWM controller */
 215         if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
 216                 return;
 217
 218         pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
 219 }
 220
 221 static const struct lpss_device_desc lpt_dev_desc = {
 222         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 223         .prv_offset = 0x800,
 224 };
 225
 226 static const struct lpss_device_desc lpt_i2c_dev_desc = {
 227         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 228         .prv_offset = 0x800,
 229 };
 230
 231 static struct property_entry uart_properties[] = {
 232         PROPERTY_ENTRY_U32("reg-io-width", 4),
 233         PROPERTY_ENTRY_U32("reg-shift", 2),
 234         PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
 235         { },
 236 };
 237
 238 static const struct lpss_device_desc lpt_uart_dev_desc = {
 239         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 240         .clk_con_id = "baudclk",
 241         .prv_offset = 0x800,
 242         .setup = lpss_uart_setup,
 243         .properties = uart_properties,
 244 };
 245
 246 static const struct lpss_device_desc lpt_sdio_dev_desc = {
 247         .flags = LPSS_LTR,
 248         .prv_offset = 0x1000,
 249         .prv_size_override = 0x1018,
 250 };
 251
 252 static const struct lpss_device_desc byt_pwm_dev_desc = {
 253         .flags = LPSS_SAVE_CTX,
 254         .prv_offset = 0x800,
 255         .setup = byt_pwm_setup,
 256 };
 257
 258 static const struct lpss_device_desc bsw_pwm_dev_desc = {
 259         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 260         .prv_offset = 0x800,
 261         .setup = bsw_pwm_setup,
 262 };
 263
 264 static const struct lpss_device_desc byt_uart_dev_desc = {
 265         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 266         .clk_con_id = "baudclk",
 267         .prv_offset = 0x800,
 268         .setup = lpss_uart_setup,
 269         .properties = uart_properties,
 270 };
 271
 272 static const struct lpss_device_desc bsw_uart_dev_desc = {
 273         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 274                         | LPSS_NO_D3_DELAY,
 275         .clk_con_id = "baudclk",
 276         .prv_offset = 0x800,
 277         .setup = lpss_uart_setup,
 278         .properties = uart_properties,
 279 };
 280
 281 static const struct lpss_device_desc byt_spi_dev_desc = {
 282         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 283         .prv_offset = 0x400,
 284 };
 285
 286 static const struct lpss_device_desc byt_sdio_dev_desc = {
 287         .flags = LPSS_CLK,
 288 };
 289
 290 static const struct lpss_device_desc byt_i2c_dev_desc = {
 291         .flags = LPSS_CLK | LPSS_SAVE_CTX,
 292         .prv_offset = 0x800,
 293         .setup = byt_i2c_setup,
 294 };
 295
 296 static const struct lpss_device_desc bsw_i2c_dev_desc = {
 297         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 298         .prv_offset = 0x800,
 299         .setup = byt_i2c_setup,
 300 };
 301
 302 static const struct lpss_device_desc bsw_spi_dev_desc = {
 303         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 304                         | LPSS_NO_D3_DELAY,
 305         .prv_offset = 0x400,
 306         .setup = lpss_deassert_reset,
 307 };
 308
 309 #define ICPU(model)     { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 310
 311 static const struct x86_cpu_id lpss_cpu_ids[] = {
 312         ICPU(INTEL_FAM6_ATOM_SILVERMONT),       /* Valleyview, Bay Trail */
 313         ICPU(INTEL_FAM6_ATOM_AIRMONT),  /* Braswell, Cherry Trail */
 314         {}
 315 };
 316
 317 #else
 318
 319 #define LPSS_ADDR(desc) (0UL)
 320
 321 #endif /* CONFIG_X86_INTEL_LPSS */
 322
 323 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 324         /* Generic LPSS devices */
 325         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 326
 327         /* Lynxpoint LPSS devices */
 328         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 329         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 330         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 331         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 332         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 333         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 334         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 335         { "INT33C7", },
 336
 337         /* BayTrail LPSS devices */
 338         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 339         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 340         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 341         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 342         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 343         { "INT33B2", },
 344         { "INT33FC", },
 345
 346         /* Braswell LPSS devices */
 347         { "80862286", LPSS_ADDR(lpss_dma_desc) },
 348         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
 349         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
 350         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
 351         { "808622C0", LPSS_ADDR(lpss_dma_desc) },
 352         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
 353
 354         /* Broadwell LPSS devices */
 355         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 356         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 357         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 358         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 359         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 360         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 361         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 362         { "INT3437", },
 363
 364         /* Wildcat Point LPSS devices */
 365         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 366
 367         { }
 368 };
 369
 370 #ifdef CONFIG_X86_INTEL_LPSS
 371
 372 static int is_memory(struct acpi_resource *res, void *not_used)
 373 {
 374         struct resource r;
 375         return !acpi_dev_resource_memory(res, &r);
 376 }
 377
 378 /* LPSS main clock device. */
 379 static struct platform_device *lpss_clk_dev;
 380
 381 static inline void lpt_register_clock_device(void)
 382 {
 383         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 384 }
 385
 386 static int register_device_clock(struct acpi_device *adev,
 387                                  struct lpss_private_data *pdata)
 388 {
 389         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 390         const char *devname = dev_name(&adev->dev);
 391         struct clk *clk = ERR_PTR(-ENODEV);
 392         struct lpss_clk_data *clk_data;
 393         const char *parent, *clk_name;
 394         void __iomem *prv_base;
 395
 396         if (!lpss_clk_dev)
 397                 lpt_register_clock_device();
 398
 399         clk_data = platform_get_drvdata(lpss_clk_dev);
 400         if (!clk_data)
 401                 return -ENODEV;
 402         clk = clk_data->clk;
 403
 404         if (!pdata->mmio_base
 405             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 406                 return -ENODATA;
 407
 408         parent = clk_data->name;
 409         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 410
 411         if (pdata->fixed_clk_rate) {
 412                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 413                                               pdata->fixed_clk_rate);
 414                 goto out;
 415         }
 416
 417         if (dev_desc->flags & LPSS_CLK_GATE) {
 418                 clk = clk_register_gate(NULL, devname, parent, 0,
 419                                         prv_base, 0, 0, NULL);
 420                 parent = devname;
 421         }
 422
 423         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 424                 /* Prevent division by zero */
 425                 if (!readl(prv_base))
 426                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 427
 428                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 429                 if (!clk_name)
 430                         return -ENOMEM;
 431                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 432                                                       0, prv_base,
 433                                                       1, 15, 16, 15, 0, NULL);
 434                 parent = clk_name;
 435
 436                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 437                 if (!clk_name) {
 438                         kfree(parent);
 439                         return -ENOMEM;
 440                 }
 441                 clk = clk_register_gate(NULL, clk_name, parent,
 442                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 443                                         prv_base, 31, 0, NULL);
 444                 kfree(parent);
 445                 kfree(clk_name);
 446         }
 447 out:
 448         if (IS_ERR(clk))
 449                 return PTR_ERR(clk);
 450
 451         pdata->clk = clk;
 452         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
 453         return 0;
 454 }
 455
 456 static int acpi_lpss_create_device(struct acpi_device *adev,
 457                                    const struct acpi_device_id *id)
 458 {
 459         const struct lpss_device_desc *dev_desc;
 460         struct lpss_private_data *pdata;
 461         struct resource_entry *rentry;
 462         struct list_head resource_list;
 463         struct platform_device *pdev;
 464         int ret;
 465
 466         dev_desc = (const struct lpss_device_desc *)id->driver_data;
 467         if (!dev_desc) {
 468                 pdev = acpi_create_platform_device(adev, NULL);
 469                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 470         }
 471         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 472         if (!pdata)
 473                 return -ENOMEM;
 474
 475         INIT_LIST_HEAD(&resource_list);
 476         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 477         if (ret < 0)
 478                 goto err_out;
 479
 480         list_for_each_entry(rentry, &resource_list, node)
 481                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
 482                         if (dev_desc->prv_size_override)
 483                                 pdata->mmio_size = dev_desc->prv_size_override;
 484                         else
 485                                 pdata->mmio_size = resource_size(rentry->res);
 486                         pdata->mmio_base = ioremap(rentry->res->start,
 487                                                    pdata->mmio_size);
 488                         break;
 489                 }
 490
 491         acpi_dev_free_resource_list(&resource_list);
 492
 493         if (!pdata->mmio_base) {
 494                 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
 495                 adev->pnp.type.platform_id = 0;
 496                 /* Skip the device, but continue the namespace scan. */
 497                 ret = 0;
 498                 goto err_out;
 499         }
 500
 501         pdata->adev = adev;
 502         pdata->dev_desc = dev_desc;
 503
 504         if (dev_desc->setup)
 505                 dev_desc->setup(pdata);
 506
 507         if (dev_desc->flags & LPSS_CLK) {
 508                 ret = register_device_clock(adev, pdata);
 509                 if (ret) {
 510                         /* Skip the device, but continue the namespace scan. */
 511                         ret = 0;
 512                         goto err_out;
 513                 }
 514         }
 515
 516         /*
 517          * This works around a known issue in ACPI tables where LPSS devices
 518          * have _PS0 and _PS3 without _PSC (and no power resources), so
 519          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 520          */
 521         acpi_device_fix_up_power(adev);
 522
 523         adev->driver_data = pdata;
 524         pdev = acpi_create_platform_device(adev, dev_desc->properties);
 525         if (!IS_ERR_OR_NULL(pdev)) {
 526                 return 1;
 527         }
 528
 529         ret = PTR_ERR(pdev);
 530         adev->driver_data = NULL;
 531
 532  err_out:
 533         kfree(pdata);
 534         return ret;
 535 }
 536
 537 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 538 {
 539         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 540 }
 541
 542 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 543                              unsigned int reg)
 544 {
 545         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 546 }
 547
 548 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 549 {
 550         struct acpi_device *adev;
 551         struct lpss_private_data *pdata;
 552         unsigned long flags;
 553         int ret;
 554
 555         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 556         if (WARN_ON(ret))
 557                 return ret;
 558
 559         spin_lock_irqsave(&dev->power.lock, flags);
 560         if (pm_runtime_suspended(dev)) {
 561                 ret = -EAGAIN;
 562                 goto out;
 563         }
 564         pdata = acpi_driver_data(adev);
 565         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 566                 ret = -ENODEV;
 567                 goto out;
 568         }
 569         *val = __lpss_reg_read(pdata, reg);
 570
 571  out:
 572         spin_unlock_irqrestore(&dev->power.lock, flags);
 573         return ret;
 574 }
 575
 576 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 577                              char *buf)
 578 {
 579         u32 ltr_value = 0;
 580         unsigned int reg;
 581         int ret;
 582
 583         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 584         ret = lpss_reg_read(dev, reg, &ltr_value);
 585         if (ret)
 586                 return ret;
 587
 588         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 589 }
 590
 591 static ssize_t lpss_ltr_mode_show(struct device *dev,
 592                                   struct device_attribute *attr, char *buf)
 593 {
 594         u32 ltr_mode = 0;
 595         char *outstr;
 596         int ret;
 597
 598         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 599         if (ret)
 600                 return ret;
 601
 602         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 603         return sprintf(buf, "%s\n", outstr);
 604 }
 605
 606 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 607 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 608 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 609
 610 static struct attribute *lpss_attrs[] = {
 611         &dev_attr_auto_ltr.attr,
 612         &dev_attr_sw_ltr.attr,
 613         &dev_attr_ltr_mode.attr,
 614         NULL,
 615 };
 616
 617 static const struct attribute_group lpss_attr_group = {
 618         .attrs = lpss_attrs,
 619         .name = "lpss_ltr",
 620 };
 621
 622 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 623 {
 624         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 625         u32 ltr_mode, ltr_val;
 626
 627         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 628         if (val < 0) {
 629                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 630                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 631                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 632                 }
 633                 return;
 634         }
 635         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 636         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 637                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 638                 val = LPSS_LTR_MAX_VAL;
 639         } else if (val > LPSS_LTR_MAX_VAL) {
 640                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 641                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 642         } else {
 643                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 644         }
 645         ltr_val |= val;
 646         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 647         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 648                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 649                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 650         }
 651 }
 652
 653 #ifdef CONFIG_PM
 654 /**
 655  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 656  * @dev: LPSS device
 657  * @pdata: pointer to the private data of the LPSS device
 658  *
 659  * Most LPSS devices have private registers which may loose their context when
 660  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 661  * prv_reg_ctx array.
 662  */
 663 static void acpi_lpss_save_ctx(struct device *dev,
 664                                struct lpss_private_data *pdata)
 665 {
 666         unsigned int i;
 667
 668         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 669                 unsigned long offset = i * sizeof(u32);
 670
 671                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 672                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 673                         pdata->prv_reg_ctx[i], offset);
 674         }
 675 }
 676
 677 /**
 678  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 679  * @dev: LPSS device
 680  * @pdata: pointer to the private data of the LPSS device
 681  *
 682  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 683  */
 684 static void acpi_lpss_restore_ctx(struct device *dev,
 685                                   struct lpss_private_data *pdata)
 686 {
 687         unsigned int i;
 688
 689         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 690                 unsigned long offset = i * sizeof(u32);
 691
 692                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 693                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 694                         pdata->prv_reg_ctx[i], offset);
 695         }
 696 }
 697
 698 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
 699 {
 700         /*
 701          * The following delay is needed or the subsequent write operations may
 702          * fail. The LPSS devices are actually PCI devices and the PCI spec
 703          * expects 10ms delay before the device can be accessed after D3 to D0
 704          * transition. However some platforms like BSW does not need this delay.
 705          */
 706         unsigned int delay = 10;        /* default 10ms delay */
 707
 708         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
 709                 delay = 0;
 710
 711         msleep(delay);
 712 }
 713
 714 static int acpi_lpss_activate(struct device *dev)
 715 {
 716         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 717         int ret;
 718
 719         ret = acpi_dev_runtime_resume(dev);
 720         if (ret)
 721                 return ret;
 722
 723         acpi_lpss_d3_to_d0_delay(pdata);
 724
 725         /*
 726          * This is called only on ->probe() stage where a device is either in
 727          * known state defined by BIOS or most likely powered off. Due to this
 728          * we have to deassert reset line to be sure that ->probe() will
 729          * recognize the device.
 730          */
 731         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 732                 lpss_deassert_reset(pdata);
 733
 734         return 0;
 735 }
 736
 737 static void acpi_lpss_dismiss(struct device *dev)
 738 {
 739         acpi_dev_runtime_suspend(dev);
 740 }
 741
 742 #ifdef CONFIG_PM_SLEEP
 743 static int acpi_lpss_suspend_late(struct device *dev)
 744 {
 745         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 746         int ret;
 747
 748         ret = pm_generic_suspend_late(dev);
 749         if (ret)
 750                 return ret;
 751
 752         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 753                 acpi_lpss_save_ctx(dev, pdata);
 754
 755         return acpi_dev_suspend_late(dev);
 756 }
 757
 758 static int acpi_lpss_resume_early(struct device *dev)
 759 {
 760         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 761         int ret;
 762
 763         ret = acpi_dev_resume_early(dev);
 764         if (ret)
 765                 return ret;
 766
 767         acpi_lpss_d3_to_d0_delay(pdata);
 768
 769         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 770                 acpi_lpss_restore_ctx(dev, pdata);
 771
 772         return pm_generic_resume_early(dev);
 773 }
 774 #endif /* CONFIG_PM_SLEEP */
 775
 776 /* IOSF SB for LPSS island */
 777 #define LPSS_IOSF_UNIT_LPIOEP           0xA0
 778 #define LPSS_IOSF_UNIT_LPIO1            0xAB
 779 #define LPSS_IOSF_UNIT_LPIO2            0xAC
 780
 781 #define LPSS_IOSF_PMCSR                 0x84
 782 #define LPSS_PMCSR_D0                   0
 783 #define LPSS_PMCSR_D3hot                3
 784 #define LPSS_PMCSR_Dx_MASK              GENMASK(1, 0)
 785
 786 #define LPSS_IOSF_GPIODEF0              0x154
 787 #define LPSS_GPIODEF0_DMA1_D3           BIT(2)
 788 #define LPSS_GPIODEF0_DMA2_D3           BIT(3)
 789 #define LPSS_GPIODEF0_DMA_D3_MASK       GENMASK(3, 2)
 790 #define LPSS_GPIODEF0_DMA_LLP           BIT(13)
 791
 792 static DEFINE_MUTEX(lpss_iosf_mutex);
 793
 794 static void lpss_iosf_enter_d3_state(void)
 795 {
 796         u32 value1 = 0;
 797         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 798         u32 value2 = LPSS_PMCSR_D3hot;
 799         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 800         /*
 801          * PMC provides an information about actual status of the LPSS devices.
 802          * Here we read the values related to LPSS power island, i.e. LPSS
 803          * devices, excluding both LPSS DMA controllers, along with SCC domain.
 804          */
 805         u32 func_dis, d3_sts_0, pmc_status;
 806         int ret;
 807
 808         ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
 809         if (ret)
 810                 return;
 811
 812         mutex_lock(&lpss_iosf_mutex);
 813
 814         ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
 815         if (ret)
 816                 goto exit;
 817
 818         /*
 819          * Get the status of entire LPSS power island per device basis.
 820          * Shutdown both LPSS DMA controllers if and only if all other devices
 821          * are already in D3hot.
 822          */
 823         pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
 824         if (pmc_status)
 825                 goto exit;
 826
 827         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 828                         LPSS_IOSF_PMCSR, value2, mask2);
 829
 830         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 831                         LPSS_IOSF_PMCSR, value2, mask2);
 832
 833         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 834                         LPSS_IOSF_GPIODEF0, value1, mask1);
 835 exit:
 836         mutex_unlock(&lpss_iosf_mutex);
 837 }
 838
 839 static void lpss_iosf_exit_d3_state(void)
 840 {
 841         u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
 842                      LPSS_GPIODEF0_DMA_LLP;
 843         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 844         u32 value2 = LPSS_PMCSR_D0;
 845         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 846
 847         mutex_lock(&lpss_iosf_mutex);
 848
 849         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 850                         LPSS_IOSF_GPIODEF0, value1, mask1);
 851
 852         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 853                         LPSS_IOSF_PMCSR, value2, mask2);
 854
 855         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 856                         LPSS_IOSF_PMCSR, value2, mask2);
 857
 858         mutex_unlock(&lpss_iosf_mutex);
 859 }
 860
 861 static int acpi_lpss_runtime_suspend(struct device *dev)
 862 {
 863         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 864         int ret;
 865
 866         ret = pm_generic_runtime_suspend(dev);
 867         if (ret)
 868                 return ret;
 869
 870         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 871                 acpi_lpss_save_ctx(dev, pdata);
 872
 873         ret = acpi_dev_runtime_suspend(dev);
 874
 875         /*
 876          * This call must be last in the sequence, otherwise PMC will return
 877          * wrong status for devices being about to be powered off. See
 878          * lpss_iosf_enter_d3_state() for further information.
 879          */
 880         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
 881                 lpss_iosf_enter_d3_state();
 882
 883         return ret;
 884 }
 885
 886 static int acpi_lpss_runtime_resume(struct device *dev)
 887 {
 888         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 889         int ret;
 890
 891         /*
 892          * This call is kept first to be in symmetry with
 893          * acpi_lpss_runtime_suspend() one.
 894          */
 895         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
 896                 lpss_iosf_exit_d3_state();
 897
 898         ret = acpi_dev_runtime_resume(dev);
 899         if (ret)
 900                 return ret;
 901
 902         acpi_lpss_d3_to_d0_delay(pdata);
 903
 904         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 905                 acpi_lpss_restore_ctx(dev, pdata);
 906
 907         return pm_generic_runtime_resume(dev);
 908 }
 909 #endif /* CONFIG_PM */
 910
 911 static struct dev_pm_domain acpi_lpss_pm_domain = {
 912 #ifdef CONFIG_PM
 913         .activate = acpi_lpss_activate,
 914         .dismiss = acpi_lpss_dismiss,
 915 #endif
 916         .ops = {
 917 #ifdef CONFIG_PM
 918 #ifdef CONFIG_PM_SLEEP
 919                 .prepare = acpi_subsys_prepare,
 920                 .complete = pm_complete_with_resume_check,
 921                 .suspend = acpi_subsys_suspend,
 922                 .suspend_late = acpi_lpss_suspend_late,
 923                 .resume_early = acpi_lpss_resume_early,
 924                 .freeze = acpi_subsys_freeze,
 925                 .poweroff = acpi_subsys_suspend,
 926                 .poweroff_late = acpi_lpss_suspend_late,
 927                 .restore_early = acpi_lpss_resume_early,
 928 #endif
 929                 .runtime_suspend = acpi_lpss_runtime_suspend,
 930                 .runtime_resume = acpi_lpss_runtime_resume,
 931 #endif
 932         },
 933 };
 934
 935 static int acpi_lpss_platform_notify(struct notifier_block *nb,
 936                                      unsigned long action, void *data)
 937 {
 938         struct platform_device *pdev = to_platform_device(data);
 939         struct lpss_private_data *pdata;
 940         struct acpi_device *adev;
 941         const struct acpi_device_id *id;
 942
 943         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
 944         if (!id || !id->driver_data)
 945                 return 0;
 946
 947         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 948                 return 0;
 949
 950         pdata = acpi_driver_data(adev);
 951         if (!pdata)
 952                 return 0;
 953
 954         if (pdata->mmio_base &&
 955             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
 956                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
 957                 return 0;
 958         }
 959
 960         switch (action) {
 961         case BUS_NOTIFY_BIND_DRIVER:
 962                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
 963                 break;
 964         case BUS_NOTIFY_DRIVER_NOT_BOUND:
 965         case BUS_NOTIFY_UNBOUND_DRIVER:
 966                 dev_pm_domain_set(&pdev->dev, NULL);
 967                 break;
 968         case BUS_NOTIFY_ADD_DEVICE:
 969                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
 970                 if (pdata->dev_desc->flags & LPSS_LTR)
 971                         return sysfs_create_group(&pdev->dev.kobj,
 972                                                   &lpss_attr_group);
 973                 break;
 974         case BUS_NOTIFY_DEL_DEVICE:
 975                 if (pdata->dev_desc->flags & LPSS_LTR)
 976                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
 977                 dev_pm_domain_set(&pdev->dev, NULL);
 978                 break;
 979         default:
 980                 break;
 981         }
 982
 983         return 0;
 984 }
 985
 986 static struct notifier_block acpi_lpss_nb = {
 987         .notifier_call = acpi_lpss_platform_notify,
 988 };
 989
 990 static void acpi_lpss_bind(struct device *dev)
 991 {
 992         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 993
 994         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
 995                 return;
 996
 997         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
 998                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
 999         else
1000                 dev_err(dev, "MMIO size insufficient to access LTR\n");
1001 }
1002
1003 static void acpi_lpss_unbind(struct device *dev)
1004 {
1005         dev->power.set_latency_tolerance = NULL;
1006 }
1007
1008 static struct acpi_scan_handler lpss_handler = {
1009         .ids = acpi_lpss_device_ids,
1010         .attach = acpi_lpss_create_device,
1011         .bind = acpi_lpss_bind,
1012         .unbind = acpi_lpss_unbind,
1013 };
1014
1015 void __init acpi_lpss_init(void)
1016 {
1017         const struct x86_cpu_id *id;
1018         int ret;
1019
1020         ret = lpt_clk_init();
1021         if (ret)
1022                 return;
1023
1024         id = x86_match_cpu(lpss_cpu_ids);
1025         if (id)
1026                 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1027
1028         bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1029         acpi_scan_add_handler(&lpss_handler);
1030 }
1031
1032 #else
1033
1034 static struct acpi_scan_handler lpss_handler = {
1035         .ids = acpi_lpss_device_ids,
1036 };
1037
1038 void __init acpi_lpss_init(void)
1039 {
1040         acpi_scan_add_handler(&lpss_handler);
1041 }
1042
1043 #endif /* CONFIG_X86_INTEL_LPSS */