drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/mutex.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/platform_data/clk-lpss.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/delay.h>
  24
  25 #include "internal.h"
  26
  27 ACPI_MODULE_NAME("acpi_lpss");
  28
  29 #ifdef CONFIG_X86_INTEL_LPSS
  30
  31 #include <asm/cpu_device_id.h>
  32 #include <asm/intel-family.h>
  33 #include <asm/iosf_mbi.h>
  34 #include <asm/pmc_atom.h>
  35
  36 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  37
  38 #define LPSS_CLK_SIZE   0x04
  39 #define LPSS_LTR_SIZE   0x18
  40
  41 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  42 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  43 #define LPSS_RESETS                     0x04
  44 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  45 #define LPSS_RESETS_RESET_APB           BIT(1)
  46 #define LPSS_GENERAL                    0x08
  47 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  48 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  49 #define LPSS_SW_LTR                     0x10
  50 #define LPSS_AUTO_LTR                   0x14
  51 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  52 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  53 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  54 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  55 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  56 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  57 #define LPSS_LTR_MAX_VAL                0x3FF
  58 #define LPSS_TX_INT                     0x20
  59 #define LPSS_TX_INT_MASK                BIT(1)
  60
  61 #define LPSS_PRV_REG_COUNT              9
  62
  63 /* LPSS Flags */
  64 #define LPSS_CLK                        BIT(0)
  65 #define LPSS_CLK_GATE                   BIT(1)
  66 #define LPSS_CLK_DIVIDER                BIT(2)
  67 #define LPSS_LTR                        BIT(3)
  68 #define LPSS_SAVE_CTX                   BIT(4)
  69 #define LPSS_NO_D3_DELAY                BIT(5)
  70
  71 struct lpss_private_data;
  72
  73 struct lpss_device_desc {
  74         unsigned int flags;
  75         const char *clk_con_id;
  76         unsigned int prv_offset;
  77         size_t prv_size_override;
  78         struct property_entry *properties;
  79         void (*setup)(struct lpss_private_data *pdata);
  80 };
  81
  82 static const struct lpss_device_desc lpss_dma_desc = {
  83         .flags = LPSS_CLK,
  84 };
  85
  86 struct lpss_private_data {
  87         void __iomem *mmio_base;
  88         resource_size_t mmio_size;
  89         unsigned int fixed_clk_rate;
  90         struct clk *clk;
  91         const struct lpss_device_desc *dev_desc;
  92         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  93 };
  94
  95 /* LPSS run time quirks */
  96 static unsigned int lpss_quirks;
  97
  98 /*
  99  * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
 100  *
 101  * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
 102  * it can be powered off automatically whenever the last LPSS device goes down.
 103  * In case of no power any access to the DMA controller will hang the system.
 104  * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
 105  * well as on ASuS T100TA transformer.
 106  *
 107  * This quirk overrides power state of entire LPSS island to keep DMA powered
 108  * on whenever we have at least one other device in use.
 109  */
 110 #define LPSS_QUIRK_ALWAYS_POWER_ON      BIT(0)
 111
 112 /* UART Component Parameter Register */
 113 #define LPSS_UART_CPR                   0xF4
 114 #define LPSS_UART_CPR_AFCE              BIT(4)
 115
 116 static void lpss_uart_setup(struct lpss_private_data *pdata)
 117 {
 118         unsigned int offset;
 119         u32 val;
 120
 121         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
 122         val = readl(pdata->mmio_base + offset);
 123         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
 124
 125         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 126         if (!(val & LPSS_UART_CPR_AFCE)) {
 127                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 128                 val = readl(pdata->mmio_base + offset);
 129                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 130                 writel(val, pdata->mmio_base + offset);
 131         }
 132 }
 133
 134 static void lpss_deassert_reset(struct lpss_private_data *pdata)
 135 {
 136         unsigned int offset;
 137         u32 val;
 138
 139         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 140         val = readl(pdata->mmio_base + offset);
 141         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 142         writel(val, pdata->mmio_base + offset);
 143 }
 144
 145 #define LPSS_I2C_ENABLE                 0x6c
 146
 147 static void byt_i2c_setup(struct lpss_private_data *pdata)
 148 {
 149         lpss_deassert_reset(pdata);
 150
 151         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 152                 pdata->fixed_clk_rate = 133000000;
 153
 154         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
 155 }
 156
 157 static const struct lpss_device_desc lpt_dev_desc = {
 158         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 159         .prv_offset = 0x800,
 160 };
 161
 162 static const struct lpss_device_desc lpt_i2c_dev_desc = {
 163         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 164         .prv_offset = 0x800,
 165 };
 166
 167 static struct property_entry uart_properties[] = {
 168         PROPERTY_ENTRY_U32("reg-io-width", 4),
 169         PROPERTY_ENTRY_U32("reg-shift", 2),
 170         PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
 171         { },
 172 };
 173
 174 static const struct lpss_device_desc lpt_uart_dev_desc = {
 175         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 176         .clk_con_id = "baudclk",
 177         .prv_offset = 0x800,
 178         .setup = lpss_uart_setup,
 179         .properties = uart_properties,
 180 };
 181
 182 static const struct lpss_device_desc lpt_sdio_dev_desc = {
 183         .flags = LPSS_LTR,
 184         .prv_offset = 0x1000,
 185         .prv_size_override = 0x1018,
 186 };
 187
 188 static const struct lpss_device_desc byt_pwm_dev_desc = {
 189         .flags = LPSS_SAVE_CTX,
 190         .prv_offset = 0x800,
 191 };
 192
 193 static const struct lpss_device_desc bsw_pwm_dev_desc = {
 194         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 195         .prv_offset = 0x800,
 196 };
 197
 198 static const struct lpss_device_desc byt_uart_dev_desc = {
 199         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 200         .clk_con_id = "baudclk",
 201         .prv_offset = 0x800,
 202         .setup = lpss_uart_setup,
 203         .properties = uart_properties,
 204 };
 205
 206 static const struct lpss_device_desc bsw_uart_dev_desc = {
 207         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 208                         | LPSS_NO_D3_DELAY,
 209         .clk_con_id = "baudclk",
 210         .prv_offset = 0x800,
 211         .setup = lpss_uart_setup,
 212         .properties = uart_properties,
 213 };
 214
 215 static const struct lpss_device_desc byt_spi_dev_desc = {
 216         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 217         .prv_offset = 0x400,
 218 };
 219
 220 static const struct lpss_device_desc byt_sdio_dev_desc = {
 221         .flags = LPSS_CLK,
 222 };
 223
 224 static const struct lpss_device_desc byt_i2c_dev_desc = {
 225         .flags = LPSS_CLK | LPSS_SAVE_CTX,
 226         .prv_offset = 0x800,
 227         .setup = byt_i2c_setup,
 228 };
 229
 230 static const struct lpss_device_desc bsw_i2c_dev_desc = {
 231         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 232         .prv_offset = 0x800,
 233         .setup = byt_i2c_setup,
 234 };
 235
 236 static const struct lpss_device_desc bsw_spi_dev_desc = {
 237         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 238                         | LPSS_NO_D3_DELAY,
 239         .prv_offset = 0x400,
 240         .setup = lpss_deassert_reset,
 241 };
 242
 243 #define ICPU(model)     { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 244
 245 static const struct x86_cpu_id lpss_cpu_ids[] = {
 246         ICPU(INTEL_FAM6_ATOM_SILVERMONT),       /* Valleyview, Bay Trail */
 247         ICPU(INTEL_FAM6_ATOM_AIRMONT),  /* Braswell, Cherry Trail */
 248         {}
 249 };
 250
 251 #else
 252
 253 #define LPSS_ADDR(desc) (0UL)
 254
 255 #endif /* CONFIG_X86_INTEL_LPSS */
 256
 257 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 258         /* Generic LPSS devices */
 259         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 260
 261         /* Lynxpoint LPSS devices */
 262         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 263         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 264         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 265         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 266         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 267         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 268         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 269         { "INT33C7", },
 270
 271         /* BayTrail LPSS devices */
 272         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 273         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 274         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 275         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 276         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 277         { "INT33B2", },
 278         { "INT33FC", },
 279
 280         /* Braswell LPSS devices */
 281         { "80862286", LPSS_ADDR(lpss_dma_desc) },
 282         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
 283         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
 284         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
 285         { "808622C0", LPSS_ADDR(lpss_dma_desc) },
 286         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
 287
 288         /* Broadwell LPSS devices */
 289         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 290         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 291         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 292         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 293         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 294         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 295         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 296         { "INT3437", },
 297
 298         /* Wildcat Point LPSS devices */
 299         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 300
 301         { }
 302 };
 303
 304 #ifdef CONFIG_X86_INTEL_LPSS
 305
 306 static int is_memory(struct acpi_resource *res, void *not_used)
 307 {
 308         struct resource r;
 309         return !acpi_dev_resource_memory(res, &r);
 310 }
 311
 312 /* LPSS main clock device. */
 313 static struct platform_device *lpss_clk_dev;
 314
 315 static inline void lpt_register_clock_device(void)
 316 {
 317         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 318 }
 319
 320 static int register_device_clock(struct acpi_device *adev,
 321                                  struct lpss_private_data *pdata)
 322 {
 323         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 324         const char *devname = dev_name(&adev->dev);
 325         struct clk *clk = ERR_PTR(-ENODEV);
 326         struct lpss_clk_data *clk_data;
 327         const char *parent, *clk_name;
 328         void __iomem *prv_base;
 329
 330         if (!lpss_clk_dev)
 331                 lpt_register_clock_device();
 332
 333         clk_data = platform_get_drvdata(lpss_clk_dev);
 334         if (!clk_data)
 335                 return -ENODEV;
 336         clk = clk_data->clk;
 337
 338         if (!pdata->mmio_base
 339             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 340                 return -ENODATA;
 341
 342         parent = clk_data->name;
 343         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 344
 345         if (pdata->fixed_clk_rate) {
 346                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 347                                               pdata->fixed_clk_rate);
 348                 goto out;
 349         }
 350
 351         if (dev_desc->flags & LPSS_CLK_GATE) {
 352                 clk = clk_register_gate(NULL, devname, parent, 0,
 353                                         prv_base, 0, 0, NULL);
 354                 parent = devname;
 355         }
 356
 357         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 358                 /* Prevent division by zero */
 359                 if (!readl(prv_base))
 360                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 361
 362                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 363                 if (!clk_name)
 364                         return -ENOMEM;
 365                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 366                                                       0, prv_base,
 367                                                       1, 15, 16, 15, 0, NULL);
 368                 parent = clk_name;
 369
 370                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 371                 if (!clk_name) {
 372                         kfree(parent);
 373                         return -ENOMEM;
 374                 }
 375                 clk = clk_register_gate(NULL, clk_name, parent,
 376                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 377                                         prv_base, 31, 0, NULL);
 378                 kfree(parent);
 379                 kfree(clk_name);
 380         }
 381 out:
 382         if (IS_ERR(clk))
 383                 return PTR_ERR(clk);
 384
 385         pdata->clk = clk;
 386         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
 387         return 0;
 388 }
 389
 390 static int acpi_lpss_create_device(struct acpi_device *adev,
 391                                    const struct acpi_device_id *id)
 392 {
 393         const struct lpss_device_desc *dev_desc;
 394         struct lpss_private_data *pdata;
 395         struct resource_entry *rentry;
 396         struct list_head resource_list;
 397         struct platform_device *pdev;
 398         int ret;
 399
 400         dev_desc = (const struct lpss_device_desc *)id->driver_data;
 401         if (!dev_desc) {
 402                 pdev = acpi_create_platform_device(adev, NULL);
 403                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 404         }
 405         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 406         if (!pdata)
 407                 return -ENOMEM;
 408
 409         INIT_LIST_HEAD(&resource_list);
 410         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 411         if (ret < 0)
 412                 goto err_out;
 413
 414         list_for_each_entry(rentry, &resource_list, node)
 415                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
 416                         if (dev_desc->prv_size_override)
 417                                 pdata->mmio_size = dev_desc->prv_size_override;
 418                         else
 419                                 pdata->mmio_size = resource_size(rentry->res);
 420                         pdata->mmio_base = ioremap(rentry->res->start,
 421                                                    pdata->mmio_size);
 422                         break;
 423                 }
 424
 425         acpi_dev_free_resource_list(&resource_list);
 426
 427         if (!pdata->mmio_base) {
 428                 ret = -ENOMEM;
 429                 goto err_out;
 430         }
 431
 432         pdata->dev_desc = dev_desc;
 433
 434         if (dev_desc->setup)
 435                 dev_desc->setup(pdata);
 436
 437         if (dev_desc->flags & LPSS_CLK) {
 438                 ret = register_device_clock(adev, pdata);
 439                 if (ret) {
 440                         /* Skip the device, but continue the namespace scan. */
 441                         ret = 0;
 442                         goto err_out;
 443                 }
 444         }
 445
 446         /*
 447          * This works around a known issue in ACPI tables where LPSS devices
 448          * have _PS0 and _PS3 without _PSC (and no power resources), so
 449          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 450          */
 451         acpi_device_fix_up_power(adev);
 452
 453         adev->driver_data = pdata;
 454         pdev = acpi_create_platform_device(adev, dev_desc->properties);
 455         if (!IS_ERR_OR_NULL(pdev)) {
 456                 return 1;
 457         }
 458
 459         ret = PTR_ERR(pdev);
 460         adev->driver_data = NULL;
 461
 462  err_out:
 463         kfree(pdata);
 464         return ret;
 465 }
 466
 467 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 468 {
 469         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 470 }
 471
 472 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 473                              unsigned int reg)
 474 {
 475         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 476 }
 477
 478 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 479 {
 480         struct acpi_device *adev;
 481         struct lpss_private_data *pdata;
 482         unsigned long flags;
 483         int ret;
 484
 485         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 486         if (WARN_ON(ret))
 487                 return ret;
 488
 489         spin_lock_irqsave(&dev->power.lock, flags);
 490         if (pm_runtime_suspended(dev)) {
 491                 ret = -EAGAIN;
 492                 goto out;
 493         }
 494         pdata = acpi_driver_data(adev);
 495         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 496                 ret = -ENODEV;
 497                 goto out;
 498         }
 499         *val = __lpss_reg_read(pdata, reg);
 500
 501  out:
 502         spin_unlock_irqrestore(&dev->power.lock, flags);
 503         return ret;
 504 }
 505
 506 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 507                              char *buf)
 508 {
 509         u32 ltr_value = 0;
 510         unsigned int reg;
 511         int ret;
 512
 513         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 514         ret = lpss_reg_read(dev, reg, &ltr_value);
 515         if (ret)
 516                 return ret;
 517
 518         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 519 }
 520
 521 static ssize_t lpss_ltr_mode_show(struct device *dev,
 522                                   struct device_attribute *attr, char *buf)
 523 {
 524         u32 ltr_mode = 0;
 525         char *outstr;
 526         int ret;
 527
 528         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 529         if (ret)
 530                 return ret;
 531
 532         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 533         return sprintf(buf, "%s\n", outstr);
 534 }
 535
 536 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 537 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 538 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 539
 540 static struct attribute *lpss_attrs[] = {
 541         &dev_attr_auto_ltr.attr,
 542         &dev_attr_sw_ltr.attr,
 543         &dev_attr_ltr_mode.attr,
 544         NULL,
 545 };
 546
 547 static struct attribute_group lpss_attr_group = {
 548         .attrs = lpss_attrs,
 549         .name = "lpss_ltr",
 550 };
 551
 552 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 553 {
 554         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 555         u32 ltr_mode, ltr_val;
 556
 557         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 558         if (val < 0) {
 559                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 560                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 561                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 562                 }
 563                 return;
 564         }
 565         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 566         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 567                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 568                 val = LPSS_LTR_MAX_VAL;
 569         } else if (val > LPSS_LTR_MAX_VAL) {
 570                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 571                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 572         } else {
 573                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 574         }
 575         ltr_val |= val;
 576         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 577         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 578                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 579                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 580         }
 581 }
 582
 583 #ifdef CONFIG_PM
 584 /**
 585  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 586  * @dev: LPSS device
 587  * @pdata: pointer to the private data of the LPSS device
 588  *
 589  * Most LPSS devices have private registers which may loose their context when
 590  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 591  * prv_reg_ctx array.
 592  */
 593 static void acpi_lpss_save_ctx(struct device *dev,
 594                                struct lpss_private_data *pdata)
 595 {
 596         unsigned int i;
 597
 598         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 599                 unsigned long offset = i * sizeof(u32);
 600
 601                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 602                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 603                         pdata->prv_reg_ctx[i], offset);
 604         }
 605 }
 606
 607 /**
 608  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 609  * @dev: LPSS device
 610  * @pdata: pointer to the private data of the LPSS device
 611  *
 612  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 613  */
 614 static void acpi_lpss_restore_ctx(struct device *dev,
 615                                   struct lpss_private_data *pdata)
 616 {
 617         unsigned int i;
 618
 619         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 620                 unsigned long offset = i * sizeof(u32);
 621
 622                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 623                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 624                         pdata->prv_reg_ctx[i], offset);
 625         }
 626 }
 627
 628 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
 629 {
 630         /*
 631          * The following delay is needed or the subsequent write operations may
 632          * fail. The LPSS devices are actually PCI devices and the PCI spec
 633          * expects 10ms delay before the device can be accessed after D3 to D0
 634          * transition. However some platforms like BSW does not need this delay.
 635          */
 636         unsigned int delay = 10;        /* default 10ms delay */
 637
 638         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
 639                 delay = 0;
 640
 641         msleep(delay);
 642 }
 643
 644 static int acpi_lpss_activate(struct device *dev)
 645 {
 646         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 647         int ret;
 648
 649         ret = acpi_dev_runtime_resume(dev);
 650         if (ret)
 651                 return ret;
 652
 653         acpi_lpss_d3_to_d0_delay(pdata);
 654
 655         /*
 656          * This is called only on ->probe() stage where a device is either in
 657          * known state defined by BIOS or most likely powered off. Due to this
 658          * we have to deassert reset line to be sure that ->probe() will
 659          * recognize the device.
 660          */
 661         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 662                 lpss_deassert_reset(pdata);
 663
 664         return 0;
 665 }
 666
 667 static void acpi_lpss_dismiss(struct device *dev)
 668 {
 669         acpi_dev_runtime_suspend(dev);
 670 }
 671
 672 #ifdef CONFIG_PM_SLEEP
 673 static int acpi_lpss_suspend_late(struct device *dev)
 674 {
 675         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 676         int ret;
 677
 678         ret = pm_generic_suspend_late(dev);
 679         if (ret)
 680                 return ret;
 681
 682         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 683                 acpi_lpss_save_ctx(dev, pdata);
 684
 685         return acpi_dev_suspend_late(dev);
 686 }
 687
 688 static int acpi_lpss_resume_early(struct device *dev)
 689 {
 690         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 691         int ret;
 692
 693         ret = acpi_dev_resume_early(dev);
 694         if (ret)
 695                 return ret;
 696
 697         acpi_lpss_d3_to_d0_delay(pdata);
 698
 699         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 700                 acpi_lpss_restore_ctx(dev, pdata);
 701
 702         return pm_generic_resume_early(dev);
 703 }
 704 #endif /* CONFIG_PM_SLEEP */
 705
 706 /* IOSF SB for LPSS island */
 707 #define LPSS_IOSF_UNIT_LPIOEP           0xA0
 708 #define LPSS_IOSF_UNIT_LPIO1            0xAB
 709 #define LPSS_IOSF_UNIT_LPIO2            0xAC
 710
 711 #define LPSS_IOSF_PMCSR                 0x84
 712 #define LPSS_PMCSR_D0                   0
 713 #define LPSS_PMCSR_D3hot                3
 714 #define LPSS_PMCSR_Dx_MASK              GENMASK(1, 0)
 715
 716 #define LPSS_IOSF_GPIODEF0              0x154
 717 #define LPSS_GPIODEF0_DMA1_D3           BIT(2)
 718 #define LPSS_GPIODEF0_DMA2_D3           BIT(3)
 719 #define LPSS_GPIODEF0_DMA_D3_MASK       GENMASK(3, 2)
 720
 721 static DEFINE_MUTEX(lpss_iosf_mutex);
 722
 723 static void lpss_iosf_enter_d3_state(void)
 724 {
 725         u32 value1 = 0;
 726         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;
 727         u32 value2 = LPSS_PMCSR_D3hot;
 728         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 729         /*
 730          * PMC provides an information about actual status of the LPSS devices.
 731          * Here we read the values related to LPSS power island, i.e. LPSS
 732          * devices, excluding both LPSS DMA controllers, along with SCC domain.
 733          */
 734         u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe;
 735         int ret;
 736
 737         ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
 738         if (ret)
 739                 return;
 740
 741         mutex_lock(&lpss_iosf_mutex);
 742
 743         ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
 744         if (ret)
 745                 goto exit;
 746
 747         /*
 748          * Get the status of entire LPSS power island per device basis.
 749          * Shutdown both LPSS DMA controllers if and only if all other devices
 750          * are already in D3hot.
 751          */
 752         pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask;
 753         if (pmc_status)
 754                 goto exit;
 755
 756         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 757                         LPSS_IOSF_PMCSR, value2, mask2);
 758
 759         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 760                         LPSS_IOSF_PMCSR, value2, mask2);
 761
 762         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 763                         LPSS_IOSF_GPIODEF0, value1, mask1);
 764 exit:
 765         mutex_unlock(&lpss_iosf_mutex);
 766 }
 767
 768 static void lpss_iosf_exit_d3_state(void)
 769 {
 770         u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3;
 771         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;
 772         u32 value2 = LPSS_PMCSR_D0;
 773         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 774
 775         mutex_lock(&lpss_iosf_mutex);
 776
 777         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 778                         LPSS_IOSF_GPIODEF0, value1, mask1);
 779
 780         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 781                         LPSS_IOSF_PMCSR, value2, mask2);
 782
 783         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 784                         LPSS_IOSF_PMCSR, value2, mask2);
 785
 786         mutex_unlock(&lpss_iosf_mutex);
 787 }
 788
 789 static int acpi_lpss_runtime_suspend(struct device *dev)
 790 {
 791         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 792         int ret;
 793
 794         ret = pm_generic_runtime_suspend(dev);
 795         if (ret)
 796                 return ret;
 797
 798         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 799                 acpi_lpss_save_ctx(dev, pdata);
 800
 801         ret = acpi_dev_runtime_suspend(dev);
 802
 803         /*
 804          * This call must be last in the sequence, otherwise PMC will return
 805          * wrong status for devices being about to be powered off. See
 806          * lpss_iosf_enter_d3_state() for further information.
 807          */
 808         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
 809                 lpss_iosf_enter_d3_state();
 810
 811         return ret;
 812 }
 813
 814 static int acpi_lpss_runtime_resume(struct device *dev)
 815 {
 816         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 817         int ret;
 818
 819         /*
 820          * This call is kept first to be in symmetry with
 821          * acpi_lpss_runtime_suspend() one.
 822          */
 823         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
 824                 lpss_iosf_exit_d3_state();
 825
 826         ret = acpi_dev_runtime_resume(dev);
 827         if (ret)
 828                 return ret;
 829
 830         acpi_lpss_d3_to_d0_delay(pdata);
 831
 832         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 833                 acpi_lpss_restore_ctx(dev, pdata);
 834
 835         return pm_generic_runtime_resume(dev);
 836 }
 837 #endif /* CONFIG_PM */
 838
 839 static struct dev_pm_domain acpi_lpss_pm_domain = {
 840 #ifdef CONFIG_PM
 841         .activate = acpi_lpss_activate,
 842         .dismiss = acpi_lpss_dismiss,
 843 #endif
 844         .ops = {
 845 #ifdef CONFIG_PM
 846 #ifdef CONFIG_PM_SLEEP
 847                 .prepare = acpi_subsys_prepare,
 848                 .complete = pm_complete_with_resume_check,
 849                 .suspend = acpi_subsys_suspend,
 850                 .suspend_late = acpi_lpss_suspend_late,
 851                 .resume_early = acpi_lpss_resume_early,
 852                 .freeze = acpi_subsys_freeze,
 853                 .poweroff = acpi_subsys_suspend,
 854                 .poweroff_late = acpi_lpss_suspend_late,
 855                 .restore_early = acpi_lpss_resume_early,
 856 #endif
 857                 .runtime_suspend = acpi_lpss_runtime_suspend,
 858                 .runtime_resume = acpi_lpss_runtime_resume,
 859 #endif
 860         },
 861 };
 862
 863 static int acpi_lpss_platform_notify(struct notifier_block *nb,
 864                                      unsigned long action, void *data)
 865 {
 866         struct platform_device *pdev = to_platform_device(data);
 867         struct lpss_private_data *pdata;
 868         struct acpi_device *adev;
 869         const struct acpi_device_id *id;
 870
 871         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
 872         if (!id || !id->driver_data)
 873                 return 0;
 874
 875         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 876                 return 0;
 877
 878         pdata = acpi_driver_data(adev);
 879         if (!pdata)
 880                 return 0;
 881
 882         if (pdata->mmio_base &&
 883             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
 884                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
 885                 return 0;
 886         }
 887
 888         switch (action) {
 889         case BUS_NOTIFY_BIND_DRIVER:
 890                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
 891                 break;
 892         case BUS_NOTIFY_DRIVER_NOT_BOUND:
 893         case BUS_NOTIFY_UNBOUND_DRIVER:
 894                 dev_pm_domain_set(&pdev->dev, NULL);
 895                 break;
 896         case BUS_NOTIFY_ADD_DEVICE:
 897                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
 898                 if (pdata->dev_desc->flags & LPSS_LTR)
 899                         return sysfs_create_group(&pdev->dev.kobj,
 900                                                   &lpss_attr_group);
 901                 break;
 902         case BUS_NOTIFY_DEL_DEVICE:
 903                 if (pdata->dev_desc->flags & LPSS_LTR)
 904                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
 905                 dev_pm_domain_set(&pdev->dev, NULL);
 906                 break;
 907         default:
 908                 break;
 909         }
 910
 911         return 0;
 912 }
 913
 914 static struct notifier_block acpi_lpss_nb = {
 915         .notifier_call = acpi_lpss_platform_notify,
 916 };
 917
 918 static void acpi_lpss_bind(struct device *dev)
 919 {
 920         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 921
 922         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
 923                 return;
 924
 925         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
 926                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
 927         else
 928                 dev_err(dev, "MMIO size insufficient to access LTR\n");
 929 }
 930
 931 static void acpi_lpss_unbind(struct device *dev)
 932 {
 933         dev->power.set_latency_tolerance = NULL;
 934 }
 935
 936 static struct acpi_scan_handler lpss_handler = {
 937         .ids = acpi_lpss_device_ids,
 938         .attach = acpi_lpss_create_device,
 939         .bind = acpi_lpss_bind,
 940         .unbind = acpi_lpss_unbind,
 941 };
 942
 943 void __init acpi_lpss_init(void)
 944 {
 945         const struct x86_cpu_id *id;
 946         int ret;
 947
 948         ret = lpt_clk_init();
 949         if (ret)
 950                 return;
 951
 952         id = x86_match_cpu(lpss_cpu_ids);
 953         if (id)
 954                 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
 955
 956         bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
 957         acpi_scan_add_handler(&lpss_handler);
 958 }
 959
 960 #else
 961
 962 static struct acpi_scan_handler lpss_handler = {
 963         .ids = acpi_lpss_device_ids,
 964 };
 965
 966 void __init acpi_lpss_init(void)
 967 {
 968         acpi_scan_add_handler(&lpss_handler);
 969 }
 970
 971 #endif /* CONFIG_X86_INTEL_LPSS */