drivers/char/hw_random/imx-rngc.c

   1 /*
   2  * RNG driver for Freescale RNGC
   3  *
   4  * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
   5  * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
   6  *
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/clk.h>
  19 #include <linux/err.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/hw_random.h>
  23 #include <linux/completion.h>
  24 #include <linux/io.h>
  25
  26 #define RNGC_COMMAND                    0x0004
  27 #define RNGC_CONTROL                    0x0008
  28 #define RNGC_STATUS                     0x000C
  29 #define RNGC_ERROR                      0x0010
  30 #define RNGC_FIFO                       0x0014
  31
  32 #define RNGC_CMD_CLR_ERR                0x00000020
  33 #define RNGC_CMD_CLR_INT                0x00000010
  34 #define RNGC_CMD_SEED                   0x00000002
  35 #define RNGC_CMD_SELF_TEST              0x00000001
  36
  37 #define RNGC_CTRL_MASK_ERROR            0x00000040
  38 #define RNGC_CTRL_MASK_DONE             0x00000020
  39
  40 #define RNGC_STATUS_ERROR               0x00010000
  41 #define RNGC_STATUS_FIFO_LEVEL_MASK     0x00000f00
  42 #define RNGC_STATUS_FIFO_LEVEL_SHIFT    8
  43 #define RNGC_STATUS_SEED_DONE           0x00000020
  44 #define RNGC_STATUS_ST_DONE             0x00000010
  45
  46 #define RNGC_ERROR_STATUS_STAT_ERR      0x00000008
  47
  48 #define RNGC_TIMEOUT  3000 /* 3 sec */
  49
  50
  51 static bool self_test = true;
  52 module_param(self_test, bool, 0);
  53
  54 struct imx_rngc {
  55         struct device           *dev;
  56         struct clk              *clk;
  57         void __iomem            *base;
  58         struct hwrng            rng;
  59         struct completion       rng_op_done;
  60         /*
  61          * err_reg is written only by the irq handler and read only
  62          * when interrupts are masked, we need no spinlock
  63          */
  64         u32                     err_reg;
  65 };
  66
  67
  68 static inline void imx_rngc_irq_mask_clear(struct imx_rngc *rngc)
  69 {
  70         u32 ctrl, cmd;
  71
  72         /* mask interrupts */
  73         ctrl = readl(rngc->base + RNGC_CONTROL);
  74         ctrl |= RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR;
  75         writel(ctrl, rngc->base + RNGC_CONTROL);
  76
  77         /*
  78          * CLR_INT clears the interrupt only if there's no error
  79          * CLR_ERR clear the interrupt and the error register if there
  80          * is an error
  81          */
  82         cmd = readl(rngc->base + RNGC_COMMAND);
  83         cmd |= RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR;
  84         writel(cmd, rngc->base + RNGC_COMMAND);
  85 }
  86
  87 static inline void imx_rngc_irq_unmask(struct imx_rngc *rngc)
  88 {
  89         u32 ctrl;
  90
  91         ctrl = readl(rngc->base + RNGC_CONTROL);
  92         ctrl &= ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR);
  93         writel(ctrl, rngc->base + RNGC_CONTROL);
  94 }
  95
  96 static int imx_rngc_self_test(struct imx_rngc *rngc)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         imx_rngc_irq_unmask(rngc);
 102
 103         /* run self test */
 104         cmd = readl(rngc->base + RNGC_COMMAND);
 105         writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND);
 106
 107         ret = wait_for_completion_timeout(&rngc->rng_op_done, RNGC_TIMEOUT);
 108         if (!ret) {
 109                 imx_rngc_irq_mask_clear(rngc);
 110                 return -ETIMEDOUT;
 111         }
 112
 113         if (rngc->err_reg != 0) {
 114                 imx_rngc_irq_mask_clear(rngc);
 115                 return -EIO;
 116         }
 117
 118         return 0;
 119 }
 120
 121 static int imx_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait)
 122 {
 123         struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
 124         unsigned int status;
 125         unsigned int level;
 126         int retval = 0;
 127
 128         while (max >= sizeof(u32)) {
 129                 status = readl(rngc->base + RNGC_STATUS);
 130
 131                 /* is there some error while reading this random number? */
 132                 if (status & RNGC_STATUS_ERROR)
 133                         break;
 134
 135                 /* how many random numbers are in FIFO? [0-16] */
 136                 level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
 137                         RNGC_STATUS_FIFO_LEVEL_SHIFT;
 138
 139                 if (level) {
 140                         /* retrieve a random number from FIFO */
 141                         *(u32 *)data = readl(rngc->base + RNGC_FIFO);
 142
 143                         retval += sizeof(u32);
 144                         data += sizeof(u32);
 145                         max -= sizeof(u32);
 146                 }
 147         }
 148
 149         return retval ? retval : -EIO;
 150 }
 151
 152 static irqreturn_t imx_rngc_irq(int irq, void *priv)
 153 {
 154         struct imx_rngc *rngc = (struct imx_rngc *)priv;
 155         u32 status;
 156
 157         /*
 158          * clearing the interrupt will also clear the error register
 159          * read error and status before clearing
 160          */
 161         status = readl(rngc->base + RNGC_STATUS);
 162         rngc->err_reg = readl(rngc->base + RNGC_ERROR);
 163
 164         imx_rngc_irq_mask_clear(rngc);
 165
 166         if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
 167                 complete(&rngc->rng_op_done);
 168
 169         return IRQ_HANDLED;
 170 }
 171
 172 static int imx_rngc_init(struct hwrng *rng)
 173 {
 174         struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
 175         u32 cmd;
 176         int ret;
 177
 178         /* clear error */
 179         cmd = readl(rngc->base + RNGC_COMMAND);
 180         writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
 181
 182         /* create seed, repeat while there is some statistical error */
 183         do {
 184                 imx_rngc_irq_unmask(rngc);
 185
 186                 /* seed creation */
 187                 cmd = readl(rngc->base + RNGC_COMMAND);
 188                 writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
 189
 190                 ret = wait_for_completion_timeout(&rngc->rng_op_done,
 191                                 RNGC_TIMEOUT);
 192
 193                 if (!ret) {
 194                         imx_rngc_irq_mask_clear(rngc);
 195                         return -ETIMEDOUT;
 196                 }
 197
 198         } while (rngc->err_reg == RNGC_ERROR_STATUS_STAT_ERR);
 199
 200         return rngc->err_reg ? -EIO : 0;
 201 }
 202
 203 static int imx_rngc_probe(struct platform_device *pdev)
 204 {
 205         struct imx_rngc *rngc;
 206         struct resource *res;
 207         int ret;
 208         int irq;
 209
 210         rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL);
 211         if (!rngc)
 212                 return -ENOMEM;
 213
 214         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 215         rngc->base = devm_ioremap_resource(&pdev->dev, res);
 216         if (IS_ERR(rngc->base))
 217                 return PTR_ERR(rngc->base);
 218
 219         rngc->clk = devm_clk_get(&pdev->dev, NULL);
 220         if (IS_ERR(rngc->clk)) {
 221                 dev_err(&pdev->dev, "Can not get rng_clk\n");
 222                 return PTR_ERR(rngc->clk);
 223         }
 224
 225         irq = platform_get_irq(pdev, 0);
 226         if (irq <= 0) {
 227                 dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
 228                 return irq;
 229         }
 230
 231         ret = clk_prepare_enable(rngc->clk);
 232         if (ret)
 233                 return ret;
 234
 235         ret = devm_request_irq(&pdev->dev,
 236                         irq, imx_rngc_irq, 0, pdev->name, (void *)rngc);
 237         if (ret) {
 238                 dev_err(rngc->dev, "Can't get interrupt working.\n");
 239                 goto err;
 240         }
 241
 242         init_completion(&rngc->rng_op_done);
 243
 244         rngc->rng.name = pdev->name;
 245         rngc->rng.init = imx_rngc_init;
 246         rngc->rng.read = imx_rngc_read;
 247
 248         rngc->dev = &pdev->dev;
 249         platform_set_drvdata(pdev, rngc);
 250
 251         imx_rngc_irq_mask_clear(rngc);
 252
 253         if (self_test) {
 254                 ret = imx_rngc_self_test(rngc);
 255                 if (ret) {
 256                         dev_err(rngc->dev, "FSL RNGC self test failed.\n");
 257                         goto err;
 258                 }
 259         }
 260
 261         ret = hwrng_register(&rngc->rng);
 262         if (ret) {
 263                 dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", ret);
 264                 goto err;
 265         }
 266
 267         dev_info(&pdev->dev, "Freescale RNGC registered.\n");
 268         return 0;
 269
 270 err:
 271         clk_disable_unprepare(rngc->clk);
 272
 273         return ret;
 274 }
 275
 276 static int __exit imx_rngc_remove(struct platform_device *pdev)
 277 {
 278         struct imx_rngc *rngc = platform_get_drvdata(pdev);
 279
 280         hwrng_unregister(&rngc->rng);
 281
 282         clk_disable_unprepare(rngc->clk);
 283
 284         return 0;
 285 }
 286
 287 #ifdef CONFIG_PM
 288 static int imx_rngc_suspend(struct device *dev)
 289 {
 290         struct imx_rngc *rngc = dev_get_drvdata(dev);
 291
 292         clk_disable_unprepare(rngc->clk);
 293
 294         return 0;
 295 }
 296
 297 static int imx_rngc_resume(struct device *dev)
 298 {
 299         struct imx_rngc *rngc = dev_get_drvdata(dev);
 300
 301         clk_prepare_enable(rngc->clk);
 302
 303         return 0;
 304 }
 305
 306 static const struct dev_pm_ops imx_rngc_pm_ops = {
 307         .suspend        = imx_rngc_suspend,
 308         .resume         = imx_rngc_resume,
 309 };
 310 #endif
 311
 312 static const struct of_device_id imx_rngc_dt_ids[] = {
 313         { .compatible = "fsl,imx25-rngb", .data = NULL, },
 314         { /* sentinel */ }
 315 };
 316 MODULE_DEVICE_TABLE(of, imx_rngc_dt_ids);
 317
 318 static struct platform_driver imx_rngc_driver = {
 319         .driver = {
 320                 .name = "imx_rngc",
 321 #ifdef CONFIG_PM
 322                 .pm = &imx_rngc_pm_ops,
 323 #endif
 324                 .of_match_table = imx_rngc_dt_ids,
 325         },
 326         .remove = __exit_p(imx_rngc_remove),
 327 };
 328
 329 module_platform_driver_probe(imx_rngc_driver, imx_rngc_probe);
 330
 331 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 332 MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
 333 MODULE_LICENSE("GPL");