drivers/clk/at91/clk-generated.c

   1 /*
   2  *  Copyright (C) 2015 Atmel Corporation,
   3  *                     Nicolas Ferre <nicolas.ferre@atmel.com>
   4  *
   5  * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  */
  13
  14 #include <linux/clk-provider.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clk/at91_pmc.h>
  17 #include <linux/of.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/regmap.h>
  20
  21 #include "pmc.h"
  22
  23 #define PERIPHERAL_MAX          64
  24 #define PERIPHERAL_ID_MIN       2
  25
  26 #define GENERATED_SOURCE_MAX    6
  27 #define GENERATED_MAX_DIV       255
  28
  29 #define GCK_ID_SSC0             43
  30 #define GCK_ID_SSC1             44
  31 #define GCK_ID_I2S0             54
  32 #define GCK_ID_I2S1             55
  33 #define GCK_ID_CLASSD           59
  34 #define GCK_INDEX_DT_AUDIO_PLL  5
  35
  36 struct clk_generated {
  37         struct clk_hw hw;
  38         struct regmap *regmap;
  39         struct clk_range range;
  40         spinlock_t *lock;
  41         u32 id;
  42         u32 gckdiv;
  43         u8 parent_id;
  44         bool audio_pll_allowed;
  45 };
  46
  47 #define to_clk_generated(hw) \
  48         container_of(hw, struct clk_generated, hw)
  49
  50 static int clk_generated_enable(struct clk_hw *hw)
  51 {
  52         struct clk_generated *gck = to_clk_generated(hw);
  53         unsigned long flags;
  54
  55         pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
  56                  __func__, gck->gckdiv, gck->parent_id);
  57
  58         spin_lock_irqsave(gck->lock, flags);
  59         regmap_write(gck->regmap, AT91_PMC_PCR,
  60                      (gck->id & AT91_PMC_PCR_PID_MASK));
  61         regmap_update_bits(gck->regmap, AT91_PMC_PCR,
  62                            AT91_PMC_PCR_GCKDIV_MASK | AT91_PMC_PCR_GCKCSS_MASK |
  63                            AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
  64                            AT91_PMC_PCR_GCKCSS(gck->parent_id) |
  65                            AT91_PMC_PCR_CMD |
  66                            AT91_PMC_PCR_GCKDIV(gck->gckdiv) |
  67                            AT91_PMC_PCR_GCKEN);
  68         spin_unlock_irqrestore(gck->lock, flags);
  69         return 0;
  70 }
  71
  72 static void clk_generated_disable(struct clk_hw *hw)
  73 {
  74         struct clk_generated *gck = to_clk_generated(hw);
  75         unsigned long flags;
  76
  77         spin_lock_irqsave(gck->lock, flags);
  78         regmap_write(gck->regmap, AT91_PMC_PCR,
  79                      (gck->id & AT91_PMC_PCR_PID_MASK));
  80         regmap_update_bits(gck->regmap, AT91_PMC_PCR,
  81                            AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
  82                            AT91_PMC_PCR_CMD);
  83         spin_unlock_irqrestore(gck->lock, flags);
  84 }
  85
  86 static int clk_generated_is_enabled(struct clk_hw *hw)
  87 {
  88         struct clk_generated *gck = to_clk_generated(hw);
  89         unsigned long flags;
  90         unsigned int status;
  91
  92         spin_lock_irqsave(gck->lock, flags);
  93         regmap_write(gck->regmap, AT91_PMC_PCR,
  94                      (gck->id & AT91_PMC_PCR_PID_MASK));
  95         regmap_read(gck->regmap, AT91_PMC_PCR, &status);
  96         spin_unlock_irqrestore(gck->lock, flags);
  97
  98         return status & AT91_PMC_PCR_GCKEN ? 1 : 0;
  99 }
 100
 101 static unsigned long
 102 clk_generated_recalc_rate(struct clk_hw *hw,
 103                           unsigned long parent_rate)
 104 {
 105         struct clk_generated *gck = to_clk_generated(hw);
 106
 107         return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
 108 }
 109
 110 static void clk_generated_best_diff(struct clk_rate_request *req,
 111                                     struct clk_hw *parent,
 112                                     unsigned long parent_rate, u32 div,
 113                                     int *best_diff, long *best_rate)
 114 {
 115         unsigned long tmp_rate;
 116         int tmp_diff;
 117
 118         if (!div)
 119                 tmp_rate = parent_rate;
 120         else
 121                 tmp_rate = parent_rate / div;
 122
 123         if (tmp_rate < req->min_rate || tmp_rate > req->max_rate)
 124                 return;
 125
 126         tmp_diff = abs(req->rate - tmp_rate);
 127
 128         if (*best_diff < 0 || *best_diff > tmp_diff) {
 129                 *best_rate = tmp_rate;
 130                 *best_diff = tmp_diff;
 131                 req->best_parent_rate = parent_rate;
 132                 req->best_parent_hw = parent;
 133         }
 134 }
 135
 136 static int clk_generated_determine_rate(struct clk_hw *hw,
 137                                         struct clk_rate_request *req)
 138 {
 139         struct clk_generated *gck = to_clk_generated(hw);
 140         struct clk_hw *parent = NULL;
 141         struct clk_rate_request req_parent = *req;
 142         long best_rate = -EINVAL;
 143         unsigned long min_rate, parent_rate;
 144         int best_diff = -1;
 145         int i;
 146         u32 div;
 147
 148         for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
 149                 parent = clk_hw_get_parent_by_index(hw, i);
 150                 if (!parent)
 151                         continue;
 152
 153                 parent_rate = clk_hw_get_rate(parent);
 154                 min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
 155                 if (!parent_rate ||
 156                     (gck->range.max && min_rate > gck->range.max))
 157                         continue;
 158
 159                 div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
 160                 if (div > GENERATED_MAX_DIV + 1)
 161                         div = GENERATED_MAX_DIV + 1;
 162
 163                 clk_generated_best_diff(req, parent, parent_rate, div,
 164                                         &best_diff, &best_rate);
 165
 166                 if (!best_diff)
 167                         break;
 168         }
 169
 170         /*
 171          * The audio_pll rate can be modified, unlike the five others clocks
 172          * that should never be altered.
 173          * The audio_pll can technically be used by multiple consumers. However,
 174          * with the rate locking, the first consumer to enable to clock will be
 175          * the one definitely setting the rate of the clock.
 176          * Since audio IPs are most likely to request the same rate, we enforce
 177          * that the only clks able to modify gck rate are those of audio IPs.
 178          */
 179
 180         if (!gck->audio_pll_allowed)
 181                 goto end;
 182
 183         parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
 184         if (!parent)
 185                 goto end;
 186
 187         for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
 188                 req_parent.rate = req->rate * div;
 189                 __clk_determine_rate(parent, &req_parent);
 190                 clk_generated_best_diff(req, parent, req_parent.rate, div,
 191                                         &best_diff, &best_rate);
 192
 193                 if (!best_diff)
 194                         break;
 195         }
 196
 197 end:
 198         pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
 199                  __func__, best_rate,
 200                  __clk_get_name((req->best_parent_hw)->clk),
 201                  req->best_parent_rate);
 202
 203         if (best_rate < 0)
 204                 return best_rate;
 205
 206         req->rate = best_rate;
 207         return 0;
 208 }
 209
 210 /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
 211 static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
 212 {
 213         struct clk_generated *gck = to_clk_generated(hw);
 214
 215         if (index >= clk_hw_get_num_parents(hw))
 216                 return -EINVAL;
 217
 218         gck->parent_id = index;
 219         return 0;
 220 }
 221
 222 static u8 clk_generated_get_parent(struct clk_hw *hw)
 223 {
 224         struct clk_generated *gck = to_clk_generated(hw);
 225
 226         return gck->parent_id;
 227 }
 228
 229 /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
 230 static int clk_generated_set_rate(struct clk_hw *hw,
 231                                   unsigned long rate,
 232                                   unsigned long parent_rate)
 233 {
 234         struct clk_generated *gck = to_clk_generated(hw);
 235         u32 div;
 236
 237         if (!rate)
 238                 return -EINVAL;
 239
 240         if (gck->range.max && rate > gck->range.max)
 241                 return -EINVAL;
 242
 243         div = DIV_ROUND_CLOSEST(parent_rate, rate);
 244         if (div > GENERATED_MAX_DIV + 1 || !div)
 245                 return -EINVAL;
 246
 247         gck->gckdiv = div - 1;
 248         return 0;
 249 }
 250
 251 static const struct clk_ops generated_ops = {
 252         .enable = clk_generated_enable,
 253         .disable = clk_generated_disable,
 254         .is_enabled = clk_generated_is_enabled,
 255         .recalc_rate = clk_generated_recalc_rate,
 256         .determine_rate = clk_generated_determine_rate,
 257         .get_parent = clk_generated_get_parent,
 258         .set_parent = clk_generated_set_parent,
 259         .set_rate = clk_generated_set_rate,
 260 };
 261
 262 /**
 263  * clk_generated_startup - Initialize a given clock to its default parent and
 264  * divisor parameter.
 265  *
 266  * @gck:        Generated clock to set the startup parameters for.
 267  *
 268  * Take parameters from the hardware and update local clock configuration
 269  * accordingly.
 270  */
 271 static void clk_generated_startup(struct clk_generated *gck)
 272 {
 273         u32 tmp;
 274         unsigned long flags;
 275
 276         spin_lock_irqsave(gck->lock, flags);
 277         regmap_write(gck->regmap, AT91_PMC_PCR,
 278                      (gck->id & AT91_PMC_PCR_PID_MASK));
 279         regmap_read(gck->regmap, AT91_PMC_PCR, &tmp);
 280         spin_unlock_irqrestore(gck->lock, flags);
 281
 282         gck->parent_id = (tmp & AT91_PMC_PCR_GCKCSS_MASK)
 283                                         >> AT91_PMC_PCR_GCKCSS_OFFSET;
 284         gck->gckdiv = (tmp & AT91_PMC_PCR_GCKDIV_MASK)
 285                                         >> AT91_PMC_PCR_GCKDIV_OFFSET;
 286 }
 287
 288 static struct clk_hw * __init
 289 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
 290                             const char *name, const char **parent_names,
 291                             u8 num_parents, u8 id, bool pll_audio,
 292                             const struct clk_range *range)
 293 {
 294         struct clk_generated *gck;
 295         struct clk_init_data init;
 296         struct clk_hw *hw;
 297         int ret;
 298
 299         gck = kzalloc(sizeof(*gck), GFP_KERNEL);
 300         if (!gck)
 301                 return ERR_PTR(-ENOMEM);
 302
 303         init.name = name;
 304         init.ops = &generated_ops;
 305         init.parent_names = parent_names;
 306         init.num_parents = num_parents;
 307         init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 308                 CLK_SET_RATE_PARENT;
 309
 310         gck->id = id;
 311         gck->hw.init = &init;
 312         gck->regmap = regmap;
 313         gck->lock = lock;
 314         gck->range = *range;
 315         gck->audio_pll_allowed = pll_audio;
 316
 317         clk_generated_startup(gck);
 318         hw = &gck->hw;
 319         ret = clk_hw_register(NULL, &gck->hw);
 320         if (ret) {
 321                 kfree(gck);
 322                 hw = ERR_PTR(ret);
 323         } else {
 324                 pmc_register_id(id);
 325         }
 326
 327         return hw;
 328 }
 329
 330 static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
 331 {
 332         int num;
 333         u32 id;
 334         const char *name;
 335         struct clk_hw *hw;
 336         unsigned int num_parents;
 337         const char *parent_names[GENERATED_SOURCE_MAX];
 338         struct device_node *gcknp;
 339         struct clk_range range = CLK_RANGE(0, 0);
 340         struct regmap *regmap;
 341
 342         num_parents = of_clk_get_parent_count(np);
 343         if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
 344                 return;
 345
 346         of_clk_parent_fill(np, parent_names, num_parents);
 347
 348         num = of_get_child_count(np);
 349         if (!num || num > PERIPHERAL_MAX)
 350                 return;
 351
 352         regmap = syscon_node_to_regmap(of_get_parent(np));
 353         if (IS_ERR(regmap))
 354                 return;
 355
 356         for_each_child_of_node(np, gcknp) {
 357                 bool pll_audio = false;
 358
 359                 if (of_property_read_u32(gcknp, "reg", &id))
 360                         continue;
 361
 362                 if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
 363                         continue;
 364
 365                 if (of_property_read_string(np, "clock-output-names", &name))
 366                         name = gcknp->name;
 367
 368                 of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
 369                                       &range);
 370
 371                 if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
 372                     (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
 373                      id == GCK_ID_CLASSD))
 374                         pll_audio = true;
 375
 376                 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
 377                                                   parent_names, num_parents,
 378                                                   id, pll_audio, &range);
 379                 if (IS_ERR(hw))
 380                         continue;
 381
 382                 of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
 383         }
 384 }
 385 CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
 386                of_sama5d2_clk_generated_setup);