2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
20 * The clock tree on the 2835 has several levels. There's a root
21 * oscillator running at 19.2Mhz. After the oscillator there are 5
22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
23 * and "HDMI displays". Those 5 PLLs each can divide their output to
24 * produce up to 4 channels. Finally, there is the level of clocks to
25 * be consumed by other hardware components (like "H264" or "HDMI
26 * state machine"), which divide off of some subset of the PLL
29 * All of the clocks in the tree are exposed in the DT, because the DT
30 * may want to make assignments of the final layer of clocks to the
31 * PLL channels, and some components of the hardware will actually
32 * skip layers of the tree (for example, the pixel clock comes
33 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 #include <linux/clk-provider.h>
38 #include <linux/clkdev.h>
39 #include <linux/clk.h>
40 #include <linux/clk/bcm2835.h>
41 #include <linux/debugfs.h>
42 #include <linux/delay.h>
43 #include <linux/module.h>
45 #include <linux/platform_device.h>
46 #include <linux/slab.h>
47 #include <dt-bindings/clock/bcm2835.h>
49 #define CM_PASSWORD 0x5a000000
51 #define CM_GNRICCTL 0x000
52 #define CM_GNRICDIV 0x004
53 # define CM_DIV_FRAC_BITS 12
54 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
56 #define CM_VPUCTL 0x008
57 #define CM_VPUDIV 0x00c
58 #define CM_SYSCTL 0x010
59 #define CM_SYSDIV 0x014
60 #define CM_PERIACTL 0x018
61 #define CM_PERIADIV 0x01c
62 #define CM_PERIICTL 0x020
63 #define CM_PERIIDIV 0x024
64 #define CM_H264CTL 0x028
65 #define CM_H264DIV 0x02c
66 #define CM_ISPCTL 0x030
67 #define CM_ISPDIV 0x034
68 #define CM_V3DCTL 0x038
69 #define CM_V3DDIV 0x03c
70 #define CM_CAM0CTL 0x040
71 #define CM_CAM0DIV 0x044
72 #define CM_CAM1CTL 0x048
73 #define CM_CAM1DIV 0x04c
74 #define CM_CCP2CTL 0x050
75 #define CM_CCP2DIV 0x054
76 #define CM_DSI0ECTL 0x058
77 #define CM_DSI0EDIV 0x05c
78 #define CM_DSI0PCTL 0x060
79 #define CM_DSI0PDIV 0x064
80 #define CM_DPICTL 0x068
81 #define CM_DPIDIV 0x06c
82 #define CM_GP0CTL 0x070
83 #define CM_GP0DIV 0x074
84 #define CM_GP1CTL 0x078
85 #define CM_GP1DIV 0x07c
86 #define CM_GP2CTL 0x080
87 #define CM_GP2DIV 0x084
88 #define CM_HSMCTL 0x088
89 #define CM_HSMDIV 0x08c
90 #define CM_OTPCTL 0x090
91 #define CM_OTPDIV 0x094
92 #define CM_PCMCTL 0x098
93 #define CM_PCMDIV 0x09c
94 #define CM_PWMCTL 0x0a0
95 #define CM_PWMDIV 0x0a4
96 #define CM_SLIMCTL 0x0a8
97 #define CM_SLIMDIV 0x0ac
98 #define CM_SMICTL 0x0b0
99 #define CM_SMIDIV 0x0b4
100 /* no definition for 0x0b8 and 0x0bc */
101 #define CM_TCNTCTL 0x0c0
102 # define CM_TCNT_SRC1_SHIFT 12
103 #define CM_TCNTCNT 0x0c4
104 #define CM_TECCTL 0x0c8
105 #define CM_TECDIV 0x0cc
106 #define CM_TD0CTL 0x0d0
107 #define CM_TD0DIV 0x0d4
108 #define CM_TD1CTL 0x0d8
109 #define CM_TD1DIV 0x0dc
110 #define CM_TSENSCTL 0x0e0
111 #define CM_TSENSDIV 0x0e4
112 #define CM_TIMERCTL 0x0e8
113 #define CM_TIMERDIV 0x0ec
114 #define CM_UARTCTL 0x0f0
115 #define CM_UARTDIV 0x0f4
116 #define CM_VECCTL 0x0f8
117 #define CM_VECDIV 0x0fc
118 #define CM_PULSECTL 0x190
119 #define CM_PULSEDIV 0x194
120 #define CM_SDCCTL 0x1a8
121 #define CM_SDCDIV 0x1ac
122 #define CM_ARMCTL 0x1b0
123 #define CM_AVEOCTL 0x1b8
124 #define CM_AVEODIV 0x1bc
125 #define CM_EMMCCTL 0x1c0
126 #define CM_EMMCDIV 0x1c4
128 /* General bits for the CM_*CTL regs */
129 # define CM_ENABLE BIT(4)
130 # define CM_KILL BIT(5)
131 # define CM_GATE_BIT 6
132 # define CM_GATE BIT(CM_GATE_BIT)
133 # define CM_BUSY BIT(7)
134 # define CM_BUSYD BIT(8)
135 # define CM_FRAC BIT(9)
136 # define CM_SRC_SHIFT 0
137 # define CM_SRC_BITS 4
138 # define CM_SRC_MASK 0xf
139 # define CM_SRC_GND 0
140 # define CM_SRC_OSC 1
141 # define CM_SRC_TESTDEBUG0 2
142 # define CM_SRC_TESTDEBUG1 3
143 # define CM_SRC_PLLA_CORE 4
144 # define CM_SRC_PLLA_PER 4
145 # define CM_SRC_PLLC_CORE0 5
146 # define CM_SRC_PLLC_PER 5
147 # define CM_SRC_PLLC_CORE1 8
148 # define CM_SRC_PLLD_CORE 6
149 # define CM_SRC_PLLD_PER 6
150 # define CM_SRC_PLLH_AUX 7
151 # define CM_SRC_PLLC_CORE1 8
152 # define CM_SRC_PLLC_CORE2 9
154 #define CM_OSCCOUNT 0x100
156 #define CM_PLLA 0x104
157 # define CM_PLL_ANARST BIT(8)
158 # define CM_PLLA_HOLDPER BIT(7)
159 # define CM_PLLA_LOADPER BIT(6)
160 # define CM_PLLA_HOLDCORE BIT(5)
161 # define CM_PLLA_LOADCORE BIT(4)
162 # define CM_PLLA_HOLDCCP2 BIT(3)
163 # define CM_PLLA_LOADCCP2 BIT(2)
164 # define CM_PLLA_HOLDDSI0 BIT(1)
165 # define CM_PLLA_LOADDSI0 BIT(0)
167 #define CM_PLLC 0x108
168 # define CM_PLLC_HOLDPER BIT(7)
169 # define CM_PLLC_LOADPER BIT(6)
170 # define CM_PLLC_HOLDCORE2 BIT(5)
171 # define CM_PLLC_LOADCORE2 BIT(4)
172 # define CM_PLLC_HOLDCORE1 BIT(3)
173 # define CM_PLLC_LOADCORE1 BIT(2)
174 # define CM_PLLC_HOLDCORE0 BIT(1)
175 # define CM_PLLC_LOADCORE0 BIT(0)
177 #define CM_PLLD 0x10c
178 # define CM_PLLD_HOLDPER BIT(7)
179 # define CM_PLLD_LOADPER BIT(6)
180 # define CM_PLLD_HOLDCORE BIT(5)
181 # define CM_PLLD_LOADCORE BIT(4)
182 # define CM_PLLD_HOLDDSI1 BIT(3)
183 # define CM_PLLD_LOADDSI1 BIT(2)
184 # define CM_PLLD_HOLDDSI0 BIT(1)
185 # define CM_PLLD_LOADDSI0 BIT(0)
187 #define CM_PLLH 0x110
188 # define CM_PLLH_LOADRCAL BIT(2)
189 # define CM_PLLH_LOADAUX BIT(1)
190 # define CM_PLLH_LOADPIX BIT(0)
192 #define CM_LOCK 0x114
193 # define CM_LOCK_FLOCKH BIT(12)
194 # define CM_LOCK_FLOCKD BIT(11)
195 # define CM_LOCK_FLOCKC BIT(10)
196 # define CM_LOCK_FLOCKB BIT(9)
197 # define CM_LOCK_FLOCKA BIT(8)
199 #define CM_EVENT 0x118
200 #define CM_DSI1ECTL 0x158
201 #define CM_DSI1EDIV 0x15c
202 #define CM_DSI1PCTL 0x160
203 #define CM_DSI1PDIV 0x164
204 #define CM_DFTCTL 0x168
205 #define CM_DFTDIV 0x16c
207 #define CM_PLLB 0x170
208 # define CM_PLLB_HOLDARM BIT(1)
209 # define CM_PLLB_LOADARM BIT(0)
211 #define A2W_PLLA_CTRL 0x1100
212 #define A2W_PLLC_CTRL 0x1120
213 #define A2W_PLLD_CTRL 0x1140
214 #define A2W_PLLH_CTRL 0x1160
215 #define A2W_PLLB_CTRL 0x11e0
216 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
217 # define A2W_PLL_CTRL_PWRDN BIT(16)
218 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
219 # define A2W_PLL_CTRL_PDIV_SHIFT 12
220 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
221 # define A2W_PLL_CTRL_NDIV_SHIFT 0
223 #define A2W_PLLA_ANA0 0x1010
224 #define A2W_PLLC_ANA0 0x1030
225 #define A2W_PLLD_ANA0 0x1050
226 #define A2W_PLLH_ANA0 0x1070
227 #define A2W_PLLB_ANA0 0x10f0
229 #define A2W_PLL_KA_SHIFT 7
230 #define A2W_PLL_KA_MASK GENMASK(9, 7)
231 #define A2W_PLL_KI_SHIFT 19
232 #define A2W_PLL_KI_MASK GENMASK(21, 19)
233 #define A2W_PLL_KP_SHIFT 15
234 #define A2W_PLL_KP_MASK GENMASK(18, 15)
236 #define A2W_PLLH_KA_SHIFT 19
237 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
238 #define A2W_PLLH_KI_LOW_SHIFT 22
239 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
240 #define A2W_PLLH_KI_HIGH_SHIFT 0
241 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
242 #define A2W_PLLH_KP_SHIFT 1
243 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
245 #define A2W_XOSC_CTRL 0x1190
246 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
247 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
248 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
249 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
250 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
251 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
252 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
253 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
255 #define A2W_PLLA_FRAC 0x1200
256 #define A2W_PLLC_FRAC 0x1220
257 #define A2W_PLLD_FRAC 0x1240
258 #define A2W_PLLH_FRAC 0x1260
259 #define A2W_PLLB_FRAC 0x12e0
260 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
261 # define A2W_PLL_FRAC_BITS 20
263 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
264 #define A2W_PLL_DIV_BITS 8
265 #define A2W_PLL_DIV_SHIFT 0
267 #define A2W_PLLA_DSI0 0x1300
268 #define A2W_PLLA_CORE 0x1400
269 #define A2W_PLLA_PER 0x1500
270 #define A2W_PLLA_CCP2 0x1600
272 #define A2W_PLLC_CORE2 0x1320
273 #define A2W_PLLC_CORE1 0x1420
274 #define A2W_PLLC_PER 0x1520
275 #define A2W_PLLC_CORE0 0x1620
277 #define A2W_PLLD_DSI0 0x1340
278 #define A2W_PLLD_CORE 0x1440
279 #define A2W_PLLD_PER 0x1540
280 #define A2W_PLLD_DSI1 0x1640
282 #define A2W_PLLH_AUX 0x1360
283 #define A2W_PLLH_RCAL 0x1460
284 #define A2W_PLLH_PIX 0x1560
285 #define A2W_PLLH_STS 0x1660
287 #define A2W_PLLH_CTRLR 0x1960
288 #define A2W_PLLH_FRACR 0x1a60
289 #define A2W_PLLH_AUXR 0x1b60
290 #define A2W_PLLH_RCALR 0x1c60
291 #define A2W_PLLH_PIXR 0x1d60
292 #define A2W_PLLH_STSR 0x1e60
294 #define A2W_PLLB_ARM 0x13e0
295 #define A2W_PLLB_SP0 0x14e0
296 #define A2W_PLLB_SP1 0x15e0
297 #define A2W_PLLB_SP2 0x16e0
299 #define LOCK_TIMEOUT_NS 100000000
300 #define BCM2835_MAX_FB_RATE 1750000000u
303 * Names of clocks used within the driver that need to be replaced
304 * with an external parent's name. This array is in the order that
305 * the clocks node in the DT references external clocks.
307 static const char *const cprman_parent_names[] = {
317 struct bcm2835_cprman {
320 spinlock_t regs_lock; /* spinlock for all clocks */
323 * Real names of cprman clock parents looked up through
324 * of_clk_get_parent_name(), which will be used in the
325 * parent_names[] arrays for clock registration.
327 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
330 struct clk_hw_onecell_data onecell;
333 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
335 writel(CM_PASSWORD | val, cprman->regs + reg);
338 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
340 return readl(cprman->regs + reg);
343 /* Does a cycle of measuring a clock through the TCNT clock, which may
344 * source from many other clocks in the system.
346 static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
349 u32 osccount = 19200; /* 1ms */
353 spin_lock(&cprman->regs_lock);
355 cprman_write(cprman, CM_TCNTCTL, CM_KILL);
357 cprman_write(cprman, CM_TCNTCTL,
358 (tcnt_mux & CM_SRC_MASK) |
359 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
361 cprman_write(cprman, CM_OSCCOUNT, osccount);
363 /* do a kind delay at the start */
366 /* Finish off whatever is left of OSCCOUNT */
367 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
368 while (cprman_read(cprman, CM_OSCCOUNT)) {
369 if (ktime_after(ktime_get(), timeout)) {
370 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
377 /* Wait for BUSY to clear. */
378 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
379 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
380 if (ktime_after(ktime_get(), timeout)) {
381 dev_err(cprman->dev, "timeout waiting for !BUSY\n");
388 count = cprman_read(cprman, CM_TCNTCNT);
390 cprman_write(cprman, CM_TCNTCTL, 0);
393 spin_unlock(&cprman->regs_lock);
398 static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
399 struct debugfs_reg32 *regs, size_t nregs,
400 struct dentry *dentry)
402 struct dentry *regdump;
403 struct debugfs_regset32 *regset;
405 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
410 regset->nregs = nregs;
411 regset->base = cprman->regs + base;
413 regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry,
416 return regdump ? 0 : -ENOMEM;
420 * These are fixed clocks. They're probably not all root clocks and it may
421 * be possible to turn them on and off but until this is mapped out better
422 * it's the only way they can be used.
424 void __init bcm2835_init_clocks(void)
429 hw = clk_hw_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000);
431 pr_err("apb_pclk not registered\n");
433 hw = clk_hw_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000);
435 pr_err("uart0_pclk not registered\n");
436 ret = clk_hw_register_clkdev(hw, NULL, "20201000.uart");
438 pr_err("uart0_pclk alias not registered\n");
440 hw = clk_hw_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000);
442 pr_err("uart1_pclk not registered\n");
443 ret = clk_hw_register_clkdev(hw, NULL, "20215000.uart");
445 pr_err("uart1_pclk alias not registered\n");
448 struct bcm2835_pll_data {
454 u32 reference_enable_mask;
455 /* Bit in CM_LOCK to indicate when the PLL has locked. */
458 const struct bcm2835_pll_ana_bits *ana;
460 unsigned long min_rate;
461 unsigned long max_rate;
463 * Highest rate for the VCO before we have to use the
466 unsigned long max_fb_rate;
469 struct bcm2835_pll_ana_bits {
479 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
482 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
483 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
484 .mask3 = A2W_PLL_KA_MASK,
485 .set3 = (2 << A2W_PLL_KA_SHIFT),
486 .fb_prediv_mask = BIT(14),
489 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
490 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
491 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
492 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
493 .set1 = (6 << A2W_PLLH_KP_SHIFT),
496 .fb_prediv_mask = BIT(11),
499 struct bcm2835_pll_divider_data {
501 const char *source_pll;
512 struct bcm2835_clock_data {
515 const char *const *parents;
518 /* Bitmap encoding which parents accept rate change propagation. */
519 unsigned int set_rate_parent;
524 /* Number of integer bits in the divider */
526 /* Number of fractional bits in the divider */
538 struct bcm2835_gate_data {
547 struct bcm2835_cprman *cprman;
548 const struct bcm2835_pll_data *data;
551 static int bcm2835_pll_is_on(struct clk_hw *hw)
553 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
554 struct bcm2835_cprman *cprman = pll->cprman;
555 const struct bcm2835_pll_data *data = pll->data;
557 return cprman_read(cprman, data->a2w_ctrl_reg) &
558 A2W_PLL_CTRL_PRST_DISABLE;
561 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
562 unsigned long parent_rate,
563 u32 *ndiv, u32 *fdiv)
567 div = (u64)rate << A2W_PLL_FRAC_BITS;
568 do_div(div, parent_rate);
570 *ndiv = div >> A2W_PLL_FRAC_BITS;
571 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
574 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
575 u32 ndiv, u32 fdiv, u32 pdiv)
582 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
584 return rate >> A2W_PLL_FRAC_BITS;
587 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
588 unsigned long *parent_rate)
590 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
591 const struct bcm2835_pll_data *data = pll->data;
594 rate = clamp(rate, data->min_rate, data->max_rate);
596 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
598 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
601 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
602 unsigned long parent_rate)
604 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
605 struct bcm2835_cprman *cprman = pll->cprman;
606 const struct bcm2835_pll_data *data = pll->data;
607 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
608 u32 ndiv, pdiv, fdiv;
611 if (parent_rate == 0)
614 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
615 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
616 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
617 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
618 data->ana->fb_prediv_mask;
625 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
628 static void bcm2835_pll_off(struct clk_hw *hw)
630 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
631 struct bcm2835_cprman *cprman = pll->cprman;
632 const struct bcm2835_pll_data *data = pll->data;
634 spin_lock(&cprman->regs_lock);
635 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
636 cprman_write(cprman, data->a2w_ctrl_reg,
637 cprman_read(cprman, data->a2w_ctrl_reg) |
639 spin_unlock(&cprman->regs_lock);
642 static int bcm2835_pll_on(struct clk_hw *hw)
644 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
645 struct bcm2835_cprman *cprman = pll->cprman;
646 const struct bcm2835_pll_data *data = pll->data;
649 cprman_write(cprman, data->a2w_ctrl_reg,
650 cprman_read(cprman, data->a2w_ctrl_reg) &
651 ~A2W_PLL_CTRL_PWRDN);
653 /* Take the PLL out of reset. */
654 spin_lock(&cprman->regs_lock);
655 cprman_write(cprman, data->cm_ctrl_reg,
656 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
657 spin_unlock(&cprman->regs_lock);
659 /* Wait for the PLL to lock. */
660 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
661 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
662 if (ktime_after(ktime_get(), timeout)) {
663 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
664 clk_hw_get_name(hw));
671 cprman_write(cprman, data->a2w_ctrl_reg,
672 cprman_read(cprman, data->a2w_ctrl_reg) |
673 A2W_PLL_CTRL_PRST_DISABLE);
679 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
684 * ANA register setup is done as a series of writes to
685 * ANA3-ANA0, in that order. This lets us write all 4
686 * registers as a single cycle of the serdes interface (taking
687 * 100 xosc clocks), whereas if we were to update ana0, 1, and
688 * 3 individually through their partial-write registers, each
689 * would be their own serdes cycle.
691 for (i = 3; i >= 0; i--)
692 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
695 static int bcm2835_pll_set_rate(struct clk_hw *hw,
696 unsigned long rate, unsigned long parent_rate)
698 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
699 struct bcm2835_cprman *cprman = pll->cprman;
700 const struct bcm2835_pll_data *data = pll->data;
701 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
702 u32 ndiv, fdiv, a2w_ctl;
706 if (rate > data->max_fb_rate) {
707 use_fb_prediv = true;
710 use_fb_prediv = false;
713 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
715 for (i = 3; i >= 0; i--)
716 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
718 was_using_prediv = ana[1] & data->ana->fb_prediv_mask;
720 ana[0] &= ~data->ana->mask0;
721 ana[0] |= data->ana->set0;
722 ana[1] &= ~data->ana->mask1;
723 ana[1] |= data->ana->set1;
724 ana[3] &= ~data->ana->mask3;
725 ana[3] |= data->ana->set3;
727 if (was_using_prediv && !use_fb_prediv) {
728 ana[1] &= ~data->ana->fb_prediv_mask;
729 do_ana_setup_first = true;
730 } else if (!was_using_prediv && use_fb_prediv) {
731 ana[1] |= data->ana->fb_prediv_mask;
732 do_ana_setup_first = false;
734 do_ana_setup_first = true;
737 /* Unmask the reference clock from the oscillator. */
738 spin_lock(&cprman->regs_lock);
739 cprman_write(cprman, A2W_XOSC_CTRL,
740 cprman_read(cprman, A2W_XOSC_CTRL) |
741 data->reference_enable_mask);
742 spin_unlock(&cprman->regs_lock);
744 if (do_ana_setup_first)
745 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
747 /* Set the PLL multiplier from the oscillator. */
748 cprman_write(cprman, data->frac_reg, fdiv);
750 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
751 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
752 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
753 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
754 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
755 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
757 if (!do_ana_setup_first)
758 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
763 static int bcm2835_pll_debug_init(struct clk_hw *hw,
764 struct dentry *dentry)
766 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
767 struct bcm2835_cprman *cprman = pll->cprman;
768 const struct bcm2835_pll_data *data = pll->data;
769 struct debugfs_reg32 *regs;
771 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
775 regs[0].name = "cm_ctrl";
776 regs[0].offset = data->cm_ctrl_reg;
777 regs[1].name = "a2w_ctrl";
778 regs[1].offset = data->a2w_ctrl_reg;
779 regs[2].name = "frac";
780 regs[2].offset = data->frac_reg;
781 regs[3].name = "ana0";
782 regs[3].offset = data->ana_reg_base + 0 * 4;
783 regs[4].name = "ana1";
784 regs[4].offset = data->ana_reg_base + 1 * 4;
785 regs[5].name = "ana2";
786 regs[5].offset = data->ana_reg_base + 2 * 4;
787 regs[6].name = "ana3";
788 regs[6].offset = data->ana_reg_base + 3 * 4;
790 return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
793 static const struct clk_ops bcm2835_pll_clk_ops = {
794 .is_prepared = bcm2835_pll_is_on,
795 .prepare = bcm2835_pll_on,
796 .unprepare = bcm2835_pll_off,
797 .recalc_rate = bcm2835_pll_get_rate,
798 .set_rate = bcm2835_pll_set_rate,
799 .round_rate = bcm2835_pll_round_rate,
800 .debug_init = bcm2835_pll_debug_init,
803 struct bcm2835_pll_divider {
804 struct clk_divider div;
805 struct bcm2835_cprman *cprman;
806 const struct bcm2835_pll_divider_data *data;
809 static struct bcm2835_pll_divider *
810 bcm2835_pll_divider_from_hw(struct clk_hw *hw)
812 return container_of(hw, struct bcm2835_pll_divider, div.hw);
815 static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
817 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
818 struct bcm2835_cprman *cprman = divider->cprman;
819 const struct bcm2835_pll_divider_data *data = divider->data;
821 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
824 static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
826 unsigned long *parent_rate)
828 return clk_divider_ops.round_rate(hw, rate, parent_rate);
831 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
832 unsigned long parent_rate)
834 return clk_divider_ops.recalc_rate(hw, parent_rate);
837 static void bcm2835_pll_divider_off(struct clk_hw *hw)
839 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
840 struct bcm2835_cprman *cprman = divider->cprman;
841 const struct bcm2835_pll_divider_data *data = divider->data;
843 spin_lock(&cprman->regs_lock);
844 cprman_write(cprman, data->cm_reg,
845 (cprman_read(cprman, data->cm_reg) &
846 ~data->load_mask) | data->hold_mask);
847 cprman_write(cprman, data->a2w_reg,
848 cprman_read(cprman, data->a2w_reg) |
849 A2W_PLL_CHANNEL_DISABLE);
850 spin_unlock(&cprman->regs_lock);
853 static int bcm2835_pll_divider_on(struct clk_hw *hw)
855 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
856 struct bcm2835_cprman *cprman = divider->cprman;
857 const struct bcm2835_pll_divider_data *data = divider->data;
859 spin_lock(&cprman->regs_lock);
860 cprman_write(cprman, data->a2w_reg,
861 cprman_read(cprman, data->a2w_reg) &
862 ~A2W_PLL_CHANNEL_DISABLE);
864 cprman_write(cprman, data->cm_reg,
865 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
866 spin_unlock(&cprman->regs_lock);
871 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
873 unsigned long parent_rate)
875 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
876 struct bcm2835_cprman *cprman = divider->cprman;
877 const struct bcm2835_pll_divider_data *data = divider->data;
878 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
880 div = DIV_ROUND_UP_ULL(parent_rate, rate);
882 div = min(div, max_div);
886 cprman_write(cprman, data->a2w_reg, div);
887 cm = cprman_read(cprman, data->cm_reg);
888 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
889 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
894 static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
895 struct dentry *dentry)
897 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
898 struct bcm2835_cprman *cprman = divider->cprman;
899 const struct bcm2835_pll_divider_data *data = divider->data;
900 struct debugfs_reg32 *regs;
902 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
907 regs[0].offset = data->cm_reg;
908 regs[1].name = "a2w";
909 regs[1].offset = data->a2w_reg;
911 return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
914 static const struct clk_ops bcm2835_pll_divider_clk_ops = {
915 .is_prepared = bcm2835_pll_divider_is_on,
916 .prepare = bcm2835_pll_divider_on,
917 .unprepare = bcm2835_pll_divider_off,
918 .recalc_rate = bcm2835_pll_divider_get_rate,
919 .set_rate = bcm2835_pll_divider_set_rate,
920 .round_rate = bcm2835_pll_divider_round_rate,
921 .debug_init = bcm2835_pll_divider_debug_init,
925 * The CM dividers do fixed-point division, so we can't use the
926 * generic integer divider code like the PLL dividers do (and we can't
927 * fake it by having some fixed shifts preceding it in the clock tree,
928 * because we'd run out of bits in a 32-bit unsigned long).
930 struct bcm2835_clock {
932 struct bcm2835_cprman *cprman;
933 const struct bcm2835_clock_data *data;
936 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
938 return container_of(hw, struct bcm2835_clock, hw);
941 static int bcm2835_clock_is_on(struct clk_hw *hw)
943 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
944 struct bcm2835_cprman *cprman = clock->cprman;
945 const struct bcm2835_clock_data *data = clock->data;
947 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
950 static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
952 unsigned long parent_rate)
954 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
955 const struct bcm2835_clock_data *data = clock->data;
956 u32 unused_frac_mask =
957 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
958 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
960 u32 div, mindiv, maxdiv;
962 rem = do_div(temp, rate);
964 div &= ~unused_frac_mask;
966 /* different clamping limits apply for a mash clock */
967 if (data->is_mash_clock) {
968 /* clamp to min divider of 2 */
969 mindiv = 2 << CM_DIV_FRAC_BITS;
970 /* clamp to the highest possible integer divider */
971 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
973 /* clamp to min divider of 1 */
974 mindiv = 1 << CM_DIV_FRAC_BITS;
975 /* clamp to the highest possible fractional divider */
976 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
977 CM_DIV_FRAC_BITS - data->frac_bits);
980 /* apply the clamping limits */
981 div = max_t(u32, div, mindiv);
982 div = min_t(u32, div, maxdiv);
987 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
988 unsigned long parent_rate,
991 const struct bcm2835_clock_data *data = clock->data;
994 if (data->int_bits == 0 && data->frac_bits == 0)
998 * The divisor is a 12.12 fixed point field, but only some of
999 * the bits are populated in any given clock.
1001 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
1002 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
1007 temp = (u64)parent_rate << data->frac_bits;
1014 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
1015 unsigned long parent_rate)
1017 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1018 struct bcm2835_cprman *cprman = clock->cprman;
1019 const struct bcm2835_clock_data *data = clock->data;
1022 if (data->int_bits == 0 && data->frac_bits == 0)
1025 div = cprman_read(cprman, data->div_reg);
1027 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1030 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1032 struct bcm2835_cprman *cprman = clock->cprman;
1033 const struct bcm2835_clock_data *data = clock->data;
1034 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1036 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1037 if (ktime_after(ktime_get(), timeout)) {
1038 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1039 clk_hw_get_name(&clock->hw));
1046 static void bcm2835_clock_off(struct clk_hw *hw)
1048 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1049 struct bcm2835_cprman *cprman = clock->cprman;
1050 const struct bcm2835_clock_data *data = clock->data;
1052 spin_lock(&cprman->regs_lock);
1053 cprman_write(cprman, data->ctl_reg,
1054 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1055 spin_unlock(&cprman->regs_lock);
1057 /* BUSY will remain high until the divider completes its cycle. */
1058 bcm2835_clock_wait_busy(clock);
1061 static int bcm2835_clock_on(struct clk_hw *hw)
1063 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1064 struct bcm2835_cprman *cprman = clock->cprman;
1065 const struct bcm2835_clock_data *data = clock->data;
1067 spin_lock(&cprman->regs_lock);
1068 cprman_write(cprman, data->ctl_reg,
1069 cprman_read(cprman, data->ctl_reg) |
1072 spin_unlock(&cprman->regs_lock);
1074 /* Debug code to measure the clock once it's turned on to see
1075 * if it's ticking at the rate we expect.
1077 if (data->tcnt_mux && false) {
1078 dev_info(cprman->dev,
1079 "clk %s: rate %ld, measure %ld\n",
1081 clk_hw_get_rate(hw),
1082 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1088 static int bcm2835_clock_set_rate(struct clk_hw *hw,
1089 unsigned long rate, unsigned long parent_rate)
1091 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1092 struct bcm2835_cprman *cprman = clock->cprman;
1093 const struct bcm2835_clock_data *data = clock->data;
1094 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
1097 spin_lock(&cprman->regs_lock);
1100 * Setting up frac support
1102 * In principle it is recommended to stop/start the clock first,
1103 * but as we set CLK_SET_RATE_GATE during registration of the
1104 * clock this requirement should be take care of by the
1107 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1108 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
1109 cprman_write(cprman, data->ctl_reg, ctl);
1111 cprman_write(cprman, data->div_reg, div);
1113 spin_unlock(&cprman->regs_lock);
1119 bcm2835_clk_is_pllc(struct clk_hw *hw)
1124 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
1127 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
1131 unsigned long *prate,
1132 unsigned long *avgrate)
1134 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1135 struct bcm2835_cprman *cprman = clock->cprman;
1136 const struct bcm2835_clock_data *data = clock->data;
1137 unsigned long best_rate = 0;
1138 u32 curdiv, mindiv, maxdiv;
1139 struct clk_hw *parent;
1141 parent = clk_hw_get_parent_by_index(hw, parent_idx);
1143 if (!(BIT(parent_idx) & data->set_rate_parent)) {
1144 *prate = clk_hw_get_rate(parent);
1145 *div = bcm2835_clock_choose_div(hw, rate, *prate);
1147 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1149 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1150 unsigned long high, low;
1151 u32 int_div = *div & ~CM_DIV_FRAC_MASK;
1153 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1155 int_div += CM_DIV_FRAC_MASK + 1;
1156 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1160 * Return a value which is the maximum deviation
1161 * below the ideal rate, for use as a metric.
1163 return *avgrate - max(*avgrate - low, high - *avgrate);
1168 if (data->frac_bits)
1169 dev_warn(cprman->dev,
1170 "frac bits are not used when propagating rate change");
1172 /* clamp to min divider of 2 if we're dealing with a mash clock */
1173 mindiv = data->is_mash_clock ? 2 : 1;
1174 maxdiv = BIT(data->int_bits) - 1;
1176 /* TODO: Be smart, and only test a subset of the available divisors. */
1177 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
1178 unsigned long tmp_rate;
1180 tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
1182 if (curdiv == mindiv ||
1183 (tmp_rate > best_rate && tmp_rate <= rate))
1184 best_rate = tmp_rate;
1186 if (best_rate == rate)
1190 *div = curdiv << CM_DIV_FRAC_BITS;
1191 *prate = curdiv * best_rate;
1192 *avgrate = best_rate;
1197 static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1198 struct clk_rate_request *req)
1200 struct clk_hw *parent, *best_parent = NULL;
1201 bool current_parent_is_pllc;
1202 unsigned long rate, best_rate = 0;
1203 unsigned long prate, best_prate = 0;
1204 unsigned long avgrate, best_avgrate = 0;
1208 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
1211 * Select parent clock that results in the closest but lower rate
1213 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1214 parent = clk_hw_get_parent_by_index(hw, i);
1219 * Don't choose a PLLC-derived clock as our parent
1220 * unless it had been manually set that way. PLLC's
1221 * frequency gets adjusted by the firmware due to
1222 * over-temp or under-voltage conditions, without
1223 * prior notification to our clock consumer.
1225 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
1228 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
1231 if (abs(req->rate - rate) < abs(req->rate - best_rate)) {
1232 best_parent = parent;
1235 best_avgrate = avgrate;
1242 req->best_parent_hw = best_parent;
1243 req->best_parent_rate = best_prate;
1245 req->rate = best_avgrate;
1250 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1252 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1253 struct bcm2835_cprman *cprman = clock->cprman;
1254 const struct bcm2835_clock_data *data = clock->data;
1255 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1257 cprman_write(cprman, data->ctl_reg, src);
1261 static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1263 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1264 struct bcm2835_cprman *cprman = clock->cprman;
1265 const struct bcm2835_clock_data *data = clock->data;
1266 u32 src = cprman_read(cprman, data->ctl_reg);
1268 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1271 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1282 static int bcm2835_clock_debug_init(struct clk_hw *hw,
1283 struct dentry *dentry)
1285 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1286 struct bcm2835_cprman *cprman = clock->cprman;
1287 const struct bcm2835_clock_data *data = clock->data;
1289 return bcm2835_debugfs_regset(
1290 cprman, data->ctl_reg,
1291 bcm2835_debugfs_clock_reg32,
1292 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1296 static const struct clk_ops bcm2835_clock_clk_ops = {
1297 .is_prepared = bcm2835_clock_is_on,
1298 .prepare = bcm2835_clock_on,
1299 .unprepare = bcm2835_clock_off,
1300 .recalc_rate = bcm2835_clock_get_rate,
1301 .set_rate = bcm2835_clock_set_rate,
1302 .determine_rate = bcm2835_clock_determine_rate,
1303 .set_parent = bcm2835_clock_set_parent,
1304 .get_parent = bcm2835_clock_get_parent,
1305 .debug_init = bcm2835_clock_debug_init,
1308 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1314 * The VPU clock can never be disabled (it doesn't have an ENABLE
1315 * bit), so it gets its own set of clock ops.
1317 static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1318 .is_prepared = bcm2835_vpu_clock_is_on,
1319 .recalc_rate = bcm2835_clock_get_rate,
1320 .set_rate = bcm2835_clock_set_rate,
1321 .determine_rate = bcm2835_clock_determine_rate,
1322 .set_parent = bcm2835_clock_set_parent,
1323 .get_parent = bcm2835_clock_get_parent,
1324 .debug_init = bcm2835_clock_debug_init,
1327 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1328 const struct bcm2835_pll_data *data)
1330 struct bcm2835_pll *pll;
1331 struct clk_init_data init;
1334 memset(&init, 0, sizeof(init));
1336 /* All of the PLLs derive from the external oscillator. */
1337 init.parent_names = &cprman->real_parent_names[0];
1338 init.num_parents = 1;
1339 init.name = data->name;
1340 init.ops = &bcm2835_pll_clk_ops;
1341 init.flags = CLK_IGNORE_UNUSED;
1343 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1347 pll->cprman = cprman;
1349 pll->hw.init = &init;
1351 ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1359 static struct clk_hw *
1360 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1361 const struct bcm2835_pll_divider_data *data)
1363 struct bcm2835_pll_divider *divider;
1364 struct clk_init_data init;
1365 const char *divider_name;
1368 if (data->fixed_divider != 1) {
1369 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1370 "%s_prediv", data->name);
1374 divider_name = data->name;
1377 memset(&init, 0, sizeof(init));
1379 init.parent_names = &data->source_pll;
1380 init.num_parents = 1;
1381 init.name = divider_name;
1382 init.ops = &bcm2835_pll_divider_clk_ops;
1383 init.flags = data->flags | CLK_IGNORE_UNUSED;
1385 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1389 divider->div.reg = cprman->regs + data->a2w_reg;
1390 divider->div.shift = A2W_PLL_DIV_SHIFT;
1391 divider->div.width = A2W_PLL_DIV_BITS;
1392 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1393 divider->div.lock = &cprman->regs_lock;
1394 divider->div.hw.init = &init;
1395 divider->div.table = NULL;
1397 divider->cprman = cprman;
1398 divider->data = data;
1400 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);
1402 return ERR_PTR(ret);
1405 * PLLH's channels have a fixed divide by 10 afterwards, which
1406 * is what our consumers are actually using.
1408 if (data->fixed_divider != 1) {
1409 return clk_hw_register_fixed_factor(cprman->dev, data->name,
1411 CLK_SET_RATE_PARENT,
1413 data->fixed_divider);
1416 return ÷r->div.hw;
1419 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1420 const struct bcm2835_clock_data *data)
1422 struct bcm2835_clock *clock;
1423 struct clk_init_data init;
1424 const char *parents[1 << CM_SRC_BITS];
1429 * Replace our strings referencing parent clocks with the
1430 * actual clock-output-name of the parent.
1432 for (i = 0; i < data->num_mux_parents; i++) {
1433 parents[i] = data->parents[i];
1435 for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) {
1436 if (strcmp(parents[i], cprman_parent_names[j]) == 0) {
1437 parents[i] = cprman->real_parent_names[j];
1443 memset(&init, 0, sizeof(init));
1444 init.parent_names = parents;
1445 init.num_parents = data->num_mux_parents;
1446 init.name = data->name;
1447 init.flags = data->flags | CLK_IGNORE_UNUSED;
1450 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
1451 * rate changes on at least of the parents.
1453 if (data->set_rate_parent)
1454 init.flags |= CLK_SET_RATE_PARENT;
1456 if (data->is_vpu_clock) {
1457 init.ops = &bcm2835_vpu_clock_clk_ops;
1459 init.ops = &bcm2835_clock_clk_ops;
1460 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1462 /* If the clock wasn't actually enabled at boot, it's not
1465 if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE))
1466 init.flags &= ~CLK_IS_CRITICAL;
1469 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1473 clock->cprman = cprman;
1475 clock->hw.init = &init;
1477 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1479 return ERR_PTR(ret);
1483 static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1484 const struct bcm2835_gate_data *data)
1486 return clk_hw_register_gate(cprman->dev, data->name, data->parent,
1487 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1488 cprman->regs + data->ctl_reg,
1489 CM_GATE_BIT, 0, &cprman->regs_lock);
1492 typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
1494 struct bcm2835_clk_desc {
1495 bcm2835_clk_register clk_register;
1499 /* assignment helper macros for different clock types */
1500 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1501 .data = __VA_ARGS__ }
1502 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
1503 &(struct bcm2835_pll_data) \
1505 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
1506 &(struct bcm2835_pll_divider_data) \
1508 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
1509 &(struct bcm2835_clock_data) \
1511 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
1512 &(struct bcm2835_gate_data) \
1515 /* parent mux arrays plus helper macros */
1517 /* main oscillator parent mux */
1518 static const char *const bcm2835_clock_osc_parents[] = {
1525 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \
1526 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1527 .parents = bcm2835_clock_osc_parents, \
1530 /* main peripherial parent mux */
1531 static const char *const bcm2835_clock_per_parents[] = {
1542 #define REGISTER_PER_CLK(...) REGISTER_CLK( \
1543 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1544 .parents = bcm2835_clock_per_parents, \
1548 * Restrict clock sources for the PCM peripheral to the oscillator and
1549 * PLLD_PER because other source may have varying rates or be switched
1552 * Prevent other sources from being selected by replacing their names in
1553 * the list of potential parents with dummy entries (entry index is
1556 static const char *const bcm2835_pcm_per_parents[] = {
1567 #define REGISTER_PCM_CLK(...) REGISTER_CLK( \
1568 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
1569 .parents = bcm2835_pcm_per_parents, \
1572 /* main vpu parent mux */
1573 static const char *const bcm2835_clock_vpu_parents[] = {
1586 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \
1587 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1588 .parents = bcm2835_clock_vpu_parents, \
1592 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI
1593 * analog PHY. The _inv variants are generated internally to cprman,
1594 * but we don't use them so they aren't hooked up.
1596 static const char *const bcm2835_clock_dsi0_parents[] = {
1609 static const char *const bcm2835_clock_dsi1_parents[] = {
1622 #define REGISTER_DSI0_CLK(...) REGISTER_CLK( \
1623 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
1624 .parents = bcm2835_clock_dsi0_parents, \
1627 #define REGISTER_DSI1_CLK(...) REGISTER_CLK( \
1628 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
1629 .parents = bcm2835_clock_dsi1_parents, \
1633 * the real definition of all the pll, pll_dividers and clocks
1634 * these make use of the above REGISTER_* macros
1636 static const struct bcm2835_clk_desc clk_desc_array[] = {
1637 /* the PLL + PLL dividers */
1640 * PLLA is the auxiliary PLL, used to drive the CCP2
1641 * (Compact Camera Port 2) transmitter clock.
1643 * It is in the PX LDO power domain, which is on when the
1644 * AUDIO domain is on.
1646 [BCM2835_PLLA] = REGISTER_PLL(
1648 .cm_ctrl_reg = CM_PLLA,
1649 .a2w_ctrl_reg = A2W_PLLA_CTRL,
1650 .frac_reg = A2W_PLLA_FRAC,
1651 .ana_reg_base = A2W_PLLA_ANA0,
1652 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1653 .lock_mask = CM_LOCK_FLOCKA,
1655 .ana = &bcm2835_ana_default,
1657 .min_rate = 600000000u,
1658 .max_rate = 2400000000u,
1659 .max_fb_rate = BCM2835_MAX_FB_RATE),
1660 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1661 .name = "plla_core",
1662 .source_pll = "plla",
1664 .a2w_reg = A2W_PLLA_CORE,
1665 .load_mask = CM_PLLA_LOADCORE,
1666 .hold_mask = CM_PLLA_HOLDCORE,
1668 .flags = CLK_SET_RATE_PARENT),
1669 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1671 .source_pll = "plla",
1673 .a2w_reg = A2W_PLLA_PER,
1674 .load_mask = CM_PLLA_LOADPER,
1675 .hold_mask = CM_PLLA_HOLDPER,
1677 .flags = CLK_SET_RATE_PARENT),
1678 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1679 .name = "plla_dsi0",
1680 .source_pll = "plla",
1682 .a2w_reg = A2W_PLLA_DSI0,
1683 .load_mask = CM_PLLA_LOADDSI0,
1684 .hold_mask = CM_PLLA_HOLDDSI0,
1685 .fixed_divider = 1),
1686 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1687 .name = "plla_ccp2",
1688 .source_pll = "plla",
1690 .a2w_reg = A2W_PLLA_CCP2,
1691 .load_mask = CM_PLLA_LOADCCP2,
1692 .hold_mask = CM_PLLA_HOLDCCP2,
1694 .flags = CLK_SET_RATE_PARENT),
1696 /* PLLB is used for the ARM's clock. */
1697 [BCM2835_PLLB] = REGISTER_PLL(
1699 .cm_ctrl_reg = CM_PLLB,
1700 .a2w_ctrl_reg = A2W_PLLB_CTRL,
1701 .frac_reg = A2W_PLLB_FRAC,
1702 .ana_reg_base = A2W_PLLB_ANA0,
1703 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
1704 .lock_mask = CM_LOCK_FLOCKB,
1706 .ana = &bcm2835_ana_default,
1708 .min_rate = 600000000u,
1709 .max_rate = 3000000000u,
1710 .max_fb_rate = BCM2835_MAX_FB_RATE),
1711 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
1713 .source_pll = "pllb",
1715 .a2w_reg = A2W_PLLB_ARM,
1716 .load_mask = CM_PLLB_LOADARM,
1717 .hold_mask = CM_PLLB_HOLDARM,
1719 .flags = CLK_SET_RATE_PARENT),
1722 * PLLC is the core PLL, used to drive the core VPU clock.
1724 * It is in the PX LDO power domain, which is on when the
1725 * AUDIO domain is on.
1727 [BCM2835_PLLC] = REGISTER_PLL(
1729 .cm_ctrl_reg = CM_PLLC,
1730 .a2w_ctrl_reg = A2W_PLLC_CTRL,
1731 .frac_reg = A2W_PLLC_FRAC,
1732 .ana_reg_base = A2W_PLLC_ANA0,
1733 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1734 .lock_mask = CM_LOCK_FLOCKC,
1736 .ana = &bcm2835_ana_default,
1738 .min_rate = 600000000u,
1739 .max_rate = 3000000000u,
1740 .max_fb_rate = BCM2835_MAX_FB_RATE),
1741 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1742 .name = "pllc_core0",
1743 .source_pll = "pllc",
1745 .a2w_reg = A2W_PLLC_CORE0,
1746 .load_mask = CM_PLLC_LOADCORE0,
1747 .hold_mask = CM_PLLC_HOLDCORE0,
1749 .flags = CLK_SET_RATE_PARENT),
1750 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1751 .name = "pllc_core1",
1752 .source_pll = "pllc",
1754 .a2w_reg = A2W_PLLC_CORE1,
1755 .load_mask = CM_PLLC_LOADCORE1,
1756 .hold_mask = CM_PLLC_HOLDCORE1,
1758 .flags = CLK_SET_RATE_PARENT),
1759 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1760 .name = "pllc_core2",
1761 .source_pll = "pllc",
1763 .a2w_reg = A2W_PLLC_CORE2,
1764 .load_mask = CM_PLLC_LOADCORE2,
1765 .hold_mask = CM_PLLC_HOLDCORE2,
1767 .flags = CLK_SET_RATE_PARENT),
1768 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1770 .source_pll = "pllc",
1772 .a2w_reg = A2W_PLLC_PER,
1773 .load_mask = CM_PLLC_LOADPER,
1774 .hold_mask = CM_PLLC_HOLDPER,
1776 .flags = CLK_SET_RATE_PARENT),
1779 * PLLD is the display PLL, used to drive DSI display panels.
1781 * It is in the PX LDO power domain, which is on when the
1782 * AUDIO domain is on.
1784 [BCM2835_PLLD] = REGISTER_PLL(
1786 .cm_ctrl_reg = CM_PLLD,
1787 .a2w_ctrl_reg = A2W_PLLD_CTRL,
1788 .frac_reg = A2W_PLLD_FRAC,
1789 .ana_reg_base = A2W_PLLD_ANA0,
1790 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1791 .lock_mask = CM_LOCK_FLOCKD,
1793 .ana = &bcm2835_ana_default,
1795 .min_rate = 600000000u,
1796 .max_rate = 2400000000u,
1797 .max_fb_rate = BCM2835_MAX_FB_RATE),
1798 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1799 .name = "plld_core",
1800 .source_pll = "plld",
1802 .a2w_reg = A2W_PLLD_CORE,
1803 .load_mask = CM_PLLD_LOADCORE,
1804 .hold_mask = CM_PLLD_HOLDCORE,
1806 .flags = CLK_SET_RATE_PARENT),
1807 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1809 .source_pll = "plld",
1811 .a2w_reg = A2W_PLLD_PER,
1812 .load_mask = CM_PLLD_LOADPER,
1813 .hold_mask = CM_PLLD_HOLDPER,
1815 .flags = CLK_SET_RATE_PARENT),
1816 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1817 .name = "plld_dsi0",
1818 .source_pll = "plld",
1820 .a2w_reg = A2W_PLLD_DSI0,
1821 .load_mask = CM_PLLD_LOADDSI0,
1822 .hold_mask = CM_PLLD_HOLDDSI0,
1823 .fixed_divider = 1),
1824 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1825 .name = "plld_dsi1",
1826 .source_pll = "plld",
1828 .a2w_reg = A2W_PLLD_DSI1,
1829 .load_mask = CM_PLLD_LOADDSI1,
1830 .hold_mask = CM_PLLD_HOLDDSI1,
1831 .fixed_divider = 1),
1834 * PLLH is used to supply the pixel clock or the AUX clock for the
1837 * It is in the HDMI power domain.
1839 [BCM2835_PLLH] = REGISTER_PLL(
1841 .cm_ctrl_reg = CM_PLLH,
1842 .a2w_ctrl_reg = A2W_PLLH_CTRL,
1843 .frac_reg = A2W_PLLH_FRAC,
1844 .ana_reg_base = A2W_PLLH_ANA0,
1845 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1846 .lock_mask = CM_LOCK_FLOCKH,
1848 .ana = &bcm2835_ana_pllh,
1850 .min_rate = 600000000u,
1851 .max_rate = 3000000000u,
1852 .max_fb_rate = BCM2835_MAX_FB_RATE),
1853 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1854 .name = "pllh_rcal",
1855 .source_pll = "pllh",
1857 .a2w_reg = A2W_PLLH_RCAL,
1858 .load_mask = CM_PLLH_LOADRCAL,
1860 .fixed_divider = 10,
1861 .flags = CLK_SET_RATE_PARENT),
1862 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1864 .source_pll = "pllh",
1866 .a2w_reg = A2W_PLLH_AUX,
1867 .load_mask = CM_PLLH_LOADAUX,
1870 .flags = CLK_SET_RATE_PARENT),
1871 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1873 .source_pll = "pllh",
1875 .a2w_reg = A2W_PLLH_PIX,
1876 .load_mask = CM_PLLH_LOADPIX,
1878 .fixed_divider = 10,
1879 .flags = CLK_SET_RATE_PARENT),
1883 /* clocks with oscillator parent mux */
1885 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1886 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1888 .ctl_reg = CM_OTPCTL,
1889 .div_reg = CM_OTPDIV,
1894 * Used for a 1Mhz clock for the system clocksource, and also used
1895 * bythe watchdog timer and the camera pulse generator.
1897 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1899 .ctl_reg = CM_TIMERCTL,
1900 .div_reg = CM_TIMERDIV,
1904 * Clock for the temperature sensor.
1905 * Generally run at 2Mhz, max 5Mhz.
1907 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1909 .ctl_reg = CM_TSENSCTL,
1910 .div_reg = CM_TSENSDIV,
1913 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1915 .ctl_reg = CM_TECCTL,
1916 .div_reg = CM_TECDIV,
1920 /* clocks with vpu parent mux */
1921 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1923 .ctl_reg = CM_H264CTL,
1924 .div_reg = CM_H264DIV,
1928 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1930 .ctl_reg = CM_ISPCTL,
1931 .div_reg = CM_ISPDIV,
1937 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1938 * in the SDRAM controller can't be used.
1940 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
1942 .ctl_reg = CM_SDCCTL,
1943 .div_reg = CM_SDCDIV,
1947 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
1949 .ctl_reg = CM_V3DCTL,
1950 .div_reg = CM_V3DDIV,
1955 * VPU clock. This doesn't have an enable bit, since it drives
1956 * the bus for everything else, and is special so it doesn't need
1957 * to be gated for rate changes. It is also known as "clk_audio"
1958 * in various hardware documentation.
1960 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
1962 .ctl_reg = CM_VPUCTL,
1963 .div_reg = CM_VPUDIV,
1966 .flags = CLK_IS_CRITICAL,
1967 .is_vpu_clock = true,
1970 /* clocks with per parent mux */
1971 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
1973 .ctl_reg = CM_AVEOCTL,
1974 .div_reg = CM_AVEODIV,
1978 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
1980 .ctl_reg = CM_CAM0CTL,
1981 .div_reg = CM_CAM0DIV,
1985 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
1987 .ctl_reg = CM_CAM1CTL,
1988 .div_reg = CM_CAM1DIV,
1992 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
1994 .ctl_reg = CM_DFTCTL,
1995 .div_reg = CM_DFTDIV,
1998 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
2000 .ctl_reg = CM_DPICTL,
2001 .div_reg = CM_DPIDIV,
2006 /* Arasan EMMC clock */
2007 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
2009 .ctl_reg = CM_EMMCCTL,
2010 .div_reg = CM_EMMCDIV,
2015 /* General purpose (GPIO) clocks */
2016 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
2018 .ctl_reg = CM_GP0CTL,
2019 .div_reg = CM_GP0DIV,
2022 .is_mash_clock = true,
2024 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
2026 .ctl_reg = CM_GP1CTL,
2027 .div_reg = CM_GP1DIV,
2030 .flags = CLK_IS_CRITICAL,
2031 .is_mash_clock = true,
2033 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
2035 .ctl_reg = CM_GP2CTL,
2036 .div_reg = CM_GP2DIV,
2039 .flags = CLK_IS_CRITICAL),
2041 /* HDMI state machine */
2042 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
2044 .ctl_reg = CM_HSMCTL,
2045 .div_reg = CM_HSMDIV,
2049 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
2051 .ctl_reg = CM_PCMCTL,
2052 .div_reg = CM_PCMDIV,
2055 .is_mash_clock = true,
2058 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
2060 .ctl_reg = CM_PWMCTL,
2061 .div_reg = CM_PWMDIV,
2064 .is_mash_clock = true,
2066 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
2068 .ctl_reg = CM_SLIMCTL,
2069 .div_reg = CM_SLIMDIV,
2072 .is_mash_clock = true,
2074 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
2076 .ctl_reg = CM_SMICTL,
2077 .div_reg = CM_SMIDIV,
2081 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
2083 .ctl_reg = CM_UARTCTL,
2084 .div_reg = CM_UARTDIV,
2089 /* TV encoder clock. Only operating frequency is 108Mhz. */
2090 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
2092 .ctl_reg = CM_VECCTL,
2093 .div_reg = CM_VECDIV,
2097 * Allow rate change propagation only on PLLH_AUX which is
2098 * assigned index 7 in the parent array.
2100 .set_rate_parent = BIT(7),
2104 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
2106 .ctl_reg = CM_DSI0ECTL,
2107 .div_reg = CM_DSI0EDIV,
2111 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
2113 .ctl_reg = CM_DSI1ECTL,
2114 .div_reg = CM_DSI1EDIV,
2118 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
2120 .ctl_reg = CM_DSI0PCTL,
2121 .div_reg = CM_DSI0PDIV,
2125 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
2127 .ctl_reg = CM_DSI1PCTL,
2128 .div_reg = CM_DSI1PDIV,
2136 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
2137 * you have the debug bit set in the power manager, which we
2138 * don't bother exposing) are individual gates off of the
2139 * non-stop vpu clock.
2141 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2142 .name = "peri_image",
2144 .ctl_reg = CM_PERIICTL),
2148 * Permanently take a reference on the parent of the SDRAM clock.
2150 * While the SDRAM is being driven by its dedicated PLL most of the
2151 * time, there is a little loop running in the firmware that
2152 * periodically switches the SDRAM to using our CM clock to do PVT
2153 * recalibration, with the assumption that the previously configured
2154 * SDRAM parent is still enabled and running.
2156 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2158 struct clk *parent = clk_get_parent(sdc);
2161 return PTR_ERR(parent);
2163 return clk_prepare_enable(parent);
2166 static int bcm2835_clk_probe(struct platform_device *pdev)
2168 struct device *dev = &pdev->dev;
2169 struct clk_hw **hws;
2170 struct bcm2835_cprman *cprman;
2171 struct resource *res;
2172 const struct bcm2835_clk_desc *desc;
2173 const size_t asize = ARRAY_SIZE(clk_desc_array);
2177 cprman = devm_kzalloc(dev, sizeof(*cprman) +
2178 sizeof(*cprman->onecell.hws) * asize,
2183 spin_lock_init(&cprman->regs_lock);
2185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2186 cprman->regs = devm_ioremap_resource(dev, res);
2187 if (IS_ERR(cprman->regs))
2188 return PTR_ERR(cprman->regs);
2190 memcpy(cprman->real_parent_names, cprman_parent_names,
2191 sizeof(cprman_parent_names));
2192 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2193 ARRAY_SIZE(cprman_parent_names));
2196 * Make sure the external oscillator has been registered.
2198 * The other (DSI) clocks are not present on older device
2199 * trees, which we still need to support for backwards
2202 if (!cprman->real_parent_names[0])
2205 platform_set_drvdata(pdev, cprman);
2207 cprman->onecell.num = asize;
2208 hws = cprman->onecell.hws;
2210 for (i = 0; i < asize; i++) {
2211 desc = &clk_desc_array[i];
2212 if (desc->clk_register && desc->data)
2213 hws[i] = desc->clk_register(cprman, desc->data);
2216 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
2220 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2224 static const struct of_device_id bcm2835_clk_of_match[] = {
2225 { .compatible = "brcm,bcm2835-cprman", },
2228 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
2230 static struct platform_driver bcm2835_clk_driver = {
2232 .name = "bcm2835-clk",
2233 .of_match_table = bcm2835_clk_of_match,
2235 .probe = bcm2835_clk_probe,
2238 builtin_platform_driver(bcm2835_clk_driver);
2240 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2241 MODULE_DESCRIPTION("BCM2835 clock driver");
2242 MODULE_LICENSE("GPL v2");