drivers/clk/berlin/bg2q.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014 Marvell Technology Group Ltd.
   4  *
   5  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
   6  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/kernel.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/slab.h>
  15
  16 #include <dt-bindings/clock/berlin2q.h>
  17
  18 #include "berlin2-div.h"
  19 #include "berlin2-pll.h"
  20 #include "common.h"
  21
  22 #define REG_PINMUX0             0x0018
  23 #define REG_PINMUX5             0x002c
  24 #define REG_SYSPLLCTL0          0x0030
  25 #define REG_SYSPLLCTL4          0x0040
  26 #define REG_CLKENABLE           0x00e8
  27 #define REG_CLKSELECT0          0x00ec
  28 #define REG_CLKSELECT1          0x00f0
  29 #define REG_CLKSELECT2          0x00f4
  30 #define REG_CLKSWITCH0          0x00f8
  31 #define REG_CLKSWITCH1          0x00fc
  32 #define REG_SW_GENERIC0         0x0110
  33 #define REG_SW_GENERIC3         0x011c
  34 #define REG_SDIO0XIN_CLKCTL     0x0158
  35 #define REG_SDIO1XIN_CLKCTL     0x015c
  36
  37 #define MAX_CLKS 28
  38 static struct clk_hw_onecell_data *clk_data;
  39 static DEFINE_SPINLOCK(lock);
  40 static void __iomem *gbase;
  41 static void __iomem *cpupll_base;
  42
  43 enum {
  44         REFCLK,
  45         SYSPLL, CPUPLL,
  46         AVPLL_B1, AVPLL_B2, AVPLL_B3, AVPLL_B4,
  47         AVPLL_B5, AVPLL_B6, AVPLL_B7, AVPLL_B8,
  48 };
  49
  50 static const char *clk_names[] = {
  51         [REFCLK]                = "refclk",
  52         [SYSPLL]                = "syspll",
  53         [CPUPLL]                = "cpupll",
  54         [AVPLL_B1]              = "avpll_b1",
  55         [AVPLL_B2]              = "avpll_b2",
  56         [AVPLL_B3]              = "avpll_b3",
  57         [AVPLL_B4]              = "avpll_b4",
  58         [AVPLL_B5]              = "avpll_b5",
  59         [AVPLL_B6]              = "avpll_b6",
  60         [AVPLL_B7]              = "avpll_b7",
  61         [AVPLL_B8]              = "avpll_b8",
  62 };
  63
  64 static const struct berlin2_pll_map bg2q_pll_map __initconst = {
  65         .vcodiv         = {1, 0, 2, 0, 3, 4, 0, 6, 8},
  66         .mult           = 1,
  67         .fbdiv_shift    = 7,
  68         .rfdiv_shift    = 2,
  69         .divsel_shift   = 9,
  70 };
  71
  72 static const u8 default_parent_ids[] = {
  73         SYSPLL, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, SYSPLL
  74 };
  75
  76 static const struct berlin2_div_data bg2q_divs[] __initconst = {
  77         {
  78                 .name = "sys",
  79                 .parent_ids = default_parent_ids,
  80                 .num_parents = ARRAY_SIZE(default_parent_ids),
  81                 .map = {
  82                         BERLIN2_DIV_GATE(REG_CLKENABLE, 0),
  83                         BERLIN2_PLL_SELECT(REG_CLKSELECT0, 0),
  84                         BERLIN2_DIV_SELECT(REG_CLKSELECT0, 3),
  85                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 3),
  86                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4),
  87                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 5),
  88                 },
  89                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
  90                 .flags = CLK_IGNORE_UNUSED,
  91         },
  92         {
  93                 .name = "drmfigo",
  94                 .parent_ids = default_parent_ids,
  95                 .num_parents = ARRAY_SIZE(default_parent_ids),
  96                 .map = {
  97                         BERLIN2_DIV_GATE(REG_CLKENABLE, 17),
  98                         BERLIN2_PLL_SELECT(REG_CLKSELECT0, 6),
  99                         BERLIN2_DIV_SELECT(REG_CLKSELECT0, 9),
 100                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 6),
 101                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 7),
 102                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 8),
 103                 },
 104                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 105                 .flags = 0,
 106         },
 107         {
 108                 .name = "cfg",
 109                 .parent_ids = default_parent_ids,
 110                 .num_parents = ARRAY_SIZE(default_parent_ids),
 111                 .map = {
 112                         BERLIN2_DIV_GATE(REG_CLKENABLE, 1),
 113                         BERLIN2_PLL_SELECT(REG_CLKSELECT0, 12),
 114                         BERLIN2_DIV_SELECT(REG_CLKSELECT0, 15),
 115                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 9),
 116                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 10),
 117                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 11),
 118                 },
 119                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 120                 .flags = 0,
 121         },
 122         {
 123                 .name = "gfx2d",
 124                 .parent_ids = default_parent_ids,
 125                 .num_parents = ARRAY_SIZE(default_parent_ids),
 126                 .map = {
 127                         BERLIN2_DIV_GATE(REG_CLKENABLE, 4),
 128                         BERLIN2_PLL_SELECT(REG_CLKSELECT0, 18),
 129                         BERLIN2_DIV_SELECT(REG_CLKSELECT0, 21),
 130                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 12),
 131                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 13),
 132                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 14),
 133                 },
 134                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 135                 .flags = 0,
 136         },
 137         {
 138                 .name = "zsp",
 139                 .parent_ids = default_parent_ids,
 140                 .num_parents = ARRAY_SIZE(default_parent_ids),
 141                 .map = {
 142                         BERLIN2_DIV_GATE(REG_CLKENABLE, 6),
 143                         BERLIN2_PLL_SELECT(REG_CLKSELECT0, 24),
 144                         BERLIN2_DIV_SELECT(REG_CLKSELECT0, 27),
 145                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 15),
 146                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 16),
 147                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 17),
 148                 },
 149                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 150                 .flags = 0,
 151         },
 152         {
 153                 .name = "perif",
 154                 .parent_ids = default_parent_ids,
 155                 .num_parents = ARRAY_SIZE(default_parent_ids),
 156                 .map = {
 157                         BERLIN2_DIV_GATE(REG_CLKENABLE, 7),
 158                         BERLIN2_PLL_SELECT(REG_CLKSELECT1, 0),
 159                         BERLIN2_DIV_SELECT(REG_CLKSELECT1, 3),
 160                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 18),
 161                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 19),
 162                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 20),
 163                 },
 164                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 165                 .flags = CLK_IGNORE_UNUSED,
 166         },
 167         {
 168                 .name = "pcube",
 169                 .parent_ids = default_parent_ids,
 170                 .num_parents = ARRAY_SIZE(default_parent_ids),
 171                 .map = {
 172                         BERLIN2_DIV_GATE(REG_CLKENABLE, 2),
 173                         BERLIN2_PLL_SELECT(REG_CLKSELECT1, 6),
 174                         BERLIN2_DIV_SELECT(REG_CLKSELECT1, 9),
 175                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 21),
 176                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 22),
 177                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 23),
 178                 },
 179                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 180                 .flags = 0,
 181         },
 182         {
 183                 .name = "vscope",
 184                 .parent_ids = default_parent_ids,
 185                 .num_parents = ARRAY_SIZE(default_parent_ids),
 186                 .map = {
 187                         BERLIN2_DIV_GATE(REG_CLKENABLE, 3),
 188                         BERLIN2_PLL_SELECT(REG_CLKSELECT1, 12),
 189                         BERLIN2_DIV_SELECT(REG_CLKSELECT1, 15),
 190                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 24),
 191                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 25),
 192                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 26),
 193                 },
 194                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 195                 .flags = 0,
 196         },
 197         {
 198                 .name = "nfc_ecc",
 199                 .parent_ids = default_parent_ids,
 200                 .num_parents = ARRAY_SIZE(default_parent_ids),
 201                 .map = {
 202                         BERLIN2_DIV_GATE(REG_CLKENABLE, 19),
 203                         BERLIN2_PLL_SELECT(REG_CLKSELECT1, 18),
 204                         BERLIN2_DIV_SELECT(REG_CLKSELECT1, 21),
 205                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 27),
 206                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 28),
 207                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 29),
 208                 },
 209                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 210                 .flags = 0,
 211         },
 212         {
 213                 .name = "vpp",
 214                 .parent_ids = default_parent_ids,
 215                 .num_parents = ARRAY_SIZE(default_parent_ids),
 216                 .map = {
 217                         BERLIN2_DIV_GATE(REG_CLKENABLE, 21),
 218                         BERLIN2_PLL_SELECT(REG_CLKSELECT1, 24),
 219                         BERLIN2_DIV_SELECT(REG_CLKSELECT1, 27),
 220                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 30),
 221                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 31),
 222                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 0),
 223                 },
 224                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 225                 .flags = 0,
 226         },
 227         {
 228                 .name = "app",
 229                 .parent_ids = default_parent_ids,
 230                 .num_parents = ARRAY_SIZE(default_parent_ids),
 231                 .map = {
 232                         BERLIN2_DIV_GATE(REG_CLKENABLE, 20),
 233                         BERLIN2_PLL_SELECT(REG_CLKSELECT2, 0),
 234                         BERLIN2_DIV_SELECT(REG_CLKSELECT2, 3),
 235                         BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 1),
 236                         BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 2),
 237                         BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 3),
 238                 },
 239                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 240                 .flags = 0,
 241         },
 242         {
 243                 .name = "sdio0xin",
 244                 .parent_ids = default_parent_ids,
 245                 .num_parents = ARRAY_SIZE(default_parent_ids),
 246                 .map = {
 247                         BERLIN2_SINGLE_DIV(REG_SDIO0XIN_CLKCTL),
 248                 },
 249                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 250                 .flags = 0,
 251         },
 252         {
 253                 .name = "sdio1xin",
 254                 .parent_ids = default_parent_ids,
 255                 .num_parents = ARRAY_SIZE(default_parent_ids),
 256                 .map = {
 257                         BERLIN2_SINGLE_DIV(REG_SDIO1XIN_CLKCTL),
 258                 },
 259                 .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
 260                 .flags = 0,
 261         },
 262 };
 263
 264 static const struct berlin2_gate_data bg2q_gates[] __initconst = {
 265         { "gfx2daxi",   "perif",        5 },
 266         { "geth0",      "perif",        8 },
 267         { "sata",       "perif",        9 },
 268         { "ahbapb",     "perif",        10, CLK_IGNORE_UNUSED },
 269         { "usb0",       "perif",        11 },
 270         { "usb1",       "perif",        12 },
 271         { "usb2",       "perif",        13 },
 272         { "usb3",       "perif",        14 },
 273         { "pbridge",    "perif",        15, CLK_IGNORE_UNUSED },
 274         { "sdio",       "perif",        16 },
 275         { "nfc",        "perif",        18 },
 276         { "pcie",       "perif",        22 },
 277 };
 278
 279 static void __init berlin2q_clock_setup(struct device_node *np)
 280 {
 281         struct device_node *parent_np = of_get_parent(np);
 282         const char *parent_names[9];
 283         struct clk *clk;
 284         struct clk_hw **hws;
 285         int n, ret;
 286
 287         clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
 288         if (!clk_data) {
 289                 of_node_put(parent_np);
 290                 return;
 291         }
 292         clk_data->num = MAX_CLKS;
 293         hws = clk_data->hws;
 294
 295         gbase = of_iomap(parent_np, 0);
 296         if (!gbase) {
 297                 of_node_put(parent_np);
 298                 pr_err("%pOF: Unable to map global base\n", np);
 299                 return;
 300         }
 301
 302         /* BG2Q CPU PLL is not part of global registers */
 303         cpupll_base = of_iomap(parent_np, 1);
 304         of_node_put(parent_np);
 305         if (!cpupll_base) {
 306                 pr_err("%pOF: Unable to map cpupll base\n", np);
 307                 iounmap(gbase);
 308                 return;
 309         }
 310
 311         /* overwrite default clock names with DT provided ones */
 312         clk = of_clk_get_by_name(np, clk_names[REFCLK]);
 313         if (!IS_ERR(clk)) {
 314                 clk_names[REFCLK] = __clk_get_name(clk);
 315                 clk_put(clk);
 316         }
 317
 318         /* simple register PLLs */
 319         ret = berlin2_pll_register(&bg2q_pll_map, gbase + REG_SYSPLLCTL0,
 320                                    clk_names[SYSPLL], clk_names[REFCLK], 0);
 321         if (ret)
 322                 goto bg2q_fail;
 323
 324         ret = berlin2_pll_register(&bg2q_pll_map, cpupll_base,
 325                                    clk_names[CPUPLL], clk_names[REFCLK], 0);
 326         if (ret)
 327                 goto bg2q_fail;
 328
 329         /* TODO: add BG2Q AVPLL */
 330
 331         /*
 332          * TODO: add reference clock bypass switches:
 333          * memPLLSWBypass, cpuPLLSWBypass, and sysPLLSWBypass
 334          */
 335
 336         /* clock divider cells */
 337         for (n = 0; n < ARRAY_SIZE(bg2q_divs); n++) {
 338                 const struct berlin2_div_data *dd = &bg2q_divs[n];
 339                 int k;
 340
 341                 for (k = 0; k < dd->num_parents; k++)
 342                         parent_names[k] = clk_names[dd->parent_ids[k]];
 343
 344                 hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase,
 345                                 dd->name, dd->div_flags, parent_names,
 346                                 dd->num_parents, dd->flags, &lock);
 347         }
 348
 349         /* clock gate cells */
 350         for (n = 0; n < ARRAY_SIZE(bg2q_gates); n++) {
 351                 const struct berlin2_gate_data *gd = &bg2q_gates[n];
 352
 353                 hws[CLKID_GFX2DAXI + n] = clk_hw_register_gate(NULL, gd->name,
 354                             gd->parent_name, gd->flags, gbase + REG_CLKENABLE,
 355                             gd->bit_idx, 0, &lock);
 356         }
 357
 358         /* cpuclk divider is fixed to 1 */
 359         hws[CLKID_CPU] =
 360                 clk_hw_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL],
 361                                           0, 1, 1);
 362         /* twdclk is derived from cpu/3 */
 363         hws[CLKID_TWD] =
 364                 clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
 365
 366         /* check for errors on leaf clocks */
 367         for (n = 0; n < MAX_CLKS; n++) {
 368                 if (!IS_ERR(hws[n]))
 369                         continue;
 370
 371                 pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
 372                 goto bg2q_fail;
 373         }
 374
 375         /* register clk-provider */
 376         of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 377
 378         return;
 379
 380 bg2q_fail:
 381         iounmap(cpupll_base);
 382         iounmap(gbase);
 383 }
 384 CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",
 385                berlin2q_clock_setup);