2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Simple multiplexer clock implementation
13 #include <linux/clk-provider.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
17 #include <linux/err.h>
20 * DOC: basic adjustable multiplexer clock that cannot gate
22 * Traits of this clock:
23 * prepare - clk_prepare only ensures that parents are prepared
24 * enable - clk_enable only ensures that parents are enabled
25 * rate - rate is only affected by parent switching. No clk_set_rate support
26 * parent - parent is adjustable through clk_set_parent
29 static u8 clk_mux_get_parent(struct clk_hw *hw)
31 struct clk_mux *mux = to_clk_mux(hw);
32 int num_parents = clk_hw_get_num_parents(hw);
36 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
37 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
38 * to 0x7 (index starts at one)
39 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
40 * val = 0x4 really means "bit 2, index starts at bit 0"
42 val = clk_readl(mux->reg) >> mux->shift;
48 for (i = 0; i < num_parents; i++)
49 if (mux->table[i] == val)
54 if (val && (mux->flags & CLK_MUX_INDEX_BIT))
57 if (val && (mux->flags & CLK_MUX_INDEX_ONE))
60 if (val >= num_parents)
66 static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
68 struct clk_mux *mux = to_clk_mux(hw);
70 unsigned long flags = 0;
73 index = mux->table[index];
75 if (mux->flags & CLK_MUX_INDEX_BIT)
78 if (mux->flags & CLK_MUX_INDEX_ONE)
83 spin_lock_irqsave(mux->lock, flags);
87 if (mux->flags & CLK_MUX_HIWORD_MASK) {
88 val = mux->mask << (mux->shift + 16);
90 val = clk_readl(mux->reg);
91 val &= ~(mux->mask << mux->shift);
93 val |= index << mux->shift;
94 clk_writel(val, mux->reg);
97 spin_unlock_irqrestore(mux->lock, flags);
104 static int clk_mux_determine_rate(struct clk_hw *hw,
105 struct clk_rate_request *req)
107 struct clk_mux *mux = to_clk_mux(hw);
109 return clk_mux_determine_rate_flags(hw, req, mux->flags);
112 const struct clk_ops clk_mux_ops = {
113 .get_parent = clk_mux_get_parent,
114 .set_parent = clk_mux_set_parent,
115 .determine_rate = clk_mux_determine_rate,
117 EXPORT_SYMBOL_GPL(clk_mux_ops);
119 const struct clk_ops clk_mux_ro_ops = {
120 .get_parent = clk_mux_get_parent,
122 EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
124 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
125 const char * const *parent_names, u8 num_parents,
127 void __iomem *reg, u8 shift, u32 mask,
128 u8 clk_mux_flags, u32 *table, spinlock_t *lock)
132 struct clk_init_data init;
136 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
137 width = fls(mask) - ffs(mask) + 1;
138 if (width + shift > 16) {
139 pr_err("mux value exceeds LOWORD field\n");
140 return ERR_PTR(-EINVAL);
144 /* allocate the mux */
145 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
147 pr_err("%s: could not allocate mux clk\n", __func__);
148 return ERR_PTR(-ENOMEM);
152 if (clk_mux_flags & CLK_MUX_READ_ONLY)
153 init.ops = &clk_mux_ro_ops;
155 init.ops = &clk_mux_ops;
156 init.flags = flags | CLK_IS_BASIC;
157 init.parent_names = parent_names;
158 init.num_parents = num_parents;
160 /* struct clk_mux assignments */
164 mux->flags = clk_mux_flags;
167 mux->hw.init = &init;
170 ret = clk_hw_register(dev, hw);
178 EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);
180 struct clk *clk_register_mux_table(struct device *dev, const char *name,
181 const char * const *parent_names, u8 num_parents,
183 void __iomem *reg, u8 shift, u32 mask,
184 u8 clk_mux_flags, u32 *table, spinlock_t *lock)
188 hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
189 flags, reg, shift, mask, clk_mux_flags,
195 EXPORT_SYMBOL_GPL(clk_register_mux_table);
197 struct clk *clk_register_mux(struct device *dev, const char *name,
198 const char * const *parent_names, u8 num_parents,
200 void __iomem *reg, u8 shift, u8 width,
201 u8 clk_mux_flags, spinlock_t *lock)
203 u32 mask = BIT(width) - 1;
205 return clk_register_mux_table(dev, name, parent_names, num_parents,
206 flags, reg, shift, mask, clk_mux_flags,
209 EXPORT_SYMBOL_GPL(clk_register_mux);
211 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
212 const char * const *parent_names, u8 num_parents,
214 void __iomem *reg, u8 shift, u8 width,
215 u8 clk_mux_flags, spinlock_t *lock)
217 u32 mask = BIT(width) - 1;
219 return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
220 flags, reg, shift, mask, clk_mux_flags,
223 EXPORT_SYMBOL_GPL(clk_hw_register_mux);
225 void clk_unregister_mux(struct clk *clk)
230 hw = __clk_get_hw(clk);
234 mux = to_clk_mux(hw);
239 EXPORT_SYMBOL_GPL(clk_unregister_mux);
241 void clk_hw_unregister_mux(struct clk_hw *hw)
245 mux = to_clk_mux(hw);
247 clk_hw_unregister(hw);
250 EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);