drivers/clk/clk-versaclock5.c

   1 /*
   2  * Driver for IDT Versaclock 5
   3  *
   4  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 /*
  18  * Possible optimizations:
  19  * - Use spread spectrum
  20  * - Use integer divider in FOD if applicable
  21  */
  22
  23 #include <linux/clk.h>
  24 #include <linux/clk-provider.h>
  25 #include <linux/delay.h>
  26 #include <linux/i2c.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/mod_devicetable.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/rational.h>
  33 #include <linux/regmap.h>
  34 #include <linux/slab.h>
  35
  36 /* VersaClock5 registers */
  37 #define VC5_OTP_CONTROL                         0x00
  38
  39 /* Factory-reserved register block */
  40 #define VC5_RSVD_DEVICE_ID                      0x01
  41 #define VC5_RSVD_ADC_GAIN_7_0                   0x02
  42 #define VC5_RSVD_ADC_GAIN_15_8                  0x03
  43 #define VC5_RSVD_ADC_OFFSET_7_0                 0x04
  44 #define VC5_RSVD_ADC_OFFSET_15_8                0x05
  45 #define VC5_RSVD_TEMPY                          0x06
  46 #define VC5_RSVD_OFFSET_TBIN                    0x07
  47 #define VC5_RSVD_GAIN                           0x08
  48 #define VC5_RSVD_TEST_NP                        0x09
  49 #define VC5_RSVD_UNUSED                         0x0a
  50 #define VC5_RSVD_BANDGAP_TRIM_UP                0x0b
  51 #define VC5_RSVD_BANDGAP_TRIM_DN                0x0c
  52 #define VC5_RSVD_CLK_R_12_CLK_AMP_4             0x0d
  53 #define VC5_RSVD_CLK_R_34_CLK_AMP_4             0x0e
  54 #define VC5_RSVD_CLK_AMP_123                    0x0f
  55
  56 /* Configuration register block */
  57 #define VC5_PRIM_SRC_SHDN                       0x10
  58 #define VC5_PRIM_SRC_SHDN_EN_XTAL               BIT(7)
  59 #define VC5_PRIM_SRC_SHDN_EN_CLKIN              BIT(6)
  60 #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ   BIT(3)
  61 #define VC5_PRIM_SRC_SHDN_SP                    BIT(1)
  62 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN           BIT(0)
  63
  64 #define VC5_VCO_BAND                            0x11
  65 #define VC5_XTAL_X1_LOAD_CAP                    0x12
  66 #define VC5_XTAL_X2_LOAD_CAP                    0x13
  67 #define VC5_REF_DIVIDER                         0x15
  68 #define VC5_REF_DIVIDER_SEL_PREDIV2             BIT(7)
  69 #define VC5_REF_DIVIDER_REF_DIV(n)              ((n) & 0x3f)
  70
  71 #define VC5_VCO_CTRL_AND_PREDIV                 0x16
  72 #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV   BIT(7)
  73
  74 #define VC5_FEEDBACK_INT_DIV                    0x17
  75 #define VC5_FEEDBACK_INT_DIV_BITS               0x18
  76 #define VC5_FEEDBACK_FRAC_DIV(n)                (0x19 + (n))
  77 #define VC5_RC_CONTROL0                         0x1e
  78 #define VC5_RC_CONTROL1                         0x1f
  79 /* Register 0x20 is factory reserved */
  80
  81 /* Output divider control for divider 1,2,3,4 */
  82 #define VC5_OUT_DIV_CONTROL(idx)        (0x21 + ((idx) * 0x10))
  83 #define VC5_OUT_DIV_CONTROL_RESET       BIT(7)
  84 #define VC5_OUT_DIV_CONTROL_SELB_NORM   BIT(3)
  85 #define VC5_OUT_DIV_CONTROL_SEL_EXT     BIT(2)
  86 #define VC5_OUT_DIV_CONTROL_INT_MODE    BIT(1)
  87 #define VC5_OUT_DIV_CONTROL_EN_FOD      BIT(0)
  88
  89 #define VC5_OUT_DIV_FRAC(idx, n)        (0x22 + ((idx) * 0x10) + (n))
  90 #define VC5_OUT_DIV_FRAC4_OD_SCEE       BIT(1)
  91
  92 #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
  93 #define VC5_OUT_DIV_SPREAD_MOD(idx, n)  (0x29 + ((idx) * 0x10) + (n))
  94 #define VC5_OUT_DIV_SKEW_INT(idx, n)    (0x2b + ((idx) * 0x10) + (n))
  95 #define VC5_OUT_DIV_INT(idx, n)         (0x2d + ((idx) * 0x10) + (n))
  96 #define VC5_OUT_DIV_SKEW_FRAC(idx)      (0x2f + ((idx) * 0x10))
  97 /* Registers 0x30, 0x40, 0x50 are factory reserved */
  98
  99 /* Clock control register for clock 1,2 */
 100 #define VC5_CLK_OUTPUT_CFG(idx, n)      (0x60 + ((idx) * 0x2) + (n))
 101 #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF   BIT(0)
 102
 103 #define VC5_CLK_OE_SHDN                         0x68
 104 #define VC5_CLK_OS_SHDN                         0x69
 105
 106 #define VC5_GLOBAL_REGISTER                     0x76
 107 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET        BIT(5)
 108
 109 /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */
 110 #define VC5_PLL_VCO_MIN                         2500000000UL
 111 #define VC5_PLL_VCO_MAX                         3000000000UL
 112
 113 /* VC5 Input mux settings */
 114 #define VC5_MUX_IN_XIN          BIT(0)
 115 #define VC5_MUX_IN_CLKIN        BIT(1)
 116
 117 /* Maximum number of clk_out supported by this driver */
 118 #define VC5_MAX_CLK_OUT_NUM     5
 119
 120 /* Maximum number of FODs supported by this driver */
 121 #define VC5_MAX_FOD_NUM 4
 122
 123 /* flags to describe chip features */
 124 /* chip has built-in oscilator */
 125 #define VC5_HAS_INTERNAL_XTAL   BIT(0)
 126 /* chip has PFD requency doubler */
 127 #define VC5_HAS_PFD_FREQ_DBL    BIT(1)
 128
 129 /* Supported IDT VC5 models. */
 130 enum vc5_model {
 131         IDT_VC5_5P49V5923,
 132         IDT_VC5_5P49V5925,
 133         IDT_VC5_5P49V5933,
 134         IDT_VC5_5P49V5935,
 135         IDT_VC6_5P49V6901,
 136 };
 137
 138 /* Structure to describe features of a particular VC5 model */
 139 struct vc5_chip_info {
 140         const enum vc5_model    model;
 141         const unsigned int      clk_fod_cnt;
 142         const unsigned int      clk_out_cnt;
 143         const u32               flags;
 144 };
 145
 146 struct vc5_driver_data;
 147
 148 struct vc5_hw_data {
 149         struct clk_hw           hw;
 150         struct vc5_driver_data  *vc5;
 151         u32                     div_int;
 152         u32                     div_frc;
 153         unsigned int            num;
 154 };
 155
 156 struct vc5_driver_data {
 157         struct i2c_client       *client;
 158         struct regmap           *regmap;
 159         const struct vc5_chip_info      *chip_info;
 160
 161         struct clk              *pin_xin;
 162         struct clk              *pin_clkin;
 163         unsigned char           clk_mux_ins;
 164         struct clk_hw           clk_mux;
 165         struct clk_hw           clk_mul;
 166         struct clk_hw           clk_pfd;
 167         struct vc5_hw_data      clk_pll;
 168         struct vc5_hw_data      clk_fod[VC5_MAX_FOD_NUM];
 169         struct vc5_hw_data      clk_out[VC5_MAX_CLK_OUT_NUM];
 170 };
 171
 172 static const char * const vc5_mux_names[] = {
 173         "mux"
 174 };
 175
 176 static const char * const vc5_dbl_names[] = {
 177         "dbl"
 178 };
 179
 180 static const char * const vc5_pfd_names[] = {
 181         "pfd"
 182 };
 183
 184 static const char * const vc5_pll_names[] = {
 185         "pll"
 186 };
 187
 188 static const char * const vc5_fod_names[] = {
 189         "fod0", "fod1", "fod2", "fod3",
 190 };
 191
 192 static const char * const vc5_clk_out_names[] = {
 193         "out0_sel_i2cb", "out1", "out2", "out3", "out4",
 194 };
 195
 196 /*
 197  * VersaClock5 i2c regmap
 198  */
 199 static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
 200 {
 201         /* Factory reserved regs, make them read-only */
 202         if (reg <= 0xf)
 203                 return false;
 204
 205         /* Factory reserved regs, make them read-only */
 206         if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
 207                 return false;
 208
 209         return true;
 210 }
 211
 212 static const struct regmap_config vc5_regmap_config = {
 213         .reg_bits = 8,
 214         .val_bits = 8,
 215         .cache_type = REGCACHE_RBTREE,
 216         .max_register = 0x76,
 217         .writeable_reg = vc5_regmap_is_writeable,
 218 };
 219
 220 /*
 221  * VersaClock5 input multiplexer between XTAL and CLKIN divider
 222  */
 223 static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
 224 {
 225         struct vc5_driver_data *vc5 =
 226                 container_of(hw, struct vc5_driver_data, clk_mux);
 227         const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
 228         unsigned int src;
 229
 230         regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
 231         src &= mask;
 232
 233         if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
 234                 return 0;
 235
 236         if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
 237                 return 1;
 238
 239         dev_warn(&vc5->client->dev,
 240                  "Invalid clock input configuration (%02x)\n", src);
 241         return 0;
 242 }
 243
 244 static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
 245 {
 246         struct vc5_driver_data *vc5 =
 247                 container_of(hw, struct vc5_driver_data, clk_mux);
 248         const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
 249         u8 src;
 250
 251         if ((index > 1) || !vc5->clk_mux_ins)
 252                 return -EINVAL;
 253
 254         if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
 255                 if (index == 0)
 256                         src = VC5_PRIM_SRC_SHDN_EN_XTAL;
 257                 if (index == 1)
 258                         src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
 259         } else {
 260                 if (index != 0)
 261                         return -EINVAL;
 262
 263                 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
 264                         src = VC5_PRIM_SRC_SHDN_EN_XTAL;
 265                 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
 266                         src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
 267                 else /* Invalid; should have been caught by vc5_probe() */
 268                         return -EINVAL;
 269         }
 270
 271         return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
 272 }
 273
 274 static const struct clk_ops vc5_mux_ops = {
 275         .set_parent     = vc5_mux_set_parent,
 276         .get_parent     = vc5_mux_get_parent,
 277 };
 278
 279 static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
 280                                          unsigned long parent_rate)
 281 {
 282         struct vc5_driver_data *vc5 =
 283                 container_of(hw, struct vc5_driver_data, clk_mul);
 284         unsigned int premul;
 285
 286         regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
 287         if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
 288                 parent_rate *= 2;
 289
 290         return parent_rate;
 291 }
 292
 293 static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
 294                                unsigned long *parent_rate)
 295 {
 296         if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
 297                 return rate;
 298         else
 299                 return -EINVAL;
 300 }
 301
 302 static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
 303                             unsigned long parent_rate)
 304 {
 305         struct vc5_driver_data *vc5 =
 306                 container_of(hw, struct vc5_driver_data, clk_mul);
 307         u32 mask;
 308
 309         if ((parent_rate * 2) == rate)
 310                 mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
 311         else
 312                 mask = 0;
 313
 314         regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
 315                            VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
 316                            mask);
 317
 318         return 0;
 319 }
 320
 321 static const struct clk_ops vc5_dbl_ops = {
 322         .recalc_rate    = vc5_dbl_recalc_rate,
 323         .round_rate     = vc5_dbl_round_rate,
 324         .set_rate       = vc5_dbl_set_rate,
 325 };
 326
 327 static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
 328                                          unsigned long parent_rate)
 329 {
 330         struct vc5_driver_data *vc5 =
 331                 container_of(hw, struct vc5_driver_data, clk_pfd);
 332         unsigned int prediv, div;
 333
 334         regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
 335
 336         /* The bypass_prediv is set, PLL fed from Ref_in directly. */
 337         if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
 338                 return parent_rate;
 339
 340         regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
 341
 342         /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
 343         if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
 344                 return parent_rate / 2;
 345         else
 346                 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
 347 }
 348
 349 static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
 350                                unsigned long *parent_rate)
 351 {
 352         unsigned long idiv;
 353
 354         /* PLL cannot operate with input clock above 50 MHz. */
 355         if (rate > 50000000)
 356                 return -EINVAL;
 357
 358         /* CLKIN within range of PLL input, feed directly to PLL. */
 359         if (*parent_rate <= 50000000)
 360                 return *parent_rate;
 361
 362         idiv = DIV_ROUND_UP(*parent_rate, rate);
 363         if (idiv > 127)
 364                 return -EINVAL;
 365
 366         return *parent_rate / idiv;
 367 }
 368
 369 static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
 370                             unsigned long parent_rate)
 371 {
 372         struct vc5_driver_data *vc5 =
 373                 container_of(hw, struct vc5_driver_data, clk_pfd);
 374         unsigned long idiv;
 375         u8 div;
 376
 377         /* CLKIN within range of PLL input, feed directly to PLL. */
 378         if (parent_rate <= 50000000) {
 379                 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
 380                                    VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV,
 381                                    VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
 382                 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
 383                 return 0;
 384         }
 385
 386         idiv = DIV_ROUND_UP(parent_rate, rate);
 387
 388         /* We have dedicated div-2 predivider. */
 389         if (idiv == 2)
 390                 div = VC5_REF_DIVIDER_SEL_PREDIV2;
 391         else
 392                 div = VC5_REF_DIVIDER_REF_DIV(idiv);
 393
 394         regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
 395         regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
 396                            VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0);
 397
 398         return 0;
 399 }
 400
 401 static const struct clk_ops vc5_pfd_ops = {
 402         .recalc_rate    = vc5_pfd_recalc_rate,
 403         .round_rate     = vc5_pfd_round_rate,
 404         .set_rate       = vc5_pfd_set_rate,
 405 };
 406
 407 /*
 408  * VersaClock5 PLL/VCO
 409  */
 410 static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
 411                                          unsigned long parent_rate)
 412 {
 413         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 414         struct vc5_driver_data *vc5 = hwdata->vc5;
 415         u32 div_int, div_frc;
 416         u8 fb[5];
 417
 418         regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
 419
 420         div_int = (fb[0] << 4) | (fb[1] >> 4);
 421         div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
 422
 423         /* The PLL divider has 12 integer bits and 24 fractional bits */
 424         return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
 425 }
 426
 427 static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 428                                unsigned long *parent_rate)
 429 {
 430         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 431         u32 div_int;
 432         u64 div_frc;
 433
 434         if (rate < VC5_PLL_VCO_MIN)
 435                 rate = VC5_PLL_VCO_MIN;
 436         if (rate > VC5_PLL_VCO_MAX)
 437                 rate = VC5_PLL_VCO_MAX;
 438
 439         /* Determine integer part, which is 12 bit wide */
 440         div_int = rate / *parent_rate;
 441         if (div_int > 0xfff)
 442                 rate = *parent_rate * 0xfff;
 443
 444         /* Determine best fractional part, which is 24 bit wide */
 445         div_frc = rate % *parent_rate;
 446         div_frc *= BIT(24) - 1;
 447         do_div(div_frc, *parent_rate);
 448
 449         hwdata->div_int = div_int;
 450         hwdata->div_frc = (u32)div_frc;
 451
 452         return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);
 453 }
 454
 455 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 456                             unsigned long parent_rate)
 457 {
 458         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 459         struct vc5_driver_data *vc5 = hwdata->vc5;
 460         u8 fb[5];
 461
 462         fb[0] = hwdata->div_int >> 4;
 463         fb[1] = hwdata->div_int << 4;
 464         fb[2] = hwdata->div_frc >> 16;
 465         fb[3] = hwdata->div_frc >> 8;
 466         fb[4] = hwdata->div_frc;
 467
 468         return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
 469 }
 470
 471 static const struct clk_ops vc5_pll_ops = {
 472         .recalc_rate    = vc5_pll_recalc_rate,
 473         .round_rate     = vc5_pll_round_rate,
 474         .set_rate       = vc5_pll_set_rate,
 475 };
 476
 477 static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
 478                                          unsigned long parent_rate)
 479 {
 480         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 481         struct vc5_driver_data *vc5 = hwdata->vc5;
 482         /* VCO frequency is divided by two before entering FOD */
 483         u32 f_in = parent_rate / 2;
 484         u32 div_int, div_frc;
 485         u8 od_int[2];
 486         u8 od_frc[4];
 487
 488         regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
 489                          od_int, 2);
 490         regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
 491                          od_frc, 4);
 492
 493         div_int = (od_int[0] << 4) | (od_int[1] >> 4);
 494         div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
 495                   (od_frc[2] << 6) | (od_frc[3] >> 2);
 496
 497         /* Avoid division by zero if the output is not configured. */
 498         if (div_int == 0 && div_frc == 0)
 499                 return 0;
 500
 501         /* The PLL divider has 12 integer bits and 30 fractional bits */
 502         return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
 503 }
 504
 505 static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
 506                                unsigned long *parent_rate)
 507 {
 508         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 509         /* VCO frequency is divided by two before entering FOD */
 510         u32 f_in = *parent_rate / 2;
 511         u32 div_int;
 512         u64 div_frc;
 513
 514         /* Determine integer part, which is 12 bit wide */
 515         div_int = f_in / rate;
 516         /*
 517          * WARNING: The clock chip does not output signal if the integer part
 518          *          of the divider is 0xfff and fractional part is non-zero.
 519          *          Clamp the divider at 0xffe to keep the code simple.
 520          */
 521         if (div_int > 0xffe) {
 522                 div_int = 0xffe;
 523                 rate = f_in / div_int;
 524         }
 525
 526         /* Determine best fractional part, which is 30 bit wide */
 527         div_frc = f_in % rate;
 528         div_frc <<= 24;
 529         do_div(div_frc, rate);
 530
 531         hwdata->div_int = div_int;
 532         hwdata->div_frc = (u32)div_frc;
 533
 534         return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
 535 }
 536
 537 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
 538                             unsigned long parent_rate)
 539 {
 540         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 541         struct vc5_driver_data *vc5 = hwdata->vc5;
 542         u8 data[14] = {
 543                 hwdata->div_frc >> 22, hwdata->div_frc >> 14,
 544                 hwdata->div_frc >> 6, hwdata->div_frc << 2,
 545                 0, 0, 0, 0, 0,
 546                 0, 0,
 547                 hwdata->div_int >> 4, hwdata->div_int << 4,
 548                 0
 549         };
 550
 551         regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
 552                           data, 14);
 553
 554         /*
 555          * Toggle magic bit in undocumented register for unknown reason.
 556          * This is what the IDT timing commander tool does and the chip
 557          * datasheet somewhat implies this is needed, but the register
 558          * and the bit is not documented.
 559          */
 560         regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
 561                            VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0);
 562         regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
 563                            VC5_GLOBAL_REGISTER_GLOBAL_RESET,
 564                            VC5_GLOBAL_REGISTER_GLOBAL_RESET);
 565         return 0;
 566 }
 567
 568 static const struct clk_ops vc5_fod_ops = {
 569         .recalc_rate    = vc5_fod_recalc_rate,
 570         .round_rate     = vc5_fod_round_rate,
 571         .set_rate       = vc5_fod_set_rate,
 572 };
 573
 574 static int vc5_clk_out_prepare(struct clk_hw *hw)
 575 {
 576         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 577         struct vc5_driver_data *vc5 = hwdata->vc5;
 578         const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
 579                         VC5_OUT_DIV_CONTROL_SEL_EXT |
 580                         VC5_OUT_DIV_CONTROL_EN_FOD;
 581         unsigned int src;
 582         int ret;
 583
 584         /*
 585          * If the input mux is disabled, enable it first and
 586          * select source from matching FOD.
 587          */
 588         regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
 589         if ((src & mask) == 0) {
 590                 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
 591                 ret = regmap_update_bits(vc5->regmap,
 592                                          VC5_OUT_DIV_CONTROL(hwdata->num),
 593                                          mask | VC5_OUT_DIV_CONTROL_RESET, src);
 594                 if (ret)
 595                         return ret;
 596         }
 597
 598         /* Enable the clock buffer */
 599         regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
 600                            VC5_CLK_OUTPUT_CFG1_EN_CLKBUF,
 601                            VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
 602         return 0;
 603 }
 604
 605 static void vc5_clk_out_unprepare(struct clk_hw *hw)
 606 {
 607         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 608         struct vc5_driver_data *vc5 = hwdata->vc5;
 609
 610         /* Disable the clock buffer */
 611         regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
 612                            VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
 613 }
 614
 615 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
 616 {
 617         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 618         struct vc5_driver_data *vc5 = hwdata->vc5;
 619         const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
 620                         VC5_OUT_DIV_CONTROL_SEL_EXT |
 621                         VC5_OUT_DIV_CONTROL_EN_FOD;
 622         const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
 623                               VC5_OUT_DIV_CONTROL_EN_FOD;
 624         const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
 625                           VC5_OUT_DIV_CONTROL_SEL_EXT;
 626         unsigned int src;
 627
 628         regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
 629         src &= mask;
 630
 631         if (src == 0)   /* Input mux set to DISABLED */
 632                 return 0;
 633
 634         if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
 635                 return 0;
 636
 637         if (src == extclk)
 638                 return 1;
 639
 640         dev_warn(&vc5->client->dev,
 641                  "Invalid clock output configuration (%02x)\n", src);
 642         return 0;
 643 }
 644
 645 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
 646 {
 647         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 648         struct vc5_driver_data *vc5 = hwdata->vc5;
 649         const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
 650                         VC5_OUT_DIV_CONTROL_SELB_NORM |
 651                         VC5_OUT_DIV_CONTROL_SEL_EXT |
 652                         VC5_OUT_DIV_CONTROL_EN_FOD;
 653         const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
 654                           VC5_OUT_DIV_CONTROL_SEL_EXT;
 655         u8 src = VC5_OUT_DIV_CONTROL_RESET;
 656
 657         if (index == 0)
 658                 src |= VC5_OUT_DIV_CONTROL_EN_FOD;
 659         else
 660                 src |= extclk;
 661
 662         return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
 663                                   mask, src);
 664 }
 665
 666 static const struct clk_ops vc5_clk_out_ops = {
 667         .prepare        = vc5_clk_out_prepare,
 668         .unprepare      = vc5_clk_out_unprepare,
 669         .set_parent     = vc5_clk_out_set_parent,
 670         .get_parent     = vc5_clk_out_get_parent,
 671 };
 672
 673 static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
 674                                      void *data)
 675 {
 676         struct vc5_driver_data *vc5 = data;
 677         unsigned int idx = clkspec->args[0];
 678
 679         if (idx >= vc5->chip_info->clk_out_cnt)
 680                 return ERR_PTR(-EINVAL);
 681
 682         return &vc5->clk_out[idx].hw;
 683 }
 684
 685 static int vc5_map_index_to_output(const enum vc5_model model,
 686                                    const unsigned int n)
 687 {
 688         switch (model) {
 689         case IDT_VC5_5P49V5933:
 690                 return (n == 0) ? 0 : 3;
 691         case IDT_VC5_5P49V5923:
 692         case IDT_VC5_5P49V5925:
 693         case IDT_VC5_5P49V5935:
 694         case IDT_VC6_5P49V6901:
 695         default:
 696                 return n;
 697         }
 698 }
 699
 700 static const struct of_device_id clk_vc5_of_match[];
 701
 702 static int vc5_probe(struct i2c_client *client,
 703                      const struct i2c_device_id *id)
 704 {
 705         struct vc5_driver_data *vc5;
 706         struct clk_init_data init;
 707         const char *parent_names[2];
 708         unsigned int n, idx = 0;
 709         int ret;
 710
 711         vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
 712         if (vc5 == NULL)
 713                 return -ENOMEM;
 714
 715         i2c_set_clientdata(client, vc5);
 716         vc5->client = client;
 717         vc5->chip_info = of_device_get_match_data(&client->dev);
 718
 719         vc5->pin_xin = devm_clk_get(&client->dev, "xin");
 720         if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
 721                 return -EPROBE_DEFER;
 722
 723         vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
 724         if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
 725                 return -EPROBE_DEFER;
 726
 727         vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
 728         if (IS_ERR(vc5->regmap)) {
 729                 dev_err(&client->dev, "failed to allocate register map\n");
 730                 return PTR_ERR(vc5->regmap);
 731         }
 732
 733         /* Register clock input mux */
 734         memset(&init, 0, sizeof(init));
 735
 736         if (!IS_ERR(vc5->pin_xin)) {
 737                 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
 738                 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
 739         } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
 740                 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
 741                                                        "internal-xtal", NULL,
 742                                                        0, 25000000);
 743                 if (IS_ERR(vc5->pin_xin))
 744                         return PTR_ERR(vc5->pin_xin);
 745                 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
 746                 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
 747         }
 748
 749         if (!IS_ERR(vc5->pin_clkin)) {
 750                 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
 751                 parent_names[init.num_parents++] =
 752                         __clk_get_name(vc5->pin_clkin);
 753         }
 754
 755         if (!init.num_parents) {
 756                 dev_err(&client->dev, "no input clock specified!\n");
 757                 return -EINVAL;
 758         }
 759
 760         init.name = vc5_mux_names[0];
 761         init.ops = &vc5_mux_ops;
 762         init.flags = 0;
 763         init.parent_names = parent_names;
 764         vc5->clk_mux.init = &init;
 765         ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
 766         if (ret) {
 767                 dev_err(&client->dev, "unable to register %s\n", init.name);
 768                 goto err_clk;
 769         }
 770
 771         if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
 772                 /* Register frequency doubler */
 773                 memset(&init, 0, sizeof(init));
 774                 init.name = vc5_dbl_names[0];
 775                 init.ops = &vc5_dbl_ops;
 776                 init.flags = CLK_SET_RATE_PARENT;
 777                 init.parent_names = vc5_mux_names;
 778                 init.num_parents = 1;
 779                 vc5->clk_mul.init = &init;
 780                 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
 781                 if (ret) {
 782                         dev_err(&client->dev, "unable to register %s\n",
 783                                 init.name);
 784                         goto err_clk;
 785                 }
 786         }
 787
 788         /* Register PFD */
 789         memset(&init, 0, sizeof(init));
 790         init.name = vc5_pfd_names[0];
 791         init.ops = &vc5_pfd_ops;
 792         init.flags = CLK_SET_RATE_PARENT;
 793         if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
 794                 init.parent_names = vc5_dbl_names;
 795         else
 796                 init.parent_names = vc5_mux_names;
 797         init.num_parents = 1;
 798         vc5->clk_pfd.init = &init;
 799         ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
 800         if (ret) {
 801                 dev_err(&client->dev, "unable to register %s\n", init.name);
 802                 goto err_clk;
 803         }
 804
 805         /* Register PLL */
 806         memset(&init, 0, sizeof(init));
 807         init.name = vc5_pll_names[0];
 808         init.ops = &vc5_pll_ops;
 809         init.flags = CLK_SET_RATE_PARENT;
 810         init.parent_names = vc5_pfd_names;
 811         init.num_parents = 1;
 812         vc5->clk_pll.num = 0;
 813         vc5->clk_pll.vc5 = vc5;
 814         vc5->clk_pll.hw.init = &init;
 815         ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
 816         if (ret) {
 817                 dev_err(&client->dev, "unable to register %s\n", init.name);
 818                 goto err_clk;
 819         }
 820
 821         /* Register FODs */
 822         for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
 823                 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
 824                 memset(&init, 0, sizeof(init));
 825                 init.name = vc5_fod_names[idx];
 826                 init.ops = &vc5_fod_ops;
 827                 init.flags = CLK_SET_RATE_PARENT;
 828                 init.parent_names = vc5_pll_names;
 829                 init.num_parents = 1;
 830                 vc5->clk_fod[n].num = idx;
 831                 vc5->clk_fod[n].vc5 = vc5;
 832                 vc5->clk_fod[n].hw.init = &init;
 833                 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
 834                 if (ret) {
 835                         dev_err(&client->dev, "unable to register %s\n",
 836                                 init.name);
 837                         goto err_clk;
 838                 }
 839         }
 840
 841         /* Register MUX-connected OUT0_I2C_SELB output */
 842         memset(&init, 0, sizeof(init));
 843         init.name = vc5_clk_out_names[0];
 844         init.ops = &vc5_clk_out_ops;
 845         init.flags = CLK_SET_RATE_PARENT;
 846         init.parent_names = vc5_mux_names;
 847         init.num_parents = 1;
 848         vc5->clk_out[0].num = idx;
 849         vc5->clk_out[0].vc5 = vc5;
 850         vc5->clk_out[0].hw.init = &init;
 851         ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
 852         if (ret) {
 853                 dev_err(&client->dev, "unable to register %s\n",
 854                         init.name);
 855                 goto err_clk;
 856         }
 857
 858         /* Register FOD-connected OUTx outputs */
 859         for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
 860                 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
 861                 parent_names[0] = vc5_fod_names[idx];
 862                 if (n == 1)
 863                         parent_names[1] = vc5_mux_names[0];
 864                 else
 865                         parent_names[1] = vc5_clk_out_names[n - 1];
 866
 867                 memset(&init, 0, sizeof(init));
 868                 init.name = vc5_clk_out_names[idx + 1];
 869                 init.ops = &vc5_clk_out_ops;
 870                 init.flags = CLK_SET_RATE_PARENT;
 871                 init.parent_names = parent_names;
 872                 init.num_parents = 2;
 873                 vc5->clk_out[n].num = idx;
 874                 vc5->clk_out[n].vc5 = vc5;
 875                 vc5->clk_out[n].hw.init = &init;
 876                 ret = devm_clk_hw_register(&client->dev,
 877                                            &vc5->clk_out[n].hw);
 878                 if (ret) {
 879                         dev_err(&client->dev, "unable to register %s\n",
 880                                 init.name);
 881                         goto err_clk;
 882                 }
 883         }
 884
 885         ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
 886         if (ret) {
 887                 dev_err(&client->dev, "unable to add clk provider\n");
 888                 goto err_clk;
 889         }
 890
 891         return 0;
 892
 893 err_clk:
 894         if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
 895                 clk_unregister_fixed_rate(vc5->pin_xin);
 896         return ret;
 897 }
 898
 899 static int vc5_remove(struct i2c_client *client)
 900 {
 901         struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
 902
 903         of_clk_del_provider(client->dev.of_node);
 904
 905         if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
 906                 clk_unregister_fixed_rate(vc5->pin_xin);
 907
 908         return 0;
 909 }
 910
 911 static const struct vc5_chip_info idt_5p49v5923_info = {
 912         .model = IDT_VC5_5P49V5923,
 913         .clk_fod_cnt = 2,
 914         .clk_out_cnt = 3,
 915         .flags = 0,
 916 };
 917
 918 static const struct vc5_chip_info idt_5p49v5925_info = {
 919         .model = IDT_VC5_5P49V5925,
 920         .clk_fod_cnt = 4,
 921         .clk_out_cnt = 5,
 922         .flags = 0,
 923 };
 924
 925 static const struct vc5_chip_info idt_5p49v5933_info = {
 926         .model = IDT_VC5_5P49V5933,
 927         .clk_fod_cnt = 2,
 928         .clk_out_cnt = 3,
 929         .flags = VC5_HAS_INTERNAL_XTAL,
 930 };
 931
 932 static const struct vc5_chip_info idt_5p49v5935_info = {
 933         .model = IDT_VC5_5P49V5935,
 934         .clk_fod_cnt = 4,
 935         .clk_out_cnt = 5,
 936         .flags = VC5_HAS_INTERNAL_XTAL,
 937 };
 938
 939 static const struct vc5_chip_info idt_5p49v6901_info = {
 940         .model = IDT_VC6_5P49V6901,
 941         .clk_fod_cnt = 4,
 942         .clk_out_cnt = 5,
 943         .flags = VC5_HAS_PFD_FREQ_DBL,
 944 };
 945
 946 static const struct i2c_device_id vc5_id[] = {
 947         { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
 948         { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
 949         { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
 950         { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
 951         { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
 952         { }
 953 };
 954 MODULE_DEVICE_TABLE(i2c, vc5_id);
 955
 956 static const struct of_device_id clk_vc5_of_match[] = {
 957         { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
 958         { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
 959         { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
 960         { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
 961         { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
 962         { },
 963 };
 964 MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
 965
 966 static struct i2c_driver vc5_driver = {
 967         .driver = {
 968                 .name = "vc5",
 969                 .of_match_table = clk_vc5_of_match,
 970         },
 971         .probe          = vc5_probe,
 972         .remove         = vc5_remove,
 973         .id_table       = vc5_id,
 974 };
 975 module_i2c_driver(vc5_driver);
 976
 977 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
 978 MODULE_DESCRIPTION("IDT VersaClock 5 driver");
 979 MODULE_LICENSE("GPL");