drivers/clk/hisilicon/clk-hi3660.c

   1 /*
   2  * Copyright (c) 2016-2017 Linaro Ltd.
   3  * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <dt-bindings/clock/hi3660-clock.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include "clk.h"
  16
  17 static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
  18         { HI3660_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
  19         { HI3660_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
  20         { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, },
  21         { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, },
  22         { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
  23         { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000UL, },
  24         { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, },
  25         { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
  26         { HI3660_PCLK, "pclk", NULL, 0, 20000000, },
  27         { HI3660_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
  28         { HI3660_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
  29         { HI3660_OSC32K, "osc32k", NULL, 0, 32764, },
  30         { HI3660_OSC19M, "osc19m", NULL, 0, 19200000, },
  31         { HI3660_CLK_480M, "clk_480m", NULL, 0, 480000000, },
  32         { HI3660_CLK_INV, "clk_inv", NULL, 0, 10000000, },
  33 };
  34
  35 /* crgctrl */
  36 static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
  37         { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },
  38         { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
  39         { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
  40         { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
  41         { HI3660_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_iomcu", 1, 4, 0, },
  42         { HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, },
  43         { HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, },
  44         { HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, },
  45         { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 6, 0, },
  46         { HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, },
  47         { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, },
  48         { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },
  49         { HI3660_CLK_ABB_USB, "clk_abb_usb", "clk_gate_usb_tcxo_en", 1, 1, 0 },
  50         { HI3660_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold", 1, 1, 0, },
  51         { HI3660_CLK_FAC_ISP_SNCLK, "clk_isp_snclk_fac", "clk_isp_snclk_angt",
  52           1, 10, 0, },
  53 };
  54
  55 static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = {
  56         { HI3660_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys",
  57           CLK_SET_RATE_PARENT, 0x0, 0, 0, },
  58         { HI3660_HCLK_GATE_SDIO0, "hclk_gate_sdio0", "clk_div_sysbus",
  59           CLK_SET_RATE_PARENT, 0x0, 21, 0, },
  60         { HI3660_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
  61           CLK_SET_RATE_PARENT, 0x0, 30, 0, },
  62         { HI3660_CLK_GATE_AOMM, "clk_gate_aomm", "clk_div_aomm",
  63           CLK_SET_RATE_PARENT, 0x0, 31, 0, },
  64         { HI3660_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus",
  65           CLK_SET_RATE_PARENT, 0x10, 0, 0, },
  66         { HI3660_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus",
  67           CLK_SET_RATE_PARENT, 0x10, 1, 0, },
  68         { HI3660_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus",
  69           CLK_SET_RATE_PARENT, 0x10, 2, 0, },
  70         { HI3660_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus",
  71           CLK_SET_RATE_PARENT, 0x10, 3, 0, },
  72         { HI3660_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus",
  73           CLK_SET_RATE_PARENT, 0x10, 4, 0, },
  74         { HI3660_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus",
  75           CLK_SET_RATE_PARENT, 0x10, 5, 0, },
  76         { HI3660_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus",
  77           CLK_SET_RATE_PARENT, 0x10, 6, 0, },
  78         { HI3660_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus",
  79           CLK_SET_RATE_PARENT, 0x10, 7, 0, },
  80         { HI3660_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus",
  81           CLK_SET_RATE_PARENT, 0x10, 8, 0, },
  82         { HI3660_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus",
  83           CLK_SET_RATE_PARENT, 0x10, 9, 0, },
  84         { HI3660_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus",
  85           CLK_SET_RATE_PARENT, 0x10, 10, 0, },
  86         { HI3660_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus",
  87           CLK_SET_RATE_PARENT, 0x10, 11, 0, },
  88         { HI3660_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus",
  89           CLK_SET_RATE_PARENT, 0x10, 12, 0, },
  90         { HI3660_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus",
  91           CLK_SET_RATE_PARENT, 0x10, 13, 0, },
  92         { HI3660_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus",
  93           CLK_SET_RATE_PARENT, 0x10, 14, 0, },
  94         { HI3660_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus",
  95           CLK_SET_RATE_PARENT, 0x10, 15, 0, },
  96         { HI3660_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus",
  97           CLK_SET_RATE_PARENT, 0x10, 16, 0, },
  98         { HI3660_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus",
  99           CLK_SET_RATE_PARENT, 0x10, 17, 0, },
 100         { HI3660_PCLK_GPIO18, "pclk_gpio18", "clk_div_ioperi",
 101           CLK_SET_RATE_PARENT, 0x10, 18, 0, },
 102         { HI3660_PCLK_GPIO19, "pclk_gpio19", "clk_div_ioperi",
 103           CLK_SET_RATE_PARENT, 0x10, 19, 0, },
 104         { HI3660_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus",
 105           CLK_SET_RATE_PARENT, 0x10, 20, 0, },
 106         { HI3660_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus",
 107           CLK_SET_RATE_PARENT, 0x10, 21, 0, },
 108         { HI3660_CLK_GATE_SPI3, "clk_gate_spi3", "clk_div_ioperi",
 109           CLK_SET_RATE_PARENT, 0x10, 30, 0, },
 110         { HI3660_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c",
 111           CLK_SET_RATE_PARENT, 0x10, 31, 0, },
 112         { HI3660_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c",
 113           CLK_SET_RATE_PARENT, 0x20, 7, 0, },
 114         { HI3660_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi",
 115           CLK_SET_RATE_PARENT, 0x20, 9, 0, },
 116         { HI3660_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth",
 117           CLK_SET_RATE_PARENT, 0x20, 11, 0, },
 118         { HI3660_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uart1",
 119           CLK_SET_RATE_PARENT, 0x20, 12, 0, },
 120         { HI3660_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth",
 121           CLK_SET_RATE_PARENT, 0x20, 14, 0, },
 122         { HI3660_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uart1",
 123           CLK_SET_RATE_PARENT, 0x20, 15, 0, },
 124         { HI3660_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c",
 125           CLK_SET_RATE_PARENT, 0x20, 27, 0, },
 126         { HI3660_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus",
 127           CLK_SET_RATE_PARENT, 0x30, 1, 0, },
 128         { HI3660_CLK_GATE_VENC, "clk_gate_venc", "clk_div_venc",
 129           CLK_SET_RATE_PARENT, 0x30, 10, 0, },
 130         { HI3660_CLK_GATE_VDEC, "clk_gate_vdec", "clk_div_vdec",
 131           CLK_SET_RATE_PARENT, 0x30, 11, 0, },
 132         { HI3660_PCLK_GATE_DSS, "pclk_gate_dss", "clk_div_cfgbus",
 133           CLK_SET_RATE_PARENT, 0x30, 12, 0, },
 134         { HI3660_ACLK_GATE_DSS, "aclk_gate_dss", "clk_gate_vivobus",
 135           CLK_SET_RATE_PARENT, 0x30, 13, 0, },
 136         { HI3660_CLK_GATE_LDI1, "clk_gate_ldi1", "clk_div_ldi1",
 137           CLK_SET_RATE_PARENT, 0x30, 14, 0, },
 138         { HI3660_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0",
 139           CLK_SET_RATE_PARENT, 0x30, 15, 0, },
 140         { HI3660_CLK_GATE_VIVOBUS, "clk_gate_vivobus", "clk_div_vivobus",
 141           CLK_SET_RATE_PARENT, 0x30, 16, 0, },
 142         { HI3660_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0",
 143           CLK_SET_RATE_PARENT, 0x30, 17, 0, },
 144         { HI3660_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys",
 145           CLK_SET_RATE_PARENT, 0x30, 28, 0, },
 146         { HI3660_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys",
 147           CLK_SET_RATE_PARENT, 0x30, 29, 0, },
 148         { HI3660_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys",
 149           CLK_SET_RATE_PARENT, 0x30, 30, 0, },
 150         { HI3660_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys",
 151           CLK_SET_RATE_PARENT, 0x30, 31, 0, },
 152         { HI3660_ACLK_GATE_USB3OTG, "aclk_gate_usb3otg", "clk_div_mmc0bus",
 153           CLK_SET_RATE_PARENT, 0x40, 1, 0, },
 154         { HI3660_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi",
 155           CLK_SET_RATE_PARENT, 0x40, 4, 0, },
 156         { HI3660_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
 157           CLK_SET_RATE_PARENT, 0x40, 17, 0, },
 158         { HI3660_CLK_GATE_SDIO0, "clk_gate_sdio0", "clk_mux_sdio_sys",
 159           CLK_SET_RATE_PARENT, 0x40, 19, 0, },
 160         { HI3660_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0",
 161           "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 16, 0, },
 162         { HI3660_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1",
 163           "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
 164         { HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2",
 165           "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, },
 166         /*
 167          * clk_gate_ufs_subsys is a system bus clock, mark it as critical
 168          * clock and keep it on for system suspend and resume.
 169          */
 170         { HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus",
 171           CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 21, 0, },
 172         { HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
 173           CLK_SET_RATE_PARENT, 0x50, 28, 0, },
 174         { HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
 175           CLK_SET_RATE_PARENT, 0x50, 29, 0, },
 176         { HI3660_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_div_mmc1bus",
 177           CLK_SET_RATE_PARENT, 0x420, 5, 0, },
 178         { HI3660_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus",
 179           CLK_SET_RATE_PARENT, 0x420, 7, 0, },
 180         { HI3660_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys",
 181           CLK_SET_RATE_PARENT, 0x420, 8, 0, },
 182         { HI3660_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "clk_div_mmc1bus",
 183           CLK_SET_RATE_PARENT, 0x420, 9, 0, },
 184 };
 185
 186 static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = {
 187         { HI3660_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
 188           CLK_SET_RATE_PARENT, 0xf0, 6, CLK_GATE_HIWORD_MASK, },
 189         { HI3660_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
 190           CLK_SET_RATE_PARENT, 0xf0, 7, CLK_GATE_HIWORD_MASK, },
 191         { HI3660_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
 192           CLK_SET_RATE_PARENT, 0xf0, 8, CLK_GATE_HIWORD_MASK, },
 193         { HI3660_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec",
 194           CLK_SET_RATE_PARENT, 0xf0, 15, CLK_GATE_HIWORD_MASK, },
 195         { HI3660_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc",
 196           CLK_SET_RATE_PARENT, 0xf4, 0, CLK_GATE_HIWORD_MASK, },
 197         { HI3660_CLK_GATE_UFSPHY_GT, "clk_gate_ufsphy_gt", "clk_div_ufsperi",
 198           CLK_SET_RATE_PARENT, 0xf4, 1, CLK_GATE_HIWORD_MASK, },
 199         { HI3660_CLK_ANDGT_MMC, "clk_andgt_mmc", "clk_mux_mmc_pll",
 200           CLK_SET_RATE_PARENT, 0xf4, 2, CLK_GATE_HIWORD_MASK, },
 201         { HI3660_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
 202           CLK_SET_RATE_PARENT, 0xf4, 3, CLK_GATE_HIWORD_MASK, },
 203         { HI3660_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
 204           CLK_SET_RATE_PARENT, 0xf4, 7, CLK_GATE_HIWORD_MASK, },
 205         { HI3660_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
 206           CLK_SET_RATE_PARENT, 0xf4, 8, CLK_GATE_HIWORD_MASK, },
 207         { HI3660_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
 208           CLK_SET_RATE_PARENT, 0xf4, 9, CLK_GATE_HIWORD_MASK, },
 209         { HI3660_CLK_ANDGT_UART1, "clk_andgt_uart1", "clk_div_320m",
 210           CLK_SET_RATE_PARENT, 0xf4, 10, CLK_GATE_HIWORD_MASK, },
 211         { HI3660_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
 212           CLK_SET_RATE_PARENT, 0xf4, 11, CLK_GATE_HIWORD_MASK, },
 213         { HI3660_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
 214           CLK_SET_RATE_PARENT, 0xf4, 13, CLK_GATE_HIWORD_MASK, },
 215         { HI3660_CLK_VIVOBUS_ANDGT, "clk_vivobus_andgt", "clk_mux_vivobus",
 216           CLK_SET_RATE_PARENT, 0xf8, 1, CLK_GATE_HIWORD_MASK, },
 217         { HI3660_CLK_AOMM_ANDGT, "clk_aomm_andgt", "clk_ppll2",
 218           CLK_SET_RATE_PARENT, 0xf8, 3, CLK_GATE_HIWORD_MASK, },
 219         { HI3660_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
 220           CLK_SET_RATE_PARENT, 0xf8, 10, 0, },
 221         { HI3660_CLK_ANGT_ISP_SNCLK, "clk_isp_snclk_angt", "clk_div_a53hpm",
 222           CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
 223         { HI3660_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
 224           CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
 225         { HI3660_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
 226           CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
 227         { HI3660_CLK_GATE_UFSPHY_CFG, "clk_gate_ufsphy_cfg",
 228           "clk_div_ufsphy_cfg", CLK_SET_RATE_PARENT, 0x420, 12, 0, },
 229         { HI3660_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref",
 230           "clk_gate_ufs_tcxo_en", CLK_SET_RATE_PARENT, 0x420, 14, 0, },
 231 };
 232
 233 static const char *const
 234 clk_mux_sysbus_p[] = {"clk_ppll1", "clk_ppll0"};
 235 static const char *const
 236 clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",};
 237 static const char *const
 238 clk_mux_sd_sys_p[] = {"clk_factor_mmc", "clk_div_sd",};
 239 static const char *const
 240 clk_mux_pll_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll2",};
 241 static const char *const
 242 clk_mux_pll0123_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll3",};
 243 static const char *const
 244 clk_mux_edc0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll1", "clk_inv",
 245                     "clk_ppll2", "clk_inv", "clk_inv", "clk_inv",
 246                     "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
 247                     "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
 248 static const char *const
 249 clk_mux_ldi0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll2", "clk_inv",
 250                     "clk_ppll1", "clk_inv", "clk_inv", "clk_inv",
 251                     "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
 252                     "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
 253 static const char *const
 254 clk_mux_uart0_p[] = {"clkin_sys", "clk_div_uart0",};
 255 static const char *const
 256 clk_mux_uart1_p[] = {"clkin_sys", "clk_div_uart1",};
 257 static const char *const
 258 clk_mux_uarth_p[] = {"clkin_sys", "clk_div_uarth",};
 259 static const char *const
 260 clk_mux_pll02p[] = {"clk_ppll0", "clk_ppll2",};
 261 static const char *const
 262 clk_mux_ioperi_p[] = {"clk_div_320m", "clk_div_a53hpm",};
 263 static const char *const
 264 clk_mux_spi_p[] = {"clkin_sys", "clk_div_spi",};
 265 static const char *const
 266 clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",};
 267 static const char *const
 268 clk_mux_venc_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll3", "clk_ppll3",};
 269 static const char *const
 270 clk_mux_isp_snclk_p[] = {"clkin_sys", "clk_isp_snclk_div"};
 271
 272 static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = {
 273         { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
 274           ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
 275           CLK_MUX_HIWORD_MASK, },
 276         { HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
 277           ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
 278           CLK_MUX_HIWORD_MASK, },
 279         { HI3660_CLK_MUX_UART1, "clk_mux_uart1", clk_mux_uart1_p,
 280           ARRAY_SIZE(clk_mux_uart1_p), CLK_SET_RATE_PARENT, 0xac, 3, 1,
 281           CLK_MUX_HIWORD_MASK, },
 282         { HI3660_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p,
 283           ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT, 0xac, 4, 1,
 284           CLK_MUX_HIWORD_MASK, },
 285         { HI3660_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p,
 286           ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT, 0xac, 8, 1,
 287           CLK_MUX_HIWORD_MASK, },
 288         { HI3660_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p,
 289           ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT, 0xac, 13, 1,
 290           CLK_MUX_HIWORD_MASK, },
 291         { HI3660_CLK_MUX_MMC_PLL, "clk_mux_mmc_pll", clk_mux_pll02p,
 292           ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xb4, 0, 1,
 293           CLK_MUX_HIWORD_MASK, },
 294         { HI3660_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi0_p,
 295           ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 8, 4,
 296           CLK_MUX_HIWORD_MASK, },
 297         { HI3660_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
 298           ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 12, 4,
 299           CLK_MUX_HIWORD_MASK, },
 300         { HI3660_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_pll_p,
 301           ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xb8, 4, 2,
 302           CLK_MUX_HIWORD_MASK, },
 303         { HI3660_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p,
 304           ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT, 0xb8, 6, 1,
 305           CLK_MUX_HIWORD_MASK, },
 306         { HI3660_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
 307           ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, 0xbc, 6, 4,
 308           CLK_MUX_HIWORD_MASK, },
 309         { HI3660_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p,
 310           ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xc0, 6, 1,
 311           CLK_MUX_HIWORD_MASK, },
 312         { HI3660_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_pll_p,
 313           ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2,
 314           CLK_MUX_HIWORD_MASK, },
 315         { HI3660_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p,
 316           ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, 0xc8, 11, 2,
 317           CLK_MUX_HIWORD_MASK, },
 318         { HI3660_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_pll0123_p,
 319           ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xcc, 5, 2,
 320           CLK_MUX_HIWORD_MASK, },
 321         { HI3660_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_pll0123_p,
 322           ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2,
 323           CLK_MUX_HIWORD_MASK, },
 324         { HI3660_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_pll02p,
 325           ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xd4, 9, 1,
 326           CLK_MUX_HIWORD_MASK, },
 327         { HI3660_CLK_MUX_320M, "clk_mux_320m", clk_mux_pll02p,
 328           ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0x100, 0, 1,
 329           CLK_MUX_HIWORD_MASK, },
 330         { HI3660_CLK_MUX_ISP_SNCLK, "clk_isp_snclk_mux", clk_mux_isp_snclk_p,
 331           ARRAY_SIZE(clk_mux_isp_snclk_p), CLK_SET_RATE_PARENT, 0x108, 3, 1,
 332           CLK_MUX_HIWORD_MASK, },
 333         { HI3660_CLK_MUX_IOPERI, "clk_mux_ioperi", clk_mux_ioperi_p,
 334           ARRAY_SIZE(clk_mux_ioperi_p), CLK_SET_RATE_PARENT, 0x108, 10, 1,
 335           CLK_MUX_HIWORD_MASK, },
 336 };
 337
 338 static const struct hisi_divider_clock hi3660_crgctrl_divider_clks[] = {
 339         { HI3660_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
 340           CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 341         { HI3660_CLK_DIV_UART1, "clk_div_uart1", "clk_andgt_uart1",
 342           CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 343         { HI3660_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
 344           CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 345         { HI3660_CLK_DIV_MMC, "clk_div_mmc", "clk_andgt_mmc",
 346           CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 347         { HI3660_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
 348           CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 349         { HI3660_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
 350           CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
 351         { HI3660_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
 352           CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
 353         { HI3660_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
 354           CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 355         { HI3660_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
 356           CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
 357         { HI3660_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
 358           CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 359         { HI3660_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc",
 360           CLK_SET_RATE_PARENT, 0xc8, 6, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
 361         { HI3660_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec",
 362           CLK_SET_RATE_PARENT, 0xcc, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
 363         { HI3660_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_vivobus_andgt",
 364           CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
 365         { HI3660_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
 366           CLK_SET_RATE_PARENT, 0xe8, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 367         { HI3660_CLK_DIV_UFSPHY, "clk_div_ufsphy_cfg", "clk_gate_ufsphy_gt",
 368           CLK_SET_RATE_PARENT, 0xe8, 9, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
 369         { HI3660_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
 370           CLK_SET_RATE_PARENT, 0xec, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
 371         { HI3660_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
 372           CLK_SET_RATE_PARENT, 0xec, 2, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
 373         { HI3660_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
 374           CLK_SET_RATE_PARENT, 0xec, 3, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
 375         { HI3660_CLK_DIV_UFSPERI, "clk_div_ufsperi", "clk_gate_ufs_subsys",
 376           CLK_SET_RATE_PARENT, 0xec, 14, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
 377         { HI3660_CLK_DIV_AOMM, "clk_div_aomm", "clk_aomm_andgt",
 378           CLK_SET_RATE_PARENT, 0x100, 7, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 379         { HI3660_CLK_DIV_ISP_SNCLK, "clk_isp_snclk_div", "clk_isp_snclk_fac",
 380           CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
 381         { HI3660_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_mux_ioperi",
 382           CLK_SET_RATE_PARENT, 0x108, 11, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 383 };
 384
 385 /* clk_pmuctrl */
 386 /* pmu register need shift 2 bits */
 387 static const struct hisi_gate_clock hi3660_pmu_gate_clks[] = {
 388         { HI3660_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys",
 389           CLK_SET_RATE_PARENT, (0x10a << 2), 3, 0, },
 390 };
 391
 392 /* clk_pctrl */
 393 static const struct hisi_gate_clock hi3660_pctrl_gate_clks[] = {
 394         { HI3660_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en",
 395           "clk_gate_abb_192", CLK_SET_RATE_PARENT, 0x10, 0,
 396           CLK_GATE_HIWORD_MASK, },
 397         { HI3660_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192",
 398           CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
 399 };
 400
 401 /* clk_sctrl */
 402 static const struct hisi_gate_clock hi3660_sctrl_gate_sep_clks[] = {
 403         { HI3660_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
 404           CLK_SET_RATE_PARENT, 0x160, 11, 0, },
 405         { HI3660_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
 406           CLK_SET_RATE_PARENT, 0x160, 12, 0, },
 407         { HI3660_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus",
 408           CLK_SET_RATE_PARENT, 0x160, 13, 0, },
 409         { HI3660_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus",
 410           CLK_SET_RATE_PARENT, 0x160, 14, 0, },
 411         { HI3660_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus",
 412           CLK_SET_RATE_PARENT, 0x160, 21, 0, },
 413         { HI3660_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus",
 414           CLK_SET_RATE_PARENT, 0x160, 22, 0, },
 415         { HI3660_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus",
 416           CLK_SET_RATE_PARENT, 0x160, 25, 0, },
 417         { HI3660_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf",
 418           CLK_SET_RATE_PARENT, 0x170, 23, 0, },
 419         { HI3660_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "aclk_mux_mmbuf",
 420           CLK_SET_RATE_PARENT, 0x170, 24, 0, },
 421 };
 422
 423 static const struct hisi_gate_clock hi3660_sctrl_gate_clks[] = {
 424         { HI3660_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "clk_sw_mmbuf",
 425           CLK_SET_RATE_PARENT, 0x258, 7, CLK_GATE_HIWORD_MASK, },
 426         { HI3660_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_ppll0",
 427           CLK_SET_RATE_PARENT, 0x260, 11, CLK_DIVIDER_HIWORD_MASK, 0, },
 428         { HI3660_CLK_FLL_MMBUF_ANDGT, "clk_fll_mmbuf_andgt", "clk_fll_src",
 429           CLK_SET_RATE_PARENT, 0x260, 12, CLK_DIVIDER_HIWORD_MASK, 0, },
 430         { HI3660_CLK_SYS_MMBUF_ANDGT, "clk_sys_mmbuf_andgt", "clkin_sys",
 431           CLK_SET_RATE_PARENT, 0x260, 13, CLK_DIVIDER_HIWORD_MASK, 0, },
 432         { HI3660_CLK_GATE_PCIEPHY_GT, "clk_gate_pciephy_gt", "clk_ppll0",
 433           CLK_SET_RATE_PARENT, 0x268, 11, CLK_DIVIDER_HIWORD_MASK, 0, },
 434 };
 435
 436 static const char *const
 437 aclk_mux_mmbuf_p[] = {"aclk_div_mmbuf", "clk_gate_aomm",};
 438 static const char *const
 439 clk_sw_mmbuf_p[] = {"clk_sys_mmbuf_andgt", "clk_fll_mmbuf_andgt",
 440                     "aclk_mux_mmbuf", "aclk_mux_mmbuf"};
 441
 442 static const struct hisi_mux_clock hi3660_sctrl_mux_clks[] = {
 443         { HI3660_ACLK_MUX_MMBUF, "aclk_mux_mmbuf", aclk_mux_mmbuf_p,
 444           ARRAY_SIZE(aclk_mux_mmbuf_p), CLK_SET_RATE_PARENT, 0x250, 12, 1,
 445           CLK_MUX_HIWORD_MASK, },
 446         { HI3660_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p,
 447           ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT, 0x258, 8, 2,
 448           CLK_MUX_HIWORD_MASK, },
 449 };
 450
 451 static const struct hisi_divider_clock hi3660_sctrl_divider_clks[] = {
 452         { HI3660_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
 453           CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
 454         { HI3660_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
 455           CLK_SET_RATE_PARENT, 0x258, 10, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
 456         { HI3660_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
 457           CLK_SET_RATE_PARENT, 0x258, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 458         { HI3660_CLK_DIV_PCIEPHY, "clk_div_pciephy", "clk_gate_pciephy_gt",
 459           CLK_SET_RATE_PARENT, 0x268, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
 460 };
 461
 462 /* clk_iomcu */
 463 static const struct hisi_gate_clock hi3660_iomcu_gate_sep_clks[] = {
 464         { HI3660_CLK_I2C0_IOMCU, "clk_i2c0_iomcu", "clk_fll_src",
 465           CLK_SET_RATE_PARENT, 0x10, 3, 0, },
 466         { HI3660_CLK_I2C1_IOMCU, "clk_i2c1_iomcu", "clk_fll_src",
 467           CLK_SET_RATE_PARENT, 0x10, 4, 0, },
 468         { HI3660_CLK_I2C2_IOMCU, "clk_i2c2_iomcu", "clk_fll_src",
 469           CLK_SET_RATE_PARENT, 0x10, 5, 0, },
 470         { HI3660_CLK_I2C6_IOMCU, "clk_i2c6_iomcu", "clk_fll_src",
 471           CLK_SET_RATE_PARENT, 0x10, 27, 0, },
 472         { HI3660_CLK_IOMCU_PERI0, "iomcu_peri0", "clk_ppll0",
 473           CLK_SET_RATE_PARENT, 0x90, 0, 0, },
 474 };
 475
 476 static struct hisi_clock_data *clk_crgctrl_data;
 477
 478 static void hi3660_clk_iomcu_init(struct device_node *np)
 479 {
 480         struct hisi_clock_data *clk_data;
 481         int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks);
 482
 483         clk_data = hisi_clk_init(np, nr);
 484         if (!clk_data)
 485                 return;
 486
 487         hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks,
 488                                    ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
 489                                    clk_data);
 490 }
 491
 492 static void hi3660_clk_pmuctrl_init(struct device_node *np)
 493 {
 494         struct hisi_clock_data *clk_data;
 495         int nr = ARRAY_SIZE(hi3660_pmu_gate_clks);
 496
 497         clk_data = hisi_clk_init(np, nr);
 498         if (!clk_data)
 499                 return;
 500
 501         hisi_clk_register_gate(hi3660_pmu_gate_clks,
 502                                ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data);
 503 }
 504
 505 static void hi3660_clk_pctrl_init(struct device_node *np)
 506 {
 507         struct hisi_clock_data *clk_data;
 508         int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks);
 509
 510         clk_data = hisi_clk_init(np, nr);
 511         if (!clk_data)
 512                 return;
 513         hisi_clk_register_gate(hi3660_pctrl_gate_clks,
 514                                ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data);
 515 }
 516
 517 static void hi3660_clk_sctrl_init(struct device_node *np)
 518 {
 519         struct hisi_clock_data *clk_data;
 520         int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) +
 521                  ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) +
 522                  ARRAY_SIZE(hi3660_sctrl_mux_clks) +
 523                  ARRAY_SIZE(hi3660_sctrl_divider_clks);
 524
 525         clk_data = hisi_clk_init(np, nr);
 526         if (!clk_data)
 527                 return;
 528         hisi_clk_register_gate(hi3660_sctrl_gate_clks,
 529                                ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data);
 530         hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks,
 531                                    ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
 532                                    clk_data);
 533         hisi_clk_register_mux(hi3660_sctrl_mux_clks,
 534                               ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data);
 535         hisi_clk_register_divider(hi3660_sctrl_divider_clks,
 536                                   ARRAY_SIZE(hi3660_sctrl_divider_clks),
 537                                   clk_data);
 538 }
 539
 540 static void hi3660_clk_crgctrl_early_init(struct device_node *np)
 541 {
 542         int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) +
 543                  ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) +
 544                  ARRAY_SIZE(hi3660_crgctrl_gate_clks) +
 545                  ARRAY_SIZE(hi3660_crgctrl_mux_clks) +
 546                  ARRAY_SIZE(hi3660_crg_fixed_factor_clks) +
 547                  ARRAY_SIZE(hi3660_crgctrl_divider_clks);
 548         int i;
 549
 550         clk_crgctrl_data = hisi_clk_init(np, nr);
 551         if (!clk_crgctrl_data)
 552                 return;
 553
 554         for (i = 0; i < nr; i++)
 555                 clk_crgctrl_data->clk_data.clks[i] = ERR_PTR(-EPROBE_DEFER);
 556
 557         hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks,
 558                                      ARRAY_SIZE(hi3660_fixed_rate_clks),
 559                                      clk_crgctrl_data);
 560 }
 561 CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl",
 562                       hi3660_clk_crgctrl_early_init);
 563
 564 static void hi3660_clk_crgctrl_init(struct device_node *np)
 565 {
 566         struct clk **clks;
 567         int i;
 568
 569         if (!clk_crgctrl_data)
 570                 hi3660_clk_crgctrl_early_init(np);
 571
 572         /* clk_crgctrl_data initialization failed */
 573         if (!clk_crgctrl_data)
 574                 return;
 575
 576         hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks,
 577                                    ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
 578                                    clk_crgctrl_data);
 579         hisi_clk_register_gate(hi3660_crgctrl_gate_clks,
 580                                ARRAY_SIZE(hi3660_crgctrl_gate_clks),
 581                                clk_crgctrl_data);
 582         hisi_clk_register_mux(hi3660_crgctrl_mux_clks,
 583                               ARRAY_SIZE(hi3660_crgctrl_mux_clks),
 584                               clk_crgctrl_data);
 585         hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks,
 586                                        ARRAY_SIZE(hi3660_crg_fixed_factor_clks),
 587                                        clk_crgctrl_data);
 588         hisi_clk_register_divider(hi3660_crgctrl_divider_clks,
 589                                   ARRAY_SIZE(hi3660_crgctrl_divider_clks),
 590                                   clk_crgctrl_data);
 591
 592         clks = clk_crgctrl_data->clk_data.clks;
 593         for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) {
 594                 if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER)
 595                         pr_err("Failed to register crgctrl clock[%d] err=%ld\n",
 596                                i, PTR_ERR(clks[i]));
 597         }
 598 }
 599
 600 static const struct of_device_id hi3660_clk_match_table[] = {
 601         { .compatible = "hisilicon,hi3660-crgctrl",
 602           .data = hi3660_clk_crgctrl_init },
 603         { .compatible = "hisilicon,hi3660-pctrl",
 604           .data = hi3660_clk_pctrl_init },
 605         { .compatible = "hisilicon,hi3660-pmuctrl",
 606           .data = hi3660_clk_pmuctrl_init },
 607         { .compatible = "hisilicon,hi3660-sctrl",
 608           .data = hi3660_clk_sctrl_init },
 609         { .compatible = "hisilicon,hi3660-iomcu",
 610           .data = hi3660_clk_iomcu_init },
 611         { }
 612 };
 613
 614 static int hi3660_clk_probe(struct platform_device *pdev)
 615 {
 616         struct device *dev = &pdev->dev;
 617         struct device_node *np = pdev->dev.of_node;
 618         void (*init_func)(struct device_node *np);
 619
 620         init_func = of_device_get_match_data(dev);
 621         if (!init_func)
 622                 return -ENODEV;
 623
 624         init_func(np);
 625
 626         return 0;
 627 }
 628
 629 static struct platform_driver hi3660_clk_driver = {
 630         .probe          = hi3660_clk_probe,
 631         .driver         = {
 632                 .name   = "hi3660-clk",
 633                 .of_match_table = hi3660_clk_match_table,
 634         },
 635 };
 636
 637 static int __init hi3660_clk_init(void)
 638 {
 639         return platform_driver_register(&hi3660_clk_driver);
 640 }
 641 core_initcall(hi3660_clk_init);