drivers/clk/meson/axg.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AmLogic Meson-AXG Clock Controller Driver
   4  *
   5  * Copyright (c) 2016 Baylibre SAS.
   6  * Author: Michael Turquette <mturquette@baylibre.com>
   7  *
   8  * Copyright (c) 2017 Amlogic, inc.
   9  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/init.h>
  15 #include <linux/of_device.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19
  20 #include "clkc.h"
  21 #include "axg.h"
  22
  23 static DEFINE_SPINLOCK(meson_clk_lock);
  24
  25 static struct clk_regmap axg_fixed_pll = {
  26         .data = &(struct meson_clk_pll_data){
  27                 .m = {
  28                         .reg_off = HHI_MPLL_CNTL,
  29                         .shift   = 0,
  30                         .width   = 9,
  31                 },
  32                 .n = {
  33                         .reg_off = HHI_MPLL_CNTL,
  34                         .shift   = 9,
  35                         .width   = 5,
  36                 },
  37                 .od = {
  38                         .reg_off = HHI_MPLL_CNTL,
  39                         .shift   = 16,
  40                         .width   = 2,
  41                 },
  42                 .frac = {
  43                         .reg_off = HHI_MPLL_CNTL2,
  44                         .shift   = 0,
  45                         .width   = 12,
  46                 },
  47                 .l = {
  48                         .reg_off = HHI_MPLL_CNTL,
  49                         .shift   = 31,
  50                         .width   = 1,
  51                 },
  52                 .rst = {
  53                         .reg_off = HHI_MPLL_CNTL,
  54                         .shift   = 29,
  55                         .width   = 1,
  56                 },
  57         },
  58         .hw.init = &(struct clk_init_data){
  59                 .name = "fixed_pll",
  60                 .ops = &meson_clk_pll_ro_ops,
  61                 .parent_names = (const char *[]){ "xtal" },
  62                 .num_parents = 1,
  63         },
  64 };
  65
  66 static struct clk_regmap axg_sys_pll = {
  67         .data = &(struct meson_clk_pll_data){
  68                 .m = {
  69                         .reg_off = HHI_SYS_PLL_CNTL,
  70                         .shift   = 0,
  71                         .width   = 9,
  72                 },
  73                 .n = {
  74                         .reg_off = HHI_SYS_PLL_CNTL,
  75                         .shift   = 9,
  76                         .width   = 5,
  77                 },
  78                 .od = {
  79                         .reg_off = HHI_SYS_PLL_CNTL,
  80                         .shift   = 16,
  81                         .width   = 2,
  82                 },
  83                 .l = {
  84                         .reg_off = HHI_SYS_PLL_CNTL,
  85                         .shift   = 31,
  86                         .width   = 1,
  87                 },
  88                 .rst = {
  89                         .reg_off = HHI_SYS_PLL_CNTL,
  90                         .shift   = 29,
  91                         .width   = 1,
  92                 },
  93         },
  94         .hw.init = &(struct clk_init_data){
  95                 .name = "sys_pll",
  96                 .ops = &meson_clk_pll_ro_ops,
  97                 .parent_names = (const char *[]){ "xtal" },
  98                 .num_parents = 1,
  99         },
 100 };
 101
 102 static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
 103         PLL_RATE(240000000, 40, 1, 2),
 104         PLL_RATE(246000000, 41, 1, 2),
 105         PLL_RATE(252000000, 42, 1, 2),
 106         PLL_RATE(258000000, 43, 1, 2),
 107         PLL_RATE(264000000, 44, 1, 2),
 108         PLL_RATE(270000000, 45, 1, 2),
 109         PLL_RATE(276000000, 46, 1, 2),
 110         PLL_RATE(282000000, 47, 1, 2),
 111         PLL_RATE(288000000, 48, 1, 2),
 112         PLL_RATE(294000000, 49, 1, 2),
 113         PLL_RATE(300000000, 50, 1, 2),
 114         PLL_RATE(306000000, 51, 1, 2),
 115         PLL_RATE(312000000, 52, 1, 2),
 116         PLL_RATE(318000000, 53, 1, 2),
 117         PLL_RATE(324000000, 54, 1, 2),
 118         PLL_RATE(330000000, 55, 1, 2),
 119         PLL_RATE(336000000, 56, 1, 2),
 120         PLL_RATE(342000000, 57, 1, 2),
 121         PLL_RATE(348000000, 58, 1, 2),
 122         PLL_RATE(354000000, 59, 1, 2),
 123         PLL_RATE(360000000, 60, 1, 2),
 124         PLL_RATE(366000000, 61, 1, 2),
 125         PLL_RATE(372000000, 62, 1, 2),
 126         PLL_RATE(378000000, 63, 1, 2),
 127         PLL_RATE(384000000, 64, 1, 2),
 128         PLL_RATE(390000000, 65, 1, 3),
 129         PLL_RATE(396000000, 66, 1, 3),
 130         PLL_RATE(402000000, 67, 1, 3),
 131         PLL_RATE(408000000, 68, 1, 3),
 132         PLL_RATE(480000000, 40, 1, 1),
 133         PLL_RATE(492000000, 41, 1, 1),
 134         PLL_RATE(504000000, 42, 1, 1),
 135         PLL_RATE(516000000, 43, 1, 1),
 136         PLL_RATE(528000000, 44, 1, 1),
 137         PLL_RATE(540000000, 45, 1, 1),
 138         PLL_RATE(552000000, 46, 1, 1),
 139         PLL_RATE(564000000, 47, 1, 1),
 140         PLL_RATE(576000000, 48, 1, 1),
 141         PLL_RATE(588000000, 49, 1, 1),
 142         PLL_RATE(600000000, 50, 1, 1),
 143         PLL_RATE(612000000, 51, 1, 1),
 144         PLL_RATE(624000000, 52, 1, 1),
 145         PLL_RATE(636000000, 53, 1, 1),
 146         PLL_RATE(648000000, 54, 1, 1),
 147         PLL_RATE(660000000, 55, 1, 1),
 148         PLL_RATE(672000000, 56, 1, 1),
 149         PLL_RATE(684000000, 57, 1, 1),
 150         PLL_RATE(696000000, 58, 1, 1),
 151         PLL_RATE(708000000, 59, 1, 1),
 152         PLL_RATE(720000000, 60, 1, 1),
 153         PLL_RATE(732000000, 61, 1, 1),
 154         PLL_RATE(744000000, 62, 1, 1),
 155         PLL_RATE(756000000, 63, 1, 1),
 156         PLL_RATE(768000000, 64, 1, 1),
 157         PLL_RATE(780000000, 65, 1, 1),
 158         PLL_RATE(792000000, 66, 1, 1),
 159         PLL_RATE(804000000, 67, 1, 1),
 160         PLL_RATE(816000000, 68, 1, 1),
 161         PLL_RATE(960000000, 40, 1, 0),
 162         PLL_RATE(984000000, 41, 1, 0),
 163         PLL_RATE(1008000000, 42, 1, 0),
 164         PLL_RATE(1032000000, 43, 1, 0),
 165         PLL_RATE(1056000000, 44, 1, 0),
 166         PLL_RATE(1080000000, 45, 1, 0),
 167         PLL_RATE(1104000000, 46, 1, 0),
 168         PLL_RATE(1128000000, 47, 1, 0),
 169         PLL_RATE(1152000000, 48, 1, 0),
 170         PLL_RATE(1176000000, 49, 1, 0),
 171         PLL_RATE(1200000000, 50, 1, 0),
 172         PLL_RATE(1224000000, 51, 1, 0),
 173         PLL_RATE(1248000000, 52, 1, 0),
 174         PLL_RATE(1272000000, 53, 1, 0),
 175         PLL_RATE(1296000000, 54, 1, 0),
 176         PLL_RATE(1320000000, 55, 1, 0),
 177         PLL_RATE(1344000000, 56, 1, 0),
 178         PLL_RATE(1368000000, 57, 1, 0),
 179         PLL_RATE(1392000000, 58, 1, 0),
 180         PLL_RATE(1416000000, 59, 1, 0),
 181         PLL_RATE(1440000000, 60, 1, 0),
 182         PLL_RATE(1464000000, 61, 1, 0),
 183         PLL_RATE(1488000000, 62, 1, 0),
 184         PLL_RATE(1512000000, 63, 1, 0),
 185         PLL_RATE(1536000000, 64, 1, 0),
 186         PLL_RATE(1560000000, 65, 1, 0),
 187         PLL_RATE(1584000000, 66, 1, 0),
 188         PLL_RATE(1608000000, 67, 1, 0),
 189         PLL_RATE(1632000000, 68, 1, 0),
 190         { /* sentinel */ },
 191 };
 192
 193 static const struct reg_sequence axg_gp0_init_regs[] = {
 194         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084b000 },
 195         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 196         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 197         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 198         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 199         { .reg = HHI_GP0_PLL_CNTL,      .def = 0x40010250 },
 200 };
 201
 202 static struct clk_regmap axg_gp0_pll = {
 203         .data = &(struct meson_clk_pll_data){
 204                 .m = {
 205                         .reg_off = HHI_GP0_PLL_CNTL,
 206                         .shift   = 0,
 207                         .width   = 9,
 208                 },
 209                 .n = {
 210                         .reg_off = HHI_GP0_PLL_CNTL,
 211                         .shift   = 9,
 212                         .width   = 5,
 213                 },
 214                 .od = {
 215                         .reg_off = HHI_GP0_PLL_CNTL,
 216                         .shift   = 16,
 217                         .width   = 2,
 218                 },
 219                 .frac = {
 220                         .reg_off = HHI_GP0_PLL_CNTL1,
 221                         .shift   = 0,
 222                         .width   = 10,
 223                 },
 224                 .l = {
 225                         .reg_off = HHI_GP0_PLL_CNTL,
 226                         .shift   = 31,
 227                         .width   = 1,
 228                 },
 229                 .rst = {
 230                         .reg_off = HHI_GP0_PLL_CNTL,
 231                         .shift   = 29,
 232                         .width   = 1,
 233                 },
 234                 .table = axg_gp0_pll_rate_table,
 235                 .init_regs = axg_gp0_init_regs,
 236                 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
 237         },
 238         .hw.init = &(struct clk_init_data){
 239                 .name = "gp0_pll",
 240                 .ops = &meson_clk_pll_ops,
 241                 .parent_names = (const char *[]){ "xtal" },
 242                 .num_parents = 1,
 243         },
 244 };
 245
 246 static const struct reg_sequence axg_hifi_init_regs[] = {
 247         { .reg = HHI_HIFI_PLL_CNTL1,    .def = 0xc084b000 },
 248         { .reg = HHI_HIFI_PLL_CNTL2,    .def = 0xb75020be },
 249         { .reg = HHI_HIFI_PLL_CNTL3,    .def = 0x0a6a3a88 },
 250         { .reg = HHI_HIFI_PLL_CNTL4,    .def = 0xc000004d },
 251         { .reg = HHI_HIFI_PLL_CNTL5,    .def = 0x00058000 },
 252         { .reg = HHI_HIFI_PLL_CNTL,     .def = 0x40010250 },
 253 };
 254
 255 static struct clk_regmap axg_hifi_pll = {
 256         .data = &(struct meson_clk_pll_data){
 257                 .m = {
 258                         .reg_off = HHI_HIFI_PLL_CNTL,
 259                         .shift   = 0,
 260                         .width   = 9,
 261                 },
 262                 .n = {
 263                         .reg_off = HHI_HIFI_PLL_CNTL,
 264                         .shift   = 9,
 265                         .width   = 5,
 266                 },
 267                 .od = {
 268                         .reg_off = HHI_HIFI_PLL_CNTL,
 269                         .shift   = 16,
 270                         .width   = 2,
 271                 },
 272                 .frac = {
 273                         .reg_off = HHI_HIFI_PLL_CNTL5,
 274                         .shift   = 0,
 275                         .width   = 13,
 276                 },
 277                 .l = {
 278                         .reg_off = HHI_HIFI_PLL_CNTL,
 279                         .shift   = 31,
 280                         .width   = 1,
 281                 },
 282                 .rst = {
 283                         .reg_off = HHI_HIFI_PLL_CNTL,
 284                         .shift   = 29,
 285                         .width   = 1,
 286                 },
 287                 .table = axg_gp0_pll_rate_table,
 288                 .init_regs = axg_hifi_init_regs,
 289                 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
 290                 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
 291         },
 292         .hw.init = &(struct clk_init_data){
 293                 .name = "hifi_pll",
 294                 .ops = &meson_clk_pll_ops,
 295                 .parent_names = (const char *[]){ "xtal" },
 296                 .num_parents = 1,
 297         },
 298 };
 299
 300 static struct clk_fixed_factor axg_fclk_div2_div = {
 301         .mult = 1,
 302         .div = 2,
 303         .hw.init = &(struct clk_init_data){
 304                 .name = "fclk_div2_div",
 305                 .ops = &clk_fixed_factor_ops,
 306                 .parent_names = (const char *[]){ "fixed_pll" },
 307                 .num_parents = 1,
 308         },
 309 };
 310
 311 static struct clk_regmap axg_fclk_div2 = {
 312         .data = &(struct clk_regmap_gate_data){
 313                 .offset = HHI_MPLL_CNTL6,
 314                 .bit_idx = 27,
 315         },
 316         .hw.init = &(struct clk_init_data){
 317                 .name = "fclk_div2",
 318                 .ops = &clk_regmap_gate_ops,
 319                 .parent_names = (const char *[]){ "fclk_div2_div" },
 320                 .num_parents = 1,
 321                 .flags = CLK_IS_CRITICAL,
 322         },
 323 };
 324
 325 static struct clk_fixed_factor axg_fclk_div3_div = {
 326         .mult = 1,
 327         .div = 3,
 328         .hw.init = &(struct clk_init_data){
 329                 .name = "fclk_div3_div",
 330                 .ops = &clk_fixed_factor_ops,
 331                 .parent_names = (const char *[]){ "fixed_pll" },
 332                 .num_parents = 1,
 333         },
 334 };
 335
 336 static struct clk_regmap axg_fclk_div3 = {
 337         .data = &(struct clk_regmap_gate_data){
 338                 .offset = HHI_MPLL_CNTL6,
 339                 .bit_idx = 28,
 340         },
 341         .hw.init = &(struct clk_init_data){
 342                 .name = "fclk_div3",
 343                 .ops = &clk_regmap_gate_ops,
 344                 .parent_names = (const char *[]){ "fclk_div3_div" },
 345                 .num_parents = 1,
 346                 /*
 347                  * FIXME:
 348                  * This clock, as fdiv2, is used by the SCPI FW and is required
 349                  * by the platform to operate correctly.
 350                  * Until the following condition are met, we need this clock to
 351                  * be marked as critical:
 352                  * a) The SCPI generic driver claims and enable all the clocks
 353                  *    it needs
 354                  * b) CCF has a clock hand-off mechanism to make the sure the
 355                  *    clock stays on until the proper driver comes along
 356                  */
 357                 .flags = CLK_IS_CRITICAL,
 358         },
 359 };
 360
 361 static struct clk_fixed_factor axg_fclk_div4_div = {
 362         .mult = 1,
 363         .div = 4,
 364         .hw.init = &(struct clk_init_data){
 365                 .name = "fclk_div4_div",
 366                 .ops = &clk_fixed_factor_ops,
 367                 .parent_names = (const char *[]){ "fixed_pll" },
 368                 .num_parents = 1,
 369         },
 370 };
 371
 372 static struct clk_regmap axg_fclk_div4 = {
 373         .data = &(struct clk_regmap_gate_data){
 374                 .offset = HHI_MPLL_CNTL6,
 375                 .bit_idx = 29,
 376         },
 377         .hw.init = &(struct clk_init_data){
 378                 .name = "fclk_div4",
 379                 .ops = &clk_regmap_gate_ops,
 380                 .parent_names = (const char *[]){ "fclk_div4_div" },
 381                 .num_parents = 1,
 382         },
 383 };
 384
 385 static struct clk_fixed_factor axg_fclk_div5_div = {
 386         .mult = 1,
 387         .div = 5,
 388         .hw.init = &(struct clk_init_data){
 389                 .name = "fclk_div5_div",
 390                 .ops = &clk_fixed_factor_ops,
 391                 .parent_names = (const char *[]){ "fixed_pll" },
 392                 .num_parents = 1,
 393         },
 394 };
 395
 396 static struct clk_regmap axg_fclk_div5 = {
 397         .data = &(struct clk_regmap_gate_data){
 398                 .offset = HHI_MPLL_CNTL6,
 399                 .bit_idx = 30,
 400         },
 401         .hw.init = &(struct clk_init_data){
 402                 .name = "fclk_div5",
 403                 .ops = &clk_regmap_gate_ops,
 404                 .parent_names = (const char *[]){ "fclk_div5_div" },
 405                 .num_parents = 1,
 406         },
 407 };
 408
 409 static struct clk_fixed_factor axg_fclk_div7_div = {
 410         .mult = 1,
 411         .div = 7,
 412         .hw.init = &(struct clk_init_data){
 413                 .name = "fclk_div7_div",
 414                 .ops = &clk_fixed_factor_ops,
 415                 .parent_names = (const char *[]){ "fixed_pll" },
 416                 .num_parents = 1,
 417         },
 418 };
 419
 420 static struct clk_regmap axg_fclk_div7 = {
 421         .data = &(struct clk_regmap_gate_data){
 422                 .offset = HHI_MPLL_CNTL6,
 423                 .bit_idx = 31,
 424         },
 425         .hw.init = &(struct clk_init_data){
 426                 .name = "fclk_div7",
 427                 .ops = &clk_regmap_gate_ops,
 428                 .parent_names = (const char *[]){ "fclk_div7_div" },
 429                 .num_parents = 1,
 430         },
 431 };
 432
 433 static struct clk_regmap axg_mpll_prediv = {
 434         .data = &(struct clk_regmap_div_data){
 435                 .offset = HHI_MPLL_CNTL5,
 436                 .shift = 12,
 437                 .width = 1,
 438         },
 439         .hw.init = &(struct clk_init_data){
 440                 .name = "mpll_prediv",
 441                 .ops = &clk_regmap_divider_ro_ops,
 442                 .parent_names = (const char *[]){ "fixed_pll" },
 443                 .num_parents = 1,
 444         },
 445 };
 446
 447 static struct clk_regmap axg_mpll0_div = {
 448         .data = &(struct meson_clk_mpll_data){
 449                 .sdm = {
 450                         .reg_off = HHI_MPLL_CNTL7,
 451                         .shift   = 0,
 452                         .width   = 14,
 453                 },
 454                 .sdm_en = {
 455                         .reg_off = HHI_MPLL_CNTL7,
 456                         .shift   = 15,
 457                         .width   = 1,
 458                 },
 459                 .n2 = {
 460                         .reg_off = HHI_MPLL_CNTL7,
 461                         .shift   = 16,
 462                         .width   = 9,
 463                 },
 464                 .misc = {
 465                         .reg_off = HHI_PLL_TOP_MISC,
 466                         .shift   = 0,
 467                         .width   = 1,
 468                 },
 469                 .lock = &meson_clk_lock,
 470                 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 471         },
 472         .hw.init = &(struct clk_init_data){
 473                 .name = "mpll0_div",
 474                 .ops = &meson_clk_mpll_ops,
 475                 .parent_names = (const char *[]){ "mpll_prediv" },
 476                 .num_parents = 1,
 477         },
 478 };
 479
 480 static struct clk_regmap axg_mpll0 = {
 481         .data = &(struct clk_regmap_gate_data){
 482                 .offset = HHI_MPLL_CNTL7,
 483                 .bit_idx = 14,
 484         },
 485         .hw.init = &(struct clk_init_data){
 486                 .name = "mpll0",
 487                 .ops = &clk_regmap_gate_ops,
 488                 .parent_names = (const char *[]){ "mpll0_div" },
 489                 .num_parents = 1,
 490                 .flags = CLK_SET_RATE_PARENT,
 491         },
 492 };
 493
 494 static struct clk_regmap axg_mpll1_div = {
 495         .data = &(struct meson_clk_mpll_data){
 496                 .sdm = {
 497                         .reg_off = HHI_MPLL_CNTL8,
 498                         .shift   = 0,
 499                         .width   = 14,
 500                 },
 501                 .sdm_en = {
 502                         .reg_off = HHI_MPLL_CNTL8,
 503                         .shift   = 15,
 504                         .width   = 1,
 505                 },
 506                 .n2 = {
 507                         .reg_off = HHI_MPLL_CNTL8,
 508                         .shift   = 16,
 509                         .width   = 9,
 510                 },
 511                 .misc = {
 512                         .reg_off = HHI_PLL_TOP_MISC,
 513                         .shift   = 1,
 514                         .width   = 1,
 515                 },
 516                 .lock = &meson_clk_lock,
 517                 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 518         },
 519         .hw.init = &(struct clk_init_data){
 520                 .name = "mpll1_div",
 521                 .ops = &meson_clk_mpll_ops,
 522                 .parent_names = (const char *[]){ "mpll_prediv" },
 523                 .num_parents = 1,
 524         },
 525 };
 526
 527 static struct clk_regmap axg_mpll1 = {
 528         .data = &(struct clk_regmap_gate_data){
 529                 .offset = HHI_MPLL_CNTL8,
 530                 .bit_idx = 14,
 531         },
 532         .hw.init = &(struct clk_init_data){
 533                 .name = "mpll1",
 534                 .ops = &clk_regmap_gate_ops,
 535                 .parent_names = (const char *[]){ "mpll1_div" },
 536                 .num_parents = 1,
 537                 .flags = CLK_SET_RATE_PARENT,
 538         },
 539 };
 540
 541 static struct clk_regmap axg_mpll2_div = {
 542         .data = &(struct meson_clk_mpll_data){
 543                 .sdm = {
 544                         .reg_off = HHI_MPLL_CNTL9,
 545                         .shift   = 0,
 546                         .width   = 14,
 547                 },
 548                 .sdm_en = {
 549                         .reg_off = HHI_MPLL_CNTL9,
 550                         .shift   = 15,
 551                         .width   = 1,
 552                 },
 553                 .n2 = {
 554                         .reg_off = HHI_MPLL_CNTL9,
 555                         .shift   = 16,
 556                         .width   = 9,
 557                 },
 558                 .ssen = {
 559                         .reg_off = HHI_MPLL_CNTL,
 560                         .shift   = 25,
 561                         .width   = 1,
 562                 },
 563                 .misc = {
 564                         .reg_off = HHI_PLL_TOP_MISC,
 565                         .shift   = 2,
 566                         .width   = 1,
 567                 },
 568                 .lock = &meson_clk_lock,
 569                 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 570         },
 571         .hw.init = &(struct clk_init_data){
 572                 .name = "mpll2_div",
 573                 .ops = &meson_clk_mpll_ops,
 574                 .parent_names = (const char *[]){ "mpll_prediv" },
 575                 .num_parents = 1,
 576         },
 577 };
 578
 579 static struct clk_regmap axg_mpll2 = {
 580         .data = &(struct clk_regmap_gate_data){
 581                 .offset = HHI_MPLL_CNTL9,
 582                 .bit_idx = 14,
 583         },
 584         .hw.init = &(struct clk_init_data){
 585                 .name = "mpll2",
 586                 .ops = &clk_regmap_gate_ops,
 587                 .parent_names = (const char *[]){ "mpll2_div" },
 588                 .num_parents = 1,
 589                 .flags = CLK_SET_RATE_PARENT,
 590         },
 591 };
 592
 593 static struct clk_regmap axg_mpll3_div = {
 594         .data = &(struct meson_clk_mpll_data){
 595                 .sdm = {
 596                         .reg_off = HHI_MPLL3_CNTL0,
 597                         .shift   = 12,
 598                         .width   = 14,
 599                 },
 600                 .sdm_en = {
 601                         .reg_off = HHI_MPLL3_CNTL0,
 602                         .shift   = 11,
 603                         .width   = 1,
 604                 },
 605                 .n2 = {
 606                         .reg_off = HHI_MPLL3_CNTL0,
 607                         .shift   = 2,
 608                         .width   = 9,
 609                 },
 610                 .misc = {
 611                         .reg_off = HHI_PLL_TOP_MISC,
 612                         .shift   = 3,
 613                         .width   = 1,
 614                 },
 615                 .lock = &meson_clk_lock,
 616                 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 617         },
 618         .hw.init = &(struct clk_init_data){
 619                 .name = "mpll3_div",
 620                 .ops = &meson_clk_mpll_ops,
 621                 .parent_names = (const char *[]){ "mpll_prediv" },
 622                 .num_parents = 1,
 623         },
 624 };
 625
 626 static struct clk_regmap axg_mpll3 = {
 627         .data = &(struct clk_regmap_gate_data){
 628                 .offset = HHI_MPLL3_CNTL0,
 629                 .bit_idx = 0,
 630         },
 631         .hw.init = &(struct clk_init_data){
 632                 .name = "mpll3",
 633                 .ops = &clk_regmap_gate_ops,
 634                 .parent_names = (const char *[]){ "mpll3_div" },
 635                 .num_parents = 1,
 636                 .flags = CLK_SET_RATE_PARENT,
 637         },
 638 };
 639
 640 static const struct pll_rate_table axg_pcie_pll_rate_table[] = {
 641         {
 642                 .rate   = 100000000,
 643                 .m      = 200,
 644                 .n      = 3,
 645                 .od     = 1,
 646                 .od2    = 3,
 647         },
 648         { /* sentinel */ },
 649 };
 650
 651 static const struct reg_sequence axg_pcie_init_regs[] = {
 652         { .reg = HHI_PCIE_PLL_CNTL,     .def = 0x400106c8 },
 653         { .reg = HHI_PCIE_PLL_CNTL1,    .def = 0x0084a2aa },
 654         { .reg = HHI_PCIE_PLL_CNTL2,    .def = 0xb75020be },
 655         { .reg = HHI_PCIE_PLL_CNTL3,    .def = 0x0a47488e },
 656         { .reg = HHI_PCIE_PLL_CNTL4,    .def = 0xc000004d },
 657         { .reg = HHI_PCIE_PLL_CNTL5,    .def = 0x00078000 },
 658         { .reg = HHI_PCIE_PLL_CNTL6,    .def = 0x002323c6 },
 659 };
 660
 661 static struct clk_regmap axg_pcie_pll = {
 662         .data = &(struct meson_clk_pll_data){
 663                 .m = {
 664                         .reg_off = HHI_PCIE_PLL_CNTL,
 665                         .shift   = 0,
 666                         .width   = 9,
 667                 },
 668                 .n = {
 669                         .reg_off = HHI_PCIE_PLL_CNTL,
 670                         .shift   = 9,
 671                         .width   = 5,
 672                 },
 673                 .od = {
 674                         .reg_off = HHI_PCIE_PLL_CNTL,
 675                         .shift   = 16,
 676                         .width   = 2,
 677                 },
 678                 .od2 = {
 679                         .reg_off = HHI_PCIE_PLL_CNTL6,
 680                         .shift   = 6,
 681                         .width   = 2,
 682                 },
 683                 .frac = {
 684                         .reg_off = HHI_PCIE_PLL_CNTL1,
 685                         .shift   = 0,
 686                         .width   = 12,
 687                 },
 688                 .l = {
 689                         .reg_off = HHI_PCIE_PLL_CNTL,
 690                         .shift   = 31,
 691                         .width   = 1,
 692                 },
 693                 .rst = {
 694                         .reg_off = HHI_PCIE_PLL_CNTL,
 695                         .shift   = 29,
 696                         .width   = 1,
 697                 },
 698                 .table = axg_pcie_pll_rate_table,
 699                 .init_regs = axg_pcie_init_regs,
 700                 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
 701         },
 702         .hw.init = &(struct clk_init_data){
 703                 .name = "pcie_pll",
 704                 .ops = &meson_clk_pll_ops,
 705                 .parent_names = (const char *[]){ "xtal" },
 706                 .num_parents = 1,
 707         },
 708 };
 709
 710 static struct clk_regmap axg_pcie_mux = {
 711         .data = &(struct clk_regmap_mux_data){
 712                 .offset = HHI_PCIE_PLL_CNTL6,
 713                 .mask = 0x1,
 714                 .shift = 2,
 715                 /* skip the parent mpll3, reserved for debug */
 716                 .table = (u32[]){ 1 },
 717         },
 718         .hw.init = &(struct clk_init_data){
 719                 .name = "pcie_mux",
 720                 .ops = &clk_regmap_mux_ops,
 721                 .parent_names = (const char *[]){ "pcie_pll" },
 722                 .num_parents = 1,
 723                 .flags = CLK_SET_RATE_PARENT,
 724         },
 725 };
 726
 727 static struct clk_regmap axg_pcie_ref = {
 728         .data = &(struct clk_regmap_mux_data){
 729                 .offset = HHI_PCIE_PLL_CNTL6,
 730                 .mask = 0x1,
 731                 .shift = 1,
 732                 /* skip the parent 0, reserved for debug */
 733                 .table = (u32[]){ 1 },
 734         },
 735         .hw.init = &(struct clk_init_data){
 736                 .name = "pcie_ref",
 737                 .ops = &clk_regmap_mux_ops,
 738                 .parent_names = (const char *[]){ "pcie_mux" },
 739                 .num_parents = 1,
 740                 .flags = CLK_SET_RATE_PARENT,
 741         },
 742 };
 743
 744 static struct clk_regmap axg_pcie_cml_en0 = {
 745         .data = &(struct clk_regmap_gate_data){
 746                 .offset = HHI_PCIE_PLL_CNTL6,
 747                 .bit_idx = 4,
 748         },
 749         .hw.init = &(struct clk_init_data) {
 750                 .name = "pcie_cml_en0",
 751                 .ops = &clk_regmap_gate_ops,
 752                 .parent_names = (const char *[]){ "pcie_ref" },
 753                 .num_parents = 1,
 754                 .flags = CLK_SET_RATE_PARENT,
 755
 756         },
 757 };
 758
 759 static struct clk_regmap axg_pcie_cml_en1 = {
 760         .data = &(struct clk_regmap_gate_data){
 761                 .offset = HHI_PCIE_PLL_CNTL6,
 762                 .bit_idx = 3,
 763         },
 764         .hw.init = &(struct clk_init_data) {
 765                 .name = "pcie_cml_en1",
 766                 .ops = &clk_regmap_gate_ops,
 767                 .parent_names = (const char *[]){ "pcie_ref" },
 768                 .num_parents = 1,
 769                 .flags = CLK_SET_RATE_PARENT,
 770         },
 771 };
 772
 773 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 774 static const char * const clk81_parent_names[] = {
 775         "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
 776         "fclk_div3", "fclk_div5"
 777 };
 778
 779 static struct clk_regmap axg_mpeg_clk_sel = {
 780         .data = &(struct clk_regmap_mux_data){
 781                 .offset = HHI_MPEG_CLK_CNTL,
 782                 .mask = 0x7,
 783                 .shift = 12,
 784                 .table = mux_table_clk81,
 785         },
 786         .hw.init = &(struct clk_init_data){
 787                 .name = "mpeg_clk_sel",
 788                 .ops = &clk_regmap_mux_ro_ops,
 789                 .parent_names = clk81_parent_names,
 790                 .num_parents = ARRAY_SIZE(clk81_parent_names),
 791         },
 792 };
 793
 794 static struct clk_regmap axg_mpeg_clk_div = {
 795         .data = &(struct clk_regmap_div_data){
 796                 .offset = HHI_MPEG_CLK_CNTL,
 797                 .shift = 0,
 798                 .width = 7,
 799         },
 800         .hw.init = &(struct clk_init_data){
 801                 .name = "mpeg_clk_div",
 802                 .ops = &clk_regmap_divider_ops,
 803                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 804                 .num_parents = 1,
 805                 .flags = CLK_SET_RATE_PARENT,
 806         },
 807 };
 808
 809 static struct clk_regmap axg_clk81 = {
 810         .data = &(struct clk_regmap_gate_data){
 811                 .offset = HHI_MPEG_CLK_CNTL,
 812                 .bit_idx = 7,
 813         },
 814         .hw.init = &(struct clk_init_data){
 815                 .name = "clk81",
 816                 .ops = &clk_regmap_gate_ops,
 817                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 818                 .num_parents = 1,
 819                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
 820         },
 821 };
 822
 823 static const char * const axg_sd_emmc_clk0_parent_names[] = {
 824         "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
 825
 826         /*
 827          * Following these parent clocks, we should also have had mpll2, mpll3
 828          * and gp0_pll but these clocks are too precious to be used here. All
 829          * the necessary rates for MMC and NAND operation can be acheived using
 830          * xtal or fclk_div clocks
 831          */
 832 };
 833
 834 /* SDcard clock */
 835 static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
 836         .data = &(struct clk_regmap_mux_data){
 837                 .offset = HHI_SD_EMMC_CLK_CNTL,
 838                 .mask = 0x7,
 839                 .shift = 25,
 840         },
 841         .hw.init = &(struct clk_init_data) {
 842                 .name = "sd_emmc_b_clk0_sel",
 843                 .ops = &clk_regmap_mux_ops,
 844                 .parent_names = axg_sd_emmc_clk0_parent_names,
 845                 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
 846                 .flags = CLK_SET_RATE_PARENT,
 847         },
 848 };
 849
 850 static struct clk_regmap axg_sd_emmc_b_clk0_div = {
 851         .data = &(struct clk_regmap_div_data){
 852                 .offset = HHI_SD_EMMC_CLK_CNTL,
 853                 .shift = 16,
 854                 .width = 7,
 855                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 856         },
 857         .hw.init = &(struct clk_init_data) {
 858                 .name = "sd_emmc_b_clk0_div",
 859                 .ops = &clk_regmap_divider_ops,
 860                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
 861                 .num_parents = 1,
 862                 .flags = CLK_SET_RATE_PARENT,
 863         },
 864 };
 865
 866 static struct clk_regmap axg_sd_emmc_b_clk0 = {
 867         .data = &(struct clk_regmap_gate_data){
 868                 .offset = HHI_SD_EMMC_CLK_CNTL,
 869                 .bit_idx = 23,
 870         },
 871         .hw.init = &(struct clk_init_data){
 872                 .name = "sd_emmc_b_clk0",
 873                 .ops = &clk_regmap_gate_ops,
 874                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
 875                 .num_parents = 1,
 876                 .flags = CLK_SET_RATE_PARENT,
 877         },
 878 };
 879
 880 /* EMMC/NAND clock */
 881 static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
 882         .data = &(struct clk_regmap_mux_data){
 883                 .offset = HHI_NAND_CLK_CNTL,
 884                 .mask = 0x7,
 885                 .shift = 9,
 886         },
 887         .hw.init = &(struct clk_init_data) {
 888                 .name = "sd_emmc_c_clk0_sel",
 889                 .ops = &clk_regmap_mux_ops,
 890                 .parent_names = axg_sd_emmc_clk0_parent_names,
 891                 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
 892                 .flags = CLK_SET_RATE_PARENT,
 893         },
 894 };
 895
 896 static struct clk_regmap axg_sd_emmc_c_clk0_div = {
 897         .data = &(struct clk_regmap_div_data){
 898                 .offset = HHI_NAND_CLK_CNTL,
 899                 .shift = 0,
 900                 .width = 7,
 901                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 902         },
 903         .hw.init = &(struct clk_init_data) {
 904                 .name = "sd_emmc_c_clk0_div",
 905                 .ops = &clk_regmap_divider_ops,
 906                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
 907                 .num_parents = 1,
 908                 .flags = CLK_SET_RATE_PARENT,
 909         },
 910 };
 911
 912 static struct clk_regmap axg_sd_emmc_c_clk0 = {
 913         .data = &(struct clk_regmap_gate_data){
 914                 .offset = HHI_NAND_CLK_CNTL,
 915                 .bit_idx = 7,
 916         },
 917         .hw.init = &(struct clk_init_data){
 918                 .name = "sd_emmc_c_clk0",
 919                 .ops = &clk_regmap_gate_ops,
 920                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
 921                 .num_parents = 1,
 922                 .flags = CLK_SET_RATE_PARENT,
 923         },
 924 };
 925
 926 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
 927                                     9, 10, 11, 13, 14, };
 928 static const char * const gen_clk_parent_names[] = {
 929         "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
 930         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
 931 };
 932
 933 static struct clk_regmap axg_gen_clk_sel = {
 934         .data = &(struct clk_regmap_mux_data){
 935                 .offset = HHI_GEN_CLK_CNTL,
 936                 .mask = 0xf,
 937                 .shift = 12,
 938                 .table = mux_table_gen_clk,
 939         },
 940         .hw.init = &(struct clk_init_data){
 941                 .name = "gen_clk_sel",
 942                 .ops = &clk_regmap_mux_ops,
 943                 /*
 944                  * bits 15:12 selects from 14 possible parents:
 945                  * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
 946                  * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
 947                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
 948                  */
 949                 .parent_names = gen_clk_parent_names,
 950                 .num_parents = ARRAY_SIZE(gen_clk_parent_names),
 951         },
 952 };
 953
 954 static struct clk_regmap axg_gen_clk_div = {
 955         .data = &(struct clk_regmap_div_data){
 956                 .offset = HHI_GEN_CLK_CNTL,
 957                 .shift = 0,
 958                 .width = 11,
 959         },
 960         .hw.init = &(struct clk_init_data){
 961                 .name = "gen_clk_div",
 962                 .ops = &clk_regmap_divider_ops,
 963                 .parent_names = (const char *[]){ "gen_clk_sel" },
 964                 .num_parents = 1,
 965                 .flags = CLK_SET_RATE_PARENT,
 966         },
 967 };
 968
 969 static struct clk_regmap axg_gen_clk = {
 970         .data = &(struct clk_regmap_gate_data){
 971                 .offset = HHI_GEN_CLK_CNTL,
 972                 .bit_idx = 7,
 973         },
 974         .hw.init = &(struct clk_init_data){
 975                 .name = "gen_clk",
 976                 .ops = &clk_regmap_gate_ops,
 977                 .parent_names = (const char *[]){ "gen_clk_div" },
 978                 .num_parents = 1,
 979                 .flags = CLK_SET_RATE_PARENT,
 980         },
 981 };
 982
 983 /* Everything Else (EE) domain gates */
 984 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
 985 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
 986 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
 987 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
 988 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
 989 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
 990 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
 991 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
 992 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
 993 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
 994 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
 995 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
 996 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
 997 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
 998 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
 999 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
1000 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
1001 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
1002 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
1003 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
1004
1005 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
1006 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
1007 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
1008 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
1009 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
1010 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
1011 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
1012 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
1013 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
1014 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
1015 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
1016
1017 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1018 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1019 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1020 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
1021 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
1022 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
1023 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1024 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1025 static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
1026
1027 /* Always On (AO) domain gates */
1028
1029 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
1030 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
1031 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
1032 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
1033 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
1034
1035 /* Array of all clocks provided by this provider */
1036
1037 static struct clk_hw_onecell_data axg_hw_onecell_data = {
1038         .hws = {
1039                 [CLKID_SYS_PLL]                 = &axg_sys_pll.hw,
1040                 [CLKID_FIXED_PLL]               = &axg_fixed_pll.hw,
1041                 [CLKID_FCLK_DIV2]               = &axg_fclk_div2.hw,
1042                 [CLKID_FCLK_DIV3]               = &axg_fclk_div3.hw,
1043                 [CLKID_FCLK_DIV4]               = &axg_fclk_div4.hw,
1044                 [CLKID_FCLK_DIV5]               = &axg_fclk_div5.hw,
1045                 [CLKID_FCLK_DIV7]               = &axg_fclk_div7.hw,
1046                 [CLKID_GP0_PLL]                 = &axg_gp0_pll.hw,
1047                 [CLKID_MPEG_SEL]                = &axg_mpeg_clk_sel.hw,
1048                 [CLKID_MPEG_DIV]                = &axg_mpeg_clk_div.hw,
1049                 [CLKID_CLK81]                   = &axg_clk81.hw,
1050                 [CLKID_MPLL0]                   = &axg_mpll0.hw,
1051                 [CLKID_MPLL1]                   = &axg_mpll1.hw,
1052                 [CLKID_MPLL2]                   = &axg_mpll2.hw,
1053                 [CLKID_MPLL3]                   = &axg_mpll3.hw,
1054                 [CLKID_DDR]                     = &axg_ddr.hw,
1055                 [CLKID_AUDIO_LOCKER]            = &axg_audio_locker.hw,
1056                 [CLKID_MIPI_DSI_HOST]           = &axg_mipi_dsi_host.hw,
1057                 [CLKID_ISA]                     = &axg_isa.hw,
1058                 [CLKID_PL301]                   = &axg_pl301.hw,
1059                 [CLKID_PERIPHS]                 = &axg_periphs.hw,
1060                 [CLKID_SPICC0]                  = &axg_spicc_0.hw,
1061                 [CLKID_I2C]                     = &axg_i2c.hw,
1062                 [CLKID_RNG0]                    = &axg_rng0.hw,
1063                 [CLKID_UART0]                   = &axg_uart0.hw,
1064                 [CLKID_MIPI_DSI_PHY]            = &axg_mipi_dsi_phy.hw,
1065                 [CLKID_SPICC1]                  = &axg_spicc_1.hw,
1066                 [CLKID_PCIE_A]                  = &axg_pcie_a.hw,
1067                 [CLKID_PCIE_B]                  = &axg_pcie_b.hw,
1068                 [CLKID_HIU_IFACE]               = &axg_hiu_reg.hw,
1069                 [CLKID_ASSIST_MISC]             = &axg_assist_misc.hw,
1070                 [CLKID_SD_EMMC_B]               = &axg_emmc_b.hw,
1071                 [CLKID_SD_EMMC_C]               = &axg_emmc_c.hw,
1072                 [CLKID_DMA]                     = &axg_dma.hw,
1073                 [CLKID_SPI]                     = &axg_spi.hw,
1074                 [CLKID_AUDIO]                   = &axg_audio.hw,
1075                 [CLKID_ETH]                     = &axg_eth_core.hw,
1076                 [CLKID_UART1]                   = &axg_uart1.hw,
1077                 [CLKID_G2D]                     = &axg_g2d.hw,
1078                 [CLKID_USB0]                    = &axg_usb0.hw,
1079                 [CLKID_USB1]                    = &axg_usb1.hw,
1080                 [CLKID_RESET]                   = &axg_reset.hw,
1081                 [CLKID_USB]                     = &axg_usb_general.hw,
1082                 [CLKID_AHB_ARB0]                = &axg_ahb_arb0.hw,
1083                 [CLKID_EFUSE]                   = &axg_efuse.hw,
1084                 [CLKID_BOOT_ROM]                = &axg_boot_rom.hw,
1085                 [CLKID_AHB_DATA_BUS]            = &axg_ahb_data_bus.hw,
1086                 [CLKID_AHB_CTRL_BUS]            = &axg_ahb_ctrl_bus.hw,
1087                 [CLKID_USB1_DDR_BRIDGE]         = &axg_usb1_to_ddr.hw,
1088                 [CLKID_USB0_DDR_BRIDGE]         = &axg_usb0_to_ddr.hw,
1089                 [CLKID_MMC_PCLK]                = &axg_mmc_pclk.hw,
1090                 [CLKID_VPU_INTR]                = &axg_vpu_intr.hw,
1091                 [CLKID_SEC_AHB_AHB3_BRIDGE]     = &axg_sec_ahb_ahb3_bridge.hw,
1092                 [CLKID_GIC]                     = &axg_gic.hw,
1093                 [CLKID_AO_MEDIA_CPU]            = &axg_ao_media_cpu.hw,
1094                 [CLKID_AO_AHB_SRAM]             = &axg_ao_ahb_sram.hw,
1095                 [CLKID_AO_AHB_BUS]              = &axg_ao_ahb_bus.hw,
1096                 [CLKID_AO_IFACE]                = &axg_ao_iface.hw,
1097                 [CLKID_AO_I2C]                  = &axg_ao_i2c.hw,
1098                 [CLKID_SD_EMMC_B_CLK0_SEL]      = &axg_sd_emmc_b_clk0_sel.hw,
1099                 [CLKID_SD_EMMC_B_CLK0_DIV]      = &axg_sd_emmc_b_clk0_div.hw,
1100                 [CLKID_SD_EMMC_B_CLK0]          = &axg_sd_emmc_b_clk0.hw,
1101                 [CLKID_SD_EMMC_C_CLK0_SEL]      = &axg_sd_emmc_c_clk0_sel.hw,
1102                 [CLKID_SD_EMMC_C_CLK0_DIV]      = &axg_sd_emmc_c_clk0_div.hw,
1103                 [CLKID_SD_EMMC_C_CLK0]          = &axg_sd_emmc_c_clk0.hw,
1104                 [CLKID_MPLL0_DIV]               = &axg_mpll0_div.hw,
1105                 [CLKID_MPLL1_DIV]               = &axg_mpll1_div.hw,
1106                 [CLKID_MPLL2_DIV]               = &axg_mpll2_div.hw,
1107                 [CLKID_MPLL3_DIV]               = &axg_mpll3_div.hw,
1108                 [CLKID_HIFI_PLL]                = &axg_hifi_pll.hw,
1109                 [CLKID_MPLL_PREDIV]             = &axg_mpll_prediv.hw,
1110                 [CLKID_FCLK_DIV2_DIV]           = &axg_fclk_div2_div.hw,
1111                 [CLKID_FCLK_DIV3_DIV]           = &axg_fclk_div3_div.hw,
1112                 [CLKID_FCLK_DIV4_DIV]           = &axg_fclk_div4_div.hw,
1113                 [CLKID_FCLK_DIV5_DIV]           = &axg_fclk_div5_div.hw,
1114                 [CLKID_FCLK_DIV7_DIV]           = &axg_fclk_div7_div.hw,
1115                 [CLKID_PCIE_PLL]                = &axg_pcie_pll.hw,
1116                 [CLKID_PCIE_MUX]                = &axg_pcie_mux.hw,
1117                 [CLKID_PCIE_REF]                = &axg_pcie_ref.hw,
1118                 [CLKID_PCIE_CML_EN0]            = &axg_pcie_cml_en0.hw,
1119                 [CLKID_PCIE_CML_EN1]            = &axg_pcie_cml_en1.hw,
1120                 [CLKID_MIPI_ENABLE]             = &axg_mipi_enable.hw,
1121                 [CLKID_GEN_CLK_SEL]             = &axg_gen_clk_sel.hw,
1122                 [CLKID_GEN_CLK_DIV]             = &axg_gen_clk_div.hw,
1123                 [CLKID_GEN_CLK]                 = &axg_gen_clk.hw,
1124                 [NR_CLKS]                       = NULL,
1125         },
1126         .num = NR_CLKS,
1127 };
1128
1129 /* Convenience table to populate regmap in .probe */
1130 static struct clk_regmap *const axg_clk_regmaps[] = {
1131         &axg_clk81,
1132         &axg_ddr,
1133         &axg_audio_locker,
1134         &axg_mipi_dsi_host,
1135         &axg_isa,
1136         &axg_pl301,
1137         &axg_periphs,
1138         &axg_spicc_0,
1139         &axg_i2c,
1140         &axg_rng0,
1141         &axg_uart0,
1142         &axg_mipi_dsi_phy,
1143         &axg_spicc_1,
1144         &axg_pcie_a,
1145         &axg_pcie_b,
1146         &axg_hiu_reg,
1147         &axg_assist_misc,
1148         &axg_emmc_b,
1149         &axg_emmc_c,
1150         &axg_dma,
1151         &axg_spi,
1152         &axg_audio,
1153         &axg_eth_core,
1154         &axg_uart1,
1155         &axg_g2d,
1156         &axg_usb0,
1157         &axg_usb1,
1158         &axg_reset,
1159         &axg_usb_general,
1160         &axg_ahb_arb0,
1161         &axg_efuse,
1162         &axg_boot_rom,
1163         &axg_ahb_data_bus,
1164         &axg_ahb_ctrl_bus,
1165         &axg_usb1_to_ddr,
1166         &axg_usb0_to_ddr,
1167         &axg_mmc_pclk,
1168         &axg_vpu_intr,
1169         &axg_sec_ahb_ahb3_bridge,
1170         &axg_gic,
1171         &axg_ao_media_cpu,
1172         &axg_ao_ahb_sram,
1173         &axg_ao_ahb_bus,
1174         &axg_ao_iface,
1175         &axg_ao_i2c,
1176         &axg_sd_emmc_b_clk0,
1177         &axg_sd_emmc_c_clk0,
1178         &axg_mpeg_clk_div,
1179         &axg_sd_emmc_b_clk0_div,
1180         &axg_sd_emmc_c_clk0_div,
1181         &axg_mpeg_clk_sel,
1182         &axg_sd_emmc_b_clk0_sel,
1183         &axg_sd_emmc_c_clk0_sel,
1184         &axg_mpll0,
1185         &axg_mpll1,
1186         &axg_mpll2,
1187         &axg_mpll3,
1188         &axg_mpll0_div,
1189         &axg_mpll1_div,
1190         &axg_mpll2_div,
1191         &axg_mpll3_div,
1192         &axg_fixed_pll,
1193         &axg_sys_pll,
1194         &axg_gp0_pll,
1195         &axg_hifi_pll,
1196         &axg_mpll_prediv,
1197         &axg_fclk_div2,
1198         &axg_fclk_div3,
1199         &axg_fclk_div4,
1200         &axg_fclk_div5,
1201         &axg_fclk_div7,
1202         &axg_pcie_pll,
1203         &axg_pcie_mux,
1204         &axg_pcie_ref,
1205         &axg_pcie_cml_en0,
1206         &axg_pcie_cml_en1,
1207         &axg_mipi_enable,
1208         &axg_gen_clk_sel,
1209         &axg_gen_clk_div,
1210         &axg_gen_clk,
1211 };
1212
1213 static const struct of_device_id clkc_match_table[] = {
1214         { .compatible = "amlogic,axg-clkc" },
1215         {}
1216 };
1217
1218 static int axg_clkc_probe(struct platform_device *pdev)
1219 {
1220         struct device *dev = &pdev->dev;
1221         struct regmap *map;
1222         int ret, i;
1223
1224         /* Get the hhi system controller node if available */
1225         map = syscon_node_to_regmap(of_get_parent(dev->of_node));
1226         if (IS_ERR(map)) {
1227                 dev_err(dev, "failed to get HHI regmap\n");
1228                 return PTR_ERR(map);
1229         }
1230
1231         /* Populate regmap for the regmap backed clocks */
1232         for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
1233                 axg_clk_regmaps[i]->map = map;
1234
1235         for (i = 0; i < axg_hw_onecell_data.num; i++) {
1236                 /* array might be sparse */
1237                 if (!axg_hw_onecell_data.hws[i])
1238                         continue;
1239
1240                 ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]);
1241                 if (ret) {
1242                         dev_err(dev, "Clock registration failed\n");
1243                         return ret;
1244                 }
1245         }
1246
1247         return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1248                                            &axg_hw_onecell_data);
1249 }
1250
1251 static struct platform_driver axg_driver = {
1252         .probe          = axg_clkc_probe,
1253         .driver         = {
1254                 .name   = "axg-clkc",
1255                 .of_match_table = clkc_match_table,
1256         },
1257 };
1258
1259 builtin_platform_driver(axg_driver);