drivers/clk/meson/gxbb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016 AmLogic, Inc.
   4  * Michael Turquette <mturquette@baylibre.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/init.h>
  10 #include <linux/of_device.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regmap.h>
  14
  15 #include "clkc.h"
  16 #include "gxbb.h"
  17 #include "clk-regmap.h"
  18
  19 static DEFINE_SPINLOCK(meson_clk_lock);
  20
  21 static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = {
  22         PLL_RATE(96000000, 32, 1, 3),
  23         PLL_RATE(99000000, 33, 1, 3),
  24         PLL_RATE(102000000, 34, 1, 3),
  25         PLL_RATE(105000000, 35, 1, 3),
  26         PLL_RATE(108000000, 36, 1, 3),
  27         PLL_RATE(111000000, 37, 1, 3),
  28         PLL_RATE(114000000, 38, 1, 3),
  29         PLL_RATE(117000000, 39, 1, 3),
  30         PLL_RATE(120000000, 40, 1, 3),
  31         PLL_RATE(123000000, 41, 1, 3),
  32         PLL_RATE(126000000, 42, 1, 3),
  33         PLL_RATE(129000000, 43, 1, 3),
  34         PLL_RATE(132000000, 44, 1, 3),
  35         PLL_RATE(135000000, 45, 1, 3),
  36         PLL_RATE(138000000, 46, 1, 3),
  37         PLL_RATE(141000000, 47, 1, 3),
  38         PLL_RATE(144000000, 48, 1, 3),
  39         PLL_RATE(147000000, 49, 1, 3),
  40         PLL_RATE(150000000, 50, 1, 3),
  41         PLL_RATE(153000000, 51, 1, 3),
  42         PLL_RATE(156000000, 52, 1, 3),
  43         PLL_RATE(159000000, 53, 1, 3),
  44         PLL_RATE(162000000, 54, 1, 3),
  45         PLL_RATE(165000000, 55, 1, 3),
  46         PLL_RATE(168000000, 56, 1, 3),
  47         PLL_RATE(171000000, 57, 1, 3),
  48         PLL_RATE(174000000, 58, 1, 3),
  49         PLL_RATE(177000000, 59, 1, 3),
  50         PLL_RATE(180000000, 60, 1, 3),
  51         PLL_RATE(183000000, 61, 1, 3),
  52         PLL_RATE(186000000, 62, 1, 3),
  53         PLL_RATE(192000000, 32, 1, 2),
  54         PLL_RATE(198000000, 33, 1, 2),
  55         PLL_RATE(204000000, 34, 1, 2),
  56         PLL_RATE(210000000, 35, 1, 2),
  57         PLL_RATE(216000000, 36, 1, 2),
  58         PLL_RATE(222000000, 37, 1, 2),
  59         PLL_RATE(228000000, 38, 1, 2),
  60         PLL_RATE(234000000, 39, 1, 2),
  61         PLL_RATE(240000000, 40, 1, 2),
  62         PLL_RATE(246000000, 41, 1, 2),
  63         PLL_RATE(252000000, 42, 1, 2),
  64         PLL_RATE(258000000, 43, 1, 2),
  65         PLL_RATE(264000000, 44, 1, 2),
  66         PLL_RATE(270000000, 45, 1, 2),
  67         PLL_RATE(276000000, 46, 1, 2),
  68         PLL_RATE(282000000, 47, 1, 2),
  69         PLL_RATE(288000000, 48, 1, 2),
  70         PLL_RATE(294000000, 49, 1, 2),
  71         PLL_RATE(300000000, 50, 1, 2),
  72         PLL_RATE(306000000, 51, 1, 2),
  73         PLL_RATE(312000000, 52, 1, 2),
  74         PLL_RATE(318000000, 53, 1, 2),
  75         PLL_RATE(324000000, 54, 1, 2),
  76         PLL_RATE(330000000, 55, 1, 2),
  77         PLL_RATE(336000000, 56, 1, 2),
  78         PLL_RATE(342000000, 57, 1, 2),
  79         PLL_RATE(348000000, 58, 1, 2),
  80         PLL_RATE(354000000, 59, 1, 2),
  81         PLL_RATE(360000000, 60, 1, 2),
  82         PLL_RATE(366000000, 61, 1, 2),
  83         PLL_RATE(372000000, 62, 1, 2),
  84         PLL_RATE(384000000, 32, 1, 1),
  85         PLL_RATE(396000000, 33, 1, 1),
  86         PLL_RATE(408000000, 34, 1, 1),
  87         PLL_RATE(420000000, 35, 1, 1),
  88         PLL_RATE(432000000, 36, 1, 1),
  89         PLL_RATE(444000000, 37, 1, 1),
  90         PLL_RATE(456000000, 38, 1, 1),
  91         PLL_RATE(468000000, 39, 1, 1),
  92         PLL_RATE(480000000, 40, 1, 1),
  93         PLL_RATE(492000000, 41, 1, 1),
  94         PLL_RATE(504000000, 42, 1, 1),
  95         PLL_RATE(516000000, 43, 1, 1),
  96         PLL_RATE(528000000, 44, 1, 1),
  97         PLL_RATE(540000000, 45, 1, 1),
  98         PLL_RATE(552000000, 46, 1, 1),
  99         PLL_RATE(564000000, 47, 1, 1),
 100         PLL_RATE(576000000, 48, 1, 1),
 101         PLL_RATE(588000000, 49, 1, 1),
 102         PLL_RATE(600000000, 50, 1, 1),
 103         PLL_RATE(612000000, 51, 1, 1),
 104         PLL_RATE(624000000, 52, 1, 1),
 105         PLL_RATE(636000000, 53, 1, 1),
 106         PLL_RATE(648000000, 54, 1, 1),
 107         PLL_RATE(660000000, 55, 1, 1),
 108         PLL_RATE(672000000, 56, 1, 1),
 109         PLL_RATE(684000000, 57, 1, 1),
 110         PLL_RATE(696000000, 58, 1, 1),
 111         PLL_RATE(708000000, 59, 1, 1),
 112         PLL_RATE(720000000, 60, 1, 1),
 113         PLL_RATE(732000000, 61, 1, 1),
 114         PLL_RATE(744000000, 62, 1, 1),
 115         PLL_RATE(768000000, 32, 1, 0),
 116         PLL_RATE(792000000, 33, 1, 0),
 117         PLL_RATE(816000000, 34, 1, 0),
 118         PLL_RATE(840000000, 35, 1, 0),
 119         PLL_RATE(864000000, 36, 1, 0),
 120         PLL_RATE(888000000, 37, 1, 0),
 121         PLL_RATE(912000000, 38, 1, 0),
 122         PLL_RATE(936000000, 39, 1, 0),
 123         PLL_RATE(960000000, 40, 1, 0),
 124         PLL_RATE(984000000, 41, 1, 0),
 125         PLL_RATE(1008000000, 42, 1, 0),
 126         PLL_RATE(1032000000, 43, 1, 0),
 127         PLL_RATE(1056000000, 44, 1, 0),
 128         PLL_RATE(1080000000, 45, 1, 0),
 129         PLL_RATE(1104000000, 46, 1, 0),
 130         PLL_RATE(1128000000, 47, 1, 0),
 131         PLL_RATE(1152000000, 48, 1, 0),
 132         PLL_RATE(1176000000, 49, 1, 0),
 133         PLL_RATE(1200000000, 50, 1, 0),
 134         PLL_RATE(1224000000, 51, 1, 0),
 135         PLL_RATE(1248000000, 52, 1, 0),
 136         PLL_RATE(1272000000, 53, 1, 0),
 137         PLL_RATE(1296000000, 54, 1, 0),
 138         PLL_RATE(1320000000, 55, 1, 0),
 139         PLL_RATE(1344000000, 56, 1, 0),
 140         PLL_RATE(1368000000, 57, 1, 0),
 141         PLL_RATE(1392000000, 58, 1, 0),
 142         PLL_RATE(1416000000, 59, 1, 0),
 143         PLL_RATE(1440000000, 60, 1, 0),
 144         PLL_RATE(1464000000, 61, 1, 0),
 145         PLL_RATE(1488000000, 62, 1, 0),
 146         { /* sentinel */ },
 147 };
 148
 149 static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
 150         PLL_RATE(504000000, 42, 1, 1),
 151         PLL_RATE(516000000, 43, 1, 1),
 152         PLL_RATE(528000000, 44, 1, 1),
 153         PLL_RATE(540000000, 45, 1, 1),
 154         PLL_RATE(552000000, 46, 1, 1),
 155         PLL_RATE(564000000, 47, 1, 1),
 156         PLL_RATE(576000000, 48, 1, 1),
 157         PLL_RATE(588000000, 49, 1, 1),
 158         PLL_RATE(600000000, 50, 1, 1),
 159         PLL_RATE(612000000, 51, 1, 1),
 160         PLL_RATE(624000000, 52, 1, 1),
 161         PLL_RATE(636000000, 53, 1, 1),
 162         PLL_RATE(648000000, 54, 1, 1),
 163         PLL_RATE(660000000, 55, 1, 1),
 164         PLL_RATE(672000000, 56, 1, 1),
 165         PLL_RATE(684000000, 57, 1, 1),
 166         PLL_RATE(696000000, 58, 1, 1),
 167         PLL_RATE(708000000, 59, 1, 1),
 168         PLL_RATE(720000000, 60, 1, 1),
 169         PLL_RATE(732000000, 61, 1, 1),
 170         PLL_RATE(744000000, 62, 1, 1),
 171         PLL_RATE(756000000, 63, 1, 1),
 172         PLL_RATE(768000000, 64, 1, 1),
 173         PLL_RATE(780000000, 65, 1, 1),
 174         PLL_RATE(792000000, 66, 1, 1),
 175         { /* sentinel */ },
 176 };
 177
 178 static struct clk_regmap gxbb_fixed_pll = {
 179         .data = &(struct meson_clk_pll_data){
 180                 .m = {
 181                         .reg_off = HHI_MPLL_CNTL,
 182                         .shift   = 0,
 183                         .width   = 9,
 184                 },
 185                 .n = {
 186                         .reg_off = HHI_MPLL_CNTL,
 187                         .shift   = 9,
 188                         .width   = 5,
 189                 },
 190                 .od = {
 191                         .reg_off = HHI_MPLL_CNTL,
 192                         .shift   = 16,
 193                         .width   = 2,
 194                 },
 195                 .frac = {
 196                         .reg_off = HHI_MPLL_CNTL2,
 197                         .shift   = 0,
 198                         .width   = 12,
 199                 },
 200                 .l = {
 201                         .reg_off = HHI_MPLL_CNTL,
 202                         .shift   = 31,
 203                         .width   = 1,
 204                 },
 205                 .rst = {
 206                         .reg_off = HHI_MPLL_CNTL,
 207                         .shift   = 29,
 208                         .width   = 1,
 209                 },
 210         },
 211         .hw.init = &(struct clk_init_data){
 212                 .name = "fixed_pll",
 213                 .ops = &meson_clk_pll_ro_ops,
 214                 .parent_names = (const char *[]){ "xtal" },
 215                 .num_parents = 1,
 216         },
 217 };
 218
 219 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
 220         .mult = 2,
 221         .div = 1,
 222         .hw.init = &(struct clk_init_data){
 223                 .name = "hdmi_pll_pre_mult",
 224                 .ops = &clk_fixed_factor_ops,
 225                 .parent_names = (const char *[]){ "xtal" },
 226                 .num_parents = 1,
 227         },
 228 };
 229
 230 static struct clk_regmap gxbb_hdmi_pll = {
 231         .data = &(struct meson_clk_pll_data){
 232                 .m = {
 233                         .reg_off = HHI_HDMI_PLL_CNTL,
 234                         .shift   = 0,
 235                         .width   = 9,
 236                 },
 237                 .n = {
 238                         .reg_off = HHI_HDMI_PLL_CNTL,
 239                         .shift   = 9,
 240                         .width   = 5,
 241                 },
 242                 .frac = {
 243                         .reg_off = HHI_HDMI_PLL_CNTL2,
 244                         .shift   = 0,
 245                         .width   = 12,
 246                 },
 247                 .od = {
 248                         .reg_off = HHI_HDMI_PLL_CNTL2,
 249                         .shift   = 16,
 250                         .width   = 2,
 251                 },
 252                 .od2 = {
 253                         .reg_off = HHI_HDMI_PLL_CNTL2,
 254                         .shift   = 22,
 255                         .width   = 2,
 256                 },
 257                 .od3 = {
 258                         .reg_off = HHI_HDMI_PLL_CNTL2,
 259                         .shift   = 18,
 260                         .width   = 2,
 261                 },
 262                 .l = {
 263                         .reg_off = HHI_HDMI_PLL_CNTL,
 264                         .shift   = 31,
 265                         .width   = 1,
 266                 },
 267                 .rst = {
 268                         .reg_off = HHI_HDMI_PLL_CNTL,
 269                         .shift   = 28,
 270                         .width   = 1,
 271                 },
 272         },
 273         .hw.init = &(struct clk_init_data){
 274                 .name = "hdmi_pll",
 275                 .ops = &meson_clk_pll_ro_ops,
 276                 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
 277                 .num_parents = 1,
 278                 /*
 279                  * Display directly handle hdmi pll registers ATM, we need
 280                  * NOCACHE to keep our view of the clock as accurate as possible
 281                  */
 282                 .flags = CLK_GET_RATE_NOCACHE,
 283         },
 284 };
 285
 286 static struct clk_regmap gxl_hdmi_pll = {
 287         .data = &(struct meson_clk_pll_data){
 288                 .m = {
 289                         .reg_off = HHI_HDMI_PLL_CNTL,
 290                         .shift   = 0,
 291                         .width   = 9,
 292                 },
 293                 .n = {
 294                         .reg_off = HHI_HDMI_PLL_CNTL,
 295                         .shift   = 9,
 296                         .width   = 5,
 297                 },
 298                 /*
 299                  * On gxl, there is a register shift due to
 300                  * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
 301                  * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
 302                  * instead which is defined at the same offset.
 303                  */
 304                 .frac = {
 305                         /*
 306                          * On gxl, there is a register shift due to
 307                          * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
 308                          * so we compute the register offset based on the PLL
 309                          * base to get it right
 310                          */
 311                         .reg_off = HHI_HDMI_PLL_CNTL + 4,
 312                         .shift   = 0,
 313                         .width   = 10,
 314                 },
 315                 .od = {
 316                         .reg_off = HHI_HDMI_PLL_CNTL + 8,
 317                         .shift   = 21,
 318                         .width   = 2,
 319                 },
 320                 .od2 = {
 321                         .reg_off = HHI_HDMI_PLL_CNTL + 8,
 322                         .shift   = 23,
 323                         .width   = 2,
 324                 },
 325                 .od3 = {
 326                         .reg_off = HHI_HDMI_PLL_CNTL + 8,
 327                         .shift   = 19,
 328                         .width   = 2,
 329                 },
 330                 .l = {
 331                         .reg_off = HHI_HDMI_PLL_CNTL,
 332                         .shift   = 31,
 333                         .width   = 1,
 334                 },
 335                 .rst = {
 336                         .reg_off = HHI_HDMI_PLL_CNTL,
 337                         .shift   = 29,
 338                         .width   = 1,
 339                 },
 340         },
 341         .hw.init = &(struct clk_init_data){
 342                 .name = "hdmi_pll",
 343                 .ops = &meson_clk_pll_ro_ops,
 344                 .parent_names = (const char *[]){ "xtal" },
 345                 .num_parents = 1,
 346                 /*
 347                  * Display directly handle hdmi pll registers ATM, we need
 348                  * NOCACHE to keep our view of the clock as accurate as possible
 349                  */
 350                 .flags = CLK_GET_RATE_NOCACHE,
 351         },
 352 };
 353
 354 static struct clk_regmap gxbb_sys_pll = {
 355         .data = &(struct meson_clk_pll_data){
 356                 .m = {
 357                         .reg_off = HHI_SYS_PLL_CNTL,
 358                         .shift   = 0,
 359                         .width   = 9,
 360                 },
 361                 .n = {
 362                         .reg_off = HHI_SYS_PLL_CNTL,
 363                         .shift   = 9,
 364                         .width   = 5,
 365                 },
 366                 .od = {
 367                         .reg_off = HHI_SYS_PLL_CNTL,
 368                         .shift   = 10,
 369                         .width   = 2,
 370                 },
 371                 .l = {
 372                         .reg_off = HHI_SYS_PLL_CNTL,
 373                         .shift   = 31,
 374                         .width   = 1,
 375                 },
 376                 .rst = {
 377                         .reg_off = HHI_SYS_PLL_CNTL,
 378                         .shift   = 29,
 379                         .width   = 1,
 380                 },
 381         },
 382         .hw.init = &(struct clk_init_data){
 383                 .name = "sys_pll",
 384                 .ops = &meson_clk_pll_ro_ops,
 385                 .parent_names = (const char *[]){ "xtal" },
 386                 .num_parents = 1,
 387         },
 388 };
 389
 390 static const struct reg_sequence gxbb_gp0_init_regs[] = {
 391         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x69c80000 },
 392         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a5590c4 },
 393         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x0000500d },
 394         { .reg = HHI_GP0_PLL_CNTL,      .def = 0x4a000228 },
 395 };
 396
 397 static struct clk_regmap gxbb_gp0_pll = {
 398         .data = &(struct meson_clk_pll_data){
 399                 .m = {
 400                         .reg_off = HHI_GP0_PLL_CNTL,
 401                         .shift   = 0,
 402                         .width   = 9,
 403                 },
 404                 .n = {
 405                         .reg_off = HHI_GP0_PLL_CNTL,
 406                         .shift   = 9,
 407                         .width   = 5,
 408                 },
 409                 .od = {
 410                         .reg_off = HHI_GP0_PLL_CNTL,
 411                         .shift   = 16,
 412                         .width   = 2,
 413                 },
 414                 .l = {
 415                         .reg_off = HHI_GP0_PLL_CNTL,
 416                         .shift   = 31,
 417                         .width   = 1,
 418                 },
 419                 .rst = {
 420                         .reg_off = HHI_GP0_PLL_CNTL,
 421                         .shift   = 29,
 422                         .width   = 1,
 423                 },
 424                 .table = gxbb_gp0_pll_rate_table,
 425                 .init_regs = gxbb_gp0_init_regs,
 426                 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
 427         },
 428         .hw.init = &(struct clk_init_data){
 429                 .name = "gp0_pll",
 430                 .ops = &meson_clk_pll_ops,
 431                 .parent_names = (const char *[]){ "xtal" },
 432                 .num_parents = 1,
 433         },
 434 };
 435
 436 static const struct reg_sequence gxl_gp0_init_regs[] = {
 437         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084b000 },
 438         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 439         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 440         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 441         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 442         { .reg = HHI_GP0_PLL_CNTL,      .def = 0x40010250 },
 443 };
 444
 445 static struct clk_regmap gxl_gp0_pll = {
 446         .data = &(struct meson_clk_pll_data){
 447                 .m = {
 448                         .reg_off = HHI_GP0_PLL_CNTL,
 449                         .shift   = 0,
 450                         .width   = 9,
 451                 },
 452                 .n = {
 453                         .reg_off = HHI_GP0_PLL_CNTL,
 454                         .shift   = 9,
 455                         .width   = 5,
 456                 },
 457                 .od = {
 458                         .reg_off = HHI_GP0_PLL_CNTL,
 459                         .shift   = 16,
 460                         .width   = 2,
 461                 },
 462                 .frac = {
 463                         .reg_off = HHI_GP0_PLL_CNTL1,
 464                         .shift   = 0,
 465                         .width   = 10,
 466                 },
 467                 .l = {
 468                         .reg_off = HHI_GP0_PLL_CNTL,
 469                         .shift   = 31,
 470                         .width   = 1,
 471                 },
 472                 .rst = {
 473                         .reg_off = HHI_GP0_PLL_CNTL,
 474                         .shift   = 29,
 475                         .width   = 1,
 476                 },
 477                 .table = gxl_gp0_pll_rate_table,
 478                 .init_regs = gxl_gp0_init_regs,
 479                 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
 480         },
 481         .hw.init = &(struct clk_init_data){
 482                 .name = "gp0_pll",
 483                 .ops = &meson_clk_pll_ops,
 484                 .parent_names = (const char *[]){ "xtal" },
 485                 .num_parents = 1,
 486         },
 487 };
 488
 489 static struct clk_fixed_factor gxbb_fclk_div2_div = {
 490         .mult = 1,
 491         .div = 2,
 492         .hw.init = &(struct clk_init_data){
 493                 .name = "fclk_div2_div",
 494                 .ops = &clk_fixed_factor_ops,
 495                 .parent_names = (const char *[]){ "fixed_pll" },
 496                 .num_parents = 1,
 497         },
 498 };
 499
 500 static struct clk_regmap gxbb_fclk_div2 = {
 501         .data = &(struct clk_regmap_gate_data){
 502                 .offset = HHI_MPLL_CNTL6,
 503                 .bit_idx = 27,
 504         },
 505         .hw.init = &(struct clk_init_data){
 506                 .name = "fclk_div2",
 507                 .ops = &clk_regmap_gate_ops,
 508                 .parent_names = (const char *[]){ "fclk_div2_div" },
 509                 .num_parents = 1,
 510                 .flags = CLK_IS_CRITICAL,
 511         },
 512 };
 513
 514 static struct clk_fixed_factor gxbb_fclk_div3_div = {
 515         .mult = 1,
 516         .div = 3,
 517         .hw.init = &(struct clk_init_data){
 518                 .name = "fclk_div3_div",
 519                 .ops = &clk_fixed_factor_ops,
 520                 .parent_names = (const char *[]){ "fixed_pll" },
 521                 .num_parents = 1,
 522         },
 523 };
 524
 525 static struct clk_regmap gxbb_fclk_div3 = {
 526         .data = &(struct clk_regmap_gate_data){
 527                 .offset = HHI_MPLL_CNTL6,
 528                 .bit_idx = 28,
 529         },
 530         .hw.init = &(struct clk_init_data){
 531                 .name = "fclk_div3",
 532                 .ops = &clk_regmap_gate_ops,
 533                 .parent_names = (const char *[]){ "fclk_div3_div" },
 534                 .num_parents = 1,
 535                 /*
 536                  * FIXME:
 537                  * This clock, as fdiv2, is used by the SCPI FW and is required
 538                  * by the platform to operate correctly.
 539                  * Until the following condition are met, we need this clock to
 540                  * be marked as critical:
 541                  * a) The SCPI generic driver claims and enable all the clocks
 542                  *    it needs
 543                  * b) CCF has a clock hand-off mechanism to make the sure the
 544                  *    clock stays on until the proper driver comes along
 545                  */
 546                 .flags = CLK_IS_CRITICAL,
 547         },
 548 };
 549
 550 static struct clk_fixed_factor gxbb_fclk_div4_div = {
 551         .mult = 1,
 552         .div = 4,
 553         .hw.init = &(struct clk_init_data){
 554                 .name = "fclk_div4_div",
 555                 .ops = &clk_fixed_factor_ops,
 556                 .parent_names = (const char *[]){ "fixed_pll" },
 557                 .num_parents = 1,
 558         },
 559 };
 560
 561 static struct clk_regmap gxbb_fclk_div4 = {
 562         .data = &(struct clk_regmap_gate_data){
 563                 .offset = HHI_MPLL_CNTL6,
 564                 .bit_idx = 29,
 565         },
 566         .hw.init = &(struct clk_init_data){
 567                 .name = "fclk_div4",
 568                 .ops = &clk_regmap_gate_ops,
 569                 .parent_names = (const char *[]){ "fclk_div4_div" },
 570                 .num_parents = 1,
 571         },
 572 };
 573
 574 static struct clk_fixed_factor gxbb_fclk_div5_div = {
 575         .mult = 1,
 576         .div = 5,
 577         .hw.init = &(struct clk_init_data){
 578                 .name = "fclk_div5_div",
 579                 .ops = &clk_fixed_factor_ops,
 580                 .parent_names = (const char *[]){ "fixed_pll" },
 581                 .num_parents = 1,
 582         },
 583 };
 584
 585 static struct clk_regmap gxbb_fclk_div5 = {
 586         .data = &(struct clk_regmap_gate_data){
 587                 .offset = HHI_MPLL_CNTL6,
 588                 .bit_idx = 30,
 589         },
 590         .hw.init = &(struct clk_init_data){
 591                 .name = "fclk_div5",
 592                 .ops = &clk_regmap_gate_ops,
 593                 .parent_names = (const char *[]){ "fclk_div5_div" },
 594                 .num_parents = 1,
 595         },
 596 };
 597
 598 static struct clk_fixed_factor gxbb_fclk_div7_div = {
 599         .mult = 1,
 600         .div = 7,
 601         .hw.init = &(struct clk_init_data){
 602                 .name = "fclk_div7_div",
 603                 .ops = &clk_fixed_factor_ops,
 604                 .parent_names = (const char *[]){ "fixed_pll" },
 605                 .num_parents = 1,
 606         },
 607 };
 608
 609 static struct clk_regmap gxbb_fclk_div7 = {
 610         .data = &(struct clk_regmap_gate_data){
 611                 .offset = HHI_MPLL_CNTL6,
 612                 .bit_idx = 31,
 613         },
 614         .hw.init = &(struct clk_init_data){
 615                 .name = "fclk_div7",
 616                 .ops = &clk_regmap_gate_ops,
 617                 .parent_names = (const char *[]){ "fclk_div7_div" },
 618                 .num_parents = 1,
 619         },
 620 };
 621
 622 static struct clk_regmap gxbb_mpll_prediv = {
 623         .data = &(struct clk_regmap_div_data){
 624                 .offset = HHI_MPLL_CNTL5,
 625                 .shift = 12,
 626                 .width = 1,
 627         },
 628         .hw.init = &(struct clk_init_data){
 629                 .name = "mpll_prediv",
 630                 .ops = &clk_regmap_divider_ro_ops,
 631                 .parent_names = (const char *[]){ "fixed_pll" },
 632                 .num_parents = 1,
 633         },
 634 };
 635
 636 static struct clk_regmap gxbb_mpll0_div = {
 637         .data = &(struct meson_clk_mpll_data){
 638                 .sdm = {
 639                         .reg_off = HHI_MPLL_CNTL7,
 640                         .shift   = 0,
 641                         .width   = 14,
 642                 },
 643                 .sdm_en = {
 644                         .reg_off = HHI_MPLL_CNTL7,
 645                         .shift   = 15,
 646                         .width   = 1,
 647                 },
 648                 .n2 = {
 649                         .reg_off = HHI_MPLL_CNTL7,
 650                         .shift   = 16,
 651                         .width   = 9,
 652                 },
 653                 .lock = &meson_clk_lock,
 654         },
 655         .hw.init = &(struct clk_init_data){
 656                 .name = "mpll0_div",
 657                 .ops = &meson_clk_mpll_ops,
 658                 .parent_names = (const char *[]){ "mpll_prediv" },
 659                 .num_parents = 1,
 660         },
 661 };
 662
 663 static struct clk_regmap gxbb_mpll0 = {
 664         .data = &(struct clk_regmap_gate_data){
 665                 .offset = HHI_MPLL_CNTL7,
 666                 .bit_idx = 14,
 667         },
 668         .hw.init = &(struct clk_init_data){
 669                 .name = "mpll0",
 670                 .ops = &clk_regmap_gate_ops,
 671                 .parent_names = (const char *[]){ "mpll0_div" },
 672                 .num_parents = 1,
 673                 .flags = CLK_SET_RATE_PARENT,
 674         },
 675 };
 676
 677 static struct clk_regmap gxbb_mpll1_div = {
 678         .data = &(struct meson_clk_mpll_data){
 679                 .sdm = {
 680                         .reg_off = HHI_MPLL_CNTL8,
 681                         .shift   = 0,
 682                         .width   = 14,
 683                 },
 684                 .sdm_en = {
 685                         .reg_off = HHI_MPLL_CNTL8,
 686                         .shift   = 15,
 687                         .width   = 1,
 688                 },
 689                 .n2 = {
 690                         .reg_off = HHI_MPLL_CNTL8,
 691                         .shift   = 16,
 692                         .width   = 9,
 693                 },
 694                 .lock = &meson_clk_lock,
 695         },
 696         .hw.init = &(struct clk_init_data){
 697                 .name = "mpll1_div",
 698                 .ops = &meson_clk_mpll_ops,
 699                 .parent_names = (const char *[]){ "mpll_prediv" },
 700                 .num_parents = 1,
 701         },
 702 };
 703
 704 static struct clk_regmap gxbb_mpll1 = {
 705         .data = &(struct clk_regmap_gate_data){
 706                 .offset = HHI_MPLL_CNTL8,
 707                 .bit_idx = 14,
 708         },
 709         .hw.init = &(struct clk_init_data){
 710                 .name = "mpll1",
 711                 .ops = &clk_regmap_gate_ops,
 712                 .parent_names = (const char *[]){ "mpll1_div" },
 713                 .num_parents = 1,
 714                 .flags = CLK_SET_RATE_PARENT,
 715         },
 716 };
 717
 718 static struct clk_regmap gxbb_mpll2_div = {
 719         .data = &(struct meson_clk_mpll_data){
 720                 .sdm = {
 721                         .reg_off = HHI_MPLL_CNTL9,
 722                         .shift   = 0,
 723                         .width   = 14,
 724                 },
 725                 .sdm_en = {
 726                         .reg_off = HHI_MPLL_CNTL9,
 727                         .shift   = 15,
 728                         .width   = 1,
 729                 },
 730                 .n2 = {
 731                         .reg_off = HHI_MPLL_CNTL9,
 732                         .shift   = 16,
 733                         .width   = 9,
 734                 },
 735                 .lock = &meson_clk_lock,
 736         },
 737         .hw.init = &(struct clk_init_data){
 738                 .name = "mpll2_div",
 739                 .ops = &meson_clk_mpll_ops,
 740                 .parent_names = (const char *[]){ "mpll_prediv" },
 741                 .num_parents = 1,
 742         },
 743 };
 744
 745 static struct clk_regmap gxbb_mpll2 = {
 746         .data = &(struct clk_regmap_gate_data){
 747                 .offset = HHI_MPLL_CNTL9,
 748                 .bit_idx = 14,
 749         },
 750         .hw.init = &(struct clk_init_data){
 751                 .name = "mpll2",
 752                 .ops = &clk_regmap_gate_ops,
 753                 .parent_names = (const char *[]){ "mpll2_div" },
 754                 .num_parents = 1,
 755                 .flags = CLK_SET_RATE_PARENT,
 756         },
 757 };
 758
 759 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 760 static const char * const clk81_parent_names[] = {
 761         "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
 762         "fclk_div3", "fclk_div5"
 763 };
 764
 765 static struct clk_regmap gxbb_mpeg_clk_sel = {
 766         .data = &(struct clk_regmap_mux_data){
 767                 .offset = HHI_MPEG_CLK_CNTL,
 768                 .mask = 0x7,
 769                 .shift = 12,
 770                 .table = mux_table_clk81,
 771         },
 772         .hw.init = &(struct clk_init_data){
 773                 .name = "mpeg_clk_sel",
 774                 .ops = &clk_regmap_mux_ro_ops,
 775                 /*
 776                  * bits 14:12 selects from 8 possible parents:
 777                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 778                  * fclk_div4, fclk_div3, fclk_div5
 779                  */
 780                 .parent_names = clk81_parent_names,
 781                 .num_parents = ARRAY_SIZE(clk81_parent_names),
 782         },
 783 };
 784
 785 static struct clk_regmap gxbb_mpeg_clk_div = {
 786         .data = &(struct clk_regmap_div_data){
 787                 .offset = HHI_MPEG_CLK_CNTL,
 788                 .shift = 0,
 789                 .width = 7,
 790         },
 791         .hw.init = &(struct clk_init_data){
 792                 .name = "mpeg_clk_div",
 793                 .ops = &clk_regmap_divider_ro_ops,
 794                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 795                 .num_parents = 1,
 796         },
 797 };
 798
 799 /* the mother of dragons gates */
 800 static struct clk_regmap gxbb_clk81 = {
 801         .data = &(struct clk_regmap_gate_data){
 802                 .offset = HHI_MPEG_CLK_CNTL,
 803                 .bit_idx = 7,
 804         },
 805         .hw.init = &(struct clk_init_data){
 806                 .name = "clk81",
 807                 .ops = &clk_regmap_gate_ops,
 808                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 809                 .num_parents = 1,
 810                 .flags = CLK_IS_CRITICAL,
 811         },
 812 };
 813
 814 static struct clk_regmap gxbb_sar_adc_clk_sel = {
 815         .data = &(struct clk_regmap_mux_data){
 816                 .offset = HHI_SAR_CLK_CNTL,
 817                 .mask = 0x3,
 818                 .shift = 9,
 819         },
 820         .hw.init = &(struct clk_init_data){
 821                 .name = "sar_adc_clk_sel",
 822                 .ops = &clk_regmap_mux_ops,
 823                 /* NOTE: The datasheet doesn't list the parents for bit 10 */
 824                 .parent_names = (const char *[]){ "xtal", "clk81", },
 825                 .num_parents = 2,
 826         },
 827 };
 828
 829 static struct clk_regmap gxbb_sar_adc_clk_div = {
 830         .data = &(struct clk_regmap_div_data){
 831                 .offset = HHI_SAR_CLK_CNTL,
 832                 .shift = 0,
 833                 .width = 8,
 834         },
 835         .hw.init = &(struct clk_init_data){
 836                 .name = "sar_adc_clk_div",
 837                 .ops = &clk_regmap_divider_ops,
 838                 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
 839                 .num_parents = 1,
 840                 .flags = CLK_SET_RATE_PARENT,
 841         },
 842 };
 843
 844 static struct clk_regmap gxbb_sar_adc_clk = {
 845         .data = &(struct clk_regmap_gate_data){
 846                 .offset = HHI_SAR_CLK_CNTL,
 847                 .bit_idx = 8,
 848         },
 849         .hw.init = &(struct clk_init_data){
 850                 .name = "sar_adc_clk",
 851                 .ops = &clk_regmap_gate_ops,
 852                 .parent_names = (const char *[]){ "sar_adc_clk_div" },
 853                 .num_parents = 1,
 854                 .flags = CLK_SET_RATE_PARENT,
 855         },
 856 };
 857
 858 /*
 859  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
 860  * muxed by a glitch-free switch.
 861  */
 862
 863 static const char * const gxbb_mali_0_1_parent_names[] = {
 864         "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
 865         "fclk_div4", "fclk_div3", "fclk_div5"
 866 };
 867
 868 static struct clk_regmap gxbb_mali_0_sel = {
 869         .data = &(struct clk_regmap_mux_data){
 870                 .offset = HHI_MALI_CLK_CNTL,
 871                 .mask = 0x7,
 872                 .shift = 9,
 873         },
 874         .hw.init = &(struct clk_init_data){
 875                 .name = "mali_0_sel",
 876                 .ops = &clk_regmap_mux_ops,
 877                 /*
 878                  * bits 10:9 selects from 8 possible parents:
 879                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
 880                  * fclk_div4, fclk_div3, fclk_div5
 881                  */
 882                 .parent_names = gxbb_mali_0_1_parent_names,
 883                 .num_parents = 8,
 884                 .flags = CLK_SET_RATE_NO_REPARENT,
 885         },
 886 };
 887
 888 static struct clk_regmap gxbb_mali_0_div = {
 889         .data = &(struct clk_regmap_div_data){
 890                 .offset = HHI_MALI_CLK_CNTL,
 891                 .shift = 0,
 892                 .width = 7,
 893         },
 894         .hw.init = &(struct clk_init_data){
 895                 .name = "mali_0_div",
 896                 .ops = &clk_regmap_divider_ops,
 897                 .parent_names = (const char *[]){ "mali_0_sel" },
 898                 .num_parents = 1,
 899                 .flags = CLK_SET_RATE_NO_REPARENT,
 900         },
 901 };
 902
 903 static struct clk_regmap gxbb_mali_0 = {
 904         .data = &(struct clk_regmap_gate_data){
 905                 .offset = HHI_MALI_CLK_CNTL,
 906                 .bit_idx = 8,
 907         },
 908         .hw.init = &(struct clk_init_data){
 909                 .name = "mali_0",
 910                 .ops = &clk_regmap_gate_ops,
 911                 .parent_names = (const char *[]){ "mali_0_div" },
 912                 .num_parents = 1,
 913                 .flags = CLK_SET_RATE_PARENT,
 914         },
 915 };
 916
 917 static struct clk_regmap gxbb_mali_1_sel = {
 918         .data = &(struct clk_regmap_mux_data){
 919                 .offset = HHI_MALI_CLK_CNTL,
 920                 .mask = 0x7,
 921                 .shift = 25,
 922         },
 923         .hw.init = &(struct clk_init_data){
 924                 .name = "mali_1_sel",
 925                 .ops = &clk_regmap_mux_ops,
 926                 /*
 927                  * bits 10:9 selects from 8 possible parents:
 928                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
 929                  * fclk_div4, fclk_div3, fclk_div5
 930                  */
 931                 .parent_names = gxbb_mali_0_1_parent_names,
 932                 .num_parents = 8,
 933                 .flags = CLK_SET_RATE_NO_REPARENT,
 934         },
 935 };
 936
 937 static struct clk_regmap gxbb_mali_1_div = {
 938         .data = &(struct clk_regmap_div_data){
 939                 .offset = HHI_MALI_CLK_CNTL,
 940                 .shift = 16,
 941                 .width = 7,
 942         },
 943         .hw.init = &(struct clk_init_data){
 944                 .name = "mali_1_div",
 945                 .ops = &clk_regmap_divider_ops,
 946                 .parent_names = (const char *[]){ "mali_1_sel" },
 947                 .num_parents = 1,
 948                 .flags = CLK_SET_RATE_NO_REPARENT,
 949         },
 950 };
 951
 952 static struct clk_regmap gxbb_mali_1 = {
 953         .data = &(struct clk_regmap_gate_data){
 954                 .offset = HHI_MALI_CLK_CNTL,
 955                 .bit_idx = 24,
 956         },
 957         .hw.init = &(struct clk_init_data){
 958                 .name = "mali_1",
 959                 .ops = &clk_regmap_gate_ops,
 960                 .parent_names = (const char *[]){ "mali_1_div" },
 961                 .num_parents = 1,
 962                 .flags = CLK_SET_RATE_PARENT,
 963         },
 964 };
 965
 966 static const char * const gxbb_mali_parent_names[] = {
 967         "mali_0", "mali_1"
 968 };
 969
 970 static struct clk_regmap gxbb_mali = {
 971         .data = &(struct clk_regmap_mux_data){
 972                 .offset = HHI_MALI_CLK_CNTL,
 973                 .mask = 1,
 974                 .shift = 31,
 975         },
 976         .hw.init = &(struct clk_init_data){
 977                 .name = "mali",
 978                 .ops = &clk_regmap_mux_ops,
 979                 .parent_names = gxbb_mali_parent_names,
 980                 .num_parents = 2,
 981                 .flags = CLK_SET_RATE_NO_REPARENT,
 982         },
 983 };
 984
 985 static struct clk_regmap gxbb_cts_amclk_sel = {
 986         .data = &(struct clk_regmap_mux_data){
 987                 .offset = HHI_AUD_CLK_CNTL,
 988                 .mask = 0x3,
 989                 .shift = 9,
 990                 .table = (u32[]){ 1, 2, 3 },
 991                 .flags = CLK_MUX_ROUND_CLOSEST,
 992         },
 993         .hw.init = &(struct clk_init_data){
 994                 .name = "cts_amclk_sel",
 995                 .ops = &clk_regmap_mux_ops,
 996                 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
 997                 .num_parents = 3,
 998         },
 999 };
1000
1001 static struct clk_regmap gxbb_cts_amclk_div = {
1002         .data = &(struct clk_regmap_div_data) {
1003                 .offset = HHI_AUD_CLK_CNTL,
1004                 .shift = 0,
1005                 .width = 8,
1006                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1007         },
1008         .hw.init = &(struct clk_init_data){
1009                 .name = "cts_amclk_div",
1010                 .ops = &clk_regmap_divider_ops,
1011                 .parent_names = (const char *[]){ "cts_amclk_sel" },
1012                 .num_parents = 1,
1013                 .flags = CLK_SET_RATE_PARENT,
1014         },
1015 };
1016
1017 static struct clk_regmap gxbb_cts_amclk = {
1018         .data = &(struct clk_regmap_gate_data){
1019                 .offset = HHI_AUD_CLK_CNTL,
1020                 .bit_idx = 8,
1021         },
1022         .hw.init = &(struct clk_init_data){
1023                 .name = "cts_amclk",
1024                 .ops = &clk_regmap_gate_ops,
1025                 .parent_names = (const char *[]){ "cts_amclk_div" },
1026                 .num_parents = 1,
1027                 .flags = CLK_SET_RATE_PARENT,
1028         },
1029 };
1030
1031 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1032         .data = &(struct clk_regmap_mux_data){
1033                 .offset = HHI_AUD_CLK_CNTL2,
1034                 .mask = 0x3,
1035                 .shift = 25,
1036                 .table = (u32[]){ 1, 2, 3 },
1037                 .flags = CLK_MUX_ROUND_CLOSEST,
1038         },
1039         .hw.init = &(struct clk_init_data) {
1040                 .name = "cts_mclk_i958_sel",
1041                 .ops = &clk_regmap_mux_ops,
1042                 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
1043                 .num_parents = 3,
1044         },
1045 };
1046
1047 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1048         .data = &(struct clk_regmap_div_data){
1049                 .offset = HHI_AUD_CLK_CNTL2,
1050                 .shift = 16,
1051                 .width = 8,
1052                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1053         },
1054         .hw.init = &(struct clk_init_data) {
1055                 .name = "cts_mclk_i958_div",
1056                 .ops = &clk_regmap_divider_ops,
1057                 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
1058                 .num_parents = 1,
1059                 .flags = CLK_SET_RATE_PARENT,
1060         },
1061 };
1062
1063 static struct clk_regmap gxbb_cts_mclk_i958 = {
1064         .data = &(struct clk_regmap_gate_data){
1065                 .offset = HHI_AUD_CLK_CNTL2,
1066                 .bit_idx = 24,
1067         },
1068         .hw.init = &(struct clk_init_data){
1069                 .name = "cts_mclk_i958",
1070                 .ops = &clk_regmap_gate_ops,
1071                 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
1072                 .num_parents = 1,
1073                 .flags = CLK_SET_RATE_PARENT,
1074         },
1075 };
1076
1077 static struct clk_regmap gxbb_cts_i958 = {
1078         .data = &(struct clk_regmap_mux_data){
1079                 .offset = HHI_AUD_CLK_CNTL2,
1080                 .mask = 0x1,
1081                 .shift = 27,
1082                 },
1083         .hw.init = &(struct clk_init_data){
1084                 .name = "cts_i958",
1085                 .ops = &clk_regmap_mux_ops,
1086                 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
1087                 .num_parents = 2,
1088                 /*
1089                  *The parent is specific to origin of the audio data. Let the
1090                  * consumer choose the appropriate parent
1091                  */
1092                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1093         },
1094 };
1095
1096 static struct clk_regmap gxbb_32k_clk_div = {
1097         .data = &(struct clk_regmap_div_data){
1098                 .offset = HHI_32K_CLK_CNTL,
1099                 .shift = 0,
1100                 .width = 14,
1101         },
1102         .hw.init = &(struct clk_init_data){
1103                 .name = "32k_clk_div",
1104                 .ops = &clk_regmap_divider_ops,
1105                 .parent_names = (const char *[]){ "32k_clk_sel" },
1106                 .num_parents = 1,
1107                 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1108         },
1109 };
1110
1111 static struct clk_regmap gxbb_32k_clk = {
1112         .data = &(struct clk_regmap_gate_data){
1113                 .offset = HHI_32K_CLK_CNTL,
1114                 .bit_idx = 15,
1115         },
1116         .hw.init = &(struct clk_init_data){
1117                 .name = "32k_clk",
1118                 .ops = &clk_regmap_gate_ops,
1119                 .parent_names = (const char *[]){ "32k_clk_div" },
1120                 .num_parents = 1,
1121                 .flags = CLK_SET_RATE_PARENT,
1122         },
1123 };
1124
1125 static const char * const gxbb_32k_clk_parent_names[] = {
1126         "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1127 };
1128
1129 static struct clk_regmap gxbb_32k_clk_sel = {
1130         .data = &(struct clk_regmap_mux_data){
1131                 .offset = HHI_32K_CLK_CNTL,
1132                 .mask = 0x3,
1133                 .shift = 16,
1134                 },
1135         .hw.init = &(struct clk_init_data){
1136                 .name = "32k_clk_sel",
1137                 .ops = &clk_regmap_mux_ops,
1138                 .parent_names = gxbb_32k_clk_parent_names,
1139                 .num_parents = 4,
1140                 .flags = CLK_SET_RATE_PARENT,
1141         },
1142 };
1143
1144 static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
1145         "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1146
1147         /*
1148          * Following these parent clocks, we should also have had mpll2, mpll3
1149          * and gp0_pll but these clocks are too precious to be used here. All
1150          * the necessary rates for MMC and NAND operation can be acheived using
1151          * xtal or fclk_div clocks
1152          */
1153 };
1154
1155 /* SDIO clock */
1156 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1157         .data = &(struct clk_regmap_mux_data){
1158                 .offset = HHI_SD_EMMC_CLK_CNTL,
1159                 .mask = 0x7,
1160                 .shift = 9,
1161         },
1162         .hw.init = &(struct clk_init_data) {
1163                 .name = "sd_emmc_a_clk0_sel",
1164                 .ops = &clk_regmap_mux_ops,
1165                 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1166                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1167                 .flags = CLK_SET_RATE_PARENT,
1168         },
1169 };
1170
1171 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1172         .data = &(struct clk_regmap_div_data){
1173                 .offset = HHI_SD_EMMC_CLK_CNTL,
1174                 .shift = 0,
1175                 .width = 7,
1176                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1177         },
1178         .hw.init = &(struct clk_init_data) {
1179                 .name = "sd_emmc_a_clk0_div",
1180                 .ops = &clk_regmap_divider_ops,
1181                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1182                 .num_parents = 1,
1183                 .flags = CLK_SET_RATE_PARENT,
1184         },
1185 };
1186
1187 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1188         .data = &(struct clk_regmap_gate_data){
1189                 .offset = HHI_SD_EMMC_CLK_CNTL,
1190                 .bit_idx = 7,
1191         },
1192         .hw.init = &(struct clk_init_data){
1193                 .name = "sd_emmc_a_clk0",
1194                 .ops = &clk_regmap_gate_ops,
1195                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1196                 .num_parents = 1,
1197                 .flags = CLK_SET_RATE_PARENT,
1198         },
1199 };
1200
1201 /* SDcard clock */
1202 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1203         .data = &(struct clk_regmap_mux_data){
1204                 .offset = HHI_SD_EMMC_CLK_CNTL,
1205                 .mask = 0x7,
1206                 .shift = 25,
1207         },
1208         .hw.init = &(struct clk_init_data) {
1209                 .name = "sd_emmc_b_clk0_sel",
1210                 .ops = &clk_regmap_mux_ops,
1211                 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1212                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1213                 .flags = CLK_SET_RATE_PARENT,
1214         },
1215 };
1216
1217 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1218         .data = &(struct clk_regmap_div_data){
1219                 .offset = HHI_SD_EMMC_CLK_CNTL,
1220                 .shift = 16,
1221                 .width = 7,
1222                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1223         },
1224         .hw.init = &(struct clk_init_data) {
1225                 .name = "sd_emmc_b_clk0_div",
1226                 .ops = &clk_regmap_divider_ops,
1227                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1228                 .num_parents = 1,
1229                 .flags = CLK_SET_RATE_PARENT,
1230         },
1231 };
1232
1233 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1234         .data = &(struct clk_regmap_gate_data){
1235                 .offset = HHI_SD_EMMC_CLK_CNTL,
1236                 .bit_idx = 23,
1237         },
1238         .hw.init = &(struct clk_init_data){
1239                 .name = "sd_emmc_b_clk0",
1240                 .ops = &clk_regmap_gate_ops,
1241                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1242                 .num_parents = 1,
1243                 .flags = CLK_SET_RATE_PARENT,
1244         },
1245 };
1246
1247 /* EMMC/NAND clock */
1248 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1249         .data = &(struct clk_regmap_mux_data){
1250                 .offset = HHI_NAND_CLK_CNTL,
1251                 .mask = 0x7,
1252                 .shift = 9,
1253         },
1254         .hw.init = &(struct clk_init_data) {
1255                 .name = "sd_emmc_c_clk0_sel",
1256                 .ops = &clk_regmap_mux_ops,
1257                 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1258                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1259                 .flags = CLK_SET_RATE_PARENT,
1260         },
1261 };
1262
1263 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1264         .data = &(struct clk_regmap_div_data){
1265                 .offset = HHI_NAND_CLK_CNTL,
1266                 .shift = 0,
1267                 .width = 7,
1268                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1269         },
1270         .hw.init = &(struct clk_init_data) {
1271                 .name = "sd_emmc_c_clk0_div",
1272                 .ops = &clk_regmap_divider_ops,
1273                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1274                 .num_parents = 1,
1275                 .flags = CLK_SET_RATE_PARENT,
1276         },
1277 };
1278
1279 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1280         .data = &(struct clk_regmap_gate_data){
1281                 .offset = HHI_NAND_CLK_CNTL,
1282                 .bit_idx = 7,
1283         },
1284         .hw.init = &(struct clk_init_data){
1285                 .name = "sd_emmc_c_clk0",
1286                 .ops = &clk_regmap_gate_ops,
1287                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1288                 .num_parents = 1,
1289                 .flags = CLK_SET_RATE_PARENT,
1290         },
1291 };
1292
1293 /* VPU Clock */
1294
1295 static const char * const gxbb_vpu_parent_names[] = {
1296         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1297 };
1298
1299 static struct clk_regmap gxbb_vpu_0_sel = {
1300         .data = &(struct clk_regmap_mux_data){
1301                 .offset = HHI_VPU_CLK_CNTL,
1302                 .mask = 0x3,
1303                 .shift = 9,
1304         },
1305         .hw.init = &(struct clk_init_data){
1306                 .name = "vpu_0_sel",
1307                 .ops = &clk_regmap_mux_ops,
1308                 /*
1309                  * bits 9:10 selects from 4 possible parents:
1310                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1311                  */
1312                 .parent_names = gxbb_vpu_parent_names,
1313                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1314                 .flags = CLK_SET_RATE_NO_REPARENT,
1315         },
1316 };
1317
1318 static struct clk_regmap gxbb_vpu_0_div = {
1319         .data = &(struct clk_regmap_div_data){
1320                 .offset = HHI_VPU_CLK_CNTL,
1321                 .shift = 0,
1322                 .width = 7,
1323         },
1324         .hw.init = &(struct clk_init_data){
1325                 .name = "vpu_0_div",
1326                 .ops = &clk_regmap_divider_ops,
1327                 .parent_names = (const char *[]){ "vpu_0_sel" },
1328                 .num_parents = 1,
1329                 .flags = CLK_SET_RATE_PARENT,
1330         },
1331 };
1332
1333 static struct clk_regmap gxbb_vpu_0 = {
1334         .data = &(struct clk_regmap_gate_data){
1335                 .offset = HHI_VPU_CLK_CNTL,
1336                 .bit_idx = 8,
1337         },
1338         .hw.init = &(struct clk_init_data) {
1339                 .name = "vpu_0",
1340                 .ops = &clk_regmap_gate_ops,
1341                 .parent_names = (const char *[]){ "vpu_0_div" },
1342                 .num_parents = 1,
1343                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1344         },
1345 };
1346
1347 static struct clk_regmap gxbb_vpu_1_sel = {
1348         .data = &(struct clk_regmap_mux_data){
1349                 .offset = HHI_VPU_CLK_CNTL,
1350                 .mask = 0x3,
1351                 .shift = 25,
1352         },
1353         .hw.init = &(struct clk_init_data){
1354                 .name = "vpu_1_sel",
1355                 .ops = &clk_regmap_mux_ops,
1356                 /*
1357                  * bits 25:26 selects from 4 possible parents:
1358                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1359                  */
1360                 .parent_names = gxbb_vpu_parent_names,
1361                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1362                 .flags = CLK_SET_RATE_NO_REPARENT,
1363         },
1364 };
1365
1366 static struct clk_regmap gxbb_vpu_1_div = {
1367         .data = &(struct clk_regmap_div_data){
1368                 .offset = HHI_VPU_CLK_CNTL,
1369                 .shift = 16,
1370                 .width = 7,
1371         },
1372         .hw.init = &(struct clk_init_data){
1373                 .name = "vpu_1_div",
1374                 .ops = &clk_regmap_divider_ops,
1375                 .parent_names = (const char *[]){ "vpu_1_sel" },
1376                 .num_parents = 1,
1377                 .flags = CLK_SET_RATE_PARENT,
1378         },
1379 };
1380
1381 static struct clk_regmap gxbb_vpu_1 = {
1382         .data = &(struct clk_regmap_gate_data){
1383                 .offset = HHI_VPU_CLK_CNTL,
1384                 .bit_idx = 24,
1385         },
1386         .hw.init = &(struct clk_init_data) {
1387                 .name = "vpu_1",
1388                 .ops = &clk_regmap_gate_ops,
1389                 .parent_names = (const char *[]){ "vpu_1_div" },
1390                 .num_parents = 1,
1391                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1392         },
1393 };
1394
1395 static struct clk_regmap gxbb_vpu = {
1396         .data = &(struct clk_regmap_mux_data){
1397                 .offset = HHI_VPU_CLK_CNTL,
1398                 .mask = 1,
1399                 .shift = 31,
1400         },
1401         .hw.init = &(struct clk_init_data){
1402                 .name = "vpu",
1403                 .ops = &clk_regmap_mux_ops,
1404                 /*
1405                  * bit 31 selects from 2 possible parents:
1406                  * vpu_0 or vpu_1
1407                  */
1408                 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1409                 .num_parents = 2,
1410                 .flags = CLK_SET_RATE_NO_REPARENT,
1411         },
1412 };
1413
1414 /* VAPB Clock */
1415
1416 static const char * const gxbb_vapb_parent_names[] = {
1417         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1418 };
1419
1420 static struct clk_regmap gxbb_vapb_0_sel = {
1421         .data = &(struct clk_regmap_mux_data){
1422                 .offset = HHI_VAPBCLK_CNTL,
1423                 .mask = 0x3,
1424                 .shift = 9,
1425         },
1426         .hw.init = &(struct clk_init_data){
1427                 .name = "vapb_0_sel",
1428                 .ops = &clk_regmap_mux_ops,
1429                 /*
1430                  * bits 9:10 selects from 4 possible parents:
1431                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1432                  */
1433                 .parent_names = gxbb_vapb_parent_names,
1434                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1435                 .flags = CLK_SET_RATE_NO_REPARENT,
1436         },
1437 };
1438
1439 static struct clk_regmap gxbb_vapb_0_div = {
1440         .data = &(struct clk_regmap_div_data){
1441                 .offset = HHI_VAPBCLK_CNTL,
1442                 .shift = 0,
1443                 .width = 7,
1444         },
1445         .hw.init = &(struct clk_init_data){
1446                 .name = "vapb_0_div",
1447                 .ops = &clk_regmap_divider_ops,
1448                 .parent_names = (const char *[]){ "vapb_0_sel" },
1449                 .num_parents = 1,
1450                 .flags = CLK_SET_RATE_PARENT,
1451         },
1452 };
1453
1454 static struct clk_regmap gxbb_vapb_0 = {
1455         .data = &(struct clk_regmap_gate_data){
1456                 .offset = HHI_VAPBCLK_CNTL,
1457                 .bit_idx = 8,
1458         },
1459         .hw.init = &(struct clk_init_data) {
1460                 .name = "vapb_0",
1461                 .ops = &clk_regmap_gate_ops,
1462                 .parent_names = (const char *[]){ "vapb_0_div" },
1463                 .num_parents = 1,
1464                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1465         },
1466 };
1467
1468 static struct clk_regmap gxbb_vapb_1_sel = {
1469         .data = &(struct clk_regmap_mux_data){
1470                 .offset = HHI_VAPBCLK_CNTL,
1471                 .mask = 0x3,
1472                 .shift = 25,
1473         },
1474         .hw.init = &(struct clk_init_data){
1475                 .name = "vapb_1_sel",
1476                 .ops = &clk_regmap_mux_ops,
1477                 /*
1478                  * bits 25:26 selects from 4 possible parents:
1479                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1480                  */
1481                 .parent_names = gxbb_vapb_parent_names,
1482                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1483                 .flags = CLK_SET_RATE_NO_REPARENT,
1484         },
1485 };
1486
1487 static struct clk_regmap gxbb_vapb_1_div = {
1488         .data = &(struct clk_regmap_div_data){
1489                 .offset = HHI_VAPBCLK_CNTL,
1490                 .shift = 16,
1491                 .width = 7,
1492         },
1493         .hw.init = &(struct clk_init_data){
1494                 .name = "vapb_1_div",
1495                 .ops = &clk_regmap_divider_ops,
1496                 .parent_names = (const char *[]){ "vapb_1_sel" },
1497                 .num_parents = 1,
1498                 .flags = CLK_SET_RATE_PARENT,
1499         },
1500 };
1501
1502 static struct clk_regmap gxbb_vapb_1 = {
1503         .data = &(struct clk_regmap_gate_data){
1504                 .offset = HHI_VAPBCLK_CNTL,
1505                 .bit_idx = 24,
1506         },
1507         .hw.init = &(struct clk_init_data) {
1508                 .name = "vapb_1",
1509                 .ops = &clk_regmap_gate_ops,
1510                 .parent_names = (const char *[]){ "vapb_1_div" },
1511                 .num_parents = 1,
1512                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1513         },
1514 };
1515
1516 static struct clk_regmap gxbb_vapb_sel = {
1517         .data = &(struct clk_regmap_mux_data){
1518                 .offset = HHI_VAPBCLK_CNTL,
1519                 .mask = 1,
1520                 .shift = 31,
1521         },
1522         .hw.init = &(struct clk_init_data){
1523                 .name = "vapb_sel",
1524                 .ops = &clk_regmap_mux_ops,
1525                 /*
1526                  * bit 31 selects from 2 possible parents:
1527                  * vapb_0 or vapb_1
1528                  */
1529                 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1530                 .num_parents = 2,
1531                 .flags = CLK_SET_RATE_NO_REPARENT,
1532         },
1533 };
1534
1535 static struct clk_regmap gxbb_vapb = {
1536         .data = &(struct clk_regmap_gate_data){
1537                 .offset = HHI_VAPBCLK_CNTL,
1538                 .bit_idx = 30,
1539         },
1540         .hw.init = &(struct clk_init_data) {
1541                 .name = "vapb",
1542                 .ops = &clk_regmap_gate_ops,
1543                 .parent_names = (const char *[]){ "vapb_sel" },
1544                 .num_parents = 1,
1545                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1546         },
1547 };
1548
1549 /* VDEC clocks */
1550
1551 static const char * const gxbb_vdec_parent_names[] = {
1552         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1553 };
1554
1555 static struct clk_regmap gxbb_vdec_1_sel = {
1556         .data = &(struct clk_regmap_mux_data){
1557                 .offset = HHI_VDEC_CLK_CNTL,
1558                 .mask = 0x3,
1559                 .shift = 9,
1560                 .flags = CLK_MUX_ROUND_CLOSEST,
1561         },
1562         .hw.init = &(struct clk_init_data){
1563                 .name = "vdec_1_sel",
1564                 .ops = &clk_regmap_mux_ops,
1565                 .parent_names = gxbb_vdec_parent_names,
1566                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1567                 .flags = CLK_SET_RATE_PARENT,
1568         },
1569 };
1570
1571 static struct clk_regmap gxbb_vdec_1_div = {
1572         .data = &(struct clk_regmap_div_data){
1573                 .offset = HHI_VDEC_CLK_CNTL,
1574                 .shift = 0,
1575                 .width = 7,
1576                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1577         },
1578         .hw.init = &(struct clk_init_data){
1579                 .name = "vdec_1_div",
1580                 .ops = &clk_regmap_divider_ops,
1581                 .parent_names = (const char *[]){ "vdec_1_sel" },
1582                 .num_parents = 1,
1583                 .flags = CLK_SET_RATE_PARENT,
1584         },
1585 };
1586
1587 static struct clk_regmap gxbb_vdec_1 = {
1588         .data = &(struct clk_regmap_gate_data){
1589                 .offset = HHI_VDEC_CLK_CNTL,
1590                 .bit_idx = 8,
1591         },
1592         .hw.init = &(struct clk_init_data) {
1593                 .name = "vdec_1",
1594                 .ops = &clk_regmap_gate_ops,
1595                 .parent_names = (const char *[]){ "vdec_1_div" },
1596                 .num_parents = 1,
1597                 .flags = CLK_SET_RATE_PARENT,
1598         },
1599 };
1600
1601 static struct clk_regmap gxbb_vdec_hevc_sel = {
1602         .data = &(struct clk_regmap_mux_data){
1603                 .offset = HHI_VDEC2_CLK_CNTL,
1604                 .mask = 0x3,
1605                 .shift = 25,
1606                 .flags = CLK_MUX_ROUND_CLOSEST,
1607         },
1608         .hw.init = &(struct clk_init_data){
1609                 .name = "vdec_hevc_sel",
1610                 .ops = &clk_regmap_mux_ops,
1611                 .parent_names = gxbb_vdec_parent_names,
1612                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1613                 .flags = CLK_SET_RATE_PARENT,
1614         },
1615 };
1616
1617 static struct clk_regmap gxbb_vdec_hevc_div = {
1618         .data = &(struct clk_regmap_div_data){
1619                 .offset = HHI_VDEC2_CLK_CNTL,
1620                 .shift = 16,
1621                 .width = 7,
1622                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1623         },
1624         .hw.init = &(struct clk_init_data){
1625                 .name = "vdec_hevc_div",
1626                 .ops = &clk_regmap_divider_ops,
1627                 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1628                 .num_parents = 1,
1629                 .flags = CLK_SET_RATE_PARENT,
1630         },
1631 };
1632
1633 static struct clk_regmap gxbb_vdec_hevc = {
1634         .data = &(struct clk_regmap_gate_data){
1635                 .offset = HHI_VDEC2_CLK_CNTL,
1636                 .bit_idx = 24,
1637         },
1638         .hw.init = &(struct clk_init_data) {
1639                 .name = "vdec_hevc",
1640                 .ops = &clk_regmap_gate_ops,
1641                 .parent_names = (const char *[]){ "vdec_hevc_div" },
1642                 .num_parents = 1,
1643                 .flags = CLK_SET_RATE_PARENT,
1644         },
1645 };
1646
1647 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
1648                                     9, 10, 11, 13, 14, };
1649 static const char * const gen_clk_parent_names[] = {
1650         "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
1651         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
1652 };
1653
1654 static struct clk_regmap gxbb_gen_clk_sel = {
1655         .data = &(struct clk_regmap_mux_data){
1656                 .offset = HHI_GEN_CLK_CNTL,
1657                 .mask = 0xf,
1658                 .shift = 12,
1659                 .table = mux_table_gen_clk,
1660         },
1661         .hw.init = &(struct clk_init_data){
1662                 .name = "gen_clk_sel",
1663                 .ops = &clk_regmap_mux_ops,
1664                 /*
1665                  * bits 15:12 selects from 14 possible parents:
1666                  * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
1667                  * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
1668                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
1669                  */
1670                 .parent_names = gen_clk_parent_names,
1671                 .num_parents = ARRAY_SIZE(gen_clk_parent_names),
1672         },
1673 };
1674
1675 static struct clk_regmap gxbb_gen_clk_div = {
1676         .data = &(struct clk_regmap_div_data){
1677                 .offset = HHI_GEN_CLK_CNTL,
1678                 .shift = 0,
1679                 .width = 11,
1680         },
1681         .hw.init = &(struct clk_init_data){
1682                 .name = "gen_clk_div",
1683                 .ops = &clk_regmap_divider_ops,
1684                 .parent_names = (const char *[]){ "gen_clk_sel" },
1685                 .num_parents = 1,
1686                 .flags = CLK_SET_RATE_PARENT,
1687         },
1688 };
1689
1690 static struct clk_regmap gxbb_gen_clk = {
1691         .data = &(struct clk_regmap_gate_data){
1692                 .offset = HHI_GEN_CLK_CNTL,
1693                 .bit_idx = 7,
1694         },
1695         .hw.init = &(struct clk_init_data){
1696                 .name = "gen_clk",
1697                 .ops = &clk_regmap_gate_ops,
1698                 .parent_names = (const char *[]){ "gen_clk_div" },
1699                 .num_parents = 1,
1700                 .flags = CLK_SET_RATE_PARENT,
1701         },
1702 };
1703
1704 /* Everything Else (EE) domain gates */
1705 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1706 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
1707 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
1708 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
1709 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
1710 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
1711 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
1712 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
1713 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
1714 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
1715 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
1716 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
1717 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
1718 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
1719 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
1720 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
1721 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
1722 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
1723 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
1724 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
1725 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
1726 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
1727
1728 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
1729 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
1730 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
1731 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
1732 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
1733 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
1734 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
1735 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
1736 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
1737 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
1738 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
1739 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
1740 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
1741 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
1742 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
1743 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
1744 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
1745 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
1746 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
1747 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
1748 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
1749 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
1750 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
1751 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
1752 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
1753
1754 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1755 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1756 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
1757 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
1758 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
1759 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
1760 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
1761 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
1762 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
1763 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
1764 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
1765 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1766 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
1767
1768 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
1769 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
1770 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1771 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1772 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
1773 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
1774 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
1775 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
1776 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
1777 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
1778 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
1779 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
1780 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
1781 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
1782 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
1783 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
1784
1785 /* Always On (AO) domain gates */
1786
1787 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
1788 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
1789 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
1790 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
1791 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
1792
1793 /* Array of all clocks provided by this provider */
1794
1795 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1796         .hws = {
1797                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
1798                 [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
1799                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
1800                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
1801                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
1802                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
1803                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
1804                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
1805                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
1806                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
1807                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
1808                 [CLKID_CLK81]               = &gxbb_clk81.hw,
1809                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
1810                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
1811                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
1812                 [CLKID_DDR]                 = &gxbb_ddr.hw,
1813                 [CLKID_DOS]                 = &gxbb_dos.hw,
1814                 [CLKID_ISA]                 = &gxbb_isa.hw,
1815                 [CLKID_PL301]               = &gxbb_pl301.hw,
1816                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
1817                 [CLKID_SPICC]               = &gxbb_spicc.hw,
1818                 [CLKID_I2C]                 = &gxbb_i2c.hw,
1819                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
1820                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
1821                 [CLKID_RNG0]                = &gxbb_rng0.hw,
1822                 [CLKID_UART0]               = &gxbb_uart0.hw,
1823                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
1824                 [CLKID_STREAM]              = &gxbb_stream.hw,
1825                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
1826                 [CLKID_SDIO]                = &gxbb_sdio.hw,
1827                 [CLKID_ABUF]                = &gxbb_abuf.hw,
1828                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
1829                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
1830                 [CLKID_SPI]                 = &gxbb_spi.hw,
1831                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
1832                 [CLKID_ETH]                 = &gxbb_eth.hw,
1833                 [CLKID_DEMUX]               = &gxbb_demux.hw,
1834                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
1835                 [CLKID_IEC958]              = &gxbb_iec958.hw,
1836                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
1837                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
1838                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
1839                 [CLKID_MIXER]               = &gxbb_mixer.hw,
1840                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
1841                 [CLKID_ADC]                 = &gxbb_adc.hw,
1842                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
1843                 [CLKID_AIU]                 = &gxbb_aiu.hw,
1844                 [CLKID_UART1]               = &gxbb_uart1.hw,
1845                 [CLKID_G2D]                 = &gxbb_g2d.hw,
1846                 [CLKID_USB0]                = &gxbb_usb0.hw,
1847                 [CLKID_USB1]                = &gxbb_usb1.hw,
1848                 [CLKID_RESET]               = &gxbb_reset.hw,
1849                 [CLKID_NAND]                = &gxbb_nand.hw,
1850                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
1851                 [CLKID_USB]                 = &gxbb_usb.hw,
1852                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
1853                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
1854                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
1855                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
1856                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
1857                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
1858                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
1859                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
1860                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
1861                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
1862                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
1863                 [CLKID_DVIN]                = &gxbb_dvin.hw,
1864                 [CLKID_UART2]               = &gxbb_uart2.hw,
1865                 [CLKID_SANA]                = &gxbb_sana.hw,
1866                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
1867                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1868                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
1869                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
1870                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
1871                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
1872                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
1873                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
1874                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
1875                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
1876                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
1877                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
1878                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
1879                 [CLKID_RNG1]                = &gxbb_rng1.hw,
1880                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
1881                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
1882                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
1883                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
1884                 [CLKID_EDP]                 = &gxbb_edp.hw,
1885                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
1886                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
1887                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
1888                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
1889                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
1890                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
1891                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
1892                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
1893                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
1894                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
1895                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
1896                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
1897                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
1898                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
1899                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
1900                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
1901                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
1902                 [CLKID_MALI]                = &gxbb_mali.hw,
1903                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
1904                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
1905                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
1906                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
1907                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
1908                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
1909                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
1910                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
1911                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
1912                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
1913                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
1914                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
1915                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
1916                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
1917                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
1918                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
1919                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
1920                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
1921                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
1922                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
1923                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
1924                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
1925                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
1926                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
1927                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
1928                 [CLKID_VPU]                 = &gxbb_vpu.hw,
1929                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
1930                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
1931                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
1932                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
1933                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
1934                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
1935                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
1936                 [CLKID_VAPB]                = &gxbb_vapb.hw,
1937                 [CLKID_HDMI_PLL_PRE_MULT]   = &gxbb_hdmi_pll_pre_mult.hw,
1938                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
1939                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
1940                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
1941                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
1942                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
1943                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
1944                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
1945                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
1946                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
1947                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
1948                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
1949                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
1950                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
1951                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
1952                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
1953                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
1954                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
1955                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
1956                 [NR_CLKS]                   = NULL,
1957         },
1958         .num = NR_CLKS,
1959 };
1960
1961 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1962         .hws = {
1963                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
1964                 [CLKID_HDMI_PLL]            = &gxl_hdmi_pll.hw,
1965                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
1966                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
1967                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
1968                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
1969                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
1970                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
1971                 [CLKID_GP0_PLL]             = &gxl_gp0_pll.hw,
1972                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
1973                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
1974                 [CLKID_CLK81]               = &gxbb_clk81.hw,
1975                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
1976                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
1977                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
1978                 [CLKID_DDR]                 = &gxbb_ddr.hw,
1979                 [CLKID_DOS]                 = &gxbb_dos.hw,
1980                 [CLKID_ISA]                 = &gxbb_isa.hw,
1981                 [CLKID_PL301]               = &gxbb_pl301.hw,
1982                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
1983                 [CLKID_SPICC]               = &gxbb_spicc.hw,
1984                 [CLKID_I2C]                 = &gxbb_i2c.hw,
1985                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
1986                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
1987                 [CLKID_RNG0]                = &gxbb_rng0.hw,
1988                 [CLKID_UART0]               = &gxbb_uart0.hw,
1989                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
1990                 [CLKID_STREAM]              = &gxbb_stream.hw,
1991                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
1992                 [CLKID_SDIO]                = &gxbb_sdio.hw,
1993                 [CLKID_ABUF]                = &gxbb_abuf.hw,
1994                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
1995                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
1996                 [CLKID_SPI]                 = &gxbb_spi.hw,
1997                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
1998                 [CLKID_ETH]                 = &gxbb_eth.hw,
1999                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2000                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2001                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2002                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2003                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2004                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2005                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2006                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2007                 [CLKID_ADC]                 = &gxbb_adc.hw,
2008                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2009                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2010                 [CLKID_UART1]               = &gxbb_uart1.hw,
2011                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2012                 [CLKID_USB0]                = &gxbb_usb0.hw,
2013                 [CLKID_USB1]                = &gxbb_usb1.hw,
2014                 [CLKID_RESET]               = &gxbb_reset.hw,
2015                 [CLKID_NAND]                = &gxbb_nand.hw,
2016                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2017                 [CLKID_USB]                 = &gxbb_usb.hw,
2018                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
2019                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
2020                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
2021                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
2022                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
2023                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
2024                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
2025                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
2026                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
2027                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
2028                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
2029                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2030                 [CLKID_UART2]               = &gxbb_uart2.hw,
2031                 [CLKID_SANA]                = &gxbb_sana.hw,
2032                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2033                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2034                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2035                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2036                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2037                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2038                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2039                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2040                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2041                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2042                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2043                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2044                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2045                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2046                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2047                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2048                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2049                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2050                 [CLKID_EDP]                 = &gxbb_edp.hw,
2051                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2052                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2053                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2054                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2055                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
2056                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
2057                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
2058                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
2059                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
2060                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
2061                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
2062                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
2063                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
2064                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
2065                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
2066                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
2067                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
2068                 [CLKID_MALI]                = &gxbb_mali.hw,
2069                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
2070                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
2071                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
2072                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
2073                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2074                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2075                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
2076                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
2077                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
2078                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
2079                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2080                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2081                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
2082                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2083                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2084                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
2085                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2086                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2087                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
2088                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
2089                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
2090                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
2091                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
2092                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
2093                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
2094                 [CLKID_VPU]                 = &gxbb_vpu.hw,
2095                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
2096                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
2097                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
2098                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
2099                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
2100                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
2101                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
2102                 [CLKID_VAPB]                = &gxbb_vapb.hw,
2103                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
2104                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
2105                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
2106                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
2107                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
2108                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
2109                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
2110                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
2111                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
2112                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
2113                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
2114                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
2115                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
2116                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
2117                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
2118                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
2119                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
2120                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
2121                 [NR_CLKS]                   = NULL,
2122         },
2123         .num = NR_CLKS,
2124 };
2125
2126 static struct clk_regmap *const gxbb_clk_regmaps[] = {
2127         &gxbb_gp0_pll,
2128         &gxbb_hdmi_pll,
2129 };
2130
2131 static struct clk_regmap *const gxl_clk_regmaps[] = {
2132         &gxl_gp0_pll,
2133         &gxl_hdmi_pll,
2134 };
2135
2136 static struct clk_regmap *const gx_clk_regmaps[] = {
2137         &gxbb_clk81,
2138         &gxbb_ddr,
2139         &gxbb_dos,
2140         &gxbb_isa,
2141         &gxbb_pl301,
2142         &gxbb_periphs,
2143         &gxbb_spicc,
2144         &gxbb_i2c,
2145         &gxbb_sar_adc,
2146         &gxbb_smart_card,
2147         &gxbb_rng0,
2148         &gxbb_uart0,
2149         &gxbb_sdhc,
2150         &gxbb_stream,
2151         &gxbb_async_fifo,
2152         &gxbb_sdio,
2153         &gxbb_abuf,
2154         &gxbb_hiu_iface,
2155         &gxbb_assist_misc,
2156         &gxbb_spi,
2157         &gxbb_i2s_spdif,
2158         &gxbb_eth,
2159         &gxbb_demux,
2160         &gxbb_aiu_glue,
2161         &gxbb_iec958,
2162         &gxbb_i2s_out,
2163         &gxbb_amclk,
2164         &gxbb_aififo2,
2165         &gxbb_mixer,
2166         &gxbb_mixer_iface,
2167         &gxbb_adc,
2168         &gxbb_blkmv,
2169         &gxbb_aiu,
2170         &gxbb_uart1,
2171         &gxbb_g2d,
2172         &gxbb_usb0,
2173         &gxbb_usb1,
2174         &gxbb_reset,
2175         &gxbb_nand,
2176         &gxbb_dos_parser,
2177         &gxbb_usb,
2178         &gxbb_vdin1,
2179         &gxbb_ahb_arb0,
2180         &gxbb_efuse,
2181         &gxbb_boot_rom,
2182         &gxbb_ahb_data_bus,
2183         &gxbb_ahb_ctrl_bus,
2184         &gxbb_hdmi_intr_sync,
2185         &gxbb_hdmi_pclk,
2186         &gxbb_usb1_ddr_bridge,
2187         &gxbb_usb0_ddr_bridge,
2188         &gxbb_mmc_pclk,
2189         &gxbb_dvin,
2190         &gxbb_uart2,
2191         &gxbb_sana,
2192         &gxbb_vpu_intr,
2193         &gxbb_sec_ahb_ahb3_bridge,
2194         &gxbb_clk81_a53,
2195         &gxbb_vclk2_venci0,
2196         &gxbb_vclk2_venci1,
2197         &gxbb_vclk2_vencp0,
2198         &gxbb_vclk2_vencp1,
2199         &gxbb_gclk_venci_int0,
2200         &gxbb_gclk_vencp_int,
2201         &gxbb_dac_clk,
2202         &gxbb_aoclk_gate,
2203         &gxbb_iec958_gate,
2204         &gxbb_enc480p,
2205         &gxbb_rng1,
2206         &gxbb_gclk_venci_int1,
2207         &gxbb_vclk2_venclmcc,
2208         &gxbb_vclk2_vencl,
2209         &gxbb_vclk_other,
2210         &gxbb_edp,
2211         &gxbb_ao_media_cpu,
2212         &gxbb_ao_ahb_sram,
2213         &gxbb_ao_ahb_bus,
2214         &gxbb_ao_iface,
2215         &gxbb_ao_i2c,
2216         &gxbb_emmc_a,
2217         &gxbb_emmc_b,
2218         &gxbb_emmc_c,
2219         &gxbb_sar_adc_clk,
2220         &gxbb_mali_0,
2221         &gxbb_mali_1,
2222         &gxbb_cts_amclk,
2223         &gxbb_cts_mclk_i958,
2224         &gxbb_32k_clk,
2225         &gxbb_sd_emmc_a_clk0,
2226         &gxbb_sd_emmc_b_clk0,
2227         &gxbb_sd_emmc_c_clk0,
2228         &gxbb_vpu_0,
2229         &gxbb_vpu_1,
2230         &gxbb_vapb_0,
2231         &gxbb_vapb_1,
2232         &gxbb_vapb,
2233         &gxbb_mpeg_clk_div,
2234         &gxbb_sar_adc_clk_div,
2235         &gxbb_mali_0_div,
2236         &gxbb_mali_1_div,
2237         &gxbb_cts_mclk_i958_div,
2238         &gxbb_32k_clk_div,
2239         &gxbb_sd_emmc_a_clk0_div,
2240         &gxbb_sd_emmc_b_clk0_div,
2241         &gxbb_sd_emmc_c_clk0_div,
2242         &gxbb_vpu_0_div,
2243         &gxbb_vpu_1_div,
2244         &gxbb_vapb_0_div,
2245         &gxbb_vapb_1_div,
2246         &gxbb_mpeg_clk_sel,
2247         &gxbb_sar_adc_clk_sel,
2248         &gxbb_mali_0_sel,
2249         &gxbb_mali_1_sel,
2250         &gxbb_mali,
2251         &gxbb_cts_amclk_sel,
2252         &gxbb_cts_mclk_i958_sel,
2253         &gxbb_cts_i958,
2254         &gxbb_32k_clk_sel,
2255         &gxbb_sd_emmc_a_clk0_sel,
2256         &gxbb_sd_emmc_b_clk0_sel,
2257         &gxbb_sd_emmc_c_clk0_sel,
2258         &gxbb_vpu_0_sel,
2259         &gxbb_vpu_1_sel,
2260         &gxbb_vpu,
2261         &gxbb_vapb_0_sel,
2262         &gxbb_vapb_1_sel,
2263         &gxbb_vapb_sel,
2264         &gxbb_mpll0,
2265         &gxbb_mpll1,
2266         &gxbb_mpll2,
2267         &gxbb_mpll0_div,
2268         &gxbb_mpll1_div,
2269         &gxbb_mpll2_div,
2270         &gxbb_cts_amclk_div,
2271         &gxbb_fixed_pll,
2272         &gxbb_sys_pll,
2273         &gxbb_mpll_prediv,
2274         &gxbb_fclk_div2,
2275         &gxbb_fclk_div3,
2276         &gxbb_fclk_div4,
2277         &gxbb_fclk_div5,
2278         &gxbb_fclk_div7,
2279         &gxbb_vdec_1_sel,
2280         &gxbb_vdec_1_div,
2281         &gxbb_vdec_1,
2282         &gxbb_vdec_hevc_sel,
2283         &gxbb_vdec_hevc_div,
2284         &gxbb_vdec_hevc,
2285         &gxbb_gen_clk_sel,
2286         &gxbb_gen_clk_div,
2287         &gxbb_gen_clk,
2288 };
2289
2290 struct clkc_data {
2291         struct clk_regmap *const *regmap_clks;
2292         unsigned int regmap_clks_count;
2293         struct clk_hw_onecell_data *hw_onecell_data;
2294 };
2295
2296 static const struct clkc_data gxbb_clkc_data = {
2297         .regmap_clks = gxbb_clk_regmaps,
2298         .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps),
2299         .hw_onecell_data = &gxbb_hw_onecell_data,
2300 };
2301
2302 static const struct clkc_data gxl_clkc_data = {
2303         .regmap_clks = gxl_clk_regmaps,
2304         .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps),
2305         .hw_onecell_data = &gxl_hw_onecell_data,
2306 };
2307
2308 static const struct of_device_id clkc_match_table[] = {
2309         { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
2310         { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
2311         {},
2312 };
2313
2314 static int gxbb_clkc_probe(struct platform_device *pdev)
2315 {
2316         const struct clkc_data *clkc_data;
2317         struct regmap *map;
2318         int ret, i;
2319         struct device *dev = &pdev->dev;
2320
2321         clkc_data = of_device_get_match_data(dev);
2322         if (!clkc_data)
2323                 return -EINVAL;
2324
2325         /* Get the hhi system controller node if available */
2326         map = syscon_node_to_regmap(of_get_parent(dev->of_node));
2327         if (IS_ERR(map)) {
2328                 dev_err(dev, "failed to get HHI regmap\n");
2329                 return PTR_ERR(map);
2330         }
2331
2332         /* Populate regmap for the common regmap backed clocks */
2333         for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)
2334                 gx_clk_regmaps[i]->map = map;
2335
2336         /* Populate regmap for soc specific clocks */
2337         for (i = 0; i < clkc_data->regmap_clks_count; i++)
2338                 clkc_data->regmap_clks[i]->map = map;
2339
2340         /* Register all clks */
2341         for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
2342                 /* array might be sparse */
2343                 if (!clkc_data->hw_onecell_data->hws[i])
2344                         continue;
2345
2346                 ret = devm_clk_hw_register(dev,
2347                                            clkc_data->hw_onecell_data->hws[i]);
2348                 if (ret) {
2349                         dev_err(dev, "Clock registration failed\n");
2350                         return ret;
2351                 }
2352         }
2353
2354         return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
2355                                            clkc_data->hw_onecell_data);
2356 }
2357
2358 static struct platform_driver gxbb_driver = {
2359         .probe          = gxbb_clkc_probe,
2360         .driver         = {
2361                 .name   = "gxbb-clkc",
2362                 .of_match_table = clkc_match_table,
2363         },
2364 };
2365
2366 builtin_platform_driver(gxbb_driver);