drivers/clk/meson/meson8b.c

   1 /*
   2  * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
   3  * Driver
   4  *
   5  * Copyright (c) 2015 Endless Mobile, Inc.
   6  * Author: Carlo Caione <carlo@endlessm.com>
   7  *
   8  * Copyright (c) 2016 BayLibre, Inc.
   9  * Michael Turquette <mturquette@baylibre.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms and conditions of the GNU General Public License,
  13  * version 2, as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program.  If not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/of_address.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/init.h>
  29
  30 #include "clkc.h"
  31 #include "meson8b.h"
  32
  33 static DEFINE_SPINLOCK(clk_lock);
  34
  35 static const struct pll_rate_table sys_pll_rate_table[] = {
  36         PLL_RATE(312000000, 52, 1, 2),
  37         PLL_RATE(336000000, 56, 1, 2),
  38         PLL_RATE(360000000, 60, 1, 2),
  39         PLL_RATE(384000000, 64, 1, 2),
  40         PLL_RATE(408000000, 68, 1, 2),
  41         PLL_RATE(432000000, 72, 1, 2),
  42         PLL_RATE(456000000, 76, 1, 2),
  43         PLL_RATE(480000000, 80, 1, 2),
  44         PLL_RATE(504000000, 84, 1, 2),
  45         PLL_RATE(528000000, 88, 1, 2),
  46         PLL_RATE(552000000, 92, 1, 2),
  47         PLL_RATE(576000000, 96, 1, 2),
  48         PLL_RATE(600000000, 50, 1, 1),
  49         PLL_RATE(624000000, 52, 1, 1),
  50         PLL_RATE(648000000, 54, 1, 1),
  51         PLL_RATE(672000000, 56, 1, 1),
  52         PLL_RATE(696000000, 58, 1, 1),
  53         PLL_RATE(720000000, 60, 1, 1),
  54         PLL_RATE(744000000, 62, 1, 1),
  55         PLL_RATE(768000000, 64, 1, 1),
  56         PLL_RATE(792000000, 66, 1, 1),
  57         PLL_RATE(816000000, 68, 1, 1),
  58         PLL_RATE(840000000, 70, 1, 1),
  59         PLL_RATE(864000000, 72, 1, 1),
  60         PLL_RATE(888000000, 74, 1, 1),
  61         PLL_RATE(912000000, 76, 1, 1),
  62         PLL_RATE(936000000, 78, 1, 1),
  63         PLL_RATE(960000000, 80, 1, 1),
  64         PLL_RATE(984000000, 82, 1, 1),
  65         PLL_RATE(1008000000, 84, 1, 1),
  66         PLL_RATE(1032000000, 86, 1, 1),
  67         PLL_RATE(1056000000, 88, 1, 1),
  68         PLL_RATE(1080000000, 90, 1, 1),
  69         PLL_RATE(1104000000, 92, 1, 1),
  70         PLL_RATE(1128000000, 94, 1, 1),
  71         PLL_RATE(1152000000, 96, 1, 1),
  72         PLL_RATE(1176000000, 98, 1, 1),
  73         PLL_RATE(1200000000, 50, 1, 0),
  74         PLL_RATE(1224000000, 51, 1, 0),
  75         PLL_RATE(1248000000, 52, 1, 0),
  76         PLL_RATE(1272000000, 53, 1, 0),
  77         PLL_RATE(1296000000, 54, 1, 0),
  78         PLL_RATE(1320000000, 55, 1, 0),
  79         PLL_RATE(1344000000, 56, 1, 0),
  80         PLL_RATE(1368000000, 57, 1, 0),
  81         PLL_RATE(1392000000, 58, 1, 0),
  82         PLL_RATE(1416000000, 59, 1, 0),
  83         PLL_RATE(1440000000, 60, 1, 0),
  84         PLL_RATE(1464000000, 61, 1, 0),
  85         PLL_RATE(1488000000, 62, 1, 0),
  86         PLL_RATE(1512000000, 63, 1, 0),
  87         PLL_RATE(1536000000, 64, 1, 0),
  88         { /* sentinel */ },
  89 };
  90
  91 static const struct clk_div_table cpu_div_table[] = {
  92         { .val = 1, .div = 1 },
  93         { .val = 2, .div = 2 },
  94         { .val = 3, .div = 3 },
  95         { .val = 2, .div = 4 },
  96         { .val = 3, .div = 6 },
  97         { .val = 4, .div = 8 },
  98         { .val = 5, .div = 10 },
  99         { .val = 6, .div = 12 },
 100         { .val = 7, .div = 14 },
 101         { .val = 8, .div = 16 },
 102         { /* sentinel */ },
 103 };
 104
 105 static struct clk_fixed_rate meson8b_xtal = {
 106         .fixed_rate = 24000000,
 107         .hw.init = &(struct clk_init_data){
 108                 .name = "xtal",
 109                 .num_parents = 0,
 110                 .ops = &clk_fixed_rate_ops,
 111         },
 112 };
 113
 114 static struct meson_clk_pll meson8b_fixed_pll = {
 115         .m = {
 116                 .reg_off = HHI_MPLL_CNTL,
 117                 .shift   = 0,
 118                 .width   = 9,
 119         },
 120         .n = {
 121                 .reg_off = HHI_MPLL_CNTL,
 122                 .shift   = 9,
 123                 .width   = 5,
 124         },
 125         .od = {
 126                 .reg_off = HHI_MPLL_CNTL,
 127                 .shift   = 16,
 128                 .width   = 2,
 129         },
 130         .lock = &clk_lock,
 131         .hw.init = &(struct clk_init_data){
 132                 .name = "fixed_pll",
 133                 .ops = &meson_clk_pll_ro_ops,
 134                 .parent_names = (const char *[]){ "xtal" },
 135                 .num_parents = 1,
 136                 .flags = CLK_GET_RATE_NOCACHE,
 137         },
 138 };
 139
 140 static struct meson_clk_pll meson8b_vid_pll = {
 141         .m = {
 142                 .reg_off = HHI_VID_PLL_CNTL,
 143                 .shift   = 0,
 144                 .width   = 9,
 145         },
 146         .n = {
 147                 .reg_off = HHI_VID_PLL_CNTL,
 148                 .shift   = 9,
 149                 .width   = 5,
 150         },
 151         .od = {
 152                 .reg_off = HHI_VID_PLL_CNTL,
 153                 .shift   = 16,
 154                 .width   = 2,
 155         },
 156         .lock = &clk_lock,
 157         .hw.init = &(struct clk_init_data){
 158                 .name = "vid_pll",
 159                 .ops = &meson_clk_pll_ro_ops,
 160                 .parent_names = (const char *[]){ "xtal" },
 161                 .num_parents = 1,
 162                 .flags = CLK_GET_RATE_NOCACHE,
 163         },
 164 };
 165
 166 static struct meson_clk_pll meson8b_sys_pll = {
 167         .m = {
 168                 .reg_off = HHI_SYS_PLL_CNTL,
 169                 .shift   = 0,
 170                 .width   = 9,
 171         },
 172         .n = {
 173                 .reg_off = HHI_SYS_PLL_CNTL,
 174                 .shift   = 9,
 175                 .width   = 5,
 176         },
 177         .od = {
 178                 .reg_off = HHI_SYS_PLL_CNTL,
 179                 .shift   = 16,
 180                 .width   = 2,
 181         },
 182         .rate_table = sys_pll_rate_table,
 183         .rate_count = ARRAY_SIZE(sys_pll_rate_table),
 184         .lock = &clk_lock,
 185         .hw.init = &(struct clk_init_data){
 186                 .name = "sys_pll",
 187                 .ops = &meson_clk_pll_ops,
 188                 .parent_names = (const char *[]){ "xtal" },
 189                 .num_parents = 1,
 190                 .flags = CLK_GET_RATE_NOCACHE,
 191         },
 192 };
 193
 194 static struct clk_fixed_factor meson8b_fclk_div2 = {
 195         .mult = 1,
 196         .div = 2,
 197         .hw.init = &(struct clk_init_data){
 198                 .name = "fclk_div2",
 199                 .ops = &clk_fixed_factor_ops,
 200                 .parent_names = (const char *[]){ "fixed_pll" },
 201                 .num_parents = 1,
 202         },
 203 };
 204
 205 static struct clk_fixed_factor meson8b_fclk_div3 = {
 206         .mult = 1,
 207         .div = 3,
 208         .hw.init = &(struct clk_init_data){
 209                 .name = "fclk_div3",
 210                 .ops = &clk_fixed_factor_ops,
 211                 .parent_names = (const char *[]){ "fixed_pll" },
 212                 .num_parents = 1,
 213         },
 214 };
 215
 216 static struct clk_fixed_factor meson8b_fclk_div4 = {
 217         .mult = 1,
 218         .div = 4,
 219         .hw.init = &(struct clk_init_data){
 220                 .name = "fclk_div4",
 221                 .ops = &clk_fixed_factor_ops,
 222                 .parent_names = (const char *[]){ "fixed_pll" },
 223                 .num_parents = 1,
 224         },
 225 };
 226
 227 static struct clk_fixed_factor meson8b_fclk_div5 = {
 228         .mult = 1,
 229         .div = 5,
 230         .hw.init = &(struct clk_init_data){
 231                 .name = "fclk_div5",
 232                 .ops = &clk_fixed_factor_ops,
 233                 .parent_names = (const char *[]){ "fixed_pll" },
 234                 .num_parents = 1,
 235         },
 236 };
 237
 238 static struct clk_fixed_factor meson8b_fclk_div7 = {
 239         .mult = 1,
 240         .div = 7,
 241         .hw.init = &(struct clk_init_data){
 242                 .name = "fclk_div7",
 243                 .ops = &clk_fixed_factor_ops,
 244                 .parent_names = (const char *[]){ "fixed_pll" },
 245                 .num_parents = 1,
 246         },
 247 };
 248
 249 /*
 250  * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
 251  * post-dividers and should be modeled with their respective PLLs via the
 252  * forthcoming coordinated clock rates feature
 253  */
 254 static struct meson_clk_cpu meson8b_cpu_clk = {
 255         .reg_off = HHI_SYS_CPU_CLK_CNTL1,
 256         .div_table = cpu_div_table,
 257         .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
 258         .hw.init = &(struct clk_init_data){
 259                 .name = "cpu_clk",
 260                 .ops = &meson_clk_cpu_ops,
 261                 .parent_names = (const char *[]){ "sys_pll" },
 262                 .num_parents = 1,
 263         },
 264 };
 265
 266 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 267
 268 struct clk_mux meson8b_mpeg_clk_sel = {
 269         .reg = (void *)HHI_MPEG_CLK_CNTL,
 270         .mask = 0x7,
 271         .shift = 12,
 272         .flags = CLK_MUX_READ_ONLY,
 273         .table = mux_table_clk81,
 274         .lock = &clk_lock,
 275         .hw.init = &(struct clk_init_data){
 276                 .name = "mpeg_clk_sel",
 277                 .ops = &clk_mux_ro_ops,
 278                 /*
 279                  * FIXME bits 14:12 selects from 8 possible parents:
 280                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 281                  * fclk_div4, fclk_div3, fclk_div5
 282                  */
 283                 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
 284                         "fclk_div5" },
 285                 .num_parents = 3,
 286                 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
 287         },
 288 };
 289
 290 struct clk_divider meson8b_mpeg_clk_div = {
 291         .reg = (void *)HHI_MPEG_CLK_CNTL,
 292         .shift = 0,
 293         .width = 7,
 294         .lock = &clk_lock,
 295         .hw.init = &(struct clk_init_data){
 296                 .name = "mpeg_clk_div",
 297                 .ops = &clk_divider_ops,
 298                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 299                 .num_parents = 1,
 300                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
 301         },
 302 };
 303
 304 struct clk_gate meson8b_clk81 = {
 305         .reg = (void *)HHI_MPEG_CLK_CNTL,
 306         .bit_idx = 7,
 307         .lock = &clk_lock,
 308         .hw.init = &(struct clk_init_data){
 309                 .name = "clk81",
 310                 .ops = &clk_gate_ops,
 311                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 312                 .num_parents = 1,
 313                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
 314         },
 315 };
 316
 317 /* Everything Else (EE) domain gates */
 318
 319 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
 320 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
 321 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
 322 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
 323 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
 324 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
 325 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
 326 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
 327 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
 328 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
 329 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
 330 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
 331 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
 332 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
 333 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
 334 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
 335 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
 336 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
 337 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
 338
 339 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
 340 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
 341 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
 342 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
 343 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
 344 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
 345 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
 346 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
 347 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
 348 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
 349 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
 350 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
 351 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
 352 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
 353 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
 354 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
 355 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
 356 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
 357 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
 358 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
 359 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
 360 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
 361 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
 362 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
 363 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
 364
 365 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
 366 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
 367 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
 368 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
 369 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
 370 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
 371 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
 372 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
 373 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
 374 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
 375 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
 376 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
 377 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
 378
 379 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
 380 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
 381 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
 382 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
 383 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
 384 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
 385 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
 386 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
 387 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
 388 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
 389 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
 390 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
 391 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
 392 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
 393 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
 394 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
 395
 396 /* Always On (AO) domain gates */
 397
 398 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
 399 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
 400 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
 401 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
 402
 403 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 404         .hws = {
 405                 [CLKID_XTAL] = &meson8b_xtal.hw,
 406                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
 407                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
 408                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
 409                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
 410                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
 411                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
 412                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
 413                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
 414                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
 415                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
 416                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
 417                 [CLKID_CLK81] = &meson8b_clk81.hw,
 418                 [CLKID_DDR]                 = &meson8b_ddr.hw,
 419                 [CLKID_DOS]                 = &meson8b_dos.hw,
 420                 [CLKID_ISA]                 = &meson8b_isa.hw,
 421                 [CLKID_PL301]               = &meson8b_pl301.hw,
 422                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
 423                 [CLKID_SPICC]               = &meson8b_spicc.hw,
 424                 [CLKID_I2C]                 = &meson8b_i2c.hw,
 425                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
 426                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
 427                 [CLKID_RNG0]                = &meson8b_rng0.hw,
 428                 [CLKID_UART0]               = &meson8b_uart0.hw,
 429                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
 430                 [CLKID_STREAM]              = &meson8b_stream.hw,
 431                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
 432                 [CLKID_SDIO]                = &meson8b_sdio.hw,
 433                 [CLKID_ABUF]                = &meson8b_abuf.hw,
 434                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
 435                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
 436                 [CLKID_SPI]                 = &meson8b_spi.hw,
 437                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
 438                 [CLKID_ETH]                 = &meson8b_eth.hw,
 439                 [CLKID_DEMUX]               = &meson8b_demux.hw,
 440                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
 441                 [CLKID_IEC958]              = &meson8b_iec958.hw,
 442                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
 443                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
 444                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
 445                 [CLKID_MIXER]               = &meson8b_mixer.hw,
 446                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
 447                 [CLKID_ADC]                 = &meson8b_adc.hw,
 448                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
 449                 [CLKID_AIU]                 = &meson8b_aiu.hw,
 450                 [CLKID_UART1]               = &meson8b_uart1.hw,
 451                 [CLKID_G2D]                 = &meson8b_g2d.hw,
 452                 [CLKID_USB0]                = &meson8b_usb0.hw,
 453                 [CLKID_USB1]                = &meson8b_usb1.hw,
 454                 [CLKID_RESET]               = &meson8b_reset.hw,
 455                 [CLKID_NAND]                = &meson8b_nand.hw,
 456                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
 457                 [CLKID_USB]                 = &meson8b_usb.hw,
 458                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
 459                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
 460                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
 461                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
 462                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
 463                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
 464                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
 465                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
 466                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
 467                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
 468                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
 469                 [CLKID_DVIN]                = &meson8b_dvin.hw,
 470                 [CLKID_UART2]               = &meson8b_uart2.hw,
 471                 [CLKID_SANA]                = &meson8b_sana.hw,
 472                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
 473                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
 474                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
 475                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
 476                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
 477                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
 478                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
 479                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
 480                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
 481                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
 482                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
 483                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
 484                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
 485                 [CLKID_RNG1]                = &meson8b_rng1.hw,
 486                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
 487                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
 488                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
 489                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
 490                 [CLKID_EDP]                 = &meson8b_edp.hw,
 491                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
 492                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
 493                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
 494                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
 495         },
 496         .num = CLK_NR_CLKS,
 497 };
 498
 499 static struct meson_clk_pll *const meson8b_clk_plls[] = {
 500         &meson8b_fixed_pll,
 501         &meson8b_vid_pll,
 502         &meson8b_sys_pll,
 503 };
 504
 505 static struct clk_gate *meson8b_clk_gates[] = {
 506         &meson8b_clk81,
 507         &meson8b_ddr,
 508         &meson8b_dos,
 509         &meson8b_isa,
 510         &meson8b_pl301,
 511         &meson8b_periphs,
 512         &meson8b_spicc,
 513         &meson8b_i2c,
 514         &meson8b_sar_adc,
 515         &meson8b_smart_card,
 516         &meson8b_rng0,
 517         &meson8b_uart0,
 518         &meson8b_sdhc,
 519         &meson8b_stream,
 520         &meson8b_async_fifo,
 521         &meson8b_sdio,
 522         &meson8b_abuf,
 523         &meson8b_hiu_iface,
 524         &meson8b_assist_misc,
 525         &meson8b_spi,
 526         &meson8b_i2s_spdif,
 527         &meson8b_eth,
 528         &meson8b_demux,
 529         &meson8b_aiu_glue,
 530         &meson8b_iec958,
 531         &meson8b_i2s_out,
 532         &meson8b_amclk,
 533         &meson8b_aififo2,
 534         &meson8b_mixer,
 535         &meson8b_mixer_iface,
 536         &meson8b_adc,
 537         &meson8b_blkmv,
 538         &meson8b_aiu,
 539         &meson8b_uart1,
 540         &meson8b_g2d,
 541         &meson8b_usb0,
 542         &meson8b_usb1,
 543         &meson8b_reset,
 544         &meson8b_nand,
 545         &meson8b_dos_parser,
 546         &meson8b_usb,
 547         &meson8b_vdin1,
 548         &meson8b_ahb_arb0,
 549         &meson8b_efuse,
 550         &meson8b_boot_rom,
 551         &meson8b_ahb_data_bus,
 552         &meson8b_ahb_ctrl_bus,
 553         &meson8b_hdmi_intr_sync,
 554         &meson8b_hdmi_pclk,
 555         &meson8b_usb1_ddr_bridge,
 556         &meson8b_usb0_ddr_bridge,
 557         &meson8b_mmc_pclk,
 558         &meson8b_dvin,
 559         &meson8b_uart2,
 560         &meson8b_sana,
 561         &meson8b_vpu_intr,
 562         &meson8b_sec_ahb_ahb3_bridge,
 563         &meson8b_clk81_a9,
 564         &meson8b_vclk2_venci0,
 565         &meson8b_vclk2_venci1,
 566         &meson8b_vclk2_vencp0,
 567         &meson8b_vclk2_vencp1,
 568         &meson8b_gclk_venci_int,
 569         &meson8b_gclk_vencp_int,
 570         &meson8b_dac_clk,
 571         &meson8b_aoclk_gate,
 572         &meson8b_iec958_gate,
 573         &meson8b_enc480p,
 574         &meson8b_rng1,
 575         &meson8b_gclk_vencl_int,
 576         &meson8b_vclk2_venclmcc,
 577         &meson8b_vclk2_vencl,
 578         &meson8b_vclk2_other,
 579         &meson8b_edp,
 580         &meson8b_ao_media_cpu,
 581         &meson8b_ao_ahb_sram,
 582         &meson8b_ao_ahb_bus,
 583         &meson8b_ao_iface,
 584 };
 585
 586 static int meson8b_clkc_probe(struct platform_device *pdev)
 587 {
 588         void __iomem *clk_base;
 589         int ret, clkid, i;
 590         struct clk_hw *parent_hw;
 591         struct clk *parent_clk;
 592         struct device *dev = &pdev->dev;
 593
 594         /*  Generic clocks and PLLs */
 595         clk_base = of_iomap(dev->of_node, 1);
 596         if (!clk_base) {
 597                 pr_err("%s: Unable to map clk base\n", __func__);
 598                 return -ENXIO;
 599         }
 600
 601         /* Populate base address for PLLs */
 602         for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
 603                 meson8b_clk_plls[i]->base = clk_base;
 604
 605         /* Populate the base address for CPU clk */
 606         meson8b_cpu_clk.base = clk_base;
 607
 608         /* Populate the base address for the MPEG clks */
 609         meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
 610         meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
 611         meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
 612
 613         /* Populate base address for gates */
 614         for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
 615                 meson8b_clk_gates[i]->reg = clk_base +
 616                         (u32)meson8b_clk_gates[i]->reg;
 617
 618         /*
 619          * register all clks
 620          * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
 621          */
 622         for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
 623                 /* array might be sparse */
 624                 if (!meson8b_hw_onecell_data.hws[clkid])
 625                         continue;
 626
 627                 /* FIXME convert to devm_clk_register */
 628                 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
 629                 if (ret)
 630                         goto iounmap;
 631         }
 632
 633         /*
 634          * Register CPU clk notifier
 635          *
 636          * FIXME this is wrong for a lot of reasons. First, the muxes should be
 637          * struct clk_hw objects. Second, we shouldn't program the muxes in
 638          * notifier handlers. The tricky programming sequence will be handled
 639          * by the forthcoming coordinated clock rates mechanism once that
 640          * feature is released.
 641          *
 642          * Furthermore, looking up the parent this way is terrible. At some
 643          * point we will stop allocating a default struct clk when registering
 644          * a new clk_hw, and this hack will no longer work. Releasing the ccr
 645          * feature before that time solves the problem :-)
 646          */
 647         parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
 648         parent_clk = parent_hw->clk;
 649         ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
 650         if (ret) {
 651                 pr_err("%s: failed to register clock notifier for cpu_clk\n",
 652                                 __func__);
 653                 goto iounmap;
 654         }
 655
 656         return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
 657                         &meson8b_hw_onecell_data);
 658
 659 iounmap:
 660         iounmap(clk_base);
 661         return ret;
 662 }
 663
 664 static const struct of_device_id meson8b_clkc_match_table[] = {
 665         { .compatible = "amlogic,meson8-clkc" },
 666         { .compatible = "amlogic,meson8b-clkc" },
 667         { .compatible = "amlogic,meson8m2-clkc" },
 668         { }
 669 };
 670
 671 static struct platform_driver meson8b_driver = {
 672         .probe          = meson8b_clkc_probe,
 673         .driver         = {
 674                 .name   = "meson8b-clkc",
 675                 .of_match_table = meson8b_clkc_match_table,
 676         },
 677 };
 678
 679 builtin_platform_driver(meson8b_driver);