drivers/clk/qcom/gcc-ipq806x.c

   1 /*
   2  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34
  35 static struct clk_pll pll0 = {
  36         .l_reg = 0x30c4,
  37         .m_reg = 0x30c8,
  38         .n_reg = 0x30cc,
  39         .config_reg = 0x30d4,
  40         .mode_reg = 0x30c0,
  41         .status_reg = 0x30d8,
  42         .status_bit = 16,
  43         .clkr.hw.init = &(struct clk_init_data){
  44                 .name = "pll0",
  45                 .parent_names = (const char *[]){ "pxo" },
  46                 .num_parents = 1,
  47                 .ops = &clk_pll_ops,
  48         },
  49 };
  50
  51 static struct clk_regmap pll0_vote = {
  52         .enable_reg = 0x34c0,
  53         .enable_mask = BIT(0),
  54         .hw.init = &(struct clk_init_data){
  55                 .name = "pll0_vote",
  56                 .parent_names = (const char *[]){ "pll0" },
  57                 .num_parents = 1,
  58                 .ops = &clk_pll_vote_ops,
  59         },
  60 };
  61
  62 static struct clk_pll pll3 = {
  63         .l_reg = 0x3164,
  64         .m_reg = 0x3168,
  65         .n_reg = 0x316c,
  66         .config_reg = 0x3174,
  67         .mode_reg = 0x3160,
  68         .status_reg = 0x3178,
  69         .status_bit = 16,
  70         .clkr.hw.init = &(struct clk_init_data){
  71                 .name = "pll3",
  72                 .parent_names = (const char *[]){ "pxo" },
  73                 .num_parents = 1,
  74                 .ops = &clk_pll_ops,
  75         },
  76 };
  77
  78 static struct clk_regmap pll4_vote = {
  79         .enable_reg = 0x34c0,
  80         .enable_mask = BIT(4),
  81         .hw.init = &(struct clk_init_data){
  82                 .name = "pll4_vote",
  83                 .parent_names = (const char *[]){ "pll4" },
  84                 .num_parents = 1,
  85                 .ops = &clk_pll_vote_ops,
  86         },
  87 };
  88
  89 static struct clk_pll pll8 = {
  90         .l_reg = 0x3144,
  91         .m_reg = 0x3148,
  92         .n_reg = 0x314c,
  93         .config_reg = 0x3154,
  94         .mode_reg = 0x3140,
  95         .status_reg = 0x3158,
  96         .status_bit = 16,
  97         .clkr.hw.init = &(struct clk_init_data){
  98                 .name = "pll8",
  99                 .parent_names = (const char *[]){ "pxo" },
 100                 .num_parents = 1,
 101                 .ops = &clk_pll_ops,
 102         },
 103 };
 104
 105 static struct clk_regmap pll8_vote = {
 106         .enable_reg = 0x34c0,
 107         .enable_mask = BIT(8),
 108         .hw.init = &(struct clk_init_data){
 109                 .name = "pll8_vote",
 110                 .parent_names = (const char *[]){ "pll8" },
 111                 .num_parents = 1,
 112                 .ops = &clk_pll_vote_ops,
 113         },
 114 };
 115
 116 static struct clk_pll pll14 = {
 117         .l_reg = 0x31c4,
 118         .m_reg = 0x31c8,
 119         .n_reg = 0x31cc,
 120         .config_reg = 0x31d4,
 121         .mode_reg = 0x31c0,
 122         .status_reg = 0x31d8,
 123         .status_bit = 16,
 124         .clkr.hw.init = &(struct clk_init_data){
 125                 .name = "pll14",
 126                 .parent_names = (const char *[]){ "pxo" },
 127                 .num_parents = 1,
 128                 .ops = &clk_pll_ops,
 129         },
 130 };
 131
 132 static struct clk_regmap pll14_vote = {
 133         .enable_reg = 0x34c0,
 134         .enable_mask = BIT(14),
 135         .hw.init = &(struct clk_init_data){
 136                 .name = "pll14_vote",
 137                 .parent_names = (const char *[]){ "pll14" },
 138                 .num_parents = 1,
 139                 .ops = &clk_pll_vote_ops,
 140         },
 141 };
 142
 143 #define NSS_PLL_RATE(f, _l, _m, _n, i) \
 144         {  \
 145                 .freq = f,  \
 146                 .l = _l, \
 147                 .m = _m, \
 148                 .n = _n, \
 149                 .ibits = i, \
 150         }
 151
 152 static struct pll_freq_tbl pll18_freq_tbl[] = {
 153         NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
 154         NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
 155 };
 156
 157 static struct clk_pll pll18 = {
 158         .l_reg = 0x31a4,
 159         .m_reg = 0x31a8,
 160         .n_reg = 0x31ac,
 161         .config_reg = 0x31b4,
 162         .mode_reg = 0x31a0,
 163         .status_reg = 0x31b8,
 164         .status_bit = 16,
 165         .post_div_shift = 16,
 166         .post_div_width = 1,
 167         .freq_tbl = pll18_freq_tbl,
 168         .clkr.hw.init = &(struct clk_init_data){
 169                 .name = "pll18",
 170                 .parent_names = (const char *[]){ "pxo" },
 171                 .num_parents = 1,
 172                 .ops = &clk_pll_ops,
 173         },
 174 };
 175
 176 enum {
 177         P_PXO,
 178         P_PLL8,
 179         P_PLL3,
 180         P_PLL0,
 181         P_CXO,
 182         P_PLL14,
 183         P_PLL18,
 184 };
 185
 186 static const struct parent_map gcc_pxo_pll8_map[] = {
 187         { P_PXO, 0 },
 188         { P_PLL8, 3 }
 189 };
 190
 191 static const char * const gcc_pxo_pll8[] = {
 192         "pxo",
 193         "pll8_vote",
 194 };
 195
 196 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
 197         { P_PXO, 0 },
 198         { P_PLL8, 3 },
 199         { P_CXO, 5 }
 200 };
 201
 202 static const char * const gcc_pxo_pll8_cxo[] = {
 203         "pxo",
 204         "pll8_vote",
 205         "cxo",
 206 };
 207
 208 static const struct parent_map gcc_pxo_pll3_map[] = {
 209         { P_PXO, 0 },
 210         { P_PLL3, 1 }
 211 };
 212
 213 static const struct parent_map gcc_pxo_pll3_sata_map[] = {
 214         { P_PXO, 0 },
 215         { P_PLL3, 6 }
 216 };
 217
 218 static const char * const gcc_pxo_pll3[] = {
 219         "pxo",
 220         "pll3",
 221 };
 222
 223 static const struct parent_map gcc_pxo_pll8_pll0[] = {
 224         { P_PXO, 0 },
 225         { P_PLL8, 3 },
 226         { P_PLL0, 2 }
 227 };
 228
 229 static const char * const gcc_pxo_pll8_pll0_map[] = {
 230         "pxo",
 231         "pll8_vote",
 232         "pll0_vote",
 233 };
 234
 235 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
 236         { P_PXO, 0 },
 237         { P_PLL8, 4 },
 238         { P_PLL0, 2 },
 239         { P_PLL14, 5 },
 240         { P_PLL18, 1 }
 241 };
 242
 243 static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
 244         "pxo",
 245         "pll8_vote",
 246         "pll0_vote",
 247         "pll14",
 248         "pll18",
 249 };
 250
 251 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 252         {  1843200, P_PLL8, 2,  6, 625 },
 253         {  3686400, P_PLL8, 2, 12, 625 },
 254         {  7372800, P_PLL8, 2, 24, 625 },
 255         { 14745600, P_PLL8, 2, 48, 625 },
 256         { 16000000, P_PLL8, 4,  1,   6 },
 257         { 24000000, P_PLL8, 4,  1,   4 },
 258         { 32000000, P_PLL8, 4,  1,   3 },
 259         { 40000000, P_PLL8, 1,  5,  48 },
 260         { 46400000, P_PLL8, 1, 29, 240 },
 261         { 48000000, P_PLL8, 4,  1,   2 },
 262         { 51200000, P_PLL8, 1,  2,  15 },
 263         { 56000000, P_PLL8, 1,  7,  48 },
 264         { 58982400, P_PLL8, 1, 96, 625 },
 265         { 64000000, P_PLL8, 2,  1,   3 },
 266         { }
 267 };
 268
 269 static struct clk_rcg gsbi1_uart_src = {
 270         .ns_reg = 0x29d4,
 271         .md_reg = 0x29d0,
 272         .mn = {
 273                 .mnctr_en_bit = 8,
 274                 .mnctr_reset_bit = 7,
 275                 .mnctr_mode_shift = 5,
 276                 .n_val_shift = 16,
 277                 .m_val_shift = 16,
 278                 .width = 16,
 279         },
 280         .p = {
 281                 .pre_div_shift = 3,
 282                 .pre_div_width = 2,
 283         },
 284         .s = {
 285                 .src_sel_shift = 0,
 286                 .parent_map = gcc_pxo_pll8_map,
 287         },
 288         .freq_tbl = clk_tbl_gsbi_uart,
 289         .clkr = {
 290                 .enable_reg = 0x29d4,
 291                 .enable_mask = BIT(11),
 292                 .hw.init = &(struct clk_init_data){
 293                         .name = "gsbi1_uart_src",
 294                         .parent_names = gcc_pxo_pll8,
 295                         .num_parents = 2,
 296                         .ops = &clk_rcg_ops,
 297                         .flags = CLK_SET_PARENT_GATE,
 298                 },
 299         },
 300 };
 301
 302 static struct clk_branch gsbi1_uart_clk = {
 303         .halt_reg = 0x2fcc,
 304         .halt_bit = 12,
 305         .clkr = {
 306                 .enable_reg = 0x29d4,
 307                 .enable_mask = BIT(9),
 308                 .hw.init = &(struct clk_init_data){
 309                         .name = "gsbi1_uart_clk",
 310                         .parent_names = (const char *[]){
 311                                 "gsbi1_uart_src",
 312                         },
 313                         .num_parents = 1,
 314                         .ops = &clk_branch_ops,
 315                         .flags = CLK_SET_RATE_PARENT,
 316                 },
 317         },
 318 };
 319
 320 static struct clk_rcg gsbi2_uart_src = {
 321         .ns_reg = 0x29f4,
 322         .md_reg = 0x29f0,
 323         .mn = {
 324                 .mnctr_en_bit = 8,
 325                 .mnctr_reset_bit = 7,
 326                 .mnctr_mode_shift = 5,
 327                 .n_val_shift = 16,
 328                 .m_val_shift = 16,
 329                 .width = 16,
 330         },
 331         .p = {
 332                 .pre_div_shift = 3,
 333                 .pre_div_width = 2,
 334         },
 335         .s = {
 336                 .src_sel_shift = 0,
 337                 .parent_map = gcc_pxo_pll8_map,
 338         },
 339         .freq_tbl = clk_tbl_gsbi_uart,
 340         .clkr = {
 341                 .enable_reg = 0x29f4,
 342                 .enable_mask = BIT(11),
 343                 .hw.init = &(struct clk_init_data){
 344                         .name = "gsbi2_uart_src",
 345                         .parent_names = gcc_pxo_pll8,
 346                         .num_parents = 2,
 347                         .ops = &clk_rcg_ops,
 348                         .flags = CLK_SET_PARENT_GATE,
 349                 },
 350         },
 351 };
 352
 353 static struct clk_branch gsbi2_uart_clk = {
 354         .halt_reg = 0x2fcc,
 355         .halt_bit = 8,
 356         .clkr = {
 357                 .enable_reg = 0x29f4,
 358                 .enable_mask = BIT(9),
 359                 .hw.init = &(struct clk_init_data){
 360                         .name = "gsbi2_uart_clk",
 361                         .parent_names = (const char *[]){
 362                                 "gsbi2_uart_src",
 363                         },
 364                         .num_parents = 1,
 365                         .ops = &clk_branch_ops,
 366                         .flags = CLK_SET_RATE_PARENT,
 367                 },
 368         },
 369 };
 370
 371 static struct clk_rcg gsbi4_uart_src = {
 372         .ns_reg = 0x2a34,
 373         .md_reg = 0x2a30,
 374         .mn = {
 375                 .mnctr_en_bit = 8,
 376                 .mnctr_reset_bit = 7,
 377                 .mnctr_mode_shift = 5,
 378                 .n_val_shift = 16,
 379                 .m_val_shift = 16,
 380                 .width = 16,
 381         },
 382         .p = {
 383                 .pre_div_shift = 3,
 384                 .pre_div_width = 2,
 385         },
 386         .s = {
 387                 .src_sel_shift = 0,
 388                 .parent_map = gcc_pxo_pll8_map,
 389         },
 390         .freq_tbl = clk_tbl_gsbi_uart,
 391         .clkr = {
 392                 .enable_reg = 0x2a34,
 393                 .enable_mask = BIT(11),
 394                 .hw.init = &(struct clk_init_data){
 395                         .name = "gsbi4_uart_src",
 396                         .parent_names = gcc_pxo_pll8,
 397                         .num_parents = 2,
 398                         .ops = &clk_rcg_ops,
 399                         .flags = CLK_SET_PARENT_GATE,
 400                 },
 401         },
 402 };
 403
 404 static struct clk_branch gsbi4_uart_clk = {
 405         .halt_reg = 0x2fd0,
 406         .halt_bit = 26,
 407         .clkr = {
 408                 .enable_reg = 0x2a34,
 409                 .enable_mask = BIT(9),
 410                 .hw.init = &(struct clk_init_data){
 411                         .name = "gsbi4_uart_clk",
 412                         .parent_names = (const char *[]){
 413                                 "gsbi4_uart_src",
 414                         },
 415                         .num_parents = 1,
 416                         .ops = &clk_branch_ops,
 417                         .flags = CLK_SET_RATE_PARENT,
 418                 },
 419         },
 420 };
 421
 422 static struct clk_rcg gsbi5_uart_src = {
 423         .ns_reg = 0x2a54,
 424         .md_reg = 0x2a50,
 425         .mn = {
 426                 .mnctr_en_bit = 8,
 427                 .mnctr_reset_bit = 7,
 428                 .mnctr_mode_shift = 5,
 429                 .n_val_shift = 16,
 430                 .m_val_shift = 16,
 431                 .width = 16,
 432         },
 433         .p = {
 434                 .pre_div_shift = 3,
 435                 .pre_div_width = 2,
 436         },
 437         .s = {
 438                 .src_sel_shift = 0,
 439                 .parent_map = gcc_pxo_pll8_map,
 440         },
 441         .freq_tbl = clk_tbl_gsbi_uart,
 442         .clkr = {
 443                 .enable_reg = 0x2a54,
 444                 .enable_mask = BIT(11),
 445                 .hw.init = &(struct clk_init_data){
 446                         .name = "gsbi5_uart_src",
 447                         .parent_names = gcc_pxo_pll8,
 448                         .num_parents = 2,
 449                         .ops = &clk_rcg_ops,
 450                         .flags = CLK_SET_PARENT_GATE,
 451                 },
 452         },
 453 };
 454
 455 static struct clk_branch gsbi5_uart_clk = {
 456         .halt_reg = 0x2fd0,
 457         .halt_bit = 22,
 458         .clkr = {
 459                 .enable_reg = 0x2a54,
 460                 .enable_mask = BIT(9),
 461                 .hw.init = &(struct clk_init_data){
 462                         .name = "gsbi5_uart_clk",
 463                         .parent_names = (const char *[]){
 464                                 "gsbi5_uart_src",
 465                         },
 466                         .num_parents = 1,
 467                         .ops = &clk_branch_ops,
 468                         .flags = CLK_SET_RATE_PARENT,
 469                 },
 470         },
 471 };
 472
 473 static struct clk_rcg gsbi6_uart_src = {
 474         .ns_reg = 0x2a74,
 475         .md_reg = 0x2a70,
 476         .mn = {
 477                 .mnctr_en_bit = 8,
 478                 .mnctr_reset_bit = 7,
 479                 .mnctr_mode_shift = 5,
 480                 .n_val_shift = 16,
 481                 .m_val_shift = 16,
 482                 .width = 16,
 483         },
 484         .p = {
 485                 .pre_div_shift = 3,
 486                 .pre_div_width = 2,
 487         },
 488         .s = {
 489                 .src_sel_shift = 0,
 490                 .parent_map = gcc_pxo_pll8_map,
 491         },
 492         .freq_tbl = clk_tbl_gsbi_uart,
 493         .clkr = {
 494                 .enable_reg = 0x2a74,
 495                 .enable_mask = BIT(11),
 496                 .hw.init = &(struct clk_init_data){
 497                         .name = "gsbi6_uart_src",
 498                         .parent_names = gcc_pxo_pll8,
 499                         .num_parents = 2,
 500                         .ops = &clk_rcg_ops,
 501                         .flags = CLK_SET_PARENT_GATE,
 502                 },
 503         },
 504 };
 505
 506 static struct clk_branch gsbi6_uart_clk = {
 507         .halt_reg = 0x2fd0,
 508         .halt_bit = 18,
 509         .clkr = {
 510                 .enable_reg = 0x2a74,
 511                 .enable_mask = BIT(9),
 512                 .hw.init = &(struct clk_init_data){
 513                         .name = "gsbi6_uart_clk",
 514                         .parent_names = (const char *[]){
 515                                 "gsbi6_uart_src",
 516                         },
 517                         .num_parents = 1,
 518                         .ops = &clk_branch_ops,
 519                         .flags = CLK_SET_RATE_PARENT,
 520                 },
 521         },
 522 };
 523
 524 static struct clk_rcg gsbi7_uart_src = {
 525         .ns_reg = 0x2a94,
 526         .md_reg = 0x2a90,
 527         .mn = {
 528                 .mnctr_en_bit = 8,
 529                 .mnctr_reset_bit = 7,
 530                 .mnctr_mode_shift = 5,
 531                 .n_val_shift = 16,
 532                 .m_val_shift = 16,
 533                 .width = 16,
 534         },
 535         .p = {
 536                 .pre_div_shift = 3,
 537                 .pre_div_width = 2,
 538         },
 539         .s = {
 540                 .src_sel_shift = 0,
 541                 .parent_map = gcc_pxo_pll8_map,
 542         },
 543         .freq_tbl = clk_tbl_gsbi_uart,
 544         .clkr = {
 545                 .enable_reg = 0x2a94,
 546                 .enable_mask = BIT(11),
 547                 .hw.init = &(struct clk_init_data){
 548                         .name = "gsbi7_uart_src",
 549                         .parent_names = gcc_pxo_pll8,
 550                         .num_parents = 2,
 551                         .ops = &clk_rcg_ops,
 552                         .flags = CLK_SET_PARENT_GATE,
 553                 },
 554         },
 555 };
 556
 557 static struct clk_branch gsbi7_uart_clk = {
 558         .halt_reg = 0x2fd0,
 559         .halt_bit = 14,
 560         .clkr = {
 561                 .enable_reg = 0x2a94,
 562                 .enable_mask = BIT(9),
 563                 .hw.init = &(struct clk_init_data){
 564                         .name = "gsbi7_uart_clk",
 565                         .parent_names = (const char *[]){
 566                                 "gsbi7_uart_src",
 567                         },
 568                         .num_parents = 1,
 569                         .ops = &clk_branch_ops,
 570                         .flags = CLK_SET_RATE_PARENT,
 571                 },
 572         },
 573 };
 574
 575 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 576         {  1100000, P_PXO,  1, 2, 49 },
 577         {  5400000, P_PXO,  1, 1,  5 },
 578         { 10800000, P_PXO,  1, 2,  5 },
 579         { 15060000, P_PLL8, 1, 2, 51 },
 580         { 24000000, P_PLL8, 4, 1,  4 },
 581         { 25000000, P_PXO,  1, 0,  0 },
 582         { 25600000, P_PLL8, 1, 1, 15 },
 583         { 48000000, P_PLL8, 4, 1,  2 },
 584         { 51200000, P_PLL8, 1, 2, 15 },
 585         { }
 586 };
 587
 588 static struct clk_rcg gsbi1_qup_src = {
 589         .ns_reg = 0x29cc,
 590         .md_reg = 0x29c8,
 591         .mn = {
 592                 .mnctr_en_bit = 8,
 593                 .mnctr_reset_bit = 7,
 594                 .mnctr_mode_shift = 5,
 595                 .n_val_shift = 16,
 596                 .m_val_shift = 16,
 597                 .width = 8,
 598         },
 599         .p = {
 600                 .pre_div_shift = 3,
 601                 .pre_div_width = 2,
 602         },
 603         .s = {
 604                 .src_sel_shift = 0,
 605                 .parent_map = gcc_pxo_pll8_map,
 606         },
 607         .freq_tbl = clk_tbl_gsbi_qup,
 608         .clkr = {
 609                 .enable_reg = 0x29cc,
 610                 .enable_mask = BIT(11),
 611                 .hw.init = &(struct clk_init_data){
 612                         .name = "gsbi1_qup_src",
 613                         .parent_names = gcc_pxo_pll8,
 614                         .num_parents = 2,
 615                         .ops = &clk_rcg_ops,
 616                         .flags = CLK_SET_PARENT_GATE,
 617                 },
 618         },
 619 };
 620
 621 static struct clk_branch gsbi1_qup_clk = {
 622         .halt_reg = 0x2fcc,
 623         .halt_bit = 11,
 624         .clkr = {
 625                 .enable_reg = 0x29cc,
 626                 .enable_mask = BIT(9),
 627                 .hw.init = &(struct clk_init_data){
 628                         .name = "gsbi1_qup_clk",
 629                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 630                         .num_parents = 1,
 631                         .ops = &clk_branch_ops,
 632                         .flags = CLK_SET_RATE_PARENT,
 633                 },
 634         },
 635 };
 636
 637 static struct clk_rcg gsbi2_qup_src = {
 638         .ns_reg = 0x29ec,
 639         .md_reg = 0x29e8,
 640         .mn = {
 641                 .mnctr_en_bit = 8,
 642                 .mnctr_reset_bit = 7,
 643                 .mnctr_mode_shift = 5,
 644                 .n_val_shift = 16,
 645                 .m_val_shift = 16,
 646                 .width = 8,
 647         },
 648         .p = {
 649                 .pre_div_shift = 3,
 650                 .pre_div_width = 2,
 651         },
 652         .s = {
 653                 .src_sel_shift = 0,
 654                 .parent_map = gcc_pxo_pll8_map,
 655         },
 656         .freq_tbl = clk_tbl_gsbi_qup,
 657         .clkr = {
 658                 .enable_reg = 0x29ec,
 659                 .enable_mask = BIT(11),
 660                 .hw.init = &(struct clk_init_data){
 661                         .name = "gsbi2_qup_src",
 662                         .parent_names = gcc_pxo_pll8,
 663                         .num_parents = 2,
 664                         .ops = &clk_rcg_ops,
 665                         .flags = CLK_SET_PARENT_GATE,
 666                 },
 667         },
 668 };
 669
 670 static struct clk_branch gsbi2_qup_clk = {
 671         .halt_reg = 0x2fcc,
 672         .halt_bit = 6,
 673         .clkr = {
 674                 .enable_reg = 0x29ec,
 675                 .enable_mask = BIT(9),
 676                 .hw.init = &(struct clk_init_data){
 677                         .name = "gsbi2_qup_clk",
 678                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
 679                         .num_parents = 1,
 680                         .ops = &clk_branch_ops,
 681                         .flags = CLK_SET_RATE_PARENT,
 682                 },
 683         },
 684 };
 685
 686 static struct clk_rcg gsbi4_qup_src = {
 687         .ns_reg = 0x2a2c,
 688         .md_reg = 0x2a28,
 689         .mn = {
 690                 .mnctr_en_bit = 8,
 691                 .mnctr_reset_bit = 7,
 692                 .mnctr_mode_shift = 5,
 693                 .n_val_shift = 16,
 694                 .m_val_shift = 16,
 695                 .width = 8,
 696         },
 697         .p = {
 698                 .pre_div_shift = 3,
 699                 .pre_div_width = 2,
 700         },
 701         .s = {
 702                 .src_sel_shift = 0,
 703                 .parent_map = gcc_pxo_pll8_map,
 704         },
 705         .freq_tbl = clk_tbl_gsbi_qup,
 706         .clkr = {
 707                 .enable_reg = 0x2a2c,
 708                 .enable_mask = BIT(11),
 709                 .hw.init = &(struct clk_init_data){
 710                         .name = "gsbi4_qup_src",
 711                         .parent_names = gcc_pxo_pll8,
 712                         .num_parents = 2,
 713                         .ops = &clk_rcg_ops,
 714                         .flags = CLK_SET_PARENT_GATE,
 715                 },
 716         },
 717 };
 718
 719 static struct clk_branch gsbi4_qup_clk = {
 720         .halt_reg = 0x2fd0,
 721         .halt_bit = 24,
 722         .clkr = {
 723                 .enable_reg = 0x2a2c,
 724                 .enable_mask = BIT(9),
 725                 .hw.init = &(struct clk_init_data){
 726                         .name = "gsbi4_qup_clk",
 727                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
 728                         .num_parents = 1,
 729                         .ops = &clk_branch_ops,
 730                         .flags = CLK_SET_RATE_PARENT,
 731                 },
 732         },
 733 };
 734
 735 static struct clk_rcg gsbi5_qup_src = {
 736         .ns_reg = 0x2a4c,
 737         .md_reg = 0x2a48,
 738         .mn = {
 739                 .mnctr_en_bit = 8,
 740                 .mnctr_reset_bit = 7,
 741                 .mnctr_mode_shift = 5,
 742                 .n_val_shift = 16,
 743                 .m_val_shift = 16,
 744                 .width = 8,
 745         },
 746         .p = {
 747                 .pre_div_shift = 3,
 748                 .pre_div_width = 2,
 749         },
 750         .s = {
 751                 .src_sel_shift = 0,
 752                 .parent_map = gcc_pxo_pll8_map,
 753         },
 754         .freq_tbl = clk_tbl_gsbi_qup,
 755         .clkr = {
 756                 .enable_reg = 0x2a4c,
 757                 .enable_mask = BIT(11),
 758                 .hw.init = &(struct clk_init_data){
 759                         .name = "gsbi5_qup_src",
 760                         .parent_names = gcc_pxo_pll8,
 761                         .num_parents = 2,
 762                         .ops = &clk_rcg_ops,
 763                         .flags = CLK_SET_PARENT_GATE,
 764                 },
 765         },
 766 };
 767
 768 static struct clk_branch gsbi5_qup_clk = {
 769         .halt_reg = 0x2fd0,
 770         .halt_bit = 20,
 771         .clkr = {
 772                 .enable_reg = 0x2a4c,
 773                 .enable_mask = BIT(9),
 774                 .hw.init = &(struct clk_init_data){
 775                         .name = "gsbi5_qup_clk",
 776                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
 777                         .num_parents = 1,
 778                         .ops = &clk_branch_ops,
 779                         .flags = CLK_SET_RATE_PARENT,
 780                 },
 781         },
 782 };
 783
 784 static struct clk_rcg gsbi6_qup_src = {
 785         .ns_reg = 0x2a6c,
 786         .md_reg = 0x2a68,
 787         .mn = {
 788                 .mnctr_en_bit = 8,
 789                 .mnctr_reset_bit = 7,
 790                 .mnctr_mode_shift = 5,
 791                 .n_val_shift = 16,
 792                 .m_val_shift = 16,
 793                 .width = 8,
 794         },
 795         .p = {
 796                 .pre_div_shift = 3,
 797                 .pre_div_width = 2,
 798         },
 799         .s = {
 800                 .src_sel_shift = 0,
 801                 .parent_map = gcc_pxo_pll8_map,
 802         },
 803         .freq_tbl = clk_tbl_gsbi_qup,
 804         .clkr = {
 805                 .enable_reg = 0x2a6c,
 806                 .enable_mask = BIT(11),
 807                 .hw.init = &(struct clk_init_data){
 808                         .name = "gsbi6_qup_src",
 809                         .parent_names = gcc_pxo_pll8,
 810                         .num_parents = 2,
 811                         .ops = &clk_rcg_ops,
 812                         .flags = CLK_SET_PARENT_GATE,
 813                 },
 814         },
 815 };
 816
 817 static struct clk_branch gsbi6_qup_clk = {
 818         .halt_reg = 0x2fd0,
 819         .halt_bit = 16,
 820         .clkr = {
 821                 .enable_reg = 0x2a6c,
 822                 .enable_mask = BIT(9),
 823                 .hw.init = &(struct clk_init_data){
 824                         .name = "gsbi6_qup_clk",
 825                         .parent_names = (const char *[]){ "gsbi6_qup_src" },
 826                         .num_parents = 1,
 827                         .ops = &clk_branch_ops,
 828                         .flags = CLK_SET_RATE_PARENT,
 829                 },
 830         },
 831 };
 832
 833 static struct clk_rcg gsbi7_qup_src = {
 834         .ns_reg = 0x2a8c,
 835         .md_reg = 0x2a88,
 836         .mn = {
 837                 .mnctr_en_bit = 8,
 838                 .mnctr_reset_bit = 7,
 839                 .mnctr_mode_shift = 5,
 840                 .n_val_shift = 16,
 841                 .m_val_shift = 16,
 842                 .width = 8,
 843         },
 844         .p = {
 845                 .pre_div_shift = 3,
 846                 .pre_div_width = 2,
 847         },
 848         .s = {
 849                 .src_sel_shift = 0,
 850                 .parent_map = gcc_pxo_pll8_map,
 851         },
 852         .freq_tbl = clk_tbl_gsbi_qup,
 853         .clkr = {
 854                 .enable_reg = 0x2a8c,
 855                 .enable_mask = BIT(11),
 856                 .hw.init = &(struct clk_init_data){
 857                         .name = "gsbi7_qup_src",
 858                         .parent_names = gcc_pxo_pll8,
 859                         .num_parents = 2,
 860                         .ops = &clk_rcg_ops,
 861                         .flags = CLK_SET_PARENT_GATE,
 862                 },
 863         },
 864 };
 865
 866 static struct clk_branch gsbi7_qup_clk = {
 867         .halt_reg = 0x2fd0,
 868         .halt_bit = 12,
 869         .clkr = {
 870                 .enable_reg = 0x2a8c,
 871                 .enable_mask = BIT(9),
 872                 .hw.init = &(struct clk_init_data){
 873                         .name = "gsbi7_qup_clk",
 874                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
 875                         .num_parents = 1,
 876                         .ops = &clk_branch_ops,
 877                         .flags = CLK_SET_RATE_PARENT,
 878                 },
 879         },
 880 };
 881
 882 static struct clk_branch gsbi1_h_clk = {
 883         .hwcg_reg = 0x29c0,
 884         .hwcg_bit = 6,
 885         .halt_reg = 0x2fcc,
 886         .halt_bit = 13,
 887         .clkr = {
 888                 .enable_reg = 0x29c0,
 889                 .enable_mask = BIT(4),
 890                 .hw.init = &(struct clk_init_data){
 891                         .name = "gsbi1_h_clk",
 892                         .ops = &clk_branch_ops,
 893                 },
 894         },
 895 };
 896
 897 static struct clk_branch gsbi2_h_clk = {
 898         .hwcg_reg = 0x29e0,
 899         .hwcg_bit = 6,
 900         .halt_reg = 0x2fcc,
 901         .halt_bit = 9,
 902         .clkr = {
 903                 .enable_reg = 0x29e0,
 904                 .enable_mask = BIT(4),
 905                 .hw.init = &(struct clk_init_data){
 906                         .name = "gsbi2_h_clk",
 907                         .ops = &clk_branch_ops,
 908                 },
 909         },
 910 };
 911
 912 static struct clk_branch gsbi4_h_clk = {
 913         .hwcg_reg = 0x2a20,
 914         .hwcg_bit = 6,
 915         .halt_reg = 0x2fd0,
 916         .halt_bit = 27,
 917         .clkr = {
 918                 .enable_reg = 0x2a20,
 919                 .enable_mask = BIT(4),
 920                 .hw.init = &(struct clk_init_data){
 921                         .name = "gsbi4_h_clk",
 922                         .ops = &clk_branch_ops,
 923                 },
 924         },
 925 };
 926
 927 static struct clk_branch gsbi5_h_clk = {
 928         .hwcg_reg = 0x2a40,
 929         .hwcg_bit = 6,
 930         .halt_reg = 0x2fd0,
 931         .halt_bit = 23,
 932         .clkr = {
 933                 .enable_reg = 0x2a40,
 934                 .enable_mask = BIT(4),
 935                 .hw.init = &(struct clk_init_data){
 936                         .name = "gsbi5_h_clk",
 937                         .ops = &clk_branch_ops,
 938                 },
 939         },
 940 };
 941
 942 static struct clk_branch gsbi6_h_clk = {
 943         .hwcg_reg = 0x2a60,
 944         .hwcg_bit = 6,
 945         .halt_reg = 0x2fd0,
 946         .halt_bit = 19,
 947         .clkr = {
 948                 .enable_reg = 0x2a60,
 949                 .enable_mask = BIT(4),
 950                 .hw.init = &(struct clk_init_data){
 951                         .name = "gsbi6_h_clk",
 952                         .ops = &clk_branch_ops,
 953                 },
 954         },
 955 };
 956
 957 static struct clk_branch gsbi7_h_clk = {
 958         .hwcg_reg = 0x2a80,
 959         .hwcg_bit = 6,
 960         .halt_reg = 0x2fd0,
 961         .halt_bit = 15,
 962         .clkr = {
 963                 .enable_reg = 0x2a80,
 964                 .enable_mask = BIT(4),
 965                 .hw.init = &(struct clk_init_data){
 966                         .name = "gsbi7_h_clk",
 967                         .ops = &clk_branch_ops,
 968                 },
 969         },
 970 };
 971
 972 static const struct freq_tbl clk_tbl_gp[] = {
 973         { 12500000, P_PXO,  2, 0, 0 },
 974         { 25000000, P_PXO,  1, 0, 0 },
 975         { 64000000, P_PLL8, 2, 1, 3 },
 976         { 76800000, P_PLL8, 1, 1, 5 },
 977         { 96000000, P_PLL8, 4, 0, 0 },
 978         { 128000000, P_PLL8, 3, 0, 0 },
 979         { 192000000, P_PLL8, 2, 0, 0 },
 980         { }
 981 };
 982
 983 static struct clk_rcg gp0_src = {
 984         .ns_reg = 0x2d24,
 985         .md_reg = 0x2d00,
 986         .mn = {
 987                 .mnctr_en_bit = 8,
 988                 .mnctr_reset_bit = 7,
 989                 .mnctr_mode_shift = 5,
 990                 .n_val_shift = 16,
 991                 .m_val_shift = 16,
 992                 .width = 8,
 993         },
 994         .p = {
 995                 .pre_div_shift = 3,
 996                 .pre_div_width = 2,
 997         },
 998         .s = {
 999                 .src_sel_shift = 0,
1000                 .parent_map = gcc_pxo_pll8_cxo_map,
1001         },
1002         .freq_tbl = clk_tbl_gp,
1003         .clkr = {
1004                 .enable_reg = 0x2d24,
1005                 .enable_mask = BIT(11),
1006                 .hw.init = &(struct clk_init_data){
1007                         .name = "gp0_src",
1008                         .parent_names = gcc_pxo_pll8_cxo,
1009                         .num_parents = 3,
1010                         .ops = &clk_rcg_ops,
1011                         .flags = CLK_SET_PARENT_GATE,
1012                 },
1013         }
1014 };
1015
1016 static struct clk_branch gp0_clk = {
1017         .halt_reg = 0x2fd8,
1018         .halt_bit = 7,
1019         .clkr = {
1020                 .enable_reg = 0x2d24,
1021                 .enable_mask = BIT(9),
1022                 .hw.init = &(struct clk_init_data){
1023                         .name = "gp0_clk",
1024                         .parent_names = (const char *[]){ "gp0_src" },
1025                         .num_parents = 1,
1026                         .ops = &clk_branch_ops,
1027                         .flags = CLK_SET_RATE_PARENT,
1028                 },
1029         },
1030 };
1031
1032 static struct clk_rcg gp1_src = {
1033         .ns_reg = 0x2d44,
1034         .md_reg = 0x2d40,
1035         .mn = {
1036                 .mnctr_en_bit = 8,
1037                 .mnctr_reset_bit = 7,
1038                 .mnctr_mode_shift = 5,
1039                 .n_val_shift = 16,
1040                 .m_val_shift = 16,
1041                 .width = 8,
1042         },
1043         .p = {
1044                 .pre_div_shift = 3,
1045                 .pre_div_width = 2,
1046         },
1047         .s = {
1048                 .src_sel_shift = 0,
1049                 .parent_map = gcc_pxo_pll8_cxo_map,
1050         },
1051         .freq_tbl = clk_tbl_gp,
1052         .clkr = {
1053                 .enable_reg = 0x2d44,
1054                 .enable_mask = BIT(11),
1055                 .hw.init = &(struct clk_init_data){
1056                         .name = "gp1_src",
1057                         .parent_names = gcc_pxo_pll8_cxo,
1058                         .num_parents = 3,
1059                         .ops = &clk_rcg_ops,
1060                         .flags = CLK_SET_RATE_GATE,
1061                 },
1062         }
1063 };
1064
1065 static struct clk_branch gp1_clk = {
1066         .halt_reg = 0x2fd8,
1067         .halt_bit = 6,
1068         .clkr = {
1069                 .enable_reg = 0x2d44,
1070                 .enable_mask = BIT(9),
1071                 .hw.init = &(struct clk_init_data){
1072                         .name = "gp1_clk",
1073                         .parent_names = (const char *[]){ "gp1_src" },
1074                         .num_parents = 1,
1075                         .ops = &clk_branch_ops,
1076                         .flags = CLK_SET_RATE_PARENT,
1077                 },
1078         },
1079 };
1080
1081 static struct clk_rcg gp2_src = {
1082         .ns_reg = 0x2d64,
1083         .md_reg = 0x2d60,
1084         .mn = {
1085                 .mnctr_en_bit = 8,
1086                 .mnctr_reset_bit = 7,
1087                 .mnctr_mode_shift = 5,
1088                 .n_val_shift = 16,
1089                 .m_val_shift = 16,
1090                 .width = 8,
1091         },
1092         .p = {
1093                 .pre_div_shift = 3,
1094                 .pre_div_width = 2,
1095         },
1096         .s = {
1097                 .src_sel_shift = 0,
1098                 .parent_map = gcc_pxo_pll8_cxo_map,
1099         },
1100         .freq_tbl = clk_tbl_gp,
1101         .clkr = {
1102                 .enable_reg = 0x2d64,
1103                 .enable_mask = BIT(11),
1104                 .hw.init = &(struct clk_init_data){
1105                         .name = "gp2_src",
1106                         .parent_names = gcc_pxo_pll8_cxo,
1107                         .num_parents = 3,
1108                         .ops = &clk_rcg_ops,
1109                         .flags = CLK_SET_RATE_GATE,
1110                 },
1111         }
1112 };
1113
1114 static struct clk_branch gp2_clk = {
1115         .halt_reg = 0x2fd8,
1116         .halt_bit = 5,
1117         .clkr = {
1118                 .enable_reg = 0x2d64,
1119                 .enable_mask = BIT(9),
1120                 .hw.init = &(struct clk_init_data){
1121                         .name = "gp2_clk",
1122                         .parent_names = (const char *[]){ "gp2_src" },
1123                         .num_parents = 1,
1124                         .ops = &clk_branch_ops,
1125                         .flags = CLK_SET_RATE_PARENT,
1126                 },
1127         },
1128 };
1129
1130 static struct clk_branch pmem_clk = {
1131         .hwcg_reg = 0x25a0,
1132         .hwcg_bit = 6,
1133         .halt_reg = 0x2fc8,
1134         .halt_bit = 20,
1135         .clkr = {
1136                 .enable_reg = 0x25a0,
1137                 .enable_mask = BIT(4),
1138                 .hw.init = &(struct clk_init_data){
1139                         .name = "pmem_clk",
1140                         .ops = &clk_branch_ops,
1141                 },
1142         },
1143 };
1144
1145 static struct clk_rcg prng_src = {
1146         .ns_reg = 0x2e80,
1147         .p = {
1148                 .pre_div_shift = 3,
1149                 .pre_div_width = 4,
1150         },
1151         .s = {
1152                 .src_sel_shift = 0,
1153                 .parent_map = gcc_pxo_pll8_map,
1154         },
1155         .clkr = {
1156                 .hw.init = &(struct clk_init_data){
1157                         .name = "prng_src",
1158                         .parent_names = gcc_pxo_pll8,
1159                         .num_parents = 2,
1160                         .ops = &clk_rcg_ops,
1161                 },
1162         },
1163 };
1164
1165 static struct clk_branch prng_clk = {
1166         .halt_reg = 0x2fd8,
1167         .halt_check = BRANCH_HALT_VOTED,
1168         .halt_bit = 10,
1169         .clkr = {
1170                 .enable_reg = 0x3080,
1171                 .enable_mask = BIT(10),
1172                 .hw.init = &(struct clk_init_data){
1173                         .name = "prng_clk",
1174                         .parent_names = (const char *[]){ "prng_src" },
1175                         .num_parents = 1,
1176                         .ops = &clk_branch_ops,
1177                 },
1178         },
1179 };
1180
1181 static const struct freq_tbl clk_tbl_sdc[] = {
1182         {    200000, P_PXO,   2, 2, 125 },
1183         {    400000, P_PLL8,  4, 1, 240 },
1184         {  16000000, P_PLL8,  4, 1,   6 },
1185         {  17070000, P_PLL8,  1, 2,  45 },
1186         {  20210000, P_PLL8,  1, 1,  19 },
1187         {  24000000, P_PLL8,  4, 1,   4 },
1188         {  48000000, P_PLL8,  4, 1,   2 },
1189         {  64000000, P_PLL8,  3, 1,   2 },
1190         {  96000000, P_PLL8,  4, 0,   0 },
1191         { 192000000, P_PLL8,  2, 0,   0 },
1192         { }
1193 };
1194
1195 static struct clk_rcg sdc1_src = {
1196         .ns_reg = 0x282c,
1197         .md_reg = 0x2828,
1198         .mn = {
1199                 .mnctr_en_bit = 8,
1200                 .mnctr_reset_bit = 7,
1201                 .mnctr_mode_shift = 5,
1202                 .n_val_shift = 16,
1203                 .m_val_shift = 16,
1204                 .width = 8,
1205         },
1206         .p = {
1207                 .pre_div_shift = 3,
1208                 .pre_div_width = 2,
1209         },
1210         .s = {
1211                 .src_sel_shift = 0,
1212                 .parent_map = gcc_pxo_pll8_map,
1213         },
1214         .freq_tbl = clk_tbl_sdc,
1215         .clkr = {
1216                 .enable_reg = 0x282c,
1217                 .enable_mask = BIT(11),
1218                 .hw.init = &(struct clk_init_data){
1219                         .name = "sdc1_src",
1220                         .parent_names = gcc_pxo_pll8,
1221                         .num_parents = 2,
1222                         .ops = &clk_rcg_ops,
1223                         .flags = CLK_SET_RATE_GATE,
1224                 },
1225         }
1226 };
1227
1228 static struct clk_branch sdc1_clk = {
1229         .halt_reg = 0x2fc8,
1230         .halt_bit = 6,
1231         .clkr = {
1232                 .enable_reg = 0x282c,
1233                 .enable_mask = BIT(9),
1234                 .hw.init = &(struct clk_init_data){
1235                         .name = "sdc1_clk",
1236                         .parent_names = (const char *[]){ "sdc1_src" },
1237                         .num_parents = 1,
1238                         .ops = &clk_branch_ops,
1239                         .flags = CLK_SET_RATE_PARENT,
1240                 },
1241         },
1242 };
1243
1244 static struct clk_rcg sdc3_src = {
1245         .ns_reg = 0x286c,
1246         .md_reg = 0x2868,
1247         .mn = {
1248                 .mnctr_en_bit = 8,
1249                 .mnctr_reset_bit = 7,
1250                 .mnctr_mode_shift = 5,
1251                 .n_val_shift = 16,
1252                 .m_val_shift = 16,
1253                 .width = 8,
1254         },
1255         .p = {
1256                 .pre_div_shift = 3,
1257                 .pre_div_width = 2,
1258         },
1259         .s = {
1260                 .src_sel_shift = 0,
1261                 .parent_map = gcc_pxo_pll8_map,
1262         },
1263         .freq_tbl = clk_tbl_sdc,
1264         .clkr = {
1265                 .enable_reg = 0x286c,
1266                 .enable_mask = BIT(11),
1267                 .hw.init = &(struct clk_init_data){
1268                         .name = "sdc3_src",
1269                         .parent_names = gcc_pxo_pll8,
1270                         .num_parents = 2,
1271                         .ops = &clk_rcg_ops,
1272                         .flags = CLK_SET_RATE_GATE,
1273                 },
1274         }
1275 };
1276
1277 static struct clk_branch sdc3_clk = {
1278         .halt_reg = 0x2fc8,
1279         .halt_bit = 4,
1280         .clkr = {
1281                 .enable_reg = 0x286c,
1282                 .enable_mask = BIT(9),
1283                 .hw.init = &(struct clk_init_data){
1284                         .name = "sdc3_clk",
1285                         .parent_names = (const char *[]){ "sdc3_src" },
1286                         .num_parents = 1,
1287                         .ops = &clk_branch_ops,
1288                         .flags = CLK_SET_RATE_PARENT,
1289                 },
1290         },
1291 };
1292
1293 static struct clk_branch sdc1_h_clk = {
1294         .hwcg_reg = 0x2820,
1295         .hwcg_bit = 6,
1296         .halt_reg = 0x2fc8,
1297         .halt_bit = 11,
1298         .clkr = {
1299                 .enable_reg = 0x2820,
1300                 .enable_mask = BIT(4),
1301                 .hw.init = &(struct clk_init_data){
1302                         .name = "sdc1_h_clk",
1303                         .ops = &clk_branch_ops,
1304                 },
1305         },
1306 };
1307
1308 static struct clk_branch sdc3_h_clk = {
1309         .hwcg_reg = 0x2860,
1310         .hwcg_bit = 6,
1311         .halt_reg = 0x2fc8,
1312         .halt_bit = 9,
1313         .clkr = {
1314                 .enable_reg = 0x2860,
1315                 .enable_mask = BIT(4),
1316                 .hw.init = &(struct clk_init_data){
1317                         .name = "sdc3_h_clk",
1318                         .ops = &clk_branch_ops,
1319                 },
1320         },
1321 };
1322
1323 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1324         { 105000, P_PXO,  1, 1, 256 },
1325         { }
1326 };
1327
1328 static struct clk_rcg tsif_ref_src = {
1329         .ns_reg = 0x2710,
1330         .md_reg = 0x270c,
1331         .mn = {
1332                 .mnctr_en_bit = 8,
1333                 .mnctr_reset_bit = 7,
1334                 .mnctr_mode_shift = 5,
1335                 .n_val_shift = 16,
1336                 .m_val_shift = 16,
1337                 .width = 16,
1338         },
1339         .p = {
1340                 .pre_div_shift = 3,
1341                 .pre_div_width = 2,
1342         },
1343         .s = {
1344                 .src_sel_shift = 0,
1345                 .parent_map = gcc_pxo_pll8_map,
1346         },
1347         .freq_tbl = clk_tbl_tsif_ref,
1348         .clkr = {
1349                 .enable_reg = 0x2710,
1350                 .enable_mask = BIT(11),
1351                 .hw.init = &(struct clk_init_data){
1352                         .name = "tsif_ref_src",
1353                         .parent_names = gcc_pxo_pll8,
1354                         .num_parents = 2,
1355                         .ops = &clk_rcg_ops,
1356                         .flags = CLK_SET_RATE_GATE,
1357                 },
1358         }
1359 };
1360
1361 static struct clk_branch tsif_ref_clk = {
1362         .halt_reg = 0x2fd4,
1363         .halt_bit = 5,
1364         .clkr = {
1365                 .enable_reg = 0x2710,
1366                 .enable_mask = BIT(9),
1367                 .hw.init = &(struct clk_init_data){
1368                         .name = "tsif_ref_clk",
1369                         .parent_names = (const char *[]){ "tsif_ref_src" },
1370                         .num_parents = 1,
1371                         .ops = &clk_branch_ops,
1372                         .flags = CLK_SET_RATE_PARENT,
1373                 },
1374         },
1375 };
1376
1377 static struct clk_branch tsif_h_clk = {
1378         .hwcg_reg = 0x2700,
1379         .hwcg_bit = 6,
1380         .halt_reg = 0x2fd4,
1381         .halt_bit = 7,
1382         .clkr = {
1383                 .enable_reg = 0x2700,
1384                 .enable_mask = BIT(4),
1385                 .hw.init = &(struct clk_init_data){
1386                         .name = "tsif_h_clk",
1387                         .ops = &clk_branch_ops,
1388                 },
1389         },
1390 };
1391
1392 static struct clk_branch dma_bam_h_clk = {
1393         .hwcg_reg = 0x25c0,
1394         .hwcg_bit = 6,
1395         .halt_reg = 0x2fc8,
1396         .halt_bit = 12,
1397         .clkr = {
1398                 .enable_reg = 0x25c0,
1399                 .enable_mask = BIT(4),
1400                 .hw.init = &(struct clk_init_data){
1401                         .name = "dma_bam_h_clk",
1402                         .ops = &clk_branch_ops,
1403                 },
1404         },
1405 };
1406
1407 static struct clk_branch adm0_clk = {
1408         .halt_reg = 0x2fdc,
1409         .halt_check = BRANCH_HALT_VOTED,
1410         .halt_bit = 12,
1411         .clkr = {
1412                 .enable_reg = 0x3080,
1413                 .enable_mask = BIT(2),
1414                 .hw.init = &(struct clk_init_data){
1415                         .name = "adm0_clk",
1416                         .ops = &clk_branch_ops,
1417                 },
1418         },
1419 };
1420
1421 static struct clk_branch adm0_pbus_clk = {
1422         .hwcg_reg = 0x2208,
1423         .hwcg_bit = 6,
1424         .halt_reg = 0x2fdc,
1425         .halt_check = BRANCH_HALT_VOTED,
1426         .halt_bit = 11,
1427         .clkr = {
1428                 .enable_reg = 0x3080,
1429                 .enable_mask = BIT(3),
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "adm0_pbus_clk",
1432                         .ops = &clk_branch_ops,
1433                 },
1434         },
1435 };
1436
1437 static struct clk_branch pmic_arb0_h_clk = {
1438         .halt_reg = 0x2fd8,
1439         .halt_check = BRANCH_HALT_VOTED,
1440         .halt_bit = 22,
1441         .clkr = {
1442                 .enable_reg = 0x3080,
1443                 .enable_mask = BIT(8),
1444                 .hw.init = &(struct clk_init_data){
1445                         .name = "pmic_arb0_h_clk",
1446                         .ops = &clk_branch_ops,
1447                 },
1448         },
1449 };
1450
1451 static struct clk_branch pmic_arb1_h_clk = {
1452         .halt_reg = 0x2fd8,
1453         .halt_check = BRANCH_HALT_VOTED,
1454         .halt_bit = 21,
1455         .clkr = {
1456                 .enable_reg = 0x3080,
1457                 .enable_mask = BIT(9),
1458                 .hw.init = &(struct clk_init_data){
1459                         .name = "pmic_arb1_h_clk",
1460                         .ops = &clk_branch_ops,
1461                 },
1462         },
1463 };
1464
1465 static struct clk_branch pmic_ssbi2_clk = {
1466         .halt_reg = 0x2fd8,
1467         .halt_check = BRANCH_HALT_VOTED,
1468         .halt_bit = 23,
1469         .clkr = {
1470                 .enable_reg = 0x3080,
1471                 .enable_mask = BIT(7),
1472                 .hw.init = &(struct clk_init_data){
1473                         .name = "pmic_ssbi2_clk",
1474                         .ops = &clk_branch_ops,
1475                 },
1476         },
1477 };
1478
1479 static struct clk_branch rpm_msg_ram_h_clk = {
1480         .hwcg_reg = 0x27e0,
1481         .hwcg_bit = 6,
1482         .halt_reg = 0x2fd8,
1483         .halt_check = BRANCH_HALT_VOTED,
1484         .halt_bit = 12,
1485         .clkr = {
1486                 .enable_reg = 0x3080,
1487                 .enable_mask = BIT(6),
1488                 .hw.init = &(struct clk_init_data){
1489                         .name = "rpm_msg_ram_h_clk",
1490                         .ops = &clk_branch_ops,
1491                 },
1492         },
1493 };
1494
1495 static const struct freq_tbl clk_tbl_pcie_ref[] = {
1496         { 100000000, P_PLL3,  12, 0, 0 },
1497         { }
1498 };
1499
1500 static struct clk_rcg pcie_ref_src = {
1501         .ns_reg = 0x3860,
1502         .p = {
1503                 .pre_div_shift = 3,
1504                 .pre_div_width = 4,
1505         },
1506         .s = {
1507                 .src_sel_shift = 0,
1508                 .parent_map = gcc_pxo_pll3_map,
1509         },
1510         .freq_tbl = clk_tbl_pcie_ref,
1511         .clkr = {
1512                 .enable_reg = 0x3860,
1513                 .enable_mask = BIT(11),
1514                 .hw.init = &(struct clk_init_data){
1515                         .name = "pcie_ref_src",
1516                         .parent_names = gcc_pxo_pll3,
1517                         .num_parents = 2,
1518                         .ops = &clk_rcg_ops,
1519                         .flags = CLK_SET_RATE_GATE,
1520                 },
1521         },
1522 };
1523
1524 static struct clk_branch pcie_ref_src_clk = {
1525         .halt_reg = 0x2fdc,
1526         .halt_bit = 30,
1527         .clkr = {
1528                 .enable_reg = 0x3860,
1529                 .enable_mask = BIT(9),
1530                 .hw.init = &(struct clk_init_data){
1531                         .name = "pcie_ref_src_clk",
1532                         .parent_names = (const char *[]){ "pcie_ref_src" },
1533                         .num_parents = 1,
1534                         .ops = &clk_branch_ops,
1535                         .flags = CLK_SET_RATE_PARENT,
1536                 },
1537         },
1538 };
1539
1540 static struct clk_branch pcie_a_clk = {
1541         .halt_reg = 0x2fc0,
1542         .halt_bit = 13,
1543         .clkr = {
1544                 .enable_reg = 0x22c0,
1545                 .enable_mask = BIT(4),
1546                 .hw.init = &(struct clk_init_data){
1547                         .name = "pcie_a_clk",
1548                         .ops = &clk_branch_ops,
1549                 },
1550         },
1551 };
1552
1553 static struct clk_branch pcie_aux_clk = {
1554         .halt_reg = 0x2fdc,
1555         .halt_bit = 31,
1556         .clkr = {
1557                 .enable_reg = 0x22c8,
1558                 .enable_mask = BIT(4),
1559                 .hw.init = &(struct clk_init_data){
1560                         .name = "pcie_aux_clk",
1561                         .ops = &clk_branch_ops,
1562                 },
1563         },
1564 };
1565
1566 static struct clk_branch pcie_h_clk = {
1567         .halt_reg = 0x2fd4,
1568         .halt_bit = 8,
1569         .clkr = {
1570                 .enable_reg = 0x22cc,
1571                 .enable_mask = BIT(4),
1572                 .hw.init = &(struct clk_init_data){
1573                         .name = "pcie_h_clk",
1574                         .ops = &clk_branch_ops,
1575                 },
1576         },
1577 };
1578
1579 static struct clk_branch pcie_phy_clk = {
1580         .halt_reg = 0x2fdc,
1581         .halt_bit = 29,
1582         .clkr = {
1583                 .enable_reg = 0x22d0,
1584                 .enable_mask = BIT(4),
1585                 .hw.init = &(struct clk_init_data){
1586                         .name = "pcie_phy_clk",
1587                         .ops = &clk_branch_ops,
1588                 },
1589         },
1590 };
1591
1592 static struct clk_rcg pcie1_ref_src = {
1593         .ns_reg = 0x3aa0,
1594         .p = {
1595                 .pre_div_shift = 3,
1596                 .pre_div_width = 4,
1597         },
1598         .s = {
1599                 .src_sel_shift = 0,
1600                 .parent_map = gcc_pxo_pll3_map,
1601         },
1602         .freq_tbl = clk_tbl_pcie_ref,
1603         .clkr = {
1604                 .enable_reg = 0x3aa0,
1605                 .enable_mask = BIT(11),
1606                 .hw.init = &(struct clk_init_data){
1607                         .name = "pcie1_ref_src",
1608                         .parent_names = gcc_pxo_pll3,
1609                         .num_parents = 2,
1610                         .ops = &clk_rcg_ops,
1611                         .flags = CLK_SET_RATE_GATE,
1612                 },
1613         },
1614 };
1615
1616 static struct clk_branch pcie1_ref_src_clk = {
1617         .halt_reg = 0x2fdc,
1618         .halt_bit = 27,
1619         .clkr = {
1620                 .enable_reg = 0x3aa0,
1621                 .enable_mask = BIT(9),
1622                 .hw.init = &(struct clk_init_data){
1623                         .name = "pcie1_ref_src_clk",
1624                         .parent_names = (const char *[]){ "pcie1_ref_src" },
1625                         .num_parents = 1,
1626                         .ops = &clk_branch_ops,
1627                         .flags = CLK_SET_RATE_PARENT,
1628                 },
1629         },
1630 };
1631
1632 static struct clk_branch pcie1_a_clk = {
1633         .halt_reg = 0x2fc0,
1634         .halt_bit = 10,
1635         .clkr = {
1636                 .enable_reg = 0x3a80,
1637                 .enable_mask = BIT(4),
1638                 .hw.init = &(struct clk_init_data){
1639                         .name = "pcie1_a_clk",
1640                         .ops = &clk_branch_ops,
1641                 },
1642         },
1643 };
1644
1645 static struct clk_branch pcie1_aux_clk = {
1646         .halt_reg = 0x2fdc,
1647         .halt_bit = 28,
1648         .clkr = {
1649                 .enable_reg = 0x3a88,
1650                 .enable_mask = BIT(4),
1651                 .hw.init = &(struct clk_init_data){
1652                         .name = "pcie1_aux_clk",
1653                         .ops = &clk_branch_ops,
1654                 },
1655         },
1656 };
1657
1658 static struct clk_branch pcie1_h_clk = {
1659         .halt_reg = 0x2fd4,
1660         .halt_bit = 9,
1661         .clkr = {
1662                 .enable_reg = 0x3a8c,
1663                 .enable_mask = BIT(4),
1664                 .hw.init = &(struct clk_init_data){
1665                         .name = "pcie1_h_clk",
1666                         .ops = &clk_branch_ops,
1667                 },
1668         },
1669 };
1670
1671 static struct clk_branch pcie1_phy_clk = {
1672         .halt_reg = 0x2fdc,
1673         .halt_bit = 26,
1674         .clkr = {
1675                 .enable_reg = 0x3a90,
1676                 .enable_mask = BIT(4),
1677                 .hw.init = &(struct clk_init_data){
1678                         .name = "pcie1_phy_clk",
1679                         .ops = &clk_branch_ops,
1680                 },
1681         },
1682 };
1683
1684 static struct clk_rcg pcie2_ref_src = {
1685         .ns_reg = 0x3ae0,
1686         .p = {
1687                 .pre_div_shift = 3,
1688                 .pre_div_width = 4,
1689         },
1690         .s = {
1691                 .src_sel_shift = 0,
1692                 .parent_map = gcc_pxo_pll3_map,
1693         },
1694         .freq_tbl = clk_tbl_pcie_ref,
1695         .clkr = {
1696                 .enable_reg = 0x3ae0,
1697                 .enable_mask = BIT(11),
1698                 .hw.init = &(struct clk_init_data){
1699                         .name = "pcie2_ref_src",
1700                         .parent_names = gcc_pxo_pll3,
1701                         .num_parents = 2,
1702                         .ops = &clk_rcg_ops,
1703                         .flags = CLK_SET_RATE_GATE,
1704                 },
1705         },
1706 };
1707
1708 static struct clk_branch pcie2_ref_src_clk = {
1709         .halt_reg = 0x2fdc,
1710         .halt_bit = 24,
1711         .clkr = {
1712                 .enable_reg = 0x3ae0,
1713                 .enable_mask = BIT(9),
1714                 .hw.init = &(struct clk_init_data){
1715                         .name = "pcie2_ref_src_clk",
1716                         .parent_names = (const char *[]){ "pcie2_ref_src" },
1717                         .num_parents = 1,
1718                         .ops = &clk_branch_ops,
1719                         .flags = CLK_SET_RATE_PARENT,
1720                 },
1721         },
1722 };
1723
1724 static struct clk_branch pcie2_a_clk = {
1725         .halt_reg = 0x2fc0,
1726         .halt_bit = 9,
1727         .clkr = {
1728                 .enable_reg = 0x3ac0,
1729                 .enable_mask = BIT(4),
1730                 .hw.init = &(struct clk_init_data){
1731                         .name = "pcie2_a_clk",
1732                         .ops = &clk_branch_ops,
1733                 },
1734         },
1735 };
1736
1737 static struct clk_branch pcie2_aux_clk = {
1738         .halt_reg = 0x2fdc,
1739         .halt_bit = 25,
1740         .clkr = {
1741                 .enable_reg = 0x3ac8,
1742                 .enable_mask = BIT(4),
1743                 .hw.init = &(struct clk_init_data){
1744                         .name = "pcie2_aux_clk",
1745                         .ops = &clk_branch_ops,
1746                 },
1747         },
1748 };
1749
1750 static struct clk_branch pcie2_h_clk = {
1751         .halt_reg = 0x2fd4,
1752         .halt_bit = 10,
1753         .clkr = {
1754                 .enable_reg = 0x3acc,
1755                 .enable_mask = BIT(4),
1756                 .hw.init = &(struct clk_init_data){
1757                         .name = "pcie2_h_clk",
1758                         .ops = &clk_branch_ops,
1759                 },
1760         },
1761 };
1762
1763 static struct clk_branch pcie2_phy_clk = {
1764         .halt_reg = 0x2fdc,
1765         .halt_bit = 23,
1766         .clkr = {
1767                 .enable_reg = 0x3ad0,
1768                 .enable_mask = BIT(4),
1769                 .hw.init = &(struct clk_init_data){
1770                         .name = "pcie2_phy_clk",
1771                         .ops = &clk_branch_ops,
1772                 },
1773         },
1774 };
1775
1776 static const struct freq_tbl clk_tbl_sata_ref[] = {
1777         { 100000000, P_PLL3,  12, 0, 0 },
1778         { }
1779 };
1780
1781 static struct clk_rcg sata_ref_src = {
1782         .ns_reg = 0x2c08,
1783         .p = {
1784                 .pre_div_shift = 3,
1785                 .pre_div_width = 4,
1786         },
1787         .s = {
1788                 .src_sel_shift = 0,
1789                 .parent_map = gcc_pxo_pll3_sata_map,
1790         },
1791         .freq_tbl = clk_tbl_sata_ref,
1792         .clkr = {
1793                 .enable_reg = 0x2c08,
1794                 .enable_mask = BIT(7),
1795                 .hw.init = &(struct clk_init_data){
1796                         .name = "sata_ref_src",
1797                         .parent_names = gcc_pxo_pll3,
1798                         .num_parents = 2,
1799                         .ops = &clk_rcg_ops,
1800                         .flags = CLK_SET_RATE_GATE,
1801                 },
1802         },
1803 };
1804
1805 static struct clk_branch sata_rxoob_clk = {
1806         .halt_reg = 0x2fdc,
1807         .halt_bit = 20,
1808         .clkr = {
1809                 .enable_reg = 0x2c0c,
1810                 .enable_mask = BIT(4),
1811                 .hw.init = &(struct clk_init_data){
1812                         .name = "sata_rxoob_clk",
1813                         .parent_names = (const char *[]){ "sata_ref_src" },
1814                         .num_parents = 1,
1815                         .ops = &clk_branch_ops,
1816                         .flags = CLK_SET_RATE_PARENT,
1817                 },
1818         },
1819 };
1820
1821 static struct clk_branch sata_pmalive_clk = {
1822         .halt_reg = 0x2fdc,
1823         .halt_bit = 19,
1824         .clkr = {
1825                 .enable_reg = 0x2c10,
1826                 .enable_mask = BIT(4),
1827                 .hw.init = &(struct clk_init_data){
1828                         .name = "sata_pmalive_clk",
1829                         .parent_names = (const char *[]){ "sata_ref_src" },
1830                         .num_parents = 1,
1831                         .ops = &clk_branch_ops,
1832                         .flags = CLK_SET_RATE_PARENT,
1833                 },
1834         },
1835 };
1836
1837 static struct clk_branch sata_phy_ref_clk = {
1838         .halt_reg = 0x2fdc,
1839         .halt_bit = 18,
1840         .clkr = {
1841                 .enable_reg = 0x2c14,
1842                 .enable_mask = BIT(4),
1843                 .hw.init = &(struct clk_init_data){
1844                         .name = "sata_phy_ref_clk",
1845                         .parent_names = (const char *[]){ "pxo" },
1846                         .num_parents = 1,
1847                         .ops = &clk_branch_ops,
1848                 },
1849         },
1850 };
1851
1852 static struct clk_branch sata_a_clk = {
1853         .halt_reg = 0x2fc0,
1854         .halt_bit = 12,
1855         .clkr = {
1856                 .enable_reg = 0x2c20,
1857                 .enable_mask = BIT(4),
1858                 .hw.init = &(struct clk_init_data){
1859                         .name = "sata_a_clk",
1860                         .ops = &clk_branch_ops,
1861                 },
1862         },
1863 };
1864
1865 static struct clk_branch sata_h_clk = {
1866         .halt_reg = 0x2fdc,
1867         .halt_bit = 21,
1868         .clkr = {
1869                 .enable_reg = 0x2c00,
1870                 .enable_mask = BIT(4),
1871                 .hw.init = &(struct clk_init_data){
1872                         .name = "sata_h_clk",
1873                         .ops = &clk_branch_ops,
1874                 },
1875         },
1876 };
1877
1878 static struct clk_branch sfab_sata_s_h_clk = {
1879         .halt_reg = 0x2fc4,
1880         .halt_bit = 14,
1881         .clkr = {
1882                 .enable_reg = 0x2480,
1883                 .enable_mask = BIT(4),
1884                 .hw.init = &(struct clk_init_data){
1885                         .name = "sfab_sata_s_h_clk",
1886                         .ops = &clk_branch_ops,
1887                 },
1888         },
1889 };
1890
1891 static struct clk_branch sata_phy_cfg_clk = {
1892         .halt_reg = 0x2fcc,
1893         .halt_bit = 14,
1894         .clkr = {
1895                 .enable_reg = 0x2c40,
1896                 .enable_mask = BIT(4),
1897                 .hw.init = &(struct clk_init_data){
1898                         .name = "sata_phy_cfg_clk",
1899                         .ops = &clk_branch_ops,
1900                 },
1901         },
1902 };
1903
1904 static const struct freq_tbl clk_tbl_usb30_master[] = {
1905         { 125000000, P_PLL0,  1, 5, 32 },
1906         { }
1907 };
1908
1909 static struct clk_rcg usb30_master_clk_src = {
1910         .ns_reg = 0x3b2c,
1911         .md_reg = 0x3b28,
1912         .mn = {
1913                 .mnctr_en_bit = 8,
1914                 .mnctr_reset_bit = 7,
1915                 .mnctr_mode_shift = 5,
1916                 .n_val_shift = 16,
1917                 .m_val_shift = 16,
1918                 .width = 8,
1919         },
1920         .p = {
1921                 .pre_div_shift = 3,
1922                 .pre_div_width = 2,
1923         },
1924         .s = {
1925                 .src_sel_shift = 0,
1926                 .parent_map = gcc_pxo_pll8_pll0,
1927         },
1928         .freq_tbl = clk_tbl_usb30_master,
1929         .clkr = {
1930                 .enable_reg = 0x3b2c,
1931                 .enable_mask = BIT(11),
1932                 .hw.init = &(struct clk_init_data){
1933                         .name = "usb30_master_ref_src",
1934                         .parent_names = gcc_pxo_pll8_pll0_map,
1935                         .num_parents = 3,
1936                         .ops = &clk_rcg_ops,
1937                         .flags = CLK_SET_RATE_GATE,
1938                 },
1939         },
1940 };
1941
1942 static struct clk_branch usb30_0_branch_clk = {
1943         .halt_reg = 0x2fc4,
1944         .halt_bit = 22,
1945         .clkr = {
1946                 .enable_reg = 0x3b24,
1947                 .enable_mask = BIT(4),
1948                 .hw.init = &(struct clk_init_data){
1949                         .name = "usb30_0_branch_clk",
1950                         .parent_names = (const char *[]){ "usb30_master_ref_src", },
1951                         .num_parents = 1,
1952                         .ops = &clk_branch_ops,
1953                         .flags = CLK_SET_RATE_PARENT,
1954                 },
1955         },
1956 };
1957
1958 static struct clk_branch usb30_1_branch_clk = {
1959         .halt_reg = 0x2fc4,
1960         .halt_bit = 17,
1961         .clkr = {
1962                 .enable_reg = 0x3b34,
1963                 .enable_mask = BIT(4),
1964                 .hw.init = &(struct clk_init_data){
1965                         .name = "usb30_1_branch_clk",
1966                         .parent_names = (const char *[]){ "usb30_master_ref_src", },
1967                         .num_parents = 1,
1968                         .ops = &clk_branch_ops,
1969                         .flags = CLK_SET_RATE_PARENT,
1970                 },
1971         },
1972 };
1973
1974 static const struct freq_tbl clk_tbl_usb30_utmi[] = {
1975         { 60000000, P_PLL8,  1, 5, 32 },
1976         { }
1977 };
1978
1979 static struct clk_rcg usb30_utmi_clk = {
1980         .ns_reg = 0x3b44,
1981         .md_reg = 0x3b40,
1982         .mn = {
1983                 .mnctr_en_bit = 8,
1984                 .mnctr_reset_bit = 7,
1985                 .mnctr_mode_shift = 5,
1986                 .n_val_shift = 16,
1987                 .m_val_shift = 16,
1988                 .width = 8,
1989         },
1990         .p = {
1991                 .pre_div_shift = 3,
1992                 .pre_div_width = 2,
1993         },
1994         .s = {
1995                 .src_sel_shift = 0,
1996                 .parent_map = gcc_pxo_pll8_pll0,
1997         },
1998         .freq_tbl = clk_tbl_usb30_utmi,
1999         .clkr = {
2000                 .enable_reg = 0x3b44,
2001                 .enable_mask = BIT(11),
2002                 .hw.init = &(struct clk_init_data){
2003                         .name = "usb30_utmi_clk",
2004                         .parent_names = gcc_pxo_pll8_pll0_map,
2005                         .num_parents = 3,
2006                         .ops = &clk_rcg_ops,
2007                         .flags = CLK_SET_RATE_GATE,
2008                 },
2009         },
2010 };
2011
2012 static struct clk_branch usb30_0_utmi_clk_ctl = {
2013         .halt_reg = 0x2fc4,
2014         .halt_bit = 21,
2015         .clkr = {
2016                 .enable_reg = 0x3b48,
2017                 .enable_mask = BIT(4),
2018                 .hw.init = &(struct clk_init_data){
2019                         .name = "usb30_0_utmi_clk_ctl",
2020                         .parent_names = (const char *[]){ "usb30_utmi_clk", },
2021                         .num_parents = 1,
2022                         .ops = &clk_branch_ops,
2023                         .flags = CLK_SET_RATE_PARENT,
2024                 },
2025         },
2026 };
2027
2028 static struct clk_branch usb30_1_utmi_clk_ctl = {
2029         .halt_reg = 0x2fc4,
2030         .halt_bit = 15,
2031         .clkr = {
2032                 .enable_reg = 0x3b4c,
2033                 .enable_mask = BIT(4),
2034                 .hw.init = &(struct clk_init_data){
2035                         .name = "usb30_1_utmi_clk_ctl",
2036                         .parent_names = (const char *[]){ "usb30_utmi_clk", },
2037                         .num_parents = 1,
2038                         .ops = &clk_branch_ops,
2039                         .flags = CLK_SET_RATE_PARENT,
2040                 },
2041         },
2042 };
2043
2044 static const struct freq_tbl clk_tbl_usb[] = {
2045         { 60000000, P_PLL8,  1, 5, 32 },
2046         { }
2047 };
2048
2049 static struct clk_rcg usb_hs1_xcvr_clk_src = {
2050         .ns_reg = 0x290C,
2051         .md_reg = 0x2908,
2052         .mn = {
2053                 .mnctr_en_bit = 8,
2054                 .mnctr_reset_bit = 7,
2055                 .mnctr_mode_shift = 5,
2056                 .n_val_shift = 16,
2057                 .m_val_shift = 16,
2058                 .width = 8,
2059         },
2060         .p = {
2061                 .pre_div_shift = 3,
2062                 .pre_div_width = 2,
2063         },
2064         .s = {
2065                 .src_sel_shift = 0,
2066                 .parent_map = gcc_pxo_pll8_pll0,
2067         },
2068         .freq_tbl = clk_tbl_usb,
2069         .clkr = {
2070                 .enable_reg = 0x2968,
2071                 .enable_mask = BIT(11),
2072                 .hw.init = &(struct clk_init_data){
2073                         .name = "usb_hs1_xcvr_src",
2074                         .parent_names = gcc_pxo_pll8_pll0_map,
2075                         .num_parents = 3,
2076                         .ops = &clk_rcg_ops,
2077                         .flags = CLK_SET_RATE_GATE,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch usb_hs1_xcvr_clk = {
2083         .halt_reg = 0x2fcc,
2084         .halt_bit = 17,
2085         .clkr = {
2086                 .enable_reg = 0x290c,
2087                 .enable_mask = BIT(9),
2088                 .hw.init = &(struct clk_init_data){
2089                         .name = "usb_hs1_xcvr_clk",
2090                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2091                         .num_parents = 1,
2092                         .ops = &clk_branch_ops,
2093                         .flags = CLK_SET_RATE_PARENT,
2094                 },
2095         },
2096 };
2097
2098 static struct clk_branch usb_hs1_h_clk = {
2099         .hwcg_reg = 0x2900,
2100         .hwcg_bit = 6,
2101         .halt_reg = 0x2fc8,
2102         .halt_bit = 1,
2103         .clkr = {
2104                 .enable_reg = 0x2900,
2105                 .enable_mask = BIT(4),
2106                 .hw.init = &(struct clk_init_data){
2107                         .name = "usb_hs1_h_clk",
2108                         .ops = &clk_branch_ops,
2109                 },
2110         },
2111 };
2112
2113 static struct clk_rcg usb_fs1_xcvr_clk_src = {
2114         .ns_reg = 0x2968,
2115         .md_reg = 0x2964,
2116         .mn = {
2117                 .mnctr_en_bit = 8,
2118                 .mnctr_reset_bit = 7,
2119                 .mnctr_mode_shift = 5,
2120                 .n_val_shift = 16,
2121                 .m_val_shift = 16,
2122                 .width = 8,
2123         },
2124         .p = {
2125                 .pre_div_shift = 3,
2126                 .pre_div_width = 2,
2127         },
2128         .s = {
2129                 .src_sel_shift = 0,
2130                 .parent_map = gcc_pxo_pll8_pll0,
2131         },
2132         .freq_tbl = clk_tbl_usb,
2133         .clkr = {
2134                 .enable_reg = 0x2968,
2135                 .enable_mask = BIT(11),
2136                 .hw.init = &(struct clk_init_data){
2137                         .name = "usb_fs1_xcvr_src",
2138                         .parent_names = gcc_pxo_pll8_pll0_map,
2139                         .num_parents = 3,
2140                         .ops = &clk_rcg_ops,
2141                         .flags = CLK_SET_RATE_GATE,
2142                 },
2143         },
2144 };
2145
2146 static struct clk_branch usb_fs1_xcvr_clk = {
2147         .halt_reg = 0x2fcc,
2148         .halt_bit = 17,
2149         .clkr = {
2150                 .enable_reg = 0x2968,
2151                 .enable_mask = BIT(9),
2152                 .hw.init = &(struct clk_init_data){
2153                         .name = "usb_fs1_xcvr_clk",
2154                         .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2155                         .num_parents = 1,
2156                         .ops = &clk_branch_ops,
2157                         .flags = CLK_SET_RATE_PARENT,
2158                 },
2159         },
2160 };
2161
2162 static struct clk_branch usb_fs1_sys_clk = {
2163         .halt_reg = 0x2fcc,
2164         .halt_bit = 18,
2165         .clkr = {
2166                 .enable_reg = 0x296c,
2167                 .enable_mask = BIT(4),
2168                 .hw.init = &(struct clk_init_data){
2169                         .name = "usb_fs1_sys_clk",
2170                         .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2171                         .num_parents = 1,
2172                         .ops = &clk_branch_ops,
2173                         .flags = CLK_SET_RATE_PARENT,
2174                 },
2175         },
2176 };
2177
2178 static struct clk_branch usb_fs1_h_clk = {
2179         .halt_reg = 0x2fcc,
2180         .halt_bit = 19,
2181         .clkr = {
2182                 .enable_reg = 0x2960,
2183                 .enable_mask = BIT(4),
2184                 .hw.init = &(struct clk_init_data){
2185                         .name = "usb_fs1_h_clk",
2186                         .ops = &clk_branch_ops,
2187                 },
2188         },
2189 };
2190
2191 static struct clk_branch ebi2_clk = {
2192         .hwcg_reg = 0x3b00,
2193         .hwcg_bit = 6,
2194         .halt_reg = 0x2fcc,
2195         .halt_bit = 1,
2196         .clkr = {
2197                 .enable_reg = 0x3b00,
2198                 .enable_mask = BIT(4),
2199                 .hw.init = &(struct clk_init_data){
2200                         .name = "ebi2_clk",
2201                         .ops = &clk_branch_ops,
2202                 },
2203         },
2204 };
2205
2206 static struct clk_branch ebi2_aon_clk = {
2207         .halt_reg = 0x2fcc,
2208         .halt_bit = 0,
2209         .clkr = {
2210                 .enable_reg = 0x3b00,
2211                 .enable_mask = BIT(8),
2212                 .hw.init = &(struct clk_init_data){
2213                         .name = "ebi2_always_on_clk",
2214                         .ops = &clk_branch_ops,
2215                 },
2216         },
2217 };
2218
2219 static const struct freq_tbl clk_tbl_gmac[] = {
2220         { 133000000, P_PLL0, 1,  50, 301 },
2221         { 266000000, P_PLL0, 1, 127, 382 },
2222         { }
2223 };
2224
2225 static struct clk_dyn_rcg gmac_core1_src = {
2226         .ns_reg[0] = 0x3cac,
2227         .ns_reg[1] = 0x3cb0,
2228         .md_reg[0] = 0x3ca4,
2229         .md_reg[1] = 0x3ca8,
2230         .bank_reg = 0x3ca0,
2231         .mn[0] = {
2232                 .mnctr_en_bit = 8,
2233                 .mnctr_reset_bit = 7,
2234                 .mnctr_mode_shift = 5,
2235                 .n_val_shift = 16,
2236                 .m_val_shift = 16,
2237                 .width = 8,
2238         },
2239         .mn[1] = {
2240                 .mnctr_en_bit = 8,
2241                 .mnctr_reset_bit = 7,
2242                 .mnctr_mode_shift = 5,
2243                 .n_val_shift = 16,
2244                 .m_val_shift = 16,
2245                 .width = 8,
2246         },
2247         .s[0] = {
2248                 .src_sel_shift = 0,
2249                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2250         },
2251         .s[1] = {
2252                 .src_sel_shift = 0,
2253                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2254         },
2255         .p[0] = {
2256                 .pre_div_shift = 3,
2257                 .pre_div_width = 2,
2258         },
2259         .p[1] = {
2260                 .pre_div_shift = 3,
2261                 .pre_div_width = 2,
2262         },
2263         .mux_sel_bit = 0,
2264         .freq_tbl = clk_tbl_gmac,
2265         .clkr = {
2266                 .enable_reg = 0x3ca0,
2267                 .enable_mask = BIT(1),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "gmac_core1_src",
2270                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2271                         .num_parents = 5,
2272                         .ops = &clk_dyn_rcg_ops,
2273                 },
2274         },
2275 };
2276
2277 static struct clk_branch gmac_core1_clk = {
2278         .halt_reg = 0x3c20,
2279         .halt_bit = 4,
2280         .hwcg_reg = 0x3cb4,
2281         .hwcg_bit = 6,
2282         .clkr = {
2283                 .enable_reg = 0x3cb4,
2284                 .enable_mask = BIT(4),
2285                 .hw.init = &(struct clk_init_data){
2286                         .name = "gmac_core1_clk",
2287                         .parent_names = (const char *[]){
2288                                 "gmac_core1_src",
2289                         },
2290                         .num_parents = 1,
2291                         .ops = &clk_branch_ops,
2292                         .flags = CLK_SET_RATE_PARENT,
2293                 },
2294         },
2295 };
2296
2297 static struct clk_dyn_rcg gmac_core2_src = {
2298         .ns_reg[0] = 0x3ccc,
2299         .ns_reg[1] = 0x3cd0,
2300         .md_reg[0] = 0x3cc4,
2301         .md_reg[1] = 0x3cc8,
2302         .bank_reg = 0x3ca0,
2303         .mn[0] = {
2304                 .mnctr_en_bit = 8,
2305                 .mnctr_reset_bit = 7,
2306                 .mnctr_mode_shift = 5,
2307                 .n_val_shift = 16,
2308                 .m_val_shift = 16,
2309                 .width = 8,
2310         },
2311         .mn[1] = {
2312                 .mnctr_en_bit = 8,
2313                 .mnctr_reset_bit = 7,
2314                 .mnctr_mode_shift = 5,
2315                 .n_val_shift = 16,
2316                 .m_val_shift = 16,
2317                 .width = 8,
2318         },
2319         .s[0] = {
2320                 .src_sel_shift = 0,
2321                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2322         },
2323         .s[1] = {
2324                 .src_sel_shift = 0,
2325                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2326         },
2327         .p[0] = {
2328                 .pre_div_shift = 3,
2329                 .pre_div_width = 2,
2330         },
2331         .p[1] = {
2332                 .pre_div_shift = 3,
2333                 .pre_div_width = 2,
2334         },
2335         .mux_sel_bit = 0,
2336         .freq_tbl = clk_tbl_gmac,
2337         .clkr = {
2338                 .enable_reg = 0x3cc0,
2339                 .enable_mask = BIT(1),
2340                 .hw.init = &(struct clk_init_data){
2341                         .name = "gmac_core2_src",
2342                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2343                         .num_parents = 5,
2344                         .ops = &clk_dyn_rcg_ops,
2345                 },
2346         },
2347 };
2348
2349 static struct clk_branch gmac_core2_clk = {
2350         .halt_reg = 0x3c20,
2351         .halt_bit = 5,
2352         .hwcg_reg = 0x3cd4,
2353         .hwcg_bit = 6,
2354         .clkr = {
2355                 .enable_reg = 0x3cd4,
2356                 .enable_mask = BIT(4),
2357                 .hw.init = &(struct clk_init_data){
2358                         .name = "gmac_core2_clk",
2359                         .parent_names = (const char *[]){
2360                                 "gmac_core2_src",
2361                         },
2362                         .num_parents = 1,
2363                         .ops = &clk_branch_ops,
2364                         .flags = CLK_SET_RATE_PARENT,
2365                 },
2366         },
2367 };
2368
2369 static struct clk_dyn_rcg gmac_core3_src = {
2370         .ns_reg[0] = 0x3cec,
2371         .ns_reg[1] = 0x3cf0,
2372         .md_reg[0] = 0x3ce4,
2373         .md_reg[1] = 0x3ce8,
2374         .bank_reg = 0x3ce0,
2375         .mn[0] = {
2376                 .mnctr_en_bit = 8,
2377                 .mnctr_reset_bit = 7,
2378                 .mnctr_mode_shift = 5,
2379                 .n_val_shift = 16,
2380                 .m_val_shift = 16,
2381                 .width = 8,
2382         },
2383         .mn[1] = {
2384                 .mnctr_en_bit = 8,
2385                 .mnctr_reset_bit = 7,
2386                 .mnctr_mode_shift = 5,
2387                 .n_val_shift = 16,
2388                 .m_val_shift = 16,
2389                 .width = 8,
2390         },
2391         .s[0] = {
2392                 .src_sel_shift = 0,
2393                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2394         },
2395         .s[1] = {
2396                 .src_sel_shift = 0,
2397                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2398         },
2399         .p[0] = {
2400                 .pre_div_shift = 3,
2401                 .pre_div_width = 2,
2402         },
2403         .p[1] = {
2404                 .pre_div_shift = 3,
2405                 .pre_div_width = 2,
2406         },
2407         .mux_sel_bit = 0,
2408         .freq_tbl = clk_tbl_gmac,
2409         .clkr = {
2410                 .enable_reg = 0x3ce0,
2411                 .enable_mask = BIT(1),
2412                 .hw.init = &(struct clk_init_data){
2413                         .name = "gmac_core3_src",
2414                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2415                         .num_parents = 5,
2416                         .ops = &clk_dyn_rcg_ops,
2417                 },
2418         },
2419 };
2420
2421 static struct clk_branch gmac_core3_clk = {
2422         .halt_reg = 0x3c20,
2423         .halt_bit = 6,
2424         .hwcg_reg = 0x3cf4,
2425         .hwcg_bit = 6,
2426         .clkr = {
2427                 .enable_reg = 0x3cf4,
2428                 .enable_mask = BIT(4),
2429                 .hw.init = &(struct clk_init_data){
2430                         .name = "gmac_core3_clk",
2431                         .parent_names = (const char *[]){
2432                                 "gmac_core3_src",
2433                         },
2434                         .num_parents = 1,
2435                         .ops = &clk_branch_ops,
2436                         .flags = CLK_SET_RATE_PARENT,
2437                 },
2438         },
2439 };
2440
2441 static struct clk_dyn_rcg gmac_core4_src = {
2442         .ns_reg[0] = 0x3d0c,
2443         .ns_reg[1] = 0x3d10,
2444         .md_reg[0] = 0x3d04,
2445         .md_reg[1] = 0x3d08,
2446         .bank_reg = 0x3d00,
2447         .mn[0] = {
2448                 .mnctr_en_bit = 8,
2449                 .mnctr_reset_bit = 7,
2450                 .mnctr_mode_shift = 5,
2451                 .n_val_shift = 16,
2452                 .m_val_shift = 16,
2453                 .width = 8,
2454         },
2455         .mn[1] = {
2456                 .mnctr_en_bit = 8,
2457                 .mnctr_reset_bit = 7,
2458                 .mnctr_mode_shift = 5,
2459                 .n_val_shift = 16,
2460                 .m_val_shift = 16,
2461                 .width = 8,
2462         },
2463         .s[0] = {
2464                 .src_sel_shift = 0,
2465                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2466         },
2467         .s[1] = {
2468                 .src_sel_shift = 0,
2469                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2470         },
2471         .p[0] = {
2472                 .pre_div_shift = 3,
2473                 .pre_div_width = 2,
2474         },
2475         .p[1] = {
2476                 .pre_div_shift = 3,
2477                 .pre_div_width = 2,
2478         },
2479         .mux_sel_bit = 0,
2480         .freq_tbl = clk_tbl_gmac,
2481         .clkr = {
2482                 .enable_reg = 0x3d00,
2483                 .enable_mask = BIT(1),
2484                 .hw.init = &(struct clk_init_data){
2485                         .name = "gmac_core4_src",
2486                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2487                         .num_parents = 5,
2488                         .ops = &clk_dyn_rcg_ops,
2489                 },
2490         },
2491 };
2492
2493 static struct clk_branch gmac_core4_clk = {
2494         .halt_reg = 0x3c20,
2495         .halt_bit = 7,
2496         .hwcg_reg = 0x3d14,
2497         .hwcg_bit = 6,
2498         .clkr = {
2499                 .enable_reg = 0x3d14,
2500                 .enable_mask = BIT(4),
2501                 .hw.init = &(struct clk_init_data){
2502                         .name = "gmac_core4_clk",
2503                         .parent_names = (const char *[]){
2504                                 "gmac_core4_src",
2505                         },
2506                         .num_parents = 1,
2507                         .ops = &clk_branch_ops,
2508                         .flags = CLK_SET_RATE_PARENT,
2509                 },
2510         },
2511 };
2512
2513 static const struct freq_tbl clk_tbl_nss_tcm[] = {
2514         { 266000000, P_PLL0, 3, 0, 0 },
2515         { 400000000, P_PLL0, 2, 0, 0 },
2516         { }
2517 };
2518
2519 static struct clk_dyn_rcg nss_tcm_src = {
2520         .ns_reg[0] = 0x3dc4,
2521         .ns_reg[1] = 0x3dc8,
2522         .bank_reg = 0x3dc0,
2523         .s[0] = {
2524                 .src_sel_shift = 0,
2525                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2526         },
2527         .s[1] = {
2528                 .src_sel_shift = 0,
2529                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2530         },
2531         .p[0] = {
2532                 .pre_div_shift = 3,
2533                 .pre_div_width = 4,
2534         },
2535         .p[1] = {
2536                 .pre_div_shift = 3,
2537                 .pre_div_width = 4,
2538         },
2539         .mux_sel_bit = 0,
2540         .freq_tbl = clk_tbl_nss_tcm,
2541         .clkr = {
2542                 .enable_reg = 0x3dc0,
2543                 .enable_mask = BIT(1),
2544                 .hw.init = &(struct clk_init_data){
2545                         .name = "nss_tcm_src",
2546                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2547                         .num_parents = 5,
2548                         .ops = &clk_dyn_rcg_ops,
2549                 },
2550         },
2551 };
2552
2553 static struct clk_branch nss_tcm_clk = {
2554         .halt_reg = 0x3c20,
2555         .halt_bit = 14,
2556         .clkr = {
2557                 .enable_reg = 0x3dd0,
2558                 .enable_mask = BIT(6) | BIT(4),
2559                 .hw.init = &(struct clk_init_data){
2560                         .name = "nss_tcm_clk",
2561                         .parent_names = (const char *[]){
2562                                 "nss_tcm_src",
2563                         },
2564                         .num_parents = 1,
2565                         .ops = &clk_branch_ops,
2566                         .flags = CLK_SET_RATE_PARENT,
2567                 },
2568         },
2569 };
2570
2571 static const struct freq_tbl clk_tbl_nss[] = {
2572         { 110000000, P_PLL18, 1, 1, 5 },
2573         { 275000000, P_PLL18, 2, 0, 0 },
2574         { 550000000, P_PLL18, 1, 0, 0 },
2575         { 733000000, P_PLL18, 1, 0, 0 },
2576         { }
2577 };
2578
2579 static struct clk_dyn_rcg ubi32_core1_src_clk = {
2580         .ns_reg[0] = 0x3d2c,
2581         .ns_reg[1] = 0x3d30,
2582         .md_reg[0] = 0x3d24,
2583         .md_reg[1] = 0x3d28,
2584         .bank_reg = 0x3d20,
2585         .mn[0] = {
2586                 .mnctr_en_bit = 8,
2587                 .mnctr_reset_bit = 7,
2588                 .mnctr_mode_shift = 5,
2589                 .n_val_shift = 16,
2590                 .m_val_shift = 16,
2591                 .width = 8,
2592         },
2593         .mn[1] = {
2594                 .mnctr_en_bit = 8,
2595                 .mnctr_reset_bit = 7,
2596                 .mnctr_mode_shift = 5,
2597                 .n_val_shift = 16,
2598                 .m_val_shift = 16,
2599                 .width = 8,
2600         },
2601         .s[0] = {
2602                 .src_sel_shift = 0,
2603                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2604         },
2605         .s[1] = {
2606                 .src_sel_shift = 0,
2607                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2608         },
2609         .p[0] = {
2610                 .pre_div_shift = 3,
2611                 .pre_div_width = 2,
2612         },
2613         .p[1] = {
2614                 .pre_div_shift = 3,
2615                 .pre_div_width = 2,
2616         },
2617         .mux_sel_bit = 0,
2618         .freq_tbl = clk_tbl_nss,
2619         .clkr = {
2620                 .enable_reg = 0x3d20,
2621                 .enable_mask = BIT(1),
2622                 .hw.init = &(struct clk_init_data){
2623                         .name = "ubi32_core1_src_clk",
2624                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2625                         .num_parents = 5,
2626                         .ops = &clk_dyn_rcg_ops,
2627                         .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2628                 },
2629         },
2630 };
2631
2632 static struct clk_dyn_rcg ubi32_core2_src_clk = {
2633         .ns_reg[0] = 0x3d4c,
2634         .ns_reg[1] = 0x3d50,
2635         .md_reg[0] = 0x3d44,
2636         .md_reg[1] = 0x3d48,
2637         .bank_reg = 0x3d40,
2638         .mn[0] = {
2639                 .mnctr_en_bit = 8,
2640                 .mnctr_reset_bit = 7,
2641                 .mnctr_mode_shift = 5,
2642                 .n_val_shift = 16,
2643                 .m_val_shift = 16,
2644                 .width = 8,
2645         },
2646         .mn[1] = {
2647                 .mnctr_en_bit = 8,
2648                 .mnctr_reset_bit = 7,
2649                 .mnctr_mode_shift = 5,
2650                 .n_val_shift = 16,
2651                 .m_val_shift = 16,
2652                 .width = 8,
2653         },
2654         .s[0] = {
2655                 .src_sel_shift = 0,
2656                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2657         },
2658         .s[1] = {
2659                 .src_sel_shift = 0,
2660                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2661         },
2662         .p[0] = {
2663                 .pre_div_shift = 3,
2664                 .pre_div_width = 2,
2665         },
2666         .p[1] = {
2667                 .pre_div_shift = 3,
2668                 .pre_div_width = 2,
2669         },
2670         .mux_sel_bit = 0,
2671         .freq_tbl = clk_tbl_nss,
2672         .clkr = {
2673                 .enable_reg = 0x3d40,
2674                 .enable_mask = BIT(1),
2675                 .hw.init = &(struct clk_init_data){
2676                         .name = "ubi32_core2_src_clk",
2677                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2678                         .num_parents = 5,
2679                         .ops = &clk_dyn_rcg_ops,
2680                         .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2681                 },
2682         },
2683 };
2684
2685 static struct clk_regmap *gcc_ipq806x_clks[] = {
2686         [PLL0] = &pll0.clkr,
2687         [PLL0_VOTE] = &pll0_vote,
2688         [PLL3] = &pll3.clkr,
2689         [PLL4_VOTE] = &pll4_vote,
2690         [PLL8] = &pll8.clkr,
2691         [PLL8_VOTE] = &pll8_vote,
2692         [PLL14] = &pll14.clkr,
2693         [PLL14_VOTE] = &pll14_vote,
2694         [PLL18] = &pll18.clkr,
2695         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2696         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2697         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2698         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2699         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2700         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2701         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2702         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2703         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2704         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2705         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2706         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2707         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2708         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2709         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2710         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2711         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2712         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2713         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2714         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2715         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2716         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2717         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2718         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2719         [GP0_SRC] = &gp0_src.clkr,
2720         [GP0_CLK] = &gp0_clk.clkr,
2721         [GP1_SRC] = &gp1_src.clkr,
2722         [GP1_CLK] = &gp1_clk.clkr,
2723         [GP2_SRC] = &gp2_src.clkr,
2724         [GP2_CLK] = &gp2_clk.clkr,
2725         [PMEM_A_CLK] = &pmem_clk.clkr,
2726         [PRNG_SRC] = &prng_src.clkr,
2727         [PRNG_CLK] = &prng_clk.clkr,
2728         [SDC1_SRC] = &sdc1_src.clkr,
2729         [SDC1_CLK] = &sdc1_clk.clkr,
2730         [SDC3_SRC] = &sdc3_src.clkr,
2731         [SDC3_CLK] = &sdc3_clk.clkr,
2732         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2733         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2734         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2735         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2736         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2737         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2738         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2739         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2740         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2741         [TSIF_H_CLK] = &tsif_h_clk.clkr,
2742         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2743         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2744         [ADM0_CLK] = &adm0_clk.clkr,
2745         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2746         [PCIE_A_CLK] = &pcie_a_clk.clkr,
2747         [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2748         [PCIE_H_CLK] = &pcie_h_clk.clkr,
2749         [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2750         [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2751         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2752         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2753         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2754         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2755         [SATA_H_CLK] = &sata_h_clk.clkr,
2756         [SATA_CLK_SRC] = &sata_ref_src.clkr,
2757         [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2758         [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2759         [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2760         [SATA_A_CLK] = &sata_a_clk.clkr,
2761         [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2762         [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2763         [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2764         [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2765         [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2766         [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2767         [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2768         [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2769         [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2770         [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2771         [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2772         [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2773         [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2774         [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2775         [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2776         [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2777         [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2778         [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2779         [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2780         [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2781         [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2782         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2783         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2784         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2785         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2786         [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2787         [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2788         [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2789         [EBI2_CLK] = &ebi2_clk.clkr,
2790         [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
2791         [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
2792         [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
2793         [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
2794         [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
2795         [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
2796         [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
2797         [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
2798         [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
2799         [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
2800         [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
2801         [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
2802         [NSSTCM_CLK] = &nss_tcm_clk.clkr,
2803 };
2804
2805 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2806         [QDSS_STM_RESET] = { 0x2060, 6 },
2807         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2808         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2809         [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2810         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2811         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2812         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2813         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2814         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2815         [ADM0_C2_RESET] = { 0x220c, 4 },
2816         [ADM0_C1_RESET] = { 0x220c, 3 },
2817         [ADM0_C0_RESET] = { 0x220c, 2 },
2818         [ADM0_PBUS_RESET] = { 0x220c, 1 },
2819         [ADM0_RESET] = { 0x220c, 0 },
2820         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2821         [QDSS_POR_RESET] = { 0x2260, 4 },
2822         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2823         [QDSS_HRESET_RESET] = { 0x2260, 2 },
2824         [QDSS_AXI_RESET] = { 0x2260, 1 },
2825         [QDSS_DBG_RESET] = { 0x2260, 0 },
2826         [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2827         [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2828         [PCIE_EXT_RESET] = { 0x22dc, 6 },
2829         [PCIE_PHY_RESET] = { 0x22dc, 5 },
2830         [PCIE_PCI_RESET] = { 0x22dc, 4 },
2831         [PCIE_POR_RESET] = { 0x22dc, 3 },
2832         [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2833         [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2834         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2835         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2836         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2837         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2838         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2839         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2840         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2841         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2842         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2843         [DFAB_ARB0_RESET] = { 0x2560, 7 },
2844         [DFAB_ARB1_RESET] = { 0x2564, 7 },
2845         [PPSS_PROC_RESET] = { 0x2594, 1 },
2846         [PPSS_RESET] = { 0x2594, 0 },
2847         [DMA_BAM_RESET] = { 0x25c0, 7 },
2848         [SPS_TIC_H_RESET] = { 0x2600, 7 },
2849         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2850         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2851         [TSIF_H_RESET] = { 0x2700, 7 },
2852         [CE1_H_RESET] = { 0x2720, 7 },
2853         [CE1_CORE_RESET] = { 0x2724, 7 },
2854         [CE1_SLEEP_RESET] = { 0x2728, 7 },
2855         [CE2_H_RESET] = { 0x2740, 7 },
2856         [CE2_CORE_RESET] = { 0x2744, 7 },
2857         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2858         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2859         [RPM_PROC_RESET] = { 0x27c0, 7 },
2860         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2861         [SDC1_RESET] = { 0x2830, 0 },
2862         [SDC2_RESET] = { 0x2850, 0 },
2863         [SDC3_RESET] = { 0x2870, 0 },
2864         [SDC4_RESET] = { 0x2890, 0 },
2865         [USB_HS1_RESET] = { 0x2910, 0 },
2866         [USB_HSIC_RESET] = { 0x2934, 0 },
2867         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2868         [USB_FS1_RESET] = { 0x2974, 0 },
2869         [GSBI1_RESET] = { 0x29dc, 0 },
2870         [GSBI2_RESET] = { 0x29fc, 0 },
2871         [GSBI3_RESET] = { 0x2a1c, 0 },
2872         [GSBI4_RESET] = { 0x2a3c, 0 },
2873         [GSBI5_RESET] = { 0x2a5c, 0 },
2874         [GSBI6_RESET] = { 0x2a7c, 0 },
2875         [GSBI7_RESET] = { 0x2a9c, 0 },
2876         [SPDM_RESET] = { 0x2b6c, 0 },
2877         [SEC_CTRL_RESET] = { 0x2b80, 7 },
2878         [TLMM_H_RESET] = { 0x2ba0, 7 },
2879         [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2880         [SATA_RESET] = { 0x2c1c, 0 },
2881         [TSSC_RESET] = { 0x2ca0, 7 },
2882         [PDM_RESET] = { 0x2cc0, 12 },
2883         [MPM_H_RESET] = { 0x2da0, 7 },
2884         [MPM_RESET] = { 0x2da4, 0 },
2885         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2886         [PRNG_RESET] = { 0x2e80, 12 },
2887         [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2888         [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2889         [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2890         [PCIE_1_M_RESET] = { 0x3a98, 1 },
2891         [PCIE_1_S_RESET] = { 0x3a98, 0 },
2892         [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2893         [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2894         [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2895         [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2896         [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2897         [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2898         [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2899         [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2900         [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2901         [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2902         [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2903         [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2904         [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2905         [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2906         [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2907         [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2908         [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2909         [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2910         [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2911         [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2912         [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2913         [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2914         [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2915         [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2916         [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2917         [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2918         [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2919         [NSSFB0_RESET] = { 0x3b60, 6 },
2920         [NSSFB1_RESET] = { 0x3b60, 7 },
2921         [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
2922         [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
2923         [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
2924         [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
2925         [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
2926         [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
2927         [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
2928         [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
2929         [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
2930         [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
2931         [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
2932         [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
2933         [GMAC_AHB_RESET] = { 0x3e24, 0 },
2934         [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
2935         [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
2936         [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
2937         [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
2938         [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
2939         [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
2940         [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
2941         [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
2942         [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
2943         [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
2944         [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
2945         [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
2946         [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
2947         [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
2948         [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
2949         [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
2950         [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
2951         [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
2952         [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
2953         [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
2954         [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
2955         [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
2956         [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
2957         [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
2958         [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
2959         [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
2960         [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
2961         [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
2962         [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
2963 };
2964
2965 static const struct regmap_config gcc_ipq806x_regmap_config = {
2966         .reg_bits       = 32,
2967         .reg_stride     = 4,
2968         .val_bits       = 32,
2969         .max_register   = 0x3e40,
2970         .fast_io        = true,
2971 };
2972
2973 static const struct qcom_cc_desc gcc_ipq806x_desc = {
2974         .config = &gcc_ipq806x_regmap_config,
2975         .clks = gcc_ipq806x_clks,
2976         .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
2977         .resets = gcc_ipq806x_resets,
2978         .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
2979 };
2980
2981 static const struct of_device_id gcc_ipq806x_match_table[] = {
2982         { .compatible = "qcom,gcc-ipq8064" },
2983         { }
2984 };
2985 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
2986
2987 static int gcc_ipq806x_probe(struct platform_device *pdev)
2988 {
2989         struct device *dev = &pdev->dev;
2990         struct regmap *regmap;
2991         int ret;
2992
2993         ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
2994         if (ret)
2995                 return ret;
2996
2997         ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
2998         if (ret)
2999                 return ret;
3000
3001         ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
3002         if (ret)
3003                 return ret;
3004
3005         regmap = dev_get_regmap(dev, NULL);
3006         if (!regmap)
3007                 return -ENODEV;
3008
3009         /* Setup PLL18 static bits */
3010         regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
3011         regmap_write(regmap, 0x31b0, 0x3080);
3012
3013         /* Set GMAC footswitch sleep/wakeup values */
3014         regmap_write(regmap, 0x3cb8, 8);
3015         regmap_write(regmap, 0x3cd8, 8);
3016         regmap_write(regmap, 0x3cf8, 8);
3017         regmap_write(regmap, 0x3d18, 8);
3018
3019         return 0;
3020 }
3021
3022 static struct platform_driver gcc_ipq806x_driver = {
3023         .probe          = gcc_ipq806x_probe,
3024         .driver         = {
3025                 .name   = "gcc-ipq806x",
3026                 .of_match_table = gcc_ipq806x_match_table,
3027         },
3028 };
3029
3030 static int __init gcc_ipq806x_init(void)
3031 {
3032         return platform_driver_register(&gcc_ipq806x_driver);
3033 }
3034 core_initcall(gcc_ipq806x_init);
3035
3036 static void __exit gcc_ipq806x_exit(void)
3037 {
3038         platform_driver_unregister(&gcc_ipq806x_driver);
3039 }
3040 module_exit(gcc_ipq806x_exit);
3041
3042 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
3043 MODULE_LICENSE("GPL v2");
3044 MODULE_ALIAS("platform:gcc-ipq806x");