2 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
17 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/clk-provider.h>
21 #include <linux/regmap.h>
23 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
26 #include "clk-regmap.h"
29 #include "clk-branch.h"
30 #include "clk-alpha-pll.h"
31 #include "clk-regmap-divider.h"
32 #include "clk-regmap-mux.h"
59 static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
62 "gpll0_out_main_div2",
65 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
71 static const char * const gcc_xo_gpll0[] = {
76 static const struct parent_map gcc_xo_gpll0_map[] = {
81 static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
85 "gpll0_out_main_div2",
88 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
95 static const char * const gcc_xo_gpll0_sleep_clk[] = {
101 static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
107 static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
111 "gpll0_out_main_div2",
114 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
121 static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
123 "gpll0_out_main_div2",
127 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
133 static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
134 "usb3phy_0_cc_pipe_clk",
138 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
139 { P_USB3PHY_0_PIPE, 0 },
143 static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
144 "usb3phy_1_cc_pipe_clk",
148 static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
149 { P_USB3PHY_1_PIPE, 0 },
153 static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
154 "pcie20_phy0_pipe_clk",
158 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
159 { P_PCIE20_PHY0_PIPE, 0 },
163 static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
164 "pcie20_phy1_pipe_clk",
168 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
169 { P_PCIE20_PHY1_PIPE, 0 },
173 static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
177 "gpll0_out_main_div2",
180 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
187 static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
191 "gpll0_out_main_div2",
194 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
201 static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
203 "bias_pll_nss_noc_clk",
208 static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
210 { P_BIAS_PLL_NSS_NOC, 1 },
215 static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
221 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
223 { P_NSS_CRYPTO_PLL, 1 },
227 static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
236 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
245 static const char * const gcc_xo_gpll0_out_main_div2[] = {
247 "gpll0_out_main_div2",
250 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
255 static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
264 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
269 { P_NSS_CRYPTO_PLL, 4 },
273 static const char * const gcc_xo_gpll0_gpll4[] = {
279 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
285 static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
287 "uniphy0_gcc_rx_clk",
288 "uniphy0_gcc_tx_clk",
293 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
301 static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
303 "uniphy0_gcc_tx_clk",
304 "uniphy0_gcc_rx_clk",
309 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
317 static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
319 "uniphy0_gcc_rx_clk",
320 "uniphy0_gcc_tx_clk",
321 "uniphy1_gcc_rx_clk",
322 "uniphy1_gcc_tx_clk",
327 static const struct parent_map
328 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
338 static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
340 "uniphy0_gcc_tx_clk",
341 "uniphy0_gcc_rx_clk",
342 "uniphy1_gcc_tx_clk",
343 "uniphy1_gcc_rx_clk",
348 static const struct parent_map
349 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
359 static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
361 "uniphy2_gcc_rx_clk",
362 "uniphy2_gcc_tx_clk",
367 static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
375 static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
377 "uniphy2_gcc_tx_clk",
378 "uniphy2_gcc_rx_clk",
383 static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
391 static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
395 "gpll0_out_main_div2",
399 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
407 static struct clk_alpha_pll gpll0_main = {
409 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
411 .enable_reg = 0x0b000,
412 .enable_mask = BIT(0),
413 .hw.init = &(struct clk_init_data){
414 .name = "gpll0_main",
415 .parent_names = (const char *[]){
419 .ops = &clk_alpha_pll_ops,
424 static struct clk_fixed_factor gpll0_out_main_div2 = {
427 .hw.init = &(struct clk_init_data){
428 .name = "gpll0_out_main_div2",
429 .parent_names = (const char *[]){
433 .ops = &clk_fixed_factor_ops,
434 .flags = CLK_SET_RATE_PARENT,
438 static struct clk_alpha_pll_postdiv gpll0 = {
440 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
442 .clkr.hw.init = &(struct clk_init_data){
444 .parent_names = (const char *[]){
448 .ops = &clk_alpha_pll_postdiv_ro_ops,
452 static struct clk_alpha_pll gpll2_main = {
454 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
456 .enable_reg = 0x0b000,
457 .enable_mask = BIT(2),
458 .hw.init = &(struct clk_init_data){
459 .name = "gpll2_main",
460 .parent_names = (const char *[]){
464 .ops = &clk_alpha_pll_ops,
465 .flags = CLK_IS_CRITICAL,
470 static struct clk_alpha_pll_postdiv gpll2 = {
472 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
474 .clkr.hw.init = &(struct clk_init_data){
476 .parent_names = (const char *[]){
480 .ops = &clk_alpha_pll_postdiv_ro_ops,
481 .flags = CLK_SET_RATE_PARENT,
485 static struct clk_alpha_pll gpll4_main = {
487 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
489 .enable_reg = 0x0b000,
490 .enable_mask = BIT(5),
491 .hw.init = &(struct clk_init_data){
492 .name = "gpll4_main",
493 .parent_names = (const char *[]){
497 .ops = &clk_alpha_pll_ops,
498 .flags = CLK_IS_CRITICAL,
503 static struct clk_alpha_pll_postdiv gpll4 = {
505 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
507 .clkr.hw.init = &(struct clk_init_data){
509 .parent_names = (const char *[]){
513 .ops = &clk_alpha_pll_postdiv_ro_ops,
514 .flags = CLK_SET_RATE_PARENT,
518 static struct clk_alpha_pll gpll6_main = {
520 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
521 .flags = SUPPORTS_DYNAMIC_UPDATE,
523 .enable_reg = 0x0b000,
524 .enable_mask = BIT(7),
525 .hw.init = &(struct clk_init_data){
526 .name = "gpll6_main",
527 .parent_names = (const char *[]){
531 .ops = &clk_alpha_pll_ops,
532 .flags = CLK_IS_CRITICAL,
537 static struct clk_alpha_pll_postdiv gpll6 = {
539 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
541 .clkr.hw.init = &(struct clk_init_data){
543 .parent_names = (const char *[]){
547 .ops = &clk_alpha_pll_postdiv_ro_ops,
548 .flags = CLK_SET_RATE_PARENT,
552 static struct clk_fixed_factor gpll6_out_main_div2 = {
555 .hw.init = &(struct clk_init_data){
556 .name = "gpll6_out_main_div2",
557 .parent_names = (const char *[]){
561 .ops = &clk_fixed_factor_ops,
562 .flags = CLK_SET_RATE_PARENT,
566 static struct clk_alpha_pll ubi32_pll_main = {
568 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
569 .flags = SUPPORTS_DYNAMIC_UPDATE,
571 .enable_reg = 0x0b000,
572 .enable_mask = BIT(6),
573 .hw.init = &(struct clk_init_data){
574 .name = "ubi32_pll_main",
575 .parent_names = (const char *[]){
579 .ops = &clk_alpha_pll_huayra_ops,
584 static struct clk_alpha_pll_postdiv ubi32_pll = {
586 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
588 .clkr.hw.init = &(struct clk_init_data){
590 .parent_names = (const char *[]){
594 .ops = &clk_alpha_pll_postdiv_ro_ops,
595 .flags = CLK_SET_RATE_PARENT,
599 static struct clk_alpha_pll nss_crypto_pll_main = {
601 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
603 .enable_reg = 0x0b000,
604 .enable_mask = BIT(4),
605 .hw.init = &(struct clk_init_data){
606 .name = "nss_crypto_pll_main",
607 .parent_names = (const char *[]){
611 .ops = &clk_alpha_pll_ops,
616 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
618 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
620 .clkr.hw.init = &(struct clk_init_data){
621 .name = "nss_crypto_pll",
622 .parent_names = (const char *[]){
623 "nss_crypto_pll_main"
626 .ops = &clk_alpha_pll_postdiv_ro_ops,
627 .flags = CLK_SET_RATE_PARENT,
631 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
632 F(19200000, P_XO, 1, 0, 0),
633 F(50000000, P_GPLL0, 16, 0, 0),
634 F(100000000, P_GPLL0, 8, 0, 0),
638 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
640 .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
642 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
643 .clkr.hw.init = &(struct clk_init_data){
644 .name = "pcnoc_bfdcd_clk_src",
645 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
647 .ops = &clk_rcg2_ops,
648 .flags = CLK_IS_CRITICAL,
652 static struct clk_fixed_factor pcnoc_clk_src = {
655 .hw.init = &(struct clk_init_data){
656 .name = "pcnoc_clk_src",
657 .parent_names = (const char *[]){
658 "pcnoc_bfdcd_clk_src"
661 .ops = &clk_fixed_factor_ops,
662 .flags = CLK_SET_RATE_PARENT,
666 static struct clk_branch gcc_sleep_clk_src = {
669 .enable_reg = 0x30000,
670 .enable_mask = BIT(1),
671 .hw.init = &(struct clk_init_data){
672 .name = "gcc_sleep_clk_src",
673 .parent_names = (const char *[]){
677 .ops = &clk_branch2_ops,
678 .flags = CLK_IS_CRITICAL,
683 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
684 F(19200000, P_XO, 1, 0, 0),
685 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
686 F(50000000, P_GPLL0, 16, 0, 0),
690 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
692 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
694 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
695 .clkr.hw.init = &(struct clk_init_data){
696 .name = "blsp1_qup1_i2c_apps_clk_src",
697 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
699 .ops = &clk_rcg2_ops,
703 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
704 F(960000, P_XO, 10, 1, 2),
705 F(4800000, P_XO, 4, 0, 0),
706 F(9600000, P_XO, 2, 0, 0),
707 F(12500000, P_GPLL0_DIV2, 16, 1, 2),
708 F(16000000, P_GPLL0, 10, 1, 5),
709 F(19200000, P_XO, 1, 0, 0),
710 F(25000000, P_GPLL0, 16, 1, 2),
711 F(50000000, P_GPLL0, 16, 0, 0),
715 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
717 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
720 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
721 .clkr.hw.init = &(struct clk_init_data){
722 .name = "blsp1_qup1_spi_apps_clk_src",
723 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
725 .ops = &clk_rcg2_ops,
729 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
731 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
733 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
734 .clkr.hw.init = &(struct clk_init_data){
735 .name = "blsp1_qup2_i2c_apps_clk_src",
736 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
738 .ops = &clk_rcg2_ops,
742 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
744 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
747 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
748 .clkr.hw.init = &(struct clk_init_data){
749 .name = "blsp1_qup2_spi_apps_clk_src",
750 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
752 .ops = &clk_rcg2_ops,
756 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
758 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
760 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
761 .clkr.hw.init = &(struct clk_init_data){
762 .name = "blsp1_qup3_i2c_apps_clk_src",
763 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
765 .ops = &clk_rcg2_ops,
769 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
771 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
774 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
775 .clkr.hw.init = &(struct clk_init_data){
776 .name = "blsp1_qup3_spi_apps_clk_src",
777 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
779 .ops = &clk_rcg2_ops,
783 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
785 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
787 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "blsp1_qup4_i2c_apps_clk_src",
790 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
792 .ops = &clk_rcg2_ops,
796 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
798 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
801 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
802 .clkr.hw.init = &(struct clk_init_data){
803 .name = "blsp1_qup4_spi_apps_clk_src",
804 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
806 .ops = &clk_rcg2_ops,
810 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
812 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
814 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
815 .clkr.hw.init = &(struct clk_init_data){
816 .name = "blsp1_qup5_i2c_apps_clk_src",
817 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
819 .ops = &clk_rcg2_ops,
823 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
825 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
828 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
829 .clkr.hw.init = &(struct clk_init_data){
830 .name = "blsp1_qup5_spi_apps_clk_src",
831 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
833 .ops = &clk_rcg2_ops,
837 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
839 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
841 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
842 .clkr.hw.init = &(struct clk_init_data){
843 .name = "blsp1_qup6_i2c_apps_clk_src",
844 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
846 .ops = &clk_rcg2_ops,
850 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
852 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
855 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
856 .clkr.hw.init = &(struct clk_init_data){
857 .name = "blsp1_qup6_spi_apps_clk_src",
858 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
860 .ops = &clk_rcg2_ops,
864 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
865 F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
866 F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
867 F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
868 F(16000000, P_GPLL0_DIV2, 5, 1, 5),
869 F(19200000, P_XO, 1, 0, 0),
870 F(24000000, P_GPLL0, 1, 3, 100),
871 F(25000000, P_GPLL0, 16, 1, 2),
872 F(32000000, P_GPLL0, 1, 1, 25),
873 F(40000000, P_GPLL0, 1, 1, 20),
874 F(46400000, P_GPLL0, 1, 29, 500),
875 F(48000000, P_GPLL0, 1, 3, 50),
876 F(51200000, P_GPLL0, 1, 8, 125),
877 F(56000000, P_GPLL0, 1, 7, 100),
878 F(58982400, P_GPLL0, 1, 1152, 15625),
879 F(60000000, P_GPLL0, 1, 3, 40),
880 F(64000000, P_GPLL0, 12.5, 1, 1),
884 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
886 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
889 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
890 .clkr.hw.init = &(struct clk_init_data){
891 .name = "blsp1_uart1_apps_clk_src",
892 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
894 .ops = &clk_rcg2_ops,
898 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
900 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
903 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
904 .clkr.hw.init = &(struct clk_init_data){
905 .name = "blsp1_uart2_apps_clk_src",
906 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
908 .ops = &clk_rcg2_ops,
912 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
914 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
917 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
918 .clkr.hw.init = &(struct clk_init_data){
919 .name = "blsp1_uart3_apps_clk_src",
920 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
922 .ops = &clk_rcg2_ops,
926 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
928 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
931 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
932 .clkr.hw.init = &(struct clk_init_data){
933 .name = "blsp1_uart4_apps_clk_src",
934 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
936 .ops = &clk_rcg2_ops,
940 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
942 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
945 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
946 .clkr.hw.init = &(struct clk_init_data){
947 .name = "blsp1_uart5_apps_clk_src",
948 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
950 .ops = &clk_rcg2_ops,
954 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
956 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
959 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
960 .clkr.hw.init = &(struct clk_init_data){
961 .name = "blsp1_uart6_apps_clk_src",
962 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
964 .ops = &clk_rcg2_ops,
968 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
969 F(19200000, P_XO, 1, 0, 0),
970 F(200000000, P_GPLL0, 4, 0, 0),
974 static struct clk_rcg2 pcie0_axi_clk_src = {
976 .freq_tbl = ftbl_pcie_axi_clk_src,
978 .parent_map = gcc_xo_gpll0_map,
979 .clkr.hw.init = &(struct clk_init_data){
980 .name = "pcie0_axi_clk_src",
981 .parent_names = gcc_xo_gpll0,
983 .ops = &clk_rcg2_ops,
987 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
988 F(19200000, P_XO, 1, 0, 0),
991 static struct clk_rcg2 pcie0_aux_clk_src = {
993 .freq_tbl = ftbl_pcie_aux_clk_src,
996 .parent_map = gcc_xo_gpll0_sleep_clk_map,
997 .clkr.hw.init = &(struct clk_init_data){
998 .name = "pcie0_aux_clk_src",
999 .parent_names = gcc_xo_gpll0_sleep_clk,
1001 .ops = &clk_rcg2_ops,
1005 static struct clk_regmap_mux pcie0_pipe_clk_src = {
1009 .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1011 .hw.init = &(struct clk_init_data){
1012 .name = "pcie0_pipe_clk_src",
1013 .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
1015 .ops = &clk_regmap_mux_closest_ops,
1016 .flags = CLK_SET_RATE_PARENT,
1021 static struct clk_rcg2 pcie1_axi_clk_src = {
1022 .cmd_rcgr = 0x76054,
1023 .freq_tbl = ftbl_pcie_axi_clk_src,
1025 .parent_map = gcc_xo_gpll0_map,
1026 .clkr.hw.init = &(struct clk_init_data){
1027 .name = "pcie1_axi_clk_src",
1028 .parent_names = gcc_xo_gpll0,
1030 .ops = &clk_rcg2_ops,
1034 static struct clk_rcg2 pcie1_aux_clk_src = {
1035 .cmd_rcgr = 0x76024,
1036 .freq_tbl = ftbl_pcie_aux_clk_src,
1039 .parent_map = gcc_xo_gpll0_sleep_clk_map,
1040 .clkr.hw.init = &(struct clk_init_data){
1041 .name = "pcie1_aux_clk_src",
1042 .parent_names = gcc_xo_gpll0_sleep_clk,
1044 .ops = &clk_rcg2_ops,
1048 static struct clk_regmap_mux pcie1_pipe_clk_src = {
1052 .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
1054 .hw.init = &(struct clk_init_data){
1055 .name = "pcie1_pipe_clk_src",
1056 .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
1058 .ops = &clk_regmap_mux_closest_ops,
1059 .flags = CLK_SET_RATE_PARENT,
1064 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1065 F(144000, P_XO, 16, 3, 25),
1066 F(400000, P_XO, 12, 1, 4),
1067 F(24000000, P_GPLL2, 12, 1, 4),
1068 F(48000000, P_GPLL2, 12, 1, 2),
1069 F(96000000, P_GPLL2, 12, 0, 0),
1070 F(177777778, P_GPLL0, 4.5, 0, 0),
1071 F(192000000, P_GPLL2, 6, 0, 0),
1072 F(384000000, P_GPLL2, 3, 0, 0),
1076 static struct clk_rcg2 sdcc1_apps_clk_src = {
1077 .cmd_rcgr = 0x42004,
1078 .freq_tbl = ftbl_sdcc_apps_clk_src,
1081 .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1082 .clkr.hw.init = &(struct clk_init_data){
1083 .name = "sdcc1_apps_clk_src",
1084 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1086 .ops = &clk_rcg2_floor_ops,
1090 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1091 F(19200000, P_XO, 1, 0, 0),
1092 F(160000000, P_GPLL0, 5, 0, 0),
1093 F(308570000, P_GPLL6, 3.5, 0, 0),
1096 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1097 .cmd_rcgr = 0x5d000,
1098 .freq_tbl = ftbl_sdcc_ice_core_clk_src,
1101 .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1102 .clkr.hw.init = &(struct clk_init_data){
1103 .name = "sdcc1_ice_core_clk_src",
1104 .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
1106 .ops = &clk_rcg2_ops,
1110 static struct clk_rcg2 sdcc2_apps_clk_src = {
1111 .cmd_rcgr = 0x43004,
1112 .freq_tbl = ftbl_sdcc_apps_clk_src,
1115 .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1116 .clkr.hw.init = &(struct clk_init_data){
1117 .name = "sdcc2_apps_clk_src",
1118 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1120 .ops = &clk_rcg2_ops,
1124 static const struct freq_tbl ftbl_usb_master_clk_src[] = {
1125 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1126 F(100000000, P_GPLL0, 8, 0, 0),
1127 F(133330000, P_GPLL0, 6, 0, 0),
1131 static struct clk_rcg2 usb0_master_clk_src = {
1132 .cmd_rcgr = 0x3e00c,
1133 .freq_tbl = ftbl_usb_master_clk_src,
1136 .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1137 .clkr.hw.init = &(struct clk_init_data){
1138 .name = "usb0_master_clk_src",
1139 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1141 .ops = &clk_rcg2_ops,
1145 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1146 F(19200000, P_XO, 1, 0, 0),
1150 static struct clk_rcg2 usb0_aux_clk_src = {
1151 .cmd_rcgr = 0x3e05c,
1152 .freq_tbl = ftbl_usb_aux_clk_src,
1155 .parent_map = gcc_xo_gpll0_sleep_clk_map,
1156 .clkr.hw.init = &(struct clk_init_data){
1157 .name = "usb0_aux_clk_src",
1158 .parent_names = gcc_xo_gpll0_sleep_clk,
1160 .ops = &clk_rcg2_ops,
1164 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1165 F(19200000, P_XO, 1, 0, 0),
1166 F(20000000, P_GPLL6, 6, 1, 9),
1167 F(60000000, P_GPLL6, 6, 1, 3),
1171 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1172 .cmd_rcgr = 0x3e020,
1173 .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1176 .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1177 .clkr.hw.init = &(struct clk_init_data){
1178 .name = "usb0_mock_utmi_clk_src",
1179 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1181 .ops = &clk_rcg2_ops,
1185 static struct clk_regmap_mux usb0_pipe_clk_src = {
1189 .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1191 .hw.init = &(struct clk_init_data){
1192 .name = "usb0_pipe_clk_src",
1193 .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
1195 .ops = &clk_regmap_mux_closest_ops,
1196 .flags = CLK_SET_RATE_PARENT,
1201 static struct clk_rcg2 usb1_master_clk_src = {
1202 .cmd_rcgr = 0x3f00c,
1203 .freq_tbl = ftbl_usb_master_clk_src,
1206 .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1207 .clkr.hw.init = &(struct clk_init_data){
1208 .name = "usb1_master_clk_src",
1209 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1211 .ops = &clk_rcg2_ops,
1215 static struct clk_rcg2 usb1_aux_clk_src = {
1216 .cmd_rcgr = 0x3f05c,
1217 .freq_tbl = ftbl_usb_aux_clk_src,
1220 .parent_map = gcc_xo_gpll0_sleep_clk_map,
1221 .clkr.hw.init = &(struct clk_init_data){
1222 .name = "usb1_aux_clk_src",
1223 .parent_names = gcc_xo_gpll0_sleep_clk,
1225 .ops = &clk_rcg2_ops,
1229 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1230 .cmd_rcgr = 0x3f020,
1231 .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1234 .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1235 .clkr.hw.init = &(struct clk_init_data){
1236 .name = "usb1_mock_utmi_clk_src",
1237 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1239 .ops = &clk_rcg2_ops,
1243 static struct clk_regmap_mux usb1_pipe_clk_src = {
1247 .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1249 .hw.init = &(struct clk_init_data){
1250 .name = "usb1_pipe_clk_src",
1251 .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
1253 .ops = &clk_regmap_mux_closest_ops,
1254 .flags = CLK_SET_RATE_PARENT,
1259 static struct clk_branch gcc_xo_clk_src = {
1260 .halt_reg = 0x30018,
1262 .enable_reg = 0x30018,
1263 .enable_mask = BIT(1),
1264 .hw.init = &(struct clk_init_data){
1265 .name = "gcc_xo_clk_src",
1266 .parent_names = (const char *[]){
1270 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1271 .ops = &clk_branch2_ops,
1276 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1279 .hw.init = &(struct clk_init_data){
1280 .name = "gcc_xo_div4_clk_src",
1281 .parent_names = (const char *[]){
1285 .ops = &clk_fixed_factor_ops,
1286 .flags = CLK_SET_RATE_PARENT,
1290 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1291 F(19200000, P_XO, 1, 0, 0),
1292 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1293 F(100000000, P_GPLL0, 8, 0, 0),
1294 F(133333333, P_GPLL0, 6, 0, 0),
1295 F(160000000, P_GPLL0, 5, 0, 0),
1296 F(200000000, P_GPLL0, 4, 0, 0),
1297 F(266666667, P_GPLL0, 3, 0, 0),
1301 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1302 .cmd_rcgr = 0x26004,
1303 .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1305 .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1306 .clkr.hw.init = &(struct clk_init_data){
1307 .name = "system_noc_bfdcd_clk_src",
1308 .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1310 .ops = &clk_rcg2_ops,
1311 .flags = CLK_IS_CRITICAL,
1315 static struct clk_fixed_factor system_noc_clk_src = {
1318 .hw.init = &(struct clk_init_data){
1319 .name = "system_noc_clk_src",
1320 .parent_names = (const char *[]){
1321 "system_noc_bfdcd_clk_src"
1324 .ops = &clk_fixed_factor_ops,
1325 .flags = CLK_SET_RATE_PARENT,
1329 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1330 F(19200000, P_XO, 1, 0, 0),
1331 F(200000000, P_GPLL0, 4, 0, 0),
1335 static struct clk_rcg2 nss_ce_clk_src = {
1336 .cmd_rcgr = 0x68098,
1337 .freq_tbl = ftbl_nss_ce_clk_src,
1339 .parent_map = gcc_xo_gpll0_map,
1340 .clkr.hw.init = &(struct clk_init_data){
1341 .name = "nss_ce_clk_src",
1342 .parent_names = gcc_xo_gpll0,
1344 .ops = &clk_rcg2_ops,
1348 static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1349 F(19200000, P_XO, 1, 0, 0),
1350 F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1354 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1355 .cmd_rcgr = 0x68088,
1356 .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1358 .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1359 .clkr.hw.init = &(struct clk_init_data){
1360 .name = "nss_noc_bfdcd_clk_src",
1361 .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1363 .ops = &clk_rcg2_ops,
1367 static struct clk_fixed_factor nss_noc_clk_src = {
1370 .hw.init = &(struct clk_init_data){
1371 .name = "nss_noc_clk_src",
1372 .parent_names = (const char *[]){
1373 "nss_noc_bfdcd_clk_src"
1376 .ops = &clk_fixed_factor_ops,
1377 .flags = CLK_SET_RATE_PARENT,
1381 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1382 F(19200000, P_XO, 1, 0, 0),
1383 F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1387 static struct clk_rcg2 nss_crypto_clk_src = {
1388 .cmd_rcgr = 0x68144,
1389 .freq_tbl = ftbl_nss_crypto_clk_src,
1392 .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1393 .clkr.hw.init = &(struct clk_init_data){
1394 .name = "nss_crypto_clk_src",
1395 .parent_names = gcc_xo_nss_crypto_pll_gpll0,
1397 .ops = &clk_rcg2_ops,
1401 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1402 F(19200000, P_XO, 1, 0, 0),
1403 F(187200000, P_UBI32_PLL, 8, 0, 0),
1404 F(748800000, P_UBI32_PLL, 2, 0, 0),
1405 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1406 F(1689600000, P_UBI32_PLL, 1, 0, 0),
1410 static struct clk_rcg2 nss_ubi0_clk_src = {
1411 .cmd_rcgr = 0x68104,
1412 .freq_tbl = ftbl_nss_ubi_clk_src,
1414 .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1415 .clkr.hw.init = &(struct clk_init_data){
1416 .name = "nss_ubi0_clk_src",
1417 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1419 .ops = &clk_rcg2_ops,
1420 .flags = CLK_SET_RATE_PARENT,
1424 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1429 .hw.init = &(struct clk_init_data){
1430 .name = "nss_ubi0_div_clk_src",
1431 .parent_names = (const char *[]){
1435 .ops = &clk_regmap_div_ro_ops,
1436 .flags = CLK_SET_RATE_PARENT,
1441 static struct clk_rcg2 nss_ubi1_clk_src = {
1442 .cmd_rcgr = 0x68124,
1443 .freq_tbl = ftbl_nss_ubi_clk_src,
1445 .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1446 .clkr.hw.init = &(struct clk_init_data){
1447 .name = "nss_ubi1_clk_src",
1448 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1450 .ops = &clk_rcg2_ops,
1451 .flags = CLK_SET_RATE_PARENT,
1455 static struct clk_regmap_div nss_ubi1_div_clk_src = {
1460 .hw.init = &(struct clk_init_data){
1461 .name = "nss_ubi1_div_clk_src",
1462 .parent_names = (const char *[]){
1466 .ops = &clk_regmap_div_ro_ops,
1467 .flags = CLK_SET_RATE_PARENT,
1472 static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1473 F(19200000, P_XO, 1, 0, 0),
1474 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1478 static struct clk_rcg2 ubi_mpt_clk_src = {
1479 .cmd_rcgr = 0x68090,
1480 .freq_tbl = ftbl_ubi_mpt_clk_src,
1482 .parent_map = gcc_xo_gpll0_out_main_div2_map,
1483 .clkr.hw.init = &(struct clk_init_data){
1484 .name = "ubi_mpt_clk_src",
1485 .parent_names = gcc_xo_gpll0_out_main_div2,
1487 .ops = &clk_rcg2_ops,
1491 static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1492 F(19200000, P_XO, 1, 0, 0),
1493 F(400000000, P_GPLL0, 2, 0, 0),
1497 static struct clk_rcg2 nss_imem_clk_src = {
1498 .cmd_rcgr = 0x68158,
1499 .freq_tbl = ftbl_nss_imem_clk_src,
1501 .parent_map = gcc_xo_gpll0_gpll4_map,
1502 .clkr.hw.init = &(struct clk_init_data){
1503 .name = "nss_imem_clk_src",
1504 .parent_names = gcc_xo_gpll0_gpll4,
1506 .ops = &clk_rcg2_ops,
1510 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1511 F(19200000, P_XO, 1, 0, 0),
1512 F(300000000, P_BIAS_PLL, 1, 0, 0),
1516 static struct clk_rcg2 nss_ppe_clk_src = {
1517 .cmd_rcgr = 0x68080,
1518 .freq_tbl = ftbl_nss_ppe_clk_src,
1520 .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1521 .clkr.hw.init = &(struct clk_init_data){
1522 .name = "nss_ppe_clk_src",
1523 .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1525 .ops = &clk_rcg2_ops,
1529 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1532 .hw.init = &(struct clk_init_data){
1533 .name = "nss_ppe_cdiv_clk_src",
1534 .parent_names = (const char *[]){
1538 .ops = &clk_fixed_factor_ops,
1539 .flags = CLK_SET_RATE_PARENT,
1543 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
1544 F(19200000, P_XO, 1, 0, 0),
1545 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1546 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1550 static struct clk_rcg2 nss_port1_rx_clk_src = {
1551 .cmd_rcgr = 0x68020,
1552 .freq_tbl = ftbl_nss_port1_rx_clk_src,
1554 .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1555 .clkr.hw.init = &(struct clk_init_data){
1556 .name = "nss_port1_rx_clk_src",
1557 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1559 .ops = &clk_rcg2_ops,
1563 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
1568 .hw.init = &(struct clk_init_data){
1569 .name = "nss_port1_rx_div_clk_src",
1570 .parent_names = (const char *[]){
1571 "nss_port1_rx_clk_src"
1574 .ops = &clk_regmap_div_ops,
1575 .flags = CLK_SET_RATE_PARENT,
1580 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
1581 F(19200000, P_XO, 1, 0, 0),
1582 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1583 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1587 static struct clk_rcg2 nss_port1_tx_clk_src = {
1588 .cmd_rcgr = 0x68028,
1589 .freq_tbl = ftbl_nss_port1_tx_clk_src,
1591 .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1592 .clkr.hw.init = &(struct clk_init_data){
1593 .name = "nss_port1_tx_clk_src",
1594 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1596 .ops = &clk_rcg2_ops,
1600 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
1605 .hw.init = &(struct clk_init_data){
1606 .name = "nss_port1_tx_div_clk_src",
1607 .parent_names = (const char *[]){
1608 "nss_port1_tx_clk_src"
1611 .ops = &clk_regmap_div_ops,
1612 .flags = CLK_SET_RATE_PARENT,
1617 static struct clk_rcg2 nss_port2_rx_clk_src = {
1618 .cmd_rcgr = 0x68030,
1619 .freq_tbl = ftbl_nss_port1_rx_clk_src,
1621 .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1622 .clkr.hw.init = &(struct clk_init_data){
1623 .name = "nss_port2_rx_clk_src",
1624 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1626 .ops = &clk_rcg2_ops,
1630 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1635 .hw.init = &(struct clk_init_data){
1636 .name = "nss_port2_rx_div_clk_src",
1637 .parent_names = (const char *[]){
1638 "nss_port2_rx_clk_src"
1641 .ops = &clk_regmap_div_ops,
1642 .flags = CLK_SET_RATE_PARENT,
1647 static struct clk_rcg2 nss_port2_tx_clk_src = {
1648 .cmd_rcgr = 0x68038,
1649 .freq_tbl = ftbl_nss_port1_tx_clk_src,
1651 .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1652 .clkr.hw.init = &(struct clk_init_data){
1653 .name = "nss_port2_tx_clk_src",
1654 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1656 .ops = &clk_rcg2_ops,
1660 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1665 .hw.init = &(struct clk_init_data){
1666 .name = "nss_port2_tx_div_clk_src",
1667 .parent_names = (const char *[]){
1668 "nss_port2_tx_clk_src"
1671 .ops = &clk_regmap_div_ops,
1672 .flags = CLK_SET_RATE_PARENT,
1677 static struct clk_rcg2 nss_port3_rx_clk_src = {
1678 .cmd_rcgr = 0x68040,
1679 .freq_tbl = ftbl_nss_port1_rx_clk_src,
1681 .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1682 .clkr.hw.init = &(struct clk_init_data){
1683 .name = "nss_port3_rx_clk_src",
1684 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1686 .ops = &clk_rcg2_ops,
1690 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1695 .hw.init = &(struct clk_init_data){
1696 .name = "nss_port3_rx_div_clk_src",
1697 .parent_names = (const char *[]){
1698 "nss_port3_rx_clk_src"
1701 .ops = &clk_regmap_div_ops,
1702 .flags = CLK_SET_RATE_PARENT,
1707 static struct clk_rcg2 nss_port3_tx_clk_src = {
1708 .cmd_rcgr = 0x68048,
1709 .freq_tbl = ftbl_nss_port1_tx_clk_src,
1711 .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1712 .clkr.hw.init = &(struct clk_init_data){
1713 .name = "nss_port3_tx_clk_src",
1714 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1716 .ops = &clk_rcg2_ops,
1720 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1725 .hw.init = &(struct clk_init_data){
1726 .name = "nss_port3_tx_div_clk_src",
1727 .parent_names = (const char *[]){
1728 "nss_port3_tx_clk_src"
1731 .ops = &clk_regmap_div_ops,
1732 .flags = CLK_SET_RATE_PARENT,
1737 static struct clk_rcg2 nss_port4_rx_clk_src = {
1738 .cmd_rcgr = 0x68050,
1739 .freq_tbl = ftbl_nss_port1_rx_clk_src,
1741 .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1742 .clkr.hw.init = &(struct clk_init_data){
1743 .name = "nss_port4_rx_clk_src",
1744 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1746 .ops = &clk_rcg2_ops,
1750 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1755 .hw.init = &(struct clk_init_data){
1756 .name = "nss_port4_rx_div_clk_src",
1757 .parent_names = (const char *[]){
1758 "nss_port4_rx_clk_src"
1761 .ops = &clk_regmap_div_ops,
1762 .flags = CLK_SET_RATE_PARENT,
1767 static struct clk_rcg2 nss_port4_tx_clk_src = {
1768 .cmd_rcgr = 0x68058,
1769 .freq_tbl = ftbl_nss_port1_tx_clk_src,
1771 .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1772 .clkr.hw.init = &(struct clk_init_data){
1773 .name = "nss_port4_tx_clk_src",
1774 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1776 .ops = &clk_rcg2_ops,
1780 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1785 .hw.init = &(struct clk_init_data){
1786 .name = "nss_port4_tx_div_clk_src",
1787 .parent_names = (const char *[]){
1788 "nss_port4_tx_clk_src"
1791 .ops = &clk_regmap_div_ops,
1792 .flags = CLK_SET_RATE_PARENT,
1797 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1798 F(19200000, P_XO, 1, 0, 0),
1799 F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1800 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1801 F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1802 F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1803 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1804 F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1805 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1809 static struct clk_rcg2 nss_port5_rx_clk_src = {
1810 .cmd_rcgr = 0x68060,
1811 .freq_tbl = ftbl_nss_port5_rx_clk_src,
1813 .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1814 .clkr.hw.init = &(struct clk_init_data){
1815 .name = "nss_port5_rx_clk_src",
1816 .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1818 .ops = &clk_rcg2_ops,
1822 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
1827 .hw.init = &(struct clk_init_data){
1828 .name = "nss_port5_rx_div_clk_src",
1829 .parent_names = (const char *[]){
1830 "nss_port5_rx_clk_src"
1833 .ops = &clk_regmap_div_ops,
1834 .flags = CLK_SET_RATE_PARENT,
1839 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1840 F(19200000, P_XO, 1, 0, 0),
1841 F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1842 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1843 F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1844 F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1845 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1846 F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1847 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1851 static struct clk_rcg2 nss_port5_tx_clk_src = {
1852 .cmd_rcgr = 0x68068,
1853 .freq_tbl = ftbl_nss_port5_tx_clk_src,
1855 .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1856 .clkr.hw.init = &(struct clk_init_data){
1857 .name = "nss_port5_tx_clk_src",
1858 .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1860 .ops = &clk_rcg2_ops,
1864 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
1869 .hw.init = &(struct clk_init_data){
1870 .name = "nss_port5_tx_div_clk_src",
1871 .parent_names = (const char *[]){
1872 "nss_port5_tx_clk_src"
1875 .ops = &clk_regmap_div_ops,
1876 .flags = CLK_SET_RATE_PARENT,
1881 static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1882 F(19200000, P_XO, 1, 0, 0),
1883 F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1884 F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1885 F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1886 F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1887 F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1888 F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1889 F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1893 static struct clk_rcg2 nss_port6_rx_clk_src = {
1894 .cmd_rcgr = 0x68070,
1895 .freq_tbl = ftbl_nss_port6_rx_clk_src,
1897 .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1898 .clkr.hw.init = &(struct clk_init_data){
1899 .name = "nss_port6_rx_clk_src",
1900 .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1902 .ops = &clk_rcg2_ops,
1906 static struct clk_regmap_div nss_port6_rx_div_clk_src = {
1911 .hw.init = &(struct clk_init_data){
1912 .name = "nss_port6_rx_div_clk_src",
1913 .parent_names = (const char *[]){
1914 "nss_port6_rx_clk_src"
1917 .ops = &clk_regmap_div_ops,
1918 .flags = CLK_SET_RATE_PARENT,
1923 static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1924 F(19200000, P_XO, 1, 0, 0),
1925 F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1926 F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1927 F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1928 F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1929 F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1930 F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1931 F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1935 static struct clk_rcg2 nss_port6_tx_clk_src = {
1936 .cmd_rcgr = 0x68078,
1937 .freq_tbl = ftbl_nss_port6_tx_clk_src,
1939 .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1940 .clkr.hw.init = &(struct clk_init_data){
1941 .name = "nss_port6_tx_clk_src",
1942 .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1944 .ops = &clk_rcg2_ops,
1948 static struct clk_regmap_div nss_port6_tx_div_clk_src = {
1953 .hw.init = &(struct clk_init_data){
1954 .name = "nss_port6_tx_div_clk_src",
1955 .parent_names = (const char *[]){
1956 "nss_port6_tx_clk_src"
1959 .ops = &clk_regmap_div_ops,
1960 .flags = CLK_SET_RATE_PARENT,
1965 static struct freq_tbl ftbl_crypto_clk_src[] = {
1966 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1967 F(80000000, P_GPLL0, 10, 0, 0),
1968 F(100000000, P_GPLL0, 8, 0, 0),
1969 F(160000000, P_GPLL0, 5, 0, 0),
1973 static struct clk_rcg2 crypto_clk_src = {
1974 .cmd_rcgr = 0x16004,
1975 .freq_tbl = ftbl_crypto_clk_src,
1977 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1978 .clkr.hw.init = &(struct clk_init_data){
1979 .name = "crypto_clk_src",
1980 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
1982 .ops = &clk_rcg2_ops,
1986 static struct freq_tbl ftbl_gp_clk_src[] = {
1987 F(19200000, P_XO, 1, 0, 0),
1991 static struct clk_rcg2 gp1_clk_src = {
1992 .cmd_rcgr = 0x08004,
1993 .freq_tbl = ftbl_gp_clk_src,
1996 .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1997 .clkr.hw.init = &(struct clk_init_data){
1998 .name = "gp1_clk_src",
1999 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2001 .ops = &clk_rcg2_ops,
2005 static struct clk_rcg2 gp2_clk_src = {
2006 .cmd_rcgr = 0x09004,
2007 .freq_tbl = ftbl_gp_clk_src,
2010 .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2011 .clkr.hw.init = &(struct clk_init_data){
2012 .name = "gp2_clk_src",
2013 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2015 .ops = &clk_rcg2_ops,
2019 static struct clk_rcg2 gp3_clk_src = {
2020 .cmd_rcgr = 0x0a004,
2021 .freq_tbl = ftbl_gp_clk_src,
2024 .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2025 .clkr.hw.init = &(struct clk_init_data){
2026 .name = "gp3_clk_src",
2027 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2029 .ops = &clk_rcg2_ops,
2033 static struct clk_branch gcc_blsp1_ahb_clk = {
2034 .halt_reg = 0x01008,
2036 .enable_reg = 0x01008,
2037 .enable_mask = BIT(0),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "gcc_blsp1_ahb_clk",
2040 .parent_names = (const char *[]){
2044 .flags = CLK_SET_RATE_PARENT,
2045 .ops = &clk_branch2_ops,
2050 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
2051 .halt_reg = 0x02008,
2053 .enable_reg = 0x02008,
2054 .enable_mask = BIT(0),
2055 .hw.init = &(struct clk_init_data){
2056 .name = "gcc_blsp1_qup1_i2c_apps_clk",
2057 .parent_names = (const char *[]){
2058 "blsp1_qup1_i2c_apps_clk_src"
2061 .flags = CLK_SET_RATE_PARENT,
2062 .ops = &clk_branch2_ops,
2067 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
2068 .halt_reg = 0x02004,
2070 .enable_reg = 0x02004,
2071 .enable_mask = BIT(0),
2072 .hw.init = &(struct clk_init_data){
2073 .name = "gcc_blsp1_qup1_spi_apps_clk",
2074 .parent_names = (const char *[]){
2075 "blsp1_qup1_spi_apps_clk_src"
2078 .flags = CLK_SET_RATE_PARENT,
2079 .ops = &clk_branch2_ops,
2084 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2085 .halt_reg = 0x03010,
2087 .enable_reg = 0x03010,
2088 .enable_mask = BIT(0),
2089 .hw.init = &(struct clk_init_data){
2090 .name = "gcc_blsp1_qup2_i2c_apps_clk",
2091 .parent_names = (const char *[]){
2092 "blsp1_qup2_i2c_apps_clk_src"
2095 .flags = CLK_SET_RATE_PARENT,
2096 .ops = &clk_branch2_ops,
2101 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2102 .halt_reg = 0x0300c,
2104 .enable_reg = 0x0300c,
2105 .enable_mask = BIT(0),
2106 .hw.init = &(struct clk_init_data){
2107 .name = "gcc_blsp1_qup2_spi_apps_clk",
2108 .parent_names = (const char *[]){
2109 "blsp1_qup2_spi_apps_clk_src"
2112 .flags = CLK_SET_RATE_PARENT,
2113 .ops = &clk_branch2_ops,
2118 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2119 .halt_reg = 0x04010,
2121 .enable_reg = 0x04010,
2122 .enable_mask = BIT(0),
2123 .hw.init = &(struct clk_init_data){
2124 .name = "gcc_blsp1_qup3_i2c_apps_clk",
2125 .parent_names = (const char *[]){
2126 "blsp1_qup3_i2c_apps_clk_src"
2129 .flags = CLK_SET_RATE_PARENT,
2130 .ops = &clk_branch2_ops,
2135 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2136 .halt_reg = 0x0400c,
2138 .enable_reg = 0x0400c,
2139 .enable_mask = BIT(0),
2140 .hw.init = &(struct clk_init_data){
2141 .name = "gcc_blsp1_qup3_spi_apps_clk",
2142 .parent_names = (const char *[]){
2143 "blsp1_qup3_spi_apps_clk_src"
2146 .flags = CLK_SET_RATE_PARENT,
2147 .ops = &clk_branch2_ops,
2152 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2153 .halt_reg = 0x05010,
2155 .enable_reg = 0x05010,
2156 .enable_mask = BIT(0),
2157 .hw.init = &(struct clk_init_data){
2158 .name = "gcc_blsp1_qup4_i2c_apps_clk",
2159 .parent_names = (const char *[]){
2160 "blsp1_qup4_i2c_apps_clk_src"
2163 .flags = CLK_SET_RATE_PARENT,
2164 .ops = &clk_branch2_ops,
2169 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2170 .halt_reg = 0x0500c,
2172 .enable_reg = 0x0500c,
2173 .enable_mask = BIT(0),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "gcc_blsp1_qup4_spi_apps_clk",
2176 .parent_names = (const char *[]){
2177 "blsp1_qup4_spi_apps_clk_src"
2180 .flags = CLK_SET_RATE_PARENT,
2181 .ops = &clk_branch2_ops,
2186 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2187 .halt_reg = 0x06010,
2189 .enable_reg = 0x06010,
2190 .enable_mask = BIT(0),
2191 .hw.init = &(struct clk_init_data){
2192 .name = "gcc_blsp1_qup5_i2c_apps_clk",
2193 .parent_names = (const char *[]){
2194 "blsp1_qup5_i2c_apps_clk_src"
2197 .flags = CLK_SET_RATE_PARENT,
2198 .ops = &clk_branch2_ops,
2203 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2204 .halt_reg = 0x0600c,
2206 .enable_reg = 0x0600c,
2207 .enable_mask = BIT(0),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "gcc_blsp1_qup5_spi_apps_clk",
2210 .parent_names = (const char *[]){
2211 "blsp1_qup5_spi_apps_clk_src"
2214 .flags = CLK_SET_RATE_PARENT,
2215 .ops = &clk_branch2_ops,
2220 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2221 .halt_reg = 0x07010,
2223 .enable_reg = 0x07010,
2224 .enable_mask = BIT(0),
2225 .hw.init = &(struct clk_init_data){
2226 .name = "gcc_blsp1_qup6_i2c_apps_clk",
2227 .parent_names = (const char *[]){
2228 "blsp1_qup6_i2c_apps_clk_src"
2231 .flags = CLK_SET_RATE_PARENT,
2232 .ops = &clk_branch2_ops,
2237 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2238 .halt_reg = 0x0700c,
2240 .enable_reg = 0x0700c,
2241 .enable_mask = BIT(0),
2242 .hw.init = &(struct clk_init_data){
2243 .name = "gcc_blsp1_qup6_spi_apps_clk",
2244 .parent_names = (const char *[]){
2245 "blsp1_qup6_spi_apps_clk_src"
2248 .flags = CLK_SET_RATE_PARENT,
2249 .ops = &clk_branch2_ops,
2254 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2255 .halt_reg = 0x0203c,
2257 .enable_reg = 0x0203c,
2258 .enable_mask = BIT(0),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "gcc_blsp1_uart1_apps_clk",
2261 .parent_names = (const char *[]){
2262 "blsp1_uart1_apps_clk_src"
2265 .flags = CLK_SET_RATE_PARENT,
2266 .ops = &clk_branch2_ops,
2271 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2272 .halt_reg = 0x0302c,
2274 .enable_reg = 0x0302c,
2275 .enable_mask = BIT(0),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "gcc_blsp1_uart2_apps_clk",
2278 .parent_names = (const char *[]){
2279 "blsp1_uart2_apps_clk_src"
2282 .flags = CLK_SET_RATE_PARENT,
2283 .ops = &clk_branch2_ops,
2288 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2289 .halt_reg = 0x0402c,
2291 .enable_reg = 0x0402c,
2292 .enable_mask = BIT(0),
2293 .hw.init = &(struct clk_init_data){
2294 .name = "gcc_blsp1_uart3_apps_clk",
2295 .parent_names = (const char *[]){
2296 "blsp1_uart3_apps_clk_src"
2299 .flags = CLK_SET_RATE_PARENT,
2300 .ops = &clk_branch2_ops,
2305 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2306 .halt_reg = 0x0502c,
2308 .enable_reg = 0x0502c,
2309 .enable_mask = BIT(0),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "gcc_blsp1_uart4_apps_clk",
2312 .parent_names = (const char *[]){
2313 "blsp1_uart4_apps_clk_src"
2316 .flags = CLK_SET_RATE_PARENT,
2317 .ops = &clk_branch2_ops,
2322 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2323 .halt_reg = 0x0602c,
2325 .enable_reg = 0x0602c,
2326 .enable_mask = BIT(0),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "gcc_blsp1_uart5_apps_clk",
2329 .parent_names = (const char *[]){
2330 "blsp1_uart5_apps_clk_src"
2333 .flags = CLK_SET_RATE_PARENT,
2334 .ops = &clk_branch2_ops,
2339 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2340 .halt_reg = 0x0702c,
2342 .enable_reg = 0x0702c,
2343 .enable_mask = BIT(0),
2344 .hw.init = &(struct clk_init_data){
2345 .name = "gcc_blsp1_uart6_apps_clk",
2346 .parent_names = (const char *[]){
2347 "blsp1_uart6_apps_clk_src"
2350 .flags = CLK_SET_RATE_PARENT,
2351 .ops = &clk_branch2_ops,
2356 static struct clk_branch gcc_prng_ahb_clk = {
2357 .halt_reg = 0x13004,
2358 .halt_check = BRANCH_HALT_VOTED,
2360 .enable_reg = 0x0b004,
2361 .enable_mask = BIT(8),
2362 .hw.init = &(struct clk_init_data){
2363 .name = "gcc_prng_ahb_clk",
2364 .parent_names = (const char *[]){
2368 .flags = CLK_SET_RATE_PARENT,
2369 .ops = &clk_branch2_ops,
2374 static struct clk_branch gcc_qpic_ahb_clk = {
2375 .halt_reg = 0x57024,
2377 .enable_reg = 0x57024,
2378 .enable_mask = BIT(0),
2379 .hw.init = &(struct clk_init_data){
2380 .name = "gcc_qpic_ahb_clk",
2381 .parent_names = (const char *[]){
2385 .flags = CLK_SET_RATE_PARENT,
2386 .ops = &clk_branch2_ops,
2391 static struct clk_branch gcc_qpic_clk = {
2392 .halt_reg = 0x57020,
2394 .enable_reg = 0x57020,
2395 .enable_mask = BIT(0),
2396 .hw.init = &(struct clk_init_data){
2397 .name = "gcc_qpic_clk",
2398 .parent_names = (const char *[]){
2402 .flags = CLK_SET_RATE_PARENT,
2403 .ops = &clk_branch2_ops,
2408 static struct clk_branch gcc_pcie0_ahb_clk = {
2409 .halt_reg = 0x75010,
2411 .enable_reg = 0x75010,
2412 .enable_mask = BIT(0),
2413 .hw.init = &(struct clk_init_data){
2414 .name = "gcc_pcie0_ahb_clk",
2415 .parent_names = (const char *[]){
2419 .flags = CLK_SET_RATE_PARENT,
2420 .ops = &clk_branch2_ops,
2425 static struct clk_branch gcc_pcie0_aux_clk = {
2426 .halt_reg = 0x75014,
2428 .enable_reg = 0x75014,
2429 .enable_mask = BIT(0),
2430 .hw.init = &(struct clk_init_data){
2431 .name = "gcc_pcie0_aux_clk",
2432 .parent_names = (const char *[]){
2436 .flags = CLK_SET_RATE_PARENT,
2437 .ops = &clk_branch2_ops,
2442 static struct clk_branch gcc_pcie0_axi_m_clk = {
2443 .halt_reg = 0x75008,
2445 .enable_reg = 0x75008,
2446 .enable_mask = BIT(0),
2447 .hw.init = &(struct clk_init_data){
2448 .name = "gcc_pcie0_axi_m_clk",
2449 .parent_names = (const char *[]){
2453 .flags = CLK_SET_RATE_PARENT,
2454 .ops = &clk_branch2_ops,
2459 static struct clk_branch gcc_pcie0_axi_s_clk = {
2460 .halt_reg = 0x7500c,
2462 .enable_reg = 0x7500c,
2463 .enable_mask = BIT(0),
2464 .hw.init = &(struct clk_init_data){
2465 .name = "gcc_pcie0_axi_s_clk",
2466 .parent_names = (const char *[]){
2470 .flags = CLK_SET_RATE_PARENT,
2471 .ops = &clk_branch2_ops,
2476 static struct clk_branch gcc_pcie0_pipe_clk = {
2477 .halt_reg = 0x75018,
2478 .halt_check = BRANCH_HALT_DELAY,
2480 .enable_reg = 0x75018,
2481 .enable_mask = BIT(0),
2482 .hw.init = &(struct clk_init_data){
2483 .name = "gcc_pcie0_pipe_clk",
2484 .parent_names = (const char *[]){
2485 "pcie0_pipe_clk_src"
2488 .flags = CLK_SET_RATE_PARENT,
2489 .ops = &clk_branch2_ops,
2494 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2495 .halt_reg = 0x26048,
2497 .enable_reg = 0x26048,
2498 .enable_mask = BIT(0),
2499 .hw.init = &(struct clk_init_data){
2500 .name = "gcc_sys_noc_pcie0_axi_clk",
2501 .parent_names = (const char *[]){
2505 .flags = CLK_SET_RATE_PARENT,
2506 .ops = &clk_branch2_ops,
2511 static struct clk_branch gcc_pcie1_ahb_clk = {
2512 .halt_reg = 0x76010,
2514 .enable_reg = 0x76010,
2515 .enable_mask = BIT(0),
2516 .hw.init = &(struct clk_init_data){
2517 .name = "gcc_pcie1_ahb_clk",
2518 .parent_names = (const char *[]){
2522 .flags = CLK_SET_RATE_PARENT,
2523 .ops = &clk_branch2_ops,
2528 static struct clk_branch gcc_pcie1_aux_clk = {
2529 .halt_reg = 0x76014,
2531 .enable_reg = 0x76014,
2532 .enable_mask = BIT(0),
2533 .hw.init = &(struct clk_init_data){
2534 .name = "gcc_pcie1_aux_clk",
2535 .parent_names = (const char *[]){
2539 .flags = CLK_SET_RATE_PARENT,
2540 .ops = &clk_branch2_ops,
2545 static struct clk_branch gcc_pcie1_axi_m_clk = {
2546 .halt_reg = 0x76008,
2548 .enable_reg = 0x76008,
2549 .enable_mask = BIT(0),
2550 .hw.init = &(struct clk_init_data){
2551 .name = "gcc_pcie1_axi_m_clk",
2552 .parent_names = (const char *[]){
2556 .flags = CLK_SET_RATE_PARENT,
2557 .ops = &clk_branch2_ops,
2562 static struct clk_branch gcc_pcie1_axi_s_clk = {
2563 .halt_reg = 0x7600c,
2565 .enable_reg = 0x7600c,
2566 .enable_mask = BIT(0),
2567 .hw.init = &(struct clk_init_data){
2568 .name = "gcc_pcie1_axi_s_clk",
2569 .parent_names = (const char *[]){
2573 .flags = CLK_SET_RATE_PARENT,
2574 .ops = &clk_branch2_ops,
2579 static struct clk_branch gcc_pcie1_pipe_clk = {
2580 .halt_reg = 0x76018,
2581 .halt_check = BRANCH_HALT_DELAY,
2583 .enable_reg = 0x76018,
2584 .enable_mask = BIT(0),
2585 .hw.init = &(struct clk_init_data){
2586 .name = "gcc_pcie1_pipe_clk",
2587 .parent_names = (const char *[]){
2588 "pcie1_pipe_clk_src"
2591 .flags = CLK_SET_RATE_PARENT,
2592 .ops = &clk_branch2_ops,
2597 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2598 .halt_reg = 0x2604c,
2600 .enable_reg = 0x2604c,
2601 .enable_mask = BIT(0),
2602 .hw.init = &(struct clk_init_data){
2603 .name = "gcc_sys_noc_pcie1_axi_clk",
2604 .parent_names = (const char *[]){
2608 .flags = CLK_SET_RATE_PARENT,
2609 .ops = &clk_branch2_ops,
2614 static struct clk_branch gcc_usb0_aux_clk = {
2615 .halt_reg = 0x3e044,
2617 .enable_reg = 0x3e044,
2618 .enable_mask = BIT(0),
2619 .hw.init = &(struct clk_init_data){
2620 .name = "gcc_usb0_aux_clk",
2621 .parent_names = (const char *[]){
2625 .flags = CLK_SET_RATE_PARENT,
2626 .ops = &clk_branch2_ops,
2631 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2632 .halt_reg = 0x26040,
2634 .enable_reg = 0x26040,
2635 .enable_mask = BIT(0),
2636 .hw.init = &(struct clk_init_data){
2637 .name = "gcc_sys_noc_usb0_axi_clk",
2638 .parent_names = (const char *[]){
2639 "usb0_master_clk_src"
2642 .flags = CLK_SET_RATE_PARENT,
2643 .ops = &clk_branch2_ops,
2648 static struct clk_branch gcc_usb0_master_clk = {
2649 .halt_reg = 0x3e000,
2651 .enable_reg = 0x3e000,
2652 .enable_mask = BIT(0),
2653 .hw.init = &(struct clk_init_data){
2654 .name = "gcc_usb0_master_clk",
2655 .parent_names = (const char *[]){
2656 "usb0_master_clk_src"
2659 .flags = CLK_SET_RATE_PARENT,
2660 .ops = &clk_branch2_ops,
2665 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2666 .halt_reg = 0x3e008,
2668 .enable_reg = 0x3e008,
2669 .enable_mask = BIT(0),
2670 .hw.init = &(struct clk_init_data){
2671 .name = "gcc_usb0_mock_utmi_clk",
2672 .parent_names = (const char *[]){
2673 "usb0_mock_utmi_clk_src"
2676 .flags = CLK_SET_RATE_PARENT,
2677 .ops = &clk_branch2_ops,
2682 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2683 .halt_reg = 0x3e080,
2685 .enable_reg = 0x3e080,
2686 .enable_mask = BIT(0),
2687 .hw.init = &(struct clk_init_data){
2688 .name = "gcc_usb0_phy_cfg_ahb_clk",
2689 .parent_names = (const char *[]){
2693 .flags = CLK_SET_RATE_PARENT,
2694 .ops = &clk_branch2_ops,
2699 static struct clk_branch gcc_usb0_pipe_clk = {
2700 .halt_reg = 0x3e040,
2701 .halt_check = BRANCH_HALT_DELAY,
2703 .enable_reg = 0x3e040,
2704 .enable_mask = BIT(0),
2705 .hw.init = &(struct clk_init_data){
2706 .name = "gcc_usb0_pipe_clk",
2707 .parent_names = (const char *[]){
2711 .flags = CLK_SET_RATE_PARENT,
2712 .ops = &clk_branch2_ops,
2717 static struct clk_branch gcc_usb0_sleep_clk = {
2718 .halt_reg = 0x3e004,
2720 .enable_reg = 0x3e004,
2721 .enable_mask = BIT(0),
2722 .hw.init = &(struct clk_init_data){
2723 .name = "gcc_usb0_sleep_clk",
2724 .parent_names = (const char *[]){
2728 .flags = CLK_SET_RATE_PARENT,
2729 .ops = &clk_branch2_ops,
2734 static struct clk_branch gcc_usb1_aux_clk = {
2735 .halt_reg = 0x3f044,
2737 .enable_reg = 0x3f044,
2738 .enable_mask = BIT(0),
2739 .hw.init = &(struct clk_init_data){
2740 .name = "gcc_usb1_aux_clk",
2741 .parent_names = (const char *[]){
2745 .flags = CLK_SET_RATE_PARENT,
2746 .ops = &clk_branch2_ops,
2751 static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2752 .halt_reg = 0x26044,
2754 .enable_reg = 0x26044,
2755 .enable_mask = BIT(0),
2756 .hw.init = &(struct clk_init_data){
2757 .name = "gcc_sys_noc_usb1_axi_clk",
2758 .parent_names = (const char *[]){
2759 "usb1_master_clk_src"
2762 .flags = CLK_SET_RATE_PARENT,
2763 .ops = &clk_branch2_ops,
2768 static struct clk_branch gcc_usb1_master_clk = {
2769 .halt_reg = 0x3f000,
2771 .enable_reg = 0x3f000,
2772 .enable_mask = BIT(0),
2773 .hw.init = &(struct clk_init_data){
2774 .name = "gcc_usb1_master_clk",
2775 .parent_names = (const char *[]){
2776 "usb1_master_clk_src"
2779 .flags = CLK_SET_RATE_PARENT,
2780 .ops = &clk_branch2_ops,
2785 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2786 .halt_reg = 0x3f008,
2788 .enable_reg = 0x3f008,
2789 .enable_mask = BIT(0),
2790 .hw.init = &(struct clk_init_data){
2791 .name = "gcc_usb1_mock_utmi_clk",
2792 .parent_names = (const char *[]){
2793 "usb1_mock_utmi_clk_src"
2796 .flags = CLK_SET_RATE_PARENT,
2797 .ops = &clk_branch2_ops,
2802 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2803 .halt_reg = 0x3f080,
2805 .enable_reg = 0x3f080,
2806 .enable_mask = BIT(0),
2807 .hw.init = &(struct clk_init_data){
2808 .name = "gcc_usb1_phy_cfg_ahb_clk",
2809 .parent_names = (const char *[]){
2813 .flags = CLK_SET_RATE_PARENT,
2814 .ops = &clk_branch2_ops,
2819 static struct clk_branch gcc_usb1_pipe_clk = {
2820 .halt_reg = 0x3f040,
2821 .halt_check = BRANCH_HALT_DELAY,
2823 .enable_reg = 0x3f040,
2824 .enable_mask = BIT(0),
2825 .hw.init = &(struct clk_init_data){
2826 .name = "gcc_usb1_pipe_clk",
2827 .parent_names = (const char *[]){
2831 .flags = CLK_SET_RATE_PARENT,
2832 .ops = &clk_branch2_ops,
2837 static struct clk_branch gcc_usb1_sleep_clk = {
2838 .halt_reg = 0x3f004,
2840 .enable_reg = 0x3f004,
2841 .enable_mask = BIT(0),
2842 .hw.init = &(struct clk_init_data){
2843 .name = "gcc_usb1_sleep_clk",
2844 .parent_names = (const char *[]){
2848 .flags = CLK_SET_RATE_PARENT,
2849 .ops = &clk_branch2_ops,
2854 static struct clk_branch gcc_sdcc1_ahb_clk = {
2855 .halt_reg = 0x4201c,
2857 .enable_reg = 0x4201c,
2858 .enable_mask = BIT(0),
2859 .hw.init = &(struct clk_init_data){
2860 .name = "gcc_sdcc1_ahb_clk",
2861 .parent_names = (const char *[]){
2865 .flags = CLK_SET_RATE_PARENT,
2866 .ops = &clk_branch2_ops,
2871 static struct clk_branch gcc_sdcc1_apps_clk = {
2872 .halt_reg = 0x42018,
2874 .enable_reg = 0x42018,
2875 .enable_mask = BIT(0),
2876 .hw.init = &(struct clk_init_data){
2877 .name = "gcc_sdcc1_apps_clk",
2878 .parent_names = (const char *[]){
2879 "sdcc1_apps_clk_src"
2882 .flags = CLK_SET_RATE_PARENT,
2883 .ops = &clk_branch2_ops,
2888 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2889 .halt_reg = 0x5d014,
2891 .enable_reg = 0x5d014,
2892 .enable_mask = BIT(0),
2893 .hw.init = &(struct clk_init_data){
2894 .name = "gcc_sdcc1_ice_core_clk",
2895 .parent_names = (const char *[]){
2896 "sdcc1_ice_core_clk_src"
2899 .flags = CLK_SET_RATE_PARENT,
2900 .ops = &clk_branch2_ops,
2905 static struct clk_branch gcc_sdcc2_ahb_clk = {
2906 .halt_reg = 0x4301c,
2908 .enable_reg = 0x4301c,
2909 .enable_mask = BIT(0),
2910 .hw.init = &(struct clk_init_data){
2911 .name = "gcc_sdcc2_ahb_clk",
2912 .parent_names = (const char *[]){
2916 .flags = CLK_SET_RATE_PARENT,
2917 .ops = &clk_branch2_ops,
2922 static struct clk_branch gcc_sdcc2_apps_clk = {
2923 .halt_reg = 0x43018,
2925 .enable_reg = 0x43018,
2926 .enable_mask = BIT(0),
2927 .hw.init = &(struct clk_init_data){
2928 .name = "gcc_sdcc2_apps_clk",
2929 .parent_names = (const char *[]){
2930 "sdcc2_apps_clk_src"
2933 .flags = CLK_SET_RATE_PARENT,
2934 .ops = &clk_branch2_ops,
2939 static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2940 .halt_reg = 0x1d03c,
2942 .enable_reg = 0x1d03c,
2943 .enable_mask = BIT(0),
2944 .hw.init = &(struct clk_init_data){
2945 .name = "gcc_mem_noc_nss_axi_clk",
2946 .parent_names = (const char *[]){
2950 .flags = CLK_SET_RATE_PARENT,
2951 .ops = &clk_branch2_ops,
2956 static struct clk_branch gcc_nss_ce_apb_clk = {
2957 .halt_reg = 0x68174,
2959 .enable_reg = 0x68174,
2960 .enable_mask = BIT(0),
2961 .hw.init = &(struct clk_init_data){
2962 .name = "gcc_nss_ce_apb_clk",
2963 .parent_names = (const char *[]){
2967 .flags = CLK_SET_RATE_PARENT,
2968 .ops = &clk_branch2_ops,
2973 static struct clk_branch gcc_nss_ce_axi_clk = {
2974 .halt_reg = 0x68170,
2976 .enable_reg = 0x68170,
2977 .enable_mask = BIT(0),
2978 .hw.init = &(struct clk_init_data){
2979 .name = "gcc_nss_ce_axi_clk",
2980 .parent_names = (const char *[]){
2984 .flags = CLK_SET_RATE_PARENT,
2985 .ops = &clk_branch2_ops,
2990 static struct clk_branch gcc_nss_cfg_clk = {
2991 .halt_reg = 0x68160,
2993 .enable_reg = 0x68160,
2994 .enable_mask = BIT(0),
2995 .hw.init = &(struct clk_init_data){
2996 .name = "gcc_nss_cfg_clk",
2997 .parent_names = (const char *[]){
3001 .flags = CLK_SET_RATE_PARENT,
3002 .ops = &clk_branch2_ops,
3007 static struct clk_branch gcc_nss_crypto_clk = {
3008 .halt_reg = 0x68164,
3010 .enable_reg = 0x68164,
3011 .enable_mask = BIT(0),
3012 .hw.init = &(struct clk_init_data){
3013 .name = "gcc_nss_crypto_clk",
3014 .parent_names = (const char *[]){
3015 "nss_crypto_clk_src"
3018 .flags = CLK_SET_RATE_PARENT,
3019 .ops = &clk_branch2_ops,
3024 static struct clk_branch gcc_nss_csr_clk = {
3025 .halt_reg = 0x68318,
3027 .enable_reg = 0x68318,
3028 .enable_mask = BIT(0),
3029 .hw.init = &(struct clk_init_data){
3030 .name = "gcc_nss_csr_clk",
3031 .parent_names = (const char *[]){
3035 .flags = CLK_SET_RATE_PARENT,
3036 .ops = &clk_branch2_ops,
3041 static struct clk_branch gcc_nss_edma_cfg_clk = {
3042 .halt_reg = 0x6819c,
3044 .enable_reg = 0x6819c,
3045 .enable_mask = BIT(0),
3046 .hw.init = &(struct clk_init_data){
3047 .name = "gcc_nss_edma_cfg_clk",
3048 .parent_names = (const char *[]){
3052 .flags = CLK_SET_RATE_PARENT,
3053 .ops = &clk_branch2_ops,
3058 static struct clk_branch gcc_nss_edma_clk = {
3059 .halt_reg = 0x68198,
3061 .enable_reg = 0x68198,
3062 .enable_mask = BIT(0),
3063 .hw.init = &(struct clk_init_data){
3064 .name = "gcc_nss_edma_clk",
3065 .parent_names = (const char *[]){
3069 .flags = CLK_SET_RATE_PARENT,
3070 .ops = &clk_branch2_ops,
3075 static struct clk_branch gcc_nss_imem_clk = {
3076 .halt_reg = 0x68178,
3078 .enable_reg = 0x68178,
3079 .enable_mask = BIT(0),
3080 .hw.init = &(struct clk_init_data){
3081 .name = "gcc_nss_imem_clk",
3082 .parent_names = (const char *[]){
3086 .flags = CLK_SET_RATE_PARENT,
3087 .ops = &clk_branch2_ops,
3092 static struct clk_branch gcc_nss_noc_clk = {
3093 .halt_reg = 0x68168,
3095 .enable_reg = 0x68168,
3096 .enable_mask = BIT(0),
3097 .hw.init = &(struct clk_init_data){
3098 .name = "gcc_nss_noc_clk",
3099 .parent_names = (const char *[]){
3103 .flags = CLK_SET_RATE_PARENT,
3104 .ops = &clk_branch2_ops,
3109 static struct clk_branch gcc_nss_ppe_btq_clk = {
3110 .halt_reg = 0x6833c,
3112 .enable_reg = 0x6833c,
3113 .enable_mask = BIT(0),
3114 .hw.init = &(struct clk_init_data){
3115 .name = "gcc_nss_ppe_btq_clk",
3116 .parent_names = (const char *[]){
3120 .flags = CLK_SET_RATE_PARENT,
3121 .ops = &clk_branch2_ops,
3126 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3127 .halt_reg = 0x68194,
3129 .enable_reg = 0x68194,
3130 .enable_mask = BIT(0),
3131 .hw.init = &(struct clk_init_data){
3132 .name = "gcc_nss_ppe_cfg_clk",
3133 .parent_names = (const char *[]){
3137 .flags = CLK_SET_RATE_PARENT,
3138 .ops = &clk_branch2_ops,
3143 static struct clk_branch gcc_nss_ppe_clk = {
3144 .halt_reg = 0x68190,
3146 .enable_reg = 0x68190,
3147 .enable_mask = BIT(0),
3148 .hw.init = &(struct clk_init_data){
3149 .name = "gcc_nss_ppe_clk",
3150 .parent_names = (const char *[]){
3154 .flags = CLK_SET_RATE_PARENT,
3155 .ops = &clk_branch2_ops,
3160 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3161 .halt_reg = 0x68338,
3163 .enable_reg = 0x68338,
3164 .enable_mask = BIT(0),
3165 .hw.init = &(struct clk_init_data){
3166 .name = "gcc_nss_ppe_ipe_clk",
3167 .parent_names = (const char *[]){
3171 .flags = CLK_SET_RATE_PARENT,
3172 .ops = &clk_branch2_ops,
3177 static struct clk_branch gcc_nss_ptp_ref_clk = {
3178 .halt_reg = 0x6816c,
3180 .enable_reg = 0x6816c,
3181 .enable_mask = BIT(0),
3182 .hw.init = &(struct clk_init_data){
3183 .name = "gcc_nss_ptp_ref_clk",
3184 .parent_names = (const char *[]){
3185 "nss_ppe_cdiv_clk_src"
3188 .flags = CLK_SET_RATE_PARENT,
3189 .ops = &clk_branch2_ops,
3194 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3195 .halt_reg = 0x6830c,
3197 .enable_reg = 0x6830c,
3198 .enable_mask = BIT(0),
3199 .hw.init = &(struct clk_init_data){
3200 .name = "gcc_nssnoc_ce_apb_clk",
3201 .parent_names = (const char *[]){
3205 .flags = CLK_SET_RATE_PARENT,
3206 .ops = &clk_branch2_ops,
3211 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3212 .halt_reg = 0x68308,
3214 .enable_reg = 0x68308,
3215 .enable_mask = BIT(0),
3216 .hw.init = &(struct clk_init_data){
3217 .name = "gcc_nssnoc_ce_axi_clk",
3218 .parent_names = (const char *[]){
3222 .flags = CLK_SET_RATE_PARENT,
3223 .ops = &clk_branch2_ops,
3228 static struct clk_branch gcc_nssnoc_crypto_clk = {
3229 .halt_reg = 0x68314,
3231 .enable_reg = 0x68314,
3232 .enable_mask = BIT(0),
3233 .hw.init = &(struct clk_init_data){
3234 .name = "gcc_nssnoc_crypto_clk",
3235 .parent_names = (const char *[]){
3236 "nss_crypto_clk_src"
3239 .flags = CLK_SET_RATE_PARENT,
3240 .ops = &clk_branch2_ops,
3245 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3246 .halt_reg = 0x68304,
3248 .enable_reg = 0x68304,
3249 .enable_mask = BIT(0),
3250 .hw.init = &(struct clk_init_data){
3251 .name = "gcc_nssnoc_ppe_cfg_clk",
3252 .parent_names = (const char *[]){
3256 .flags = CLK_SET_RATE_PARENT,
3257 .ops = &clk_branch2_ops,
3262 static struct clk_branch gcc_nssnoc_ppe_clk = {
3263 .halt_reg = 0x68300,
3265 .enable_reg = 0x68300,
3266 .enable_mask = BIT(0),
3267 .hw.init = &(struct clk_init_data){
3268 .name = "gcc_nssnoc_ppe_clk",
3269 .parent_names = (const char *[]){
3273 .flags = CLK_SET_RATE_PARENT,
3274 .ops = &clk_branch2_ops,
3279 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3280 .halt_reg = 0x68180,
3282 .enable_reg = 0x68180,
3283 .enable_mask = BIT(0),
3284 .hw.init = &(struct clk_init_data){
3285 .name = "gcc_nssnoc_qosgen_ref_clk",
3286 .parent_names = (const char *[]){
3290 .flags = CLK_SET_RATE_PARENT,
3291 .ops = &clk_branch2_ops,
3296 static struct clk_branch gcc_nssnoc_snoc_clk = {
3297 .halt_reg = 0x68188,
3299 .enable_reg = 0x68188,
3300 .enable_mask = BIT(0),
3301 .hw.init = &(struct clk_init_data){
3302 .name = "gcc_nssnoc_snoc_clk",
3303 .parent_names = (const char *[]){
3304 "system_noc_clk_src"
3307 .flags = CLK_SET_RATE_PARENT,
3308 .ops = &clk_branch2_ops,
3313 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3314 .halt_reg = 0x68184,
3316 .enable_reg = 0x68184,
3317 .enable_mask = BIT(0),
3318 .hw.init = &(struct clk_init_data){
3319 .name = "gcc_nssnoc_timeout_ref_clk",
3320 .parent_names = (const char *[]){
3321 "gcc_xo_div4_clk_src"
3324 .flags = CLK_SET_RATE_PARENT,
3325 .ops = &clk_branch2_ops,
3330 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3331 .halt_reg = 0x68270,
3333 .enable_reg = 0x68270,
3334 .enable_mask = BIT(0),
3335 .hw.init = &(struct clk_init_data){
3336 .name = "gcc_nssnoc_ubi0_ahb_clk",
3337 .parent_names = (const char *[]){
3341 .flags = CLK_SET_RATE_PARENT,
3342 .ops = &clk_branch2_ops,
3347 static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
3348 .halt_reg = 0x68274,
3350 .enable_reg = 0x68274,
3351 .enable_mask = BIT(0),
3352 .hw.init = &(struct clk_init_data){
3353 .name = "gcc_nssnoc_ubi1_ahb_clk",
3354 .parent_names = (const char *[]){
3358 .flags = CLK_SET_RATE_PARENT,
3359 .ops = &clk_branch2_ops,
3364 static struct clk_branch gcc_ubi0_ahb_clk = {
3365 .halt_reg = 0x6820c,
3366 .halt_check = BRANCH_HALT_DELAY,
3368 .enable_reg = 0x6820c,
3369 .enable_mask = BIT(0),
3370 .hw.init = &(struct clk_init_data){
3371 .name = "gcc_ubi0_ahb_clk",
3372 .parent_names = (const char *[]){
3376 .flags = CLK_SET_RATE_PARENT,
3377 .ops = &clk_branch2_ops,
3382 static struct clk_branch gcc_ubi0_axi_clk = {
3383 .halt_reg = 0x68200,
3384 .halt_check = BRANCH_HALT_DELAY,
3386 .enable_reg = 0x68200,
3387 .enable_mask = BIT(0),
3388 .hw.init = &(struct clk_init_data){
3389 .name = "gcc_ubi0_axi_clk",
3390 .parent_names = (const char *[]){
3394 .flags = CLK_SET_RATE_PARENT,
3395 .ops = &clk_branch2_ops,
3400 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3401 .halt_reg = 0x68204,
3402 .halt_check = BRANCH_HALT_DELAY,
3404 .enable_reg = 0x68204,
3405 .enable_mask = BIT(0),
3406 .hw.init = &(struct clk_init_data){
3407 .name = "gcc_ubi0_nc_axi_clk",
3408 .parent_names = (const char *[]){
3412 .flags = CLK_SET_RATE_PARENT,
3413 .ops = &clk_branch2_ops,
3418 static struct clk_branch gcc_ubi0_core_clk = {
3419 .halt_reg = 0x68210,
3420 .halt_check = BRANCH_HALT_DELAY,
3422 .enable_reg = 0x68210,
3423 .enable_mask = BIT(0),
3424 .hw.init = &(struct clk_init_data){
3425 .name = "gcc_ubi0_core_clk",
3426 .parent_names = (const char *[]){
3427 "nss_ubi0_div_clk_src"
3430 .flags = CLK_SET_RATE_PARENT,
3431 .ops = &clk_branch2_ops,
3436 static struct clk_branch gcc_ubi0_mpt_clk = {
3437 .halt_reg = 0x68208,
3438 .halt_check = BRANCH_HALT_DELAY,
3440 .enable_reg = 0x68208,
3441 .enable_mask = BIT(0),
3442 .hw.init = &(struct clk_init_data){
3443 .name = "gcc_ubi0_mpt_clk",
3444 .parent_names = (const char *[]){
3448 .flags = CLK_SET_RATE_PARENT,
3449 .ops = &clk_branch2_ops,
3454 static struct clk_branch gcc_ubi1_ahb_clk = {
3455 .halt_reg = 0x6822c,
3456 .halt_check = BRANCH_HALT_DELAY,
3458 .enable_reg = 0x6822c,
3459 .enable_mask = BIT(0),
3460 .hw.init = &(struct clk_init_data){
3461 .name = "gcc_ubi1_ahb_clk",
3462 .parent_names = (const char *[]){
3466 .flags = CLK_SET_RATE_PARENT,
3467 .ops = &clk_branch2_ops,
3472 static struct clk_branch gcc_ubi1_axi_clk = {
3473 .halt_reg = 0x68220,
3474 .halt_check = BRANCH_HALT_DELAY,
3476 .enable_reg = 0x68220,
3477 .enable_mask = BIT(0),
3478 .hw.init = &(struct clk_init_data){
3479 .name = "gcc_ubi1_axi_clk",
3480 .parent_names = (const char *[]){
3484 .flags = CLK_SET_RATE_PARENT,
3485 .ops = &clk_branch2_ops,
3490 static struct clk_branch gcc_ubi1_nc_axi_clk = {
3491 .halt_reg = 0x68224,
3492 .halt_check = BRANCH_HALT_DELAY,
3494 .enable_reg = 0x68224,
3495 .enable_mask = BIT(0),
3496 .hw.init = &(struct clk_init_data){
3497 .name = "gcc_ubi1_nc_axi_clk",
3498 .parent_names = (const char *[]){
3502 .flags = CLK_SET_RATE_PARENT,
3503 .ops = &clk_branch2_ops,
3508 static struct clk_branch gcc_ubi1_core_clk = {
3509 .halt_reg = 0x68230,
3510 .halt_check = BRANCH_HALT_DELAY,
3512 .enable_reg = 0x68230,
3513 .enable_mask = BIT(0),
3514 .hw.init = &(struct clk_init_data){
3515 .name = "gcc_ubi1_core_clk",
3516 .parent_names = (const char *[]){
3517 "nss_ubi1_div_clk_src"
3520 .flags = CLK_SET_RATE_PARENT,
3521 .ops = &clk_branch2_ops,
3526 static struct clk_branch gcc_ubi1_mpt_clk = {
3527 .halt_reg = 0x68228,
3528 .halt_check = BRANCH_HALT_DELAY,
3530 .enable_reg = 0x68228,
3531 .enable_mask = BIT(0),
3532 .hw.init = &(struct clk_init_data){
3533 .name = "gcc_ubi1_mpt_clk",
3534 .parent_names = (const char *[]){
3538 .flags = CLK_SET_RATE_PARENT,
3539 .ops = &clk_branch2_ops,
3544 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
3545 .halt_reg = 0x56308,
3547 .enable_reg = 0x56308,
3548 .enable_mask = BIT(0),
3549 .hw.init = &(struct clk_init_data){
3550 .name = "gcc_cmn_12gpll_ahb_clk",
3551 .parent_names = (const char *[]){
3555 .flags = CLK_SET_RATE_PARENT,
3556 .ops = &clk_branch2_ops,
3561 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3562 .halt_reg = 0x5630c,
3564 .enable_reg = 0x5630c,
3565 .enable_mask = BIT(0),
3566 .hw.init = &(struct clk_init_data){
3567 .name = "gcc_cmn_12gpll_sys_clk",
3568 .parent_names = (const char *[]){
3572 .flags = CLK_SET_RATE_PARENT,
3573 .ops = &clk_branch2_ops,
3578 static struct clk_branch gcc_mdio_ahb_clk = {
3579 .halt_reg = 0x58004,
3581 .enable_reg = 0x58004,
3582 .enable_mask = BIT(0),
3583 .hw.init = &(struct clk_init_data){
3584 .name = "gcc_mdio_ahb_clk",
3585 .parent_names = (const char *[]){
3589 .flags = CLK_SET_RATE_PARENT,
3590 .ops = &clk_branch2_ops,
3595 static struct clk_branch gcc_uniphy0_ahb_clk = {
3596 .halt_reg = 0x56008,
3598 .enable_reg = 0x56008,
3599 .enable_mask = BIT(0),
3600 .hw.init = &(struct clk_init_data){
3601 .name = "gcc_uniphy0_ahb_clk",
3602 .parent_names = (const char *[]){
3606 .flags = CLK_SET_RATE_PARENT,
3607 .ops = &clk_branch2_ops,
3612 static struct clk_branch gcc_uniphy0_sys_clk = {
3613 .halt_reg = 0x5600c,
3615 .enable_reg = 0x5600c,
3616 .enable_mask = BIT(0),
3617 .hw.init = &(struct clk_init_data){
3618 .name = "gcc_uniphy0_sys_clk",
3619 .parent_names = (const char *[]){
3623 .flags = CLK_SET_RATE_PARENT,
3624 .ops = &clk_branch2_ops,
3629 static struct clk_branch gcc_uniphy1_ahb_clk = {
3630 .halt_reg = 0x56108,
3632 .enable_reg = 0x56108,
3633 .enable_mask = BIT(0),
3634 .hw.init = &(struct clk_init_data){
3635 .name = "gcc_uniphy1_ahb_clk",
3636 .parent_names = (const char *[]){
3640 .flags = CLK_SET_RATE_PARENT,
3641 .ops = &clk_branch2_ops,
3646 static struct clk_branch gcc_uniphy1_sys_clk = {
3647 .halt_reg = 0x5610c,
3649 .enable_reg = 0x5610c,
3650 .enable_mask = BIT(0),
3651 .hw.init = &(struct clk_init_data){
3652 .name = "gcc_uniphy1_sys_clk",
3653 .parent_names = (const char *[]){
3657 .flags = CLK_SET_RATE_PARENT,
3658 .ops = &clk_branch2_ops,
3663 static struct clk_branch gcc_uniphy2_ahb_clk = {
3664 .halt_reg = 0x56208,
3666 .enable_reg = 0x56208,
3667 .enable_mask = BIT(0),
3668 .hw.init = &(struct clk_init_data){
3669 .name = "gcc_uniphy2_ahb_clk",
3670 .parent_names = (const char *[]){
3674 .flags = CLK_SET_RATE_PARENT,
3675 .ops = &clk_branch2_ops,
3680 static struct clk_branch gcc_uniphy2_sys_clk = {
3681 .halt_reg = 0x5620c,
3683 .enable_reg = 0x5620c,
3684 .enable_mask = BIT(0),
3685 .hw.init = &(struct clk_init_data){
3686 .name = "gcc_uniphy2_sys_clk",
3687 .parent_names = (const char *[]){
3691 .flags = CLK_SET_RATE_PARENT,
3692 .ops = &clk_branch2_ops,
3697 static struct clk_branch gcc_nss_port1_rx_clk = {
3698 .halt_reg = 0x68240,
3700 .enable_reg = 0x68240,
3701 .enable_mask = BIT(0),
3702 .hw.init = &(struct clk_init_data){
3703 .name = "gcc_nss_port1_rx_clk",
3704 .parent_names = (const char *[]){
3705 "nss_port1_rx_div_clk_src"
3708 .flags = CLK_SET_RATE_PARENT,
3709 .ops = &clk_branch2_ops,
3714 static struct clk_branch gcc_nss_port1_tx_clk = {
3715 .halt_reg = 0x68244,
3717 .enable_reg = 0x68244,
3718 .enable_mask = BIT(0),
3719 .hw.init = &(struct clk_init_data){
3720 .name = "gcc_nss_port1_tx_clk",
3721 .parent_names = (const char *[]){
3722 "nss_port1_tx_div_clk_src"
3725 .flags = CLK_SET_RATE_PARENT,
3726 .ops = &clk_branch2_ops,
3731 static struct clk_branch gcc_nss_port2_rx_clk = {
3732 .halt_reg = 0x68248,
3734 .enable_reg = 0x68248,
3735 .enable_mask = BIT(0),
3736 .hw.init = &(struct clk_init_data){
3737 .name = "gcc_nss_port2_rx_clk",
3738 .parent_names = (const char *[]){
3739 "nss_port2_rx_div_clk_src"
3742 .flags = CLK_SET_RATE_PARENT,
3743 .ops = &clk_branch2_ops,
3748 static struct clk_branch gcc_nss_port2_tx_clk = {
3749 .halt_reg = 0x6824c,
3751 .enable_reg = 0x6824c,
3752 .enable_mask = BIT(0),
3753 .hw.init = &(struct clk_init_data){
3754 .name = "gcc_nss_port2_tx_clk",
3755 .parent_names = (const char *[]){
3756 "nss_port2_tx_div_clk_src"
3759 .flags = CLK_SET_RATE_PARENT,
3760 .ops = &clk_branch2_ops,
3765 static struct clk_branch gcc_nss_port3_rx_clk = {
3766 .halt_reg = 0x68250,
3768 .enable_reg = 0x68250,
3769 .enable_mask = BIT(0),
3770 .hw.init = &(struct clk_init_data){
3771 .name = "gcc_nss_port3_rx_clk",
3772 .parent_names = (const char *[]){
3773 "nss_port3_rx_div_clk_src"
3776 .flags = CLK_SET_RATE_PARENT,
3777 .ops = &clk_branch2_ops,
3782 static struct clk_branch gcc_nss_port3_tx_clk = {
3783 .halt_reg = 0x68254,
3785 .enable_reg = 0x68254,
3786 .enable_mask = BIT(0),
3787 .hw.init = &(struct clk_init_data){
3788 .name = "gcc_nss_port3_tx_clk",
3789 .parent_names = (const char *[]){
3790 "nss_port3_tx_div_clk_src"
3793 .flags = CLK_SET_RATE_PARENT,
3794 .ops = &clk_branch2_ops,
3799 static struct clk_branch gcc_nss_port4_rx_clk = {
3800 .halt_reg = 0x68258,
3802 .enable_reg = 0x68258,
3803 .enable_mask = BIT(0),
3804 .hw.init = &(struct clk_init_data){
3805 .name = "gcc_nss_port4_rx_clk",
3806 .parent_names = (const char *[]){
3807 "nss_port4_rx_div_clk_src"
3810 .flags = CLK_SET_RATE_PARENT,
3811 .ops = &clk_branch2_ops,
3816 static struct clk_branch gcc_nss_port4_tx_clk = {
3817 .halt_reg = 0x6825c,
3819 .enable_reg = 0x6825c,
3820 .enable_mask = BIT(0),
3821 .hw.init = &(struct clk_init_data){
3822 .name = "gcc_nss_port4_tx_clk",
3823 .parent_names = (const char *[]){
3824 "nss_port4_tx_div_clk_src"
3827 .flags = CLK_SET_RATE_PARENT,
3828 .ops = &clk_branch2_ops,
3833 static struct clk_branch gcc_nss_port5_rx_clk = {
3834 .halt_reg = 0x68260,
3836 .enable_reg = 0x68260,
3837 .enable_mask = BIT(0),
3838 .hw.init = &(struct clk_init_data){
3839 .name = "gcc_nss_port5_rx_clk",
3840 .parent_names = (const char *[]){
3841 "nss_port5_rx_div_clk_src"
3844 .flags = CLK_SET_RATE_PARENT,
3845 .ops = &clk_branch2_ops,
3850 static struct clk_branch gcc_nss_port5_tx_clk = {
3851 .halt_reg = 0x68264,
3853 .enable_reg = 0x68264,
3854 .enable_mask = BIT(0),
3855 .hw.init = &(struct clk_init_data){
3856 .name = "gcc_nss_port5_tx_clk",
3857 .parent_names = (const char *[]){
3858 "nss_port5_tx_div_clk_src"
3861 .flags = CLK_SET_RATE_PARENT,
3862 .ops = &clk_branch2_ops,
3867 static struct clk_branch gcc_nss_port6_rx_clk = {
3868 .halt_reg = 0x68268,
3870 .enable_reg = 0x68268,
3871 .enable_mask = BIT(0),
3872 .hw.init = &(struct clk_init_data){
3873 .name = "gcc_nss_port6_rx_clk",
3874 .parent_names = (const char *[]){
3875 "nss_port6_rx_div_clk_src"
3878 .flags = CLK_SET_RATE_PARENT,
3879 .ops = &clk_branch2_ops,
3884 static struct clk_branch gcc_nss_port6_tx_clk = {
3885 .halt_reg = 0x6826c,
3887 .enable_reg = 0x6826c,
3888 .enable_mask = BIT(0),
3889 .hw.init = &(struct clk_init_data){
3890 .name = "gcc_nss_port6_tx_clk",
3891 .parent_names = (const char *[]){
3892 "nss_port6_tx_div_clk_src"
3895 .flags = CLK_SET_RATE_PARENT,
3896 .ops = &clk_branch2_ops,
3901 static struct clk_branch gcc_port1_mac_clk = {
3902 .halt_reg = 0x68320,
3904 .enable_reg = 0x68320,
3905 .enable_mask = BIT(0),
3906 .hw.init = &(struct clk_init_data){
3907 .name = "gcc_port1_mac_clk",
3908 .parent_names = (const char *[]){
3912 .flags = CLK_SET_RATE_PARENT,
3913 .ops = &clk_branch2_ops,
3918 static struct clk_branch gcc_port2_mac_clk = {
3919 .halt_reg = 0x68324,
3921 .enable_reg = 0x68324,
3922 .enable_mask = BIT(0),
3923 .hw.init = &(struct clk_init_data){
3924 .name = "gcc_port2_mac_clk",
3925 .parent_names = (const char *[]){
3929 .flags = CLK_SET_RATE_PARENT,
3930 .ops = &clk_branch2_ops,
3935 static struct clk_branch gcc_port3_mac_clk = {
3936 .halt_reg = 0x68328,
3938 .enable_reg = 0x68328,
3939 .enable_mask = BIT(0),
3940 .hw.init = &(struct clk_init_data){
3941 .name = "gcc_port3_mac_clk",
3942 .parent_names = (const char *[]){
3946 .flags = CLK_SET_RATE_PARENT,
3947 .ops = &clk_branch2_ops,
3952 static struct clk_branch gcc_port4_mac_clk = {
3953 .halt_reg = 0x6832c,
3955 .enable_reg = 0x6832c,
3956 .enable_mask = BIT(0),
3957 .hw.init = &(struct clk_init_data){
3958 .name = "gcc_port4_mac_clk",
3959 .parent_names = (const char *[]){
3963 .flags = CLK_SET_RATE_PARENT,
3964 .ops = &clk_branch2_ops,
3969 static struct clk_branch gcc_port5_mac_clk = {
3970 .halt_reg = 0x68330,
3972 .enable_reg = 0x68330,
3973 .enable_mask = BIT(0),
3974 .hw.init = &(struct clk_init_data){
3975 .name = "gcc_port5_mac_clk",
3976 .parent_names = (const char *[]){
3980 .flags = CLK_SET_RATE_PARENT,
3981 .ops = &clk_branch2_ops,
3986 static struct clk_branch gcc_port6_mac_clk = {
3987 .halt_reg = 0x68334,
3989 .enable_reg = 0x68334,
3990 .enable_mask = BIT(0),
3991 .hw.init = &(struct clk_init_data){
3992 .name = "gcc_port6_mac_clk",
3993 .parent_names = (const char *[]){
3997 .flags = CLK_SET_RATE_PARENT,
3998 .ops = &clk_branch2_ops,
4003 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
4004 .halt_reg = 0x56010,
4006 .enable_reg = 0x56010,
4007 .enable_mask = BIT(0),
4008 .hw.init = &(struct clk_init_data){
4009 .name = "gcc_uniphy0_port1_rx_clk",
4010 .parent_names = (const char *[]){
4011 "nss_port1_rx_div_clk_src"
4014 .flags = CLK_SET_RATE_PARENT,
4015 .ops = &clk_branch2_ops,
4020 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
4021 .halt_reg = 0x56014,
4023 .enable_reg = 0x56014,
4024 .enable_mask = BIT(0),
4025 .hw.init = &(struct clk_init_data){
4026 .name = "gcc_uniphy0_port1_tx_clk",
4027 .parent_names = (const char *[]){
4028 "nss_port1_tx_div_clk_src"
4031 .flags = CLK_SET_RATE_PARENT,
4032 .ops = &clk_branch2_ops,
4037 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
4038 .halt_reg = 0x56018,
4040 .enable_reg = 0x56018,
4041 .enable_mask = BIT(0),
4042 .hw.init = &(struct clk_init_data){
4043 .name = "gcc_uniphy0_port2_rx_clk",
4044 .parent_names = (const char *[]){
4045 "nss_port2_rx_div_clk_src"
4048 .flags = CLK_SET_RATE_PARENT,
4049 .ops = &clk_branch2_ops,
4054 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
4055 .halt_reg = 0x5601c,
4057 .enable_reg = 0x5601c,
4058 .enable_mask = BIT(0),
4059 .hw.init = &(struct clk_init_data){
4060 .name = "gcc_uniphy0_port2_tx_clk",
4061 .parent_names = (const char *[]){
4062 "nss_port2_tx_div_clk_src"
4065 .flags = CLK_SET_RATE_PARENT,
4066 .ops = &clk_branch2_ops,
4071 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
4072 .halt_reg = 0x56020,
4074 .enable_reg = 0x56020,
4075 .enable_mask = BIT(0),
4076 .hw.init = &(struct clk_init_data){
4077 .name = "gcc_uniphy0_port3_rx_clk",
4078 .parent_names = (const char *[]){
4079 "nss_port3_rx_div_clk_src"
4082 .flags = CLK_SET_RATE_PARENT,
4083 .ops = &clk_branch2_ops,
4088 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
4089 .halt_reg = 0x56024,
4091 .enable_reg = 0x56024,
4092 .enable_mask = BIT(0),
4093 .hw.init = &(struct clk_init_data){
4094 .name = "gcc_uniphy0_port3_tx_clk",
4095 .parent_names = (const char *[]){
4096 "nss_port3_tx_div_clk_src"
4099 .flags = CLK_SET_RATE_PARENT,
4100 .ops = &clk_branch2_ops,
4105 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
4106 .halt_reg = 0x56028,
4108 .enable_reg = 0x56028,
4109 .enable_mask = BIT(0),
4110 .hw.init = &(struct clk_init_data){
4111 .name = "gcc_uniphy0_port4_rx_clk",
4112 .parent_names = (const char *[]){
4113 "nss_port4_rx_div_clk_src"
4116 .flags = CLK_SET_RATE_PARENT,
4117 .ops = &clk_branch2_ops,
4122 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
4123 .halt_reg = 0x5602c,
4125 .enable_reg = 0x5602c,
4126 .enable_mask = BIT(0),
4127 .hw.init = &(struct clk_init_data){
4128 .name = "gcc_uniphy0_port4_tx_clk",
4129 .parent_names = (const char *[]){
4130 "nss_port4_tx_div_clk_src"
4133 .flags = CLK_SET_RATE_PARENT,
4134 .ops = &clk_branch2_ops,
4139 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
4140 .halt_reg = 0x56030,
4142 .enable_reg = 0x56030,
4143 .enable_mask = BIT(0),
4144 .hw.init = &(struct clk_init_data){
4145 .name = "gcc_uniphy0_port5_rx_clk",
4146 .parent_names = (const char *[]){
4147 "nss_port5_rx_div_clk_src"
4150 .flags = CLK_SET_RATE_PARENT,
4151 .ops = &clk_branch2_ops,
4156 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
4157 .halt_reg = 0x56034,
4159 .enable_reg = 0x56034,
4160 .enable_mask = BIT(0),
4161 .hw.init = &(struct clk_init_data){
4162 .name = "gcc_uniphy0_port5_tx_clk",
4163 .parent_names = (const char *[]){
4164 "nss_port5_tx_div_clk_src"
4167 .flags = CLK_SET_RATE_PARENT,
4168 .ops = &clk_branch2_ops,
4173 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
4174 .halt_reg = 0x56110,
4176 .enable_reg = 0x56110,
4177 .enable_mask = BIT(0),
4178 .hw.init = &(struct clk_init_data){
4179 .name = "gcc_uniphy1_port5_rx_clk",
4180 .parent_names = (const char *[]){
4181 "nss_port5_rx_div_clk_src"
4184 .flags = CLK_SET_RATE_PARENT,
4185 .ops = &clk_branch2_ops,
4190 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
4191 .halt_reg = 0x56114,
4193 .enable_reg = 0x56114,
4194 .enable_mask = BIT(0),
4195 .hw.init = &(struct clk_init_data){
4196 .name = "gcc_uniphy1_port5_tx_clk",
4197 .parent_names = (const char *[]){
4198 "nss_port5_tx_div_clk_src"
4201 .flags = CLK_SET_RATE_PARENT,
4202 .ops = &clk_branch2_ops,
4207 static struct clk_branch gcc_uniphy2_port6_rx_clk = {
4208 .halt_reg = 0x56210,
4210 .enable_reg = 0x56210,
4211 .enable_mask = BIT(0),
4212 .hw.init = &(struct clk_init_data){
4213 .name = "gcc_uniphy2_port6_rx_clk",
4214 .parent_names = (const char *[]){
4215 "nss_port6_rx_div_clk_src"
4218 .flags = CLK_SET_RATE_PARENT,
4219 .ops = &clk_branch2_ops,
4224 static struct clk_branch gcc_uniphy2_port6_tx_clk = {
4225 .halt_reg = 0x56214,
4227 .enable_reg = 0x56214,
4228 .enable_mask = BIT(0),
4229 .hw.init = &(struct clk_init_data){
4230 .name = "gcc_uniphy2_port6_tx_clk",
4231 .parent_names = (const char *[]){
4232 "nss_port6_tx_div_clk_src"
4235 .flags = CLK_SET_RATE_PARENT,
4236 .ops = &clk_branch2_ops,
4241 static struct clk_branch gcc_crypto_ahb_clk = {
4242 .halt_reg = 0x16024,
4243 .halt_check = BRANCH_HALT_VOTED,
4245 .enable_reg = 0x0b004,
4246 .enable_mask = BIT(0),
4247 .hw.init = &(struct clk_init_data){
4248 .name = "gcc_crypto_ahb_clk",
4249 .parent_names = (const char *[]){
4253 .flags = CLK_SET_RATE_PARENT,
4254 .ops = &clk_branch2_ops,
4259 static struct clk_branch gcc_crypto_axi_clk = {
4260 .halt_reg = 0x16020,
4261 .halt_check = BRANCH_HALT_VOTED,
4263 .enable_reg = 0x0b004,
4264 .enable_mask = BIT(1),
4265 .hw.init = &(struct clk_init_data){
4266 .name = "gcc_crypto_axi_clk",
4267 .parent_names = (const char *[]){
4271 .flags = CLK_SET_RATE_PARENT,
4272 .ops = &clk_branch2_ops,
4277 static struct clk_branch gcc_crypto_clk = {
4278 .halt_reg = 0x1601c,
4279 .halt_check = BRANCH_HALT_VOTED,
4281 .enable_reg = 0x0b004,
4282 .enable_mask = BIT(2),
4283 .hw.init = &(struct clk_init_data){
4284 .name = "gcc_crypto_clk",
4285 .parent_names = (const char *[]){
4289 .flags = CLK_SET_RATE_PARENT,
4290 .ops = &clk_branch2_ops,
4295 static struct clk_branch gcc_gp1_clk = {
4296 .halt_reg = 0x08000,
4298 .enable_reg = 0x08000,
4299 .enable_mask = BIT(0),
4300 .hw.init = &(struct clk_init_data){
4301 .name = "gcc_gp1_clk",
4302 .parent_names = (const char *[]){
4306 .flags = CLK_SET_RATE_PARENT,
4307 .ops = &clk_branch2_ops,
4312 static struct clk_branch gcc_gp2_clk = {
4313 .halt_reg = 0x09000,
4315 .enable_reg = 0x09000,
4316 .enable_mask = BIT(0),
4317 .hw.init = &(struct clk_init_data){
4318 .name = "gcc_gp2_clk",
4319 .parent_names = (const char *[]){
4323 .flags = CLK_SET_RATE_PARENT,
4324 .ops = &clk_branch2_ops,
4329 static struct clk_branch gcc_gp3_clk = {
4330 .halt_reg = 0x0a000,
4332 .enable_reg = 0x0a000,
4333 .enable_mask = BIT(0),
4334 .hw.init = &(struct clk_init_data){
4335 .name = "gcc_gp3_clk",
4336 .parent_names = (const char *[]){
4340 .flags = CLK_SET_RATE_PARENT,
4341 .ops = &clk_branch2_ops,
4346 static struct clk_hw *gcc_ipq8074_hws[] = {
4347 &gpll0_out_main_div2.hw,
4348 &gpll6_out_main_div2.hw,
4350 &system_noc_clk_src.hw,
4351 &gcc_xo_div4_clk_src.hw,
4352 &nss_noc_clk_src.hw,
4353 &nss_ppe_cdiv_clk_src.hw,
4356 static struct clk_regmap *gcc_ipq8074_clks[] = {
4357 [GPLL0_MAIN] = &gpll0_main.clkr,
4358 [GPLL0] = &gpll0.clkr,
4359 [GPLL2_MAIN] = &gpll2_main.clkr,
4360 [GPLL2] = &gpll2.clkr,
4361 [GPLL4_MAIN] = &gpll4_main.clkr,
4362 [GPLL4] = &gpll4.clkr,
4363 [GPLL6_MAIN] = &gpll6_main.clkr,
4364 [GPLL6] = &gpll6.clkr,
4365 [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4366 [UBI32_PLL] = &ubi32_pll.clkr,
4367 [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4368 [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4369 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4370 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4371 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4372 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4373 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4374 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4375 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4376 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4377 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4378 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4379 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4380 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4381 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4382 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4383 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4384 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4385 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4386 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4387 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4388 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4389 [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4390 [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4391 [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4392 [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4393 [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4394 [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4395 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4396 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4397 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4398 [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4399 [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4400 [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4401 [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4402 [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4403 [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4404 [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4405 [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4406 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4407 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4408 [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4409 [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4410 [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4411 [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4412 [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4413 [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4414 [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4415 [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4416 [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4417 [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4418 [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4419 [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4420 [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4421 [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4422 [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4423 [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4424 [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4425 [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4426 [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4427 [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4428 [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4429 [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4430 [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4431 [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4432 [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4433 [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4434 [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4435 [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4436 [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4437 [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4438 [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4439 [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4440 [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4441 [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4442 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4443 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4444 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4445 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4446 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4447 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4448 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4449 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4450 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4451 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4452 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4453 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4454 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4455 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4456 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4457 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4458 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4459 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4460 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4461 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4462 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4463 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4464 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4465 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4466 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4467 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4468 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4469 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4470 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4471 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4472 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4473 [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4474 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4475 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4476 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4477 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4478 [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4479 [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4480 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4481 [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4482 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4483 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4484 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4485 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4486 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4487 [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4488 [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4489 [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4490 [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4491 [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4492 [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4493 [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4494 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4495 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4496 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4497 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4498 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4499 [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4500 [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4501 [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4502 [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4503 [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4504 [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4505 [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4506 [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4507 [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4508 [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4509 [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4510 [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4511 [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4512 [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4513 [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4514 [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4515 [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4516 [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4517 [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4518 [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4519 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4520 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4521 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4522 [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4523 [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4524 [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4525 [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4526 [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4527 [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4528 [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4529 [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4530 [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4531 [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4532 [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4533 [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4534 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4535 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4536 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4537 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4538 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4539 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4540 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4541 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4542 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4543 [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4544 [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4545 [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4546 [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4547 [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4548 [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4549 [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4550 [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4551 [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4552 [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4553 [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4554 [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4555 [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4556 [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4557 [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4558 [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4559 [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4560 [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4561 [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4562 [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4563 [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4564 [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4565 [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4566 [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4567 [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4568 [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4569 [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4570 [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4571 [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4572 [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4573 [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4574 [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4575 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4576 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4577 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4578 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4579 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4580 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4583 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
4584 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4585 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4586 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4587 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4588 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4589 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4590 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4591 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4592 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4593 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4594 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4595 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4596 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4597 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4598 [GCC_SMMU_BCR] = { 0x12000, 0 },
4599 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4600 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4601 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4602 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4603 [GCC_PRNG_BCR] = { 0x13000, 0 },
4604 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4605 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4606 [GCC_WCSS_BCR] = { 0x18000, 0 },
4607 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4608 [GCC_NSS_BCR] = { 0x19000, 0 },
4609 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4610 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4611 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4612 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4613 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4614 [GCC_TCSR_BCR] = { 0x28000, 0 },
4615 [GCC_QDSS_BCR] = { 0x29000, 0 },
4616 [GCC_DCD_BCR] = { 0x2a000, 0 },
4617 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4618 [GCC_MPM_BCR] = { 0x2c000, 0 },
4619 [GCC_SPMI_BCR] = { 0x2e000, 0 },
4620 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4621 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4622 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4623 [GCC_TLMM_BCR] = { 0x34000, 0 },
4624 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4625 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4626 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4627 [GCC_USB0_BCR] = { 0x3e070, 0 },
4628 [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4629 [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4630 [GCC_USB1_BCR] = { 0x3f070, 0 },
4631 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4632 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4633 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4634 [GCC_SDCC2_BCR] = { 0x43000, 0 },
4635 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4636 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4637 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4638 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4639 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4640 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4641 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4642 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4643 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4644 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4645 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4646 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4647 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4648 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4649 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4650 [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4651 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4652 [GCC_QPIC_BCR] = { 0x57018, 0 },
4653 [GCC_MDIO_BCR] = { 0x58000, 0 },
4654 [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4655 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4656 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4657 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4658 [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4659 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4660 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4661 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4662 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4663 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4664 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4665 [GCC_PCIE1_BCR] = { 0x76004, 0 },
4666 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4667 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4668 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4669 [GCC_DCC_BCR] = { 0x77000, 0 },
4670 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4671 [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4672 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4673 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4674 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4675 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4676 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4677 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4678 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4679 [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4680 [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4681 [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4682 [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4683 [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4684 [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4685 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4686 [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4687 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4688 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4689 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4690 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4691 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4692 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4693 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4694 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4695 [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4696 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4697 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4698 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4699 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4700 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4701 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4702 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4703 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4704 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4705 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4706 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4707 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4708 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4709 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4710 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4711 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4712 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4713 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4714 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4717 static const struct of_device_id gcc_ipq8074_match_table[] = {
4718 { .compatible = "qcom,gcc-ipq8074" },
4721 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
4723 static const struct regmap_config gcc_ipq8074_regmap_config = {
4727 .max_register = 0x7fffc,
4731 static const struct qcom_cc_desc gcc_ipq8074_desc = {
4732 .config = &gcc_ipq8074_regmap_config,
4733 .clks = gcc_ipq8074_clks,
4734 .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4735 .resets = gcc_ipq8074_resets,
4736 .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4739 static int gcc_ipq8074_probe(struct platform_device *pdev)
4743 for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) {
4744 ret = devm_clk_hw_register(&pdev->dev, gcc_ipq8074_hws[i]);
4749 return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
4752 static struct platform_driver gcc_ipq8074_driver = {
4753 .probe = gcc_ipq8074_probe,
4755 .name = "qcom,gcc-ipq8074",
4756 .of_match_table = gcc_ipq8074_match_table,
4760 static int __init gcc_ipq8074_init(void)
4762 return platform_driver_register(&gcc_ipq8074_driver);
4764 core_initcall(gcc_ipq8074_init);
4766 static void __exit gcc_ipq8074_exit(void)
4768 platform_driver_unregister(&gcc_ipq8074_driver);
4770 module_exit(gcc_ipq8074_exit);
4772 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
4773 MODULE_LICENSE("GPL v2");
4774 MODULE_ALIAS("platform:gcc-ipq8074");