drivers/clk/qcom/gcc-msm8960.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
  26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34
  35 static struct clk_pll pll3 = {
  36         .l_reg = 0x3164,
  37         .m_reg = 0x3168,
  38         .n_reg = 0x316c,
  39         .config_reg = 0x3174,
  40         .mode_reg = 0x3160,
  41         .status_reg = 0x3178,
  42         .status_bit = 16,
  43         .clkr.hw.init = &(struct clk_init_data){
  44                 .name = "pll3",
  45                 .parent_names = (const char *[]){ "pxo" },
  46                 .num_parents = 1,
  47                 .ops = &clk_pll_ops,
  48         },
  49 };
  50
  51 static struct clk_regmap pll4_vote = {
  52         .enable_reg = 0x34c0,
  53         .enable_mask = BIT(4),
  54         .hw.init = &(struct clk_init_data){
  55                 .name = "pll4_vote",
  56                 .parent_names = (const char *[]){ "pll4" },
  57                 .num_parents = 1,
  58                 .ops = &clk_pll_vote_ops,
  59         },
  60 };
  61
  62 static struct clk_pll pll8 = {
  63         .l_reg = 0x3144,
  64         .m_reg = 0x3148,
  65         .n_reg = 0x314c,
  66         .config_reg = 0x3154,
  67         .mode_reg = 0x3140,
  68         .status_reg = 0x3158,
  69         .status_bit = 16,
  70         .clkr.hw.init = &(struct clk_init_data){
  71                 .name = "pll8",
  72                 .parent_names = (const char *[]){ "pxo" },
  73                 .num_parents = 1,
  74                 .ops = &clk_pll_ops,
  75         },
  76 };
  77
  78 static struct clk_regmap pll8_vote = {
  79         .enable_reg = 0x34c0,
  80         .enable_mask = BIT(8),
  81         .hw.init = &(struct clk_init_data){
  82                 .name = "pll8_vote",
  83                 .parent_names = (const char *[]){ "pll8" },
  84                 .num_parents = 1,
  85                 .ops = &clk_pll_vote_ops,
  86         },
  87 };
  88
  89 static struct clk_pll pll14 = {
  90         .l_reg = 0x31c4,
  91         .m_reg = 0x31c8,
  92         .n_reg = 0x31cc,
  93         .config_reg = 0x31d4,
  94         .mode_reg = 0x31c0,
  95         .status_reg = 0x31d8,
  96         .status_bit = 16,
  97         .clkr.hw.init = &(struct clk_init_data){
  98                 .name = "pll14",
  99                 .parent_names = (const char *[]){ "pxo" },
 100                 .num_parents = 1,
 101                 .ops = &clk_pll_ops,
 102         },
 103 };
 104
 105 static struct clk_regmap pll14_vote = {
 106         .enable_reg = 0x34c0,
 107         .enable_mask = BIT(14),
 108         .hw.init = &(struct clk_init_data){
 109                 .name = "pll14_vote",
 110                 .parent_names = (const char *[]){ "pll14" },
 111                 .num_parents = 1,
 112                 .ops = &clk_pll_vote_ops,
 113         },
 114 };
 115
 116 enum {
 117         P_PXO,
 118         P_PLL8,
 119         P_PLL3,
 120         P_CXO,
 121 };
 122
 123 static const struct parent_map gcc_pxo_pll8_map[] = {
 124         { P_PXO, 0 },
 125         { P_PLL8, 3 }
 126 };
 127
 128 static const char * const gcc_pxo_pll8[] = {
 129         "pxo",
 130         "pll8_vote",
 131 };
 132
 133 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
 134         { P_PXO, 0 },
 135         { P_PLL8, 3 },
 136         { P_CXO, 5 }
 137 };
 138
 139 static const char * const gcc_pxo_pll8_cxo[] = {
 140         "pxo",
 141         "pll8_vote",
 142         "cxo",
 143 };
 144
 145 static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
 146         { P_PXO, 0 },
 147         { P_PLL8, 3 },
 148         { P_PLL3, 6 }
 149 };
 150
 151 static const char * const gcc_pxo_pll8_pll3[] = {
 152         "pxo",
 153         "pll8_vote",
 154         "pll3",
 155 };
 156
 157 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 158         {  1843200, P_PLL8, 2,  6, 625 },
 159         {  3686400, P_PLL8, 2, 12, 625 },
 160         {  7372800, P_PLL8, 2, 24, 625 },
 161         { 14745600, P_PLL8, 2, 48, 625 },
 162         { 16000000, P_PLL8, 4,  1,   6 },
 163         { 24000000, P_PLL8, 4,  1,   4 },
 164         { 32000000, P_PLL8, 4,  1,   3 },
 165         { 40000000, P_PLL8, 1,  5,  48 },
 166         { 46400000, P_PLL8, 1, 29, 240 },
 167         { 48000000, P_PLL8, 4,  1,   2 },
 168         { 51200000, P_PLL8, 1,  2,  15 },
 169         { 56000000, P_PLL8, 1,  7,  48 },
 170         { 58982400, P_PLL8, 1, 96, 625 },
 171         { 64000000, P_PLL8, 2,  1,   3 },
 172         { }
 173 };
 174
 175 static struct clk_rcg gsbi1_uart_src = {
 176         .ns_reg = 0x29d4,
 177         .md_reg = 0x29d0,
 178         .mn = {
 179                 .mnctr_en_bit = 8,
 180                 .mnctr_reset_bit = 7,
 181                 .mnctr_mode_shift = 5,
 182                 .n_val_shift = 16,
 183                 .m_val_shift = 16,
 184                 .width = 16,
 185         },
 186         .p = {
 187                 .pre_div_shift = 3,
 188                 .pre_div_width = 2,
 189         },
 190         .s = {
 191                 .src_sel_shift = 0,
 192                 .parent_map = gcc_pxo_pll8_map,
 193         },
 194         .freq_tbl = clk_tbl_gsbi_uart,
 195         .clkr = {
 196                 .enable_reg = 0x29d4,
 197                 .enable_mask = BIT(11),
 198                 .hw.init = &(struct clk_init_data){
 199                         .name = "gsbi1_uart_src",
 200                         .parent_names = gcc_pxo_pll8,
 201                         .num_parents = 2,
 202                         .ops = &clk_rcg_ops,
 203                         .flags = CLK_SET_PARENT_GATE,
 204                 },
 205         },
 206 };
 207
 208 static struct clk_branch gsbi1_uart_clk = {
 209         .halt_reg = 0x2fcc,
 210         .halt_bit = 10,
 211         .clkr = {
 212                 .enable_reg = 0x29d4,
 213                 .enable_mask = BIT(9),
 214                 .hw.init = &(struct clk_init_data){
 215                         .name = "gsbi1_uart_clk",
 216                         .parent_names = (const char *[]){
 217                                 "gsbi1_uart_src",
 218                         },
 219                         .num_parents = 1,
 220                         .ops = &clk_branch_ops,
 221                         .flags = CLK_SET_RATE_PARENT,
 222                 },
 223         },
 224 };
 225
 226 static struct clk_rcg gsbi2_uart_src = {
 227         .ns_reg = 0x29f4,
 228         .md_reg = 0x29f0,
 229         .mn = {
 230                 .mnctr_en_bit = 8,
 231                 .mnctr_reset_bit = 7,
 232                 .mnctr_mode_shift = 5,
 233                 .n_val_shift = 16,
 234                 .m_val_shift = 16,
 235                 .width = 16,
 236         },
 237         .p = {
 238                 .pre_div_shift = 3,
 239                 .pre_div_width = 2,
 240         },
 241         .s = {
 242                 .src_sel_shift = 0,
 243                 .parent_map = gcc_pxo_pll8_map,
 244         },
 245         .freq_tbl = clk_tbl_gsbi_uart,
 246         .clkr = {
 247                 .enable_reg = 0x29f4,
 248                 .enable_mask = BIT(11),
 249                 .hw.init = &(struct clk_init_data){
 250                         .name = "gsbi2_uart_src",
 251                         .parent_names = gcc_pxo_pll8,
 252                         .num_parents = 2,
 253                         .ops = &clk_rcg_ops,
 254                         .flags = CLK_SET_PARENT_GATE,
 255                 },
 256         },
 257 };
 258
 259 static struct clk_branch gsbi2_uart_clk = {
 260         .halt_reg = 0x2fcc,
 261         .halt_bit = 6,
 262         .clkr = {
 263                 .enable_reg = 0x29f4,
 264                 .enable_mask = BIT(9),
 265                 .hw.init = &(struct clk_init_data){
 266                         .name = "gsbi2_uart_clk",
 267                         .parent_names = (const char *[]){
 268                                 "gsbi2_uart_src",
 269                         },
 270                         .num_parents = 1,
 271                         .ops = &clk_branch_ops,
 272                         .flags = CLK_SET_RATE_PARENT,
 273                 },
 274         },
 275 };
 276
 277 static struct clk_rcg gsbi3_uart_src = {
 278         .ns_reg = 0x2a14,
 279         .md_reg = 0x2a10,
 280         .mn = {
 281                 .mnctr_en_bit = 8,
 282                 .mnctr_reset_bit = 7,
 283                 .mnctr_mode_shift = 5,
 284                 .n_val_shift = 16,
 285                 .m_val_shift = 16,
 286                 .width = 16,
 287         },
 288         .p = {
 289                 .pre_div_shift = 3,
 290                 .pre_div_width = 2,
 291         },
 292         .s = {
 293                 .src_sel_shift = 0,
 294                 .parent_map = gcc_pxo_pll8_map,
 295         },
 296         .freq_tbl = clk_tbl_gsbi_uart,
 297         .clkr = {
 298                 .enable_reg = 0x2a14,
 299                 .enable_mask = BIT(11),
 300                 .hw.init = &(struct clk_init_data){
 301                         .name = "gsbi3_uart_src",
 302                         .parent_names = gcc_pxo_pll8,
 303                         .num_parents = 2,
 304                         .ops = &clk_rcg_ops,
 305                         .flags = CLK_SET_PARENT_GATE,
 306                 },
 307         },
 308 };
 309
 310 static struct clk_branch gsbi3_uart_clk = {
 311         .halt_reg = 0x2fcc,
 312         .halt_bit = 2,
 313         .clkr = {
 314                 .enable_reg = 0x2a14,
 315                 .enable_mask = BIT(9),
 316                 .hw.init = &(struct clk_init_data){
 317                         .name = "gsbi3_uart_clk",
 318                         .parent_names = (const char *[]){
 319                                 "gsbi3_uart_src",
 320                         },
 321                         .num_parents = 1,
 322                         .ops = &clk_branch_ops,
 323                         .flags = CLK_SET_RATE_PARENT,
 324                 },
 325         },
 326 };
 327
 328 static struct clk_rcg gsbi4_uart_src = {
 329         .ns_reg = 0x2a34,
 330         .md_reg = 0x2a30,
 331         .mn = {
 332                 .mnctr_en_bit = 8,
 333                 .mnctr_reset_bit = 7,
 334                 .mnctr_mode_shift = 5,
 335                 .n_val_shift = 16,
 336                 .m_val_shift = 16,
 337                 .width = 16,
 338         },
 339         .p = {
 340                 .pre_div_shift = 3,
 341                 .pre_div_width = 2,
 342         },
 343         .s = {
 344                 .src_sel_shift = 0,
 345                 .parent_map = gcc_pxo_pll8_map,
 346         },
 347         .freq_tbl = clk_tbl_gsbi_uart,
 348         .clkr = {
 349                 .enable_reg = 0x2a34,
 350                 .enable_mask = BIT(11),
 351                 .hw.init = &(struct clk_init_data){
 352                         .name = "gsbi4_uart_src",
 353                         .parent_names = gcc_pxo_pll8,
 354                         .num_parents = 2,
 355                         .ops = &clk_rcg_ops,
 356                         .flags = CLK_SET_PARENT_GATE,
 357                 },
 358         },
 359 };
 360
 361 static struct clk_branch gsbi4_uart_clk = {
 362         .halt_reg = 0x2fd0,
 363         .halt_bit = 26,
 364         .clkr = {
 365                 .enable_reg = 0x2a34,
 366                 .enable_mask = BIT(9),
 367                 .hw.init = &(struct clk_init_data){
 368                         .name = "gsbi4_uart_clk",
 369                         .parent_names = (const char *[]){
 370                                 "gsbi4_uart_src",
 371                         },
 372                         .num_parents = 1,
 373                         .ops = &clk_branch_ops,
 374                         .flags = CLK_SET_RATE_PARENT,
 375                 },
 376         },
 377 };
 378
 379 static struct clk_rcg gsbi5_uart_src = {
 380         .ns_reg = 0x2a54,
 381         .md_reg = 0x2a50,
 382         .mn = {
 383                 .mnctr_en_bit = 8,
 384                 .mnctr_reset_bit = 7,
 385                 .mnctr_mode_shift = 5,
 386                 .n_val_shift = 16,
 387                 .m_val_shift = 16,
 388                 .width = 16,
 389         },
 390         .p = {
 391                 .pre_div_shift = 3,
 392                 .pre_div_width = 2,
 393         },
 394         .s = {
 395                 .src_sel_shift = 0,
 396                 .parent_map = gcc_pxo_pll8_map,
 397         },
 398         .freq_tbl = clk_tbl_gsbi_uart,
 399         .clkr = {
 400                 .enable_reg = 0x2a54,
 401                 .enable_mask = BIT(11),
 402                 .hw.init = &(struct clk_init_data){
 403                         .name = "gsbi5_uart_src",
 404                         .parent_names = gcc_pxo_pll8,
 405                         .num_parents = 2,
 406                         .ops = &clk_rcg_ops,
 407                         .flags = CLK_SET_PARENT_GATE,
 408                 },
 409         },
 410 };
 411
 412 static struct clk_branch gsbi5_uart_clk = {
 413         .halt_reg = 0x2fd0,
 414         .halt_bit = 22,
 415         .clkr = {
 416                 .enable_reg = 0x2a54,
 417                 .enable_mask = BIT(9),
 418                 .hw.init = &(struct clk_init_data){
 419                         .name = "gsbi5_uart_clk",
 420                         .parent_names = (const char *[]){
 421                                 "gsbi5_uart_src",
 422                         },
 423                         .num_parents = 1,
 424                         .ops = &clk_branch_ops,
 425                         .flags = CLK_SET_RATE_PARENT,
 426                 },
 427         },
 428 };
 429
 430 static struct clk_rcg gsbi6_uart_src = {
 431         .ns_reg = 0x2a74,
 432         .md_reg = 0x2a70,
 433         .mn = {
 434                 .mnctr_en_bit = 8,
 435                 .mnctr_reset_bit = 7,
 436                 .mnctr_mode_shift = 5,
 437                 .n_val_shift = 16,
 438                 .m_val_shift = 16,
 439                 .width = 16,
 440         },
 441         .p = {
 442                 .pre_div_shift = 3,
 443                 .pre_div_width = 2,
 444         },
 445         .s = {
 446                 .src_sel_shift = 0,
 447                 .parent_map = gcc_pxo_pll8_map,
 448         },
 449         .freq_tbl = clk_tbl_gsbi_uart,
 450         .clkr = {
 451                 .enable_reg = 0x2a74,
 452                 .enable_mask = BIT(11),
 453                 .hw.init = &(struct clk_init_data){
 454                         .name = "gsbi6_uart_src",
 455                         .parent_names = gcc_pxo_pll8,
 456                         .num_parents = 2,
 457                         .ops = &clk_rcg_ops,
 458                         .flags = CLK_SET_PARENT_GATE,
 459                 },
 460         },
 461 };
 462
 463 static struct clk_branch gsbi6_uart_clk = {
 464         .halt_reg = 0x2fd0,
 465         .halt_bit = 18,
 466         .clkr = {
 467                 .enable_reg = 0x2a74,
 468                 .enable_mask = BIT(9),
 469                 .hw.init = &(struct clk_init_data){
 470                         .name = "gsbi6_uart_clk",
 471                         .parent_names = (const char *[]){
 472                                 "gsbi6_uart_src",
 473                         },
 474                         .num_parents = 1,
 475                         .ops = &clk_branch_ops,
 476                         .flags = CLK_SET_RATE_PARENT,
 477                 },
 478         },
 479 };
 480
 481 static struct clk_rcg gsbi7_uart_src = {
 482         .ns_reg = 0x2a94,
 483         .md_reg = 0x2a90,
 484         .mn = {
 485                 .mnctr_en_bit = 8,
 486                 .mnctr_reset_bit = 7,
 487                 .mnctr_mode_shift = 5,
 488                 .n_val_shift = 16,
 489                 .m_val_shift = 16,
 490                 .width = 16,
 491         },
 492         .p = {
 493                 .pre_div_shift = 3,
 494                 .pre_div_width = 2,
 495         },
 496         .s = {
 497                 .src_sel_shift = 0,
 498                 .parent_map = gcc_pxo_pll8_map,
 499         },
 500         .freq_tbl = clk_tbl_gsbi_uart,
 501         .clkr = {
 502                 .enable_reg = 0x2a94,
 503                 .enable_mask = BIT(11),
 504                 .hw.init = &(struct clk_init_data){
 505                         .name = "gsbi7_uart_src",
 506                         .parent_names = gcc_pxo_pll8,
 507                         .num_parents = 2,
 508                         .ops = &clk_rcg_ops,
 509                         .flags = CLK_SET_PARENT_GATE,
 510                 },
 511         },
 512 };
 513
 514 static struct clk_branch gsbi7_uart_clk = {
 515         .halt_reg = 0x2fd0,
 516         .halt_bit = 14,
 517         .clkr = {
 518                 .enable_reg = 0x2a94,
 519                 .enable_mask = BIT(9),
 520                 .hw.init = &(struct clk_init_data){
 521                         .name = "gsbi7_uart_clk",
 522                         .parent_names = (const char *[]){
 523                                 "gsbi7_uart_src",
 524                         },
 525                         .num_parents = 1,
 526                         .ops = &clk_branch_ops,
 527                         .flags = CLK_SET_RATE_PARENT,
 528                 },
 529         },
 530 };
 531
 532 static struct clk_rcg gsbi8_uart_src = {
 533         .ns_reg = 0x2ab4,
 534         .md_reg = 0x2ab0,
 535         .mn = {
 536                 .mnctr_en_bit = 8,
 537                 .mnctr_reset_bit = 7,
 538                 .mnctr_mode_shift = 5,
 539                 .n_val_shift = 16,
 540                 .m_val_shift = 16,
 541                 .width = 16,
 542         },
 543         .p = {
 544                 .pre_div_shift = 3,
 545                 .pre_div_width = 2,
 546         },
 547         .s = {
 548                 .src_sel_shift = 0,
 549                 .parent_map = gcc_pxo_pll8_map,
 550         },
 551         .freq_tbl = clk_tbl_gsbi_uart,
 552         .clkr = {
 553                 .enable_reg = 0x2ab4,
 554                 .enable_mask = BIT(11),
 555                 .hw.init = &(struct clk_init_data){
 556                         .name = "gsbi8_uart_src",
 557                         .parent_names = gcc_pxo_pll8,
 558                         .num_parents = 2,
 559                         .ops = &clk_rcg_ops,
 560                         .flags = CLK_SET_PARENT_GATE,
 561                 },
 562         },
 563 };
 564
 565 static struct clk_branch gsbi8_uart_clk = {
 566         .halt_reg = 0x2fd0,
 567         .halt_bit = 10,
 568         .clkr = {
 569                 .enable_reg = 0x2ab4,
 570                 .enable_mask = BIT(9),
 571                 .hw.init = &(struct clk_init_data){
 572                         .name = "gsbi8_uart_clk",
 573                         .parent_names = (const char *[]){ "gsbi8_uart_src" },
 574                         .num_parents = 1,
 575                         .ops = &clk_branch_ops,
 576                         .flags = CLK_SET_RATE_PARENT,
 577                 },
 578         },
 579 };
 580
 581 static struct clk_rcg gsbi9_uart_src = {
 582         .ns_reg = 0x2ad4,
 583         .md_reg = 0x2ad0,
 584         .mn = {
 585                 .mnctr_en_bit = 8,
 586                 .mnctr_reset_bit = 7,
 587                 .mnctr_mode_shift = 5,
 588                 .n_val_shift = 16,
 589                 .m_val_shift = 16,
 590                 .width = 16,
 591         },
 592         .p = {
 593                 .pre_div_shift = 3,
 594                 .pre_div_width = 2,
 595         },
 596         .s = {
 597                 .src_sel_shift = 0,
 598                 .parent_map = gcc_pxo_pll8_map,
 599         },
 600         .freq_tbl = clk_tbl_gsbi_uart,
 601         .clkr = {
 602                 .enable_reg = 0x2ad4,
 603                 .enable_mask = BIT(11),
 604                 .hw.init = &(struct clk_init_data){
 605                         .name = "gsbi9_uart_src",
 606                         .parent_names = gcc_pxo_pll8,
 607                         .num_parents = 2,
 608                         .ops = &clk_rcg_ops,
 609                         .flags = CLK_SET_PARENT_GATE,
 610                 },
 611         },
 612 };
 613
 614 static struct clk_branch gsbi9_uart_clk = {
 615         .halt_reg = 0x2fd0,
 616         .halt_bit = 6,
 617         .clkr = {
 618                 .enable_reg = 0x2ad4,
 619                 .enable_mask = BIT(9),
 620                 .hw.init = &(struct clk_init_data){
 621                         .name = "gsbi9_uart_clk",
 622                         .parent_names = (const char *[]){ "gsbi9_uart_src" },
 623                         .num_parents = 1,
 624                         .ops = &clk_branch_ops,
 625                         .flags = CLK_SET_RATE_PARENT,
 626                 },
 627         },
 628 };
 629
 630 static struct clk_rcg gsbi10_uart_src = {
 631         .ns_reg = 0x2af4,
 632         .md_reg = 0x2af0,
 633         .mn = {
 634                 .mnctr_en_bit = 8,
 635                 .mnctr_reset_bit = 7,
 636                 .mnctr_mode_shift = 5,
 637                 .n_val_shift = 16,
 638                 .m_val_shift = 16,
 639                 .width = 16,
 640         },
 641         .p = {
 642                 .pre_div_shift = 3,
 643                 .pre_div_width = 2,
 644         },
 645         .s = {
 646                 .src_sel_shift = 0,
 647                 .parent_map = gcc_pxo_pll8_map,
 648         },
 649         .freq_tbl = clk_tbl_gsbi_uart,
 650         .clkr = {
 651                 .enable_reg = 0x2af4,
 652                 .enable_mask = BIT(11),
 653                 .hw.init = &(struct clk_init_data){
 654                         .name = "gsbi10_uart_src",
 655                         .parent_names = gcc_pxo_pll8,
 656                         .num_parents = 2,
 657                         .ops = &clk_rcg_ops,
 658                         .flags = CLK_SET_PARENT_GATE,
 659                 },
 660         },
 661 };
 662
 663 static struct clk_branch gsbi10_uart_clk = {
 664         .halt_reg = 0x2fd0,
 665         .halt_bit = 2,
 666         .clkr = {
 667                 .enable_reg = 0x2af4,
 668                 .enable_mask = BIT(9),
 669                 .hw.init = &(struct clk_init_data){
 670                         .name = "gsbi10_uart_clk",
 671                         .parent_names = (const char *[]){ "gsbi10_uart_src" },
 672                         .num_parents = 1,
 673                         .ops = &clk_branch_ops,
 674                         .flags = CLK_SET_RATE_PARENT,
 675                 },
 676         },
 677 };
 678
 679 static struct clk_rcg gsbi11_uart_src = {
 680         .ns_reg = 0x2b14,
 681         .md_reg = 0x2b10,
 682         .mn = {
 683                 .mnctr_en_bit = 8,
 684                 .mnctr_reset_bit = 7,
 685                 .mnctr_mode_shift = 5,
 686                 .n_val_shift = 16,
 687                 .m_val_shift = 16,
 688                 .width = 16,
 689         },
 690         .p = {
 691                 .pre_div_shift = 3,
 692                 .pre_div_width = 2,
 693         },
 694         .s = {
 695                 .src_sel_shift = 0,
 696                 .parent_map = gcc_pxo_pll8_map,
 697         },
 698         .freq_tbl = clk_tbl_gsbi_uart,
 699         .clkr = {
 700                 .enable_reg = 0x2b14,
 701                 .enable_mask = BIT(11),
 702                 .hw.init = &(struct clk_init_data){
 703                         .name = "gsbi11_uart_src",
 704                         .parent_names = gcc_pxo_pll8,
 705                         .num_parents = 2,
 706                         .ops = &clk_rcg_ops,
 707                         .flags = CLK_SET_PARENT_GATE,
 708                 },
 709         },
 710 };
 711
 712 static struct clk_branch gsbi11_uart_clk = {
 713         .halt_reg = 0x2fd4,
 714         .halt_bit = 17,
 715         .clkr = {
 716                 .enable_reg = 0x2b14,
 717                 .enable_mask = BIT(9),
 718                 .hw.init = &(struct clk_init_data){
 719                         .name = "gsbi11_uart_clk",
 720                         .parent_names = (const char *[]){ "gsbi11_uart_src" },
 721                         .num_parents = 1,
 722                         .ops = &clk_branch_ops,
 723                         .flags = CLK_SET_RATE_PARENT,
 724                 },
 725         },
 726 };
 727
 728 static struct clk_rcg gsbi12_uart_src = {
 729         .ns_reg = 0x2b34,
 730         .md_reg = 0x2b30,
 731         .mn = {
 732                 .mnctr_en_bit = 8,
 733                 .mnctr_reset_bit = 7,
 734                 .mnctr_mode_shift = 5,
 735                 .n_val_shift = 16,
 736                 .m_val_shift = 16,
 737                 .width = 16,
 738         },
 739         .p = {
 740                 .pre_div_shift = 3,
 741                 .pre_div_width = 2,
 742         },
 743         .s = {
 744                 .src_sel_shift = 0,
 745                 .parent_map = gcc_pxo_pll8_map,
 746         },
 747         .freq_tbl = clk_tbl_gsbi_uart,
 748         .clkr = {
 749                 .enable_reg = 0x2b34,
 750                 .enable_mask = BIT(11),
 751                 .hw.init = &(struct clk_init_data){
 752                         .name = "gsbi12_uart_src",
 753                         .parent_names = gcc_pxo_pll8,
 754                         .num_parents = 2,
 755                         .ops = &clk_rcg_ops,
 756                         .flags = CLK_SET_PARENT_GATE,
 757                 },
 758         },
 759 };
 760
 761 static struct clk_branch gsbi12_uart_clk = {
 762         .halt_reg = 0x2fd4,
 763         .halt_bit = 13,
 764         .clkr = {
 765                 .enable_reg = 0x2b34,
 766                 .enable_mask = BIT(9),
 767                 .hw.init = &(struct clk_init_data){
 768                         .name = "gsbi12_uart_clk",
 769                         .parent_names = (const char *[]){ "gsbi12_uart_src" },
 770                         .num_parents = 1,
 771                         .ops = &clk_branch_ops,
 772                         .flags = CLK_SET_RATE_PARENT,
 773                 },
 774         },
 775 };
 776
 777 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 778         {  1100000, P_PXO,  1, 2, 49 },
 779         {  5400000, P_PXO,  1, 1,  5 },
 780         { 10800000, P_PXO,  1, 2,  5 },
 781         { 15060000, P_PLL8, 1, 2, 51 },
 782         { 24000000, P_PLL8, 4, 1,  4 },
 783         { 25600000, P_PLL8, 1, 1, 15 },
 784         { 27000000, P_PXO,  1, 0,  0 },
 785         { 48000000, P_PLL8, 4, 1,  2 },
 786         { 51200000, P_PLL8, 1, 2, 15 },
 787         { }
 788 };
 789
 790 static struct clk_rcg gsbi1_qup_src = {
 791         .ns_reg = 0x29cc,
 792         .md_reg = 0x29c8,
 793         .mn = {
 794                 .mnctr_en_bit = 8,
 795                 .mnctr_reset_bit = 7,
 796                 .mnctr_mode_shift = 5,
 797                 .n_val_shift = 16,
 798                 .m_val_shift = 16,
 799                 .width = 8,
 800         },
 801         .p = {
 802                 .pre_div_shift = 3,
 803                 .pre_div_width = 2,
 804         },
 805         .s = {
 806                 .src_sel_shift = 0,
 807                 .parent_map = gcc_pxo_pll8_map,
 808         },
 809         .freq_tbl = clk_tbl_gsbi_qup,
 810         .clkr = {
 811                 .enable_reg = 0x29cc,
 812                 .enable_mask = BIT(11),
 813                 .hw.init = &(struct clk_init_data){
 814                         .name = "gsbi1_qup_src",
 815                         .parent_names = gcc_pxo_pll8,
 816                         .num_parents = 2,
 817                         .ops = &clk_rcg_ops,
 818                         .flags = CLK_SET_PARENT_GATE,
 819                 },
 820         },
 821 };
 822
 823 static struct clk_branch gsbi1_qup_clk = {
 824         .halt_reg = 0x2fcc,
 825         .halt_bit = 9,
 826         .clkr = {
 827                 .enable_reg = 0x29cc,
 828                 .enable_mask = BIT(9),
 829                 .hw.init = &(struct clk_init_data){
 830                         .name = "gsbi1_qup_clk",
 831                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 832                         .num_parents = 1,
 833                         .ops = &clk_branch_ops,
 834                         .flags = CLK_SET_RATE_PARENT,
 835                 },
 836         },
 837 };
 838
 839 static struct clk_rcg gsbi2_qup_src = {
 840         .ns_reg = 0x29ec,
 841         .md_reg = 0x29e8,
 842         .mn = {
 843                 .mnctr_en_bit = 8,
 844                 .mnctr_reset_bit = 7,
 845                 .mnctr_mode_shift = 5,
 846                 .n_val_shift = 16,
 847                 .m_val_shift = 16,
 848                 .width = 8,
 849         },
 850         .p = {
 851                 .pre_div_shift = 3,
 852                 .pre_div_width = 2,
 853         },
 854         .s = {
 855                 .src_sel_shift = 0,
 856                 .parent_map = gcc_pxo_pll8_map,
 857         },
 858         .freq_tbl = clk_tbl_gsbi_qup,
 859         .clkr = {
 860                 .enable_reg = 0x29ec,
 861                 .enable_mask = BIT(11),
 862                 .hw.init = &(struct clk_init_data){
 863                         .name = "gsbi2_qup_src",
 864                         .parent_names = gcc_pxo_pll8,
 865                         .num_parents = 2,
 866                         .ops = &clk_rcg_ops,
 867                         .flags = CLK_SET_PARENT_GATE,
 868                 },
 869         },
 870 };
 871
 872 static struct clk_branch gsbi2_qup_clk = {
 873         .halt_reg = 0x2fcc,
 874         .halt_bit = 4,
 875         .clkr = {
 876                 .enable_reg = 0x29ec,
 877                 .enable_mask = BIT(9),
 878                 .hw.init = &(struct clk_init_data){
 879                         .name = "gsbi2_qup_clk",
 880                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
 881                         .num_parents = 1,
 882                         .ops = &clk_branch_ops,
 883                         .flags = CLK_SET_RATE_PARENT,
 884                 },
 885         },
 886 };
 887
 888 static struct clk_rcg gsbi3_qup_src = {
 889         .ns_reg = 0x2a0c,
 890         .md_reg = 0x2a08,
 891         .mn = {
 892                 .mnctr_en_bit = 8,
 893                 .mnctr_reset_bit = 7,
 894                 .mnctr_mode_shift = 5,
 895                 .n_val_shift = 16,
 896                 .m_val_shift = 16,
 897                 .width = 8,
 898         },
 899         .p = {
 900                 .pre_div_shift = 3,
 901                 .pre_div_width = 2,
 902         },
 903         .s = {
 904                 .src_sel_shift = 0,
 905                 .parent_map = gcc_pxo_pll8_map,
 906         },
 907         .freq_tbl = clk_tbl_gsbi_qup,
 908         .clkr = {
 909                 .enable_reg = 0x2a0c,
 910                 .enable_mask = BIT(11),
 911                 .hw.init = &(struct clk_init_data){
 912                         .name = "gsbi3_qup_src",
 913                         .parent_names = gcc_pxo_pll8,
 914                         .num_parents = 2,
 915                         .ops = &clk_rcg_ops,
 916                         .flags = CLK_SET_PARENT_GATE,
 917                 },
 918         },
 919 };
 920
 921 static struct clk_branch gsbi3_qup_clk = {
 922         .halt_reg = 0x2fcc,
 923         .halt_bit = 0,
 924         .clkr = {
 925                 .enable_reg = 0x2a0c,
 926                 .enable_mask = BIT(9),
 927                 .hw.init = &(struct clk_init_data){
 928                         .name = "gsbi3_qup_clk",
 929                         .parent_names = (const char *[]){ "gsbi3_qup_src" },
 930                         .num_parents = 1,
 931                         .ops = &clk_branch_ops,
 932                         .flags = CLK_SET_RATE_PARENT,
 933                 },
 934         },
 935 };
 936
 937 static struct clk_rcg gsbi4_qup_src = {
 938         .ns_reg = 0x2a2c,
 939         .md_reg = 0x2a28,
 940         .mn = {
 941                 .mnctr_en_bit = 8,
 942                 .mnctr_reset_bit = 7,
 943                 .mnctr_mode_shift = 5,
 944                 .n_val_shift = 16,
 945                 .m_val_shift = 16,
 946                 .width = 8,
 947         },
 948         .p = {
 949                 .pre_div_shift = 3,
 950                 .pre_div_width = 2,
 951         },
 952         .s = {
 953                 .src_sel_shift = 0,
 954                 .parent_map = gcc_pxo_pll8_map,
 955         },
 956         .freq_tbl = clk_tbl_gsbi_qup,
 957         .clkr = {
 958                 .enable_reg = 0x2a2c,
 959                 .enable_mask = BIT(11),
 960                 .hw.init = &(struct clk_init_data){
 961                         .name = "gsbi4_qup_src",
 962                         .parent_names = gcc_pxo_pll8,
 963                         .num_parents = 2,
 964                         .ops = &clk_rcg_ops,
 965                         .flags = CLK_SET_PARENT_GATE,
 966                 },
 967         },
 968 };
 969
 970 static struct clk_branch gsbi4_qup_clk = {
 971         .halt_reg = 0x2fd0,
 972         .halt_bit = 24,
 973         .clkr = {
 974                 .enable_reg = 0x2a2c,
 975                 .enable_mask = BIT(9),
 976                 .hw.init = &(struct clk_init_data){
 977                         .name = "gsbi4_qup_clk",
 978                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
 979                         .num_parents = 1,
 980                         .ops = &clk_branch_ops,
 981                         .flags = CLK_SET_RATE_PARENT,
 982                 },
 983         },
 984 };
 985
 986 static struct clk_rcg gsbi5_qup_src = {
 987         .ns_reg = 0x2a4c,
 988         .md_reg = 0x2a48,
 989         .mn = {
 990                 .mnctr_en_bit = 8,
 991                 .mnctr_reset_bit = 7,
 992                 .mnctr_mode_shift = 5,
 993                 .n_val_shift = 16,
 994                 .m_val_shift = 16,
 995                 .width = 8,
 996         },
 997         .p = {
 998                 .pre_div_shift = 3,
 999                 .pre_div_width = 2,
1000         },
1001         .s = {
1002                 .src_sel_shift = 0,
1003                 .parent_map = gcc_pxo_pll8_map,
1004         },
1005         .freq_tbl = clk_tbl_gsbi_qup,
1006         .clkr = {
1007                 .enable_reg = 0x2a4c,
1008                 .enable_mask = BIT(11),
1009                 .hw.init = &(struct clk_init_data){
1010                         .name = "gsbi5_qup_src",
1011                         .parent_names = gcc_pxo_pll8,
1012                         .num_parents = 2,
1013                         .ops = &clk_rcg_ops,
1014                         .flags = CLK_SET_PARENT_GATE,
1015                 },
1016         },
1017 };
1018
1019 static struct clk_branch gsbi5_qup_clk = {
1020         .halt_reg = 0x2fd0,
1021         .halt_bit = 20,
1022         .clkr = {
1023                 .enable_reg = 0x2a4c,
1024                 .enable_mask = BIT(9),
1025                 .hw.init = &(struct clk_init_data){
1026                         .name = "gsbi5_qup_clk",
1027                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
1028                         .num_parents = 1,
1029                         .ops = &clk_branch_ops,
1030                         .flags = CLK_SET_RATE_PARENT,
1031                 },
1032         },
1033 };
1034
1035 static struct clk_rcg gsbi6_qup_src = {
1036         .ns_reg = 0x2a6c,
1037         .md_reg = 0x2a68,
1038         .mn = {
1039                 .mnctr_en_bit = 8,
1040                 .mnctr_reset_bit = 7,
1041                 .mnctr_mode_shift = 5,
1042                 .n_val_shift = 16,
1043                 .m_val_shift = 16,
1044                 .width = 8,
1045         },
1046         .p = {
1047                 .pre_div_shift = 3,
1048                 .pre_div_width = 2,
1049         },
1050         .s = {
1051                 .src_sel_shift = 0,
1052                 .parent_map = gcc_pxo_pll8_map,
1053         },
1054         .freq_tbl = clk_tbl_gsbi_qup,
1055         .clkr = {
1056                 .enable_reg = 0x2a6c,
1057                 .enable_mask = BIT(11),
1058                 .hw.init = &(struct clk_init_data){
1059                         .name = "gsbi6_qup_src",
1060                         .parent_names = gcc_pxo_pll8,
1061                         .num_parents = 2,
1062                         .ops = &clk_rcg_ops,
1063                         .flags = CLK_SET_PARENT_GATE,
1064                 },
1065         },
1066 };
1067
1068 static struct clk_branch gsbi6_qup_clk = {
1069         .halt_reg = 0x2fd0,
1070         .halt_bit = 16,
1071         .clkr = {
1072                 .enable_reg = 0x2a6c,
1073                 .enable_mask = BIT(9),
1074                 .hw.init = &(struct clk_init_data){
1075                         .name = "gsbi6_qup_clk",
1076                         .parent_names = (const char *[]){ "gsbi6_qup_src" },
1077                         .num_parents = 1,
1078                         .ops = &clk_branch_ops,
1079                         .flags = CLK_SET_RATE_PARENT,
1080                 },
1081         },
1082 };
1083
1084 static struct clk_rcg gsbi7_qup_src = {
1085         .ns_reg = 0x2a8c,
1086         .md_reg = 0x2a88,
1087         .mn = {
1088                 .mnctr_en_bit = 8,
1089                 .mnctr_reset_bit = 7,
1090                 .mnctr_mode_shift = 5,
1091                 .n_val_shift = 16,
1092                 .m_val_shift = 16,
1093                 .width = 8,
1094         },
1095         .p = {
1096                 .pre_div_shift = 3,
1097                 .pre_div_width = 2,
1098         },
1099         .s = {
1100                 .src_sel_shift = 0,
1101                 .parent_map = gcc_pxo_pll8_map,
1102         },
1103         .freq_tbl = clk_tbl_gsbi_qup,
1104         .clkr = {
1105                 .enable_reg = 0x2a8c,
1106                 .enable_mask = BIT(11),
1107                 .hw.init = &(struct clk_init_data){
1108                         .name = "gsbi7_qup_src",
1109                         .parent_names = gcc_pxo_pll8,
1110                         .num_parents = 2,
1111                         .ops = &clk_rcg_ops,
1112                         .flags = CLK_SET_PARENT_GATE,
1113                 },
1114         },
1115 };
1116
1117 static struct clk_branch gsbi7_qup_clk = {
1118         .halt_reg = 0x2fd0,
1119         .halt_bit = 12,
1120         .clkr = {
1121                 .enable_reg = 0x2a8c,
1122                 .enable_mask = BIT(9),
1123                 .hw.init = &(struct clk_init_data){
1124                         .name = "gsbi7_qup_clk",
1125                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
1126                         .num_parents = 1,
1127                         .ops = &clk_branch_ops,
1128                         .flags = CLK_SET_RATE_PARENT,
1129                 },
1130         },
1131 };
1132
1133 static struct clk_rcg gsbi8_qup_src = {
1134         .ns_reg = 0x2aac,
1135         .md_reg = 0x2aa8,
1136         .mn = {
1137                 .mnctr_en_bit = 8,
1138                 .mnctr_reset_bit = 7,
1139                 .mnctr_mode_shift = 5,
1140                 .n_val_shift = 16,
1141                 .m_val_shift = 16,
1142                 .width = 8,
1143         },
1144         .p = {
1145                 .pre_div_shift = 3,
1146                 .pre_div_width = 2,
1147         },
1148         .s = {
1149                 .src_sel_shift = 0,
1150                 .parent_map = gcc_pxo_pll8_map,
1151         },
1152         .freq_tbl = clk_tbl_gsbi_qup,
1153         .clkr = {
1154                 .enable_reg = 0x2aac,
1155                 .enable_mask = BIT(11),
1156                 .hw.init = &(struct clk_init_data){
1157                         .name = "gsbi8_qup_src",
1158                         .parent_names = gcc_pxo_pll8,
1159                         .num_parents = 2,
1160                         .ops = &clk_rcg_ops,
1161                         .flags = CLK_SET_PARENT_GATE,
1162                 },
1163         },
1164 };
1165
1166 static struct clk_branch gsbi8_qup_clk = {
1167         .halt_reg = 0x2fd0,
1168         .halt_bit = 8,
1169         .clkr = {
1170                 .enable_reg = 0x2aac,
1171                 .enable_mask = BIT(9),
1172                 .hw.init = &(struct clk_init_data){
1173                         .name = "gsbi8_qup_clk",
1174                         .parent_names = (const char *[]){ "gsbi8_qup_src" },
1175                         .num_parents = 1,
1176                         .ops = &clk_branch_ops,
1177                         .flags = CLK_SET_RATE_PARENT,
1178                 },
1179         },
1180 };
1181
1182 static struct clk_rcg gsbi9_qup_src = {
1183         .ns_reg = 0x2acc,
1184         .md_reg = 0x2ac8,
1185         .mn = {
1186                 .mnctr_en_bit = 8,
1187                 .mnctr_reset_bit = 7,
1188                 .mnctr_mode_shift = 5,
1189                 .n_val_shift = 16,
1190                 .m_val_shift = 16,
1191                 .width = 8,
1192         },
1193         .p = {
1194                 .pre_div_shift = 3,
1195                 .pre_div_width = 2,
1196         },
1197         .s = {
1198                 .src_sel_shift = 0,
1199                 .parent_map = gcc_pxo_pll8_map,
1200         },
1201         .freq_tbl = clk_tbl_gsbi_qup,
1202         .clkr = {
1203                 .enable_reg = 0x2acc,
1204                 .enable_mask = BIT(11),
1205                 .hw.init = &(struct clk_init_data){
1206                         .name = "gsbi9_qup_src",
1207                         .parent_names = gcc_pxo_pll8,
1208                         .num_parents = 2,
1209                         .ops = &clk_rcg_ops,
1210                         .flags = CLK_SET_PARENT_GATE,
1211                 },
1212         },
1213 };
1214
1215 static struct clk_branch gsbi9_qup_clk = {
1216         .halt_reg = 0x2fd0,
1217         .halt_bit = 4,
1218         .clkr = {
1219                 .enable_reg = 0x2acc,
1220                 .enable_mask = BIT(9),
1221                 .hw.init = &(struct clk_init_data){
1222                         .name = "gsbi9_qup_clk",
1223                         .parent_names = (const char *[]){ "gsbi9_qup_src" },
1224                         .num_parents = 1,
1225                         .ops = &clk_branch_ops,
1226                         .flags = CLK_SET_RATE_PARENT,
1227                 },
1228         },
1229 };
1230
1231 static struct clk_rcg gsbi10_qup_src = {
1232         .ns_reg = 0x2aec,
1233         .md_reg = 0x2ae8,
1234         .mn = {
1235                 .mnctr_en_bit = 8,
1236                 .mnctr_reset_bit = 7,
1237                 .mnctr_mode_shift = 5,
1238                 .n_val_shift = 16,
1239                 .m_val_shift = 16,
1240                 .width = 8,
1241         },
1242         .p = {
1243                 .pre_div_shift = 3,
1244                 .pre_div_width = 2,
1245         },
1246         .s = {
1247                 .src_sel_shift = 0,
1248                 .parent_map = gcc_pxo_pll8_map,
1249         },
1250         .freq_tbl = clk_tbl_gsbi_qup,
1251         .clkr = {
1252                 .enable_reg = 0x2aec,
1253                 .enable_mask = BIT(11),
1254                 .hw.init = &(struct clk_init_data){
1255                         .name = "gsbi10_qup_src",
1256                         .parent_names = gcc_pxo_pll8,
1257                         .num_parents = 2,
1258                         .ops = &clk_rcg_ops,
1259                         .flags = CLK_SET_PARENT_GATE,
1260                 },
1261         },
1262 };
1263
1264 static struct clk_branch gsbi10_qup_clk = {
1265         .halt_reg = 0x2fd0,
1266         .halt_bit = 0,
1267         .clkr = {
1268                 .enable_reg = 0x2aec,
1269                 .enable_mask = BIT(9),
1270                 .hw.init = &(struct clk_init_data){
1271                         .name = "gsbi10_qup_clk",
1272                         .parent_names = (const char *[]){ "gsbi10_qup_src" },
1273                         .num_parents = 1,
1274                         .ops = &clk_branch_ops,
1275                         .flags = CLK_SET_RATE_PARENT,
1276                 },
1277         },
1278 };
1279
1280 static struct clk_rcg gsbi11_qup_src = {
1281         .ns_reg = 0x2b0c,
1282         .md_reg = 0x2b08,
1283         .mn = {
1284                 .mnctr_en_bit = 8,
1285                 .mnctr_reset_bit = 7,
1286                 .mnctr_mode_shift = 5,
1287                 .n_val_shift = 16,
1288                 .m_val_shift = 16,
1289                 .width = 8,
1290         },
1291         .p = {
1292                 .pre_div_shift = 3,
1293                 .pre_div_width = 2,
1294         },
1295         .s = {
1296                 .src_sel_shift = 0,
1297                 .parent_map = gcc_pxo_pll8_map,
1298         },
1299         .freq_tbl = clk_tbl_gsbi_qup,
1300         .clkr = {
1301                 .enable_reg = 0x2b0c,
1302                 .enable_mask = BIT(11),
1303                 .hw.init = &(struct clk_init_data){
1304                         .name = "gsbi11_qup_src",
1305                         .parent_names = gcc_pxo_pll8,
1306                         .num_parents = 2,
1307                         .ops = &clk_rcg_ops,
1308                         .flags = CLK_SET_PARENT_GATE,
1309                 },
1310         },
1311 };
1312
1313 static struct clk_branch gsbi11_qup_clk = {
1314         .halt_reg = 0x2fd4,
1315         .halt_bit = 15,
1316         .clkr = {
1317                 .enable_reg = 0x2b0c,
1318                 .enable_mask = BIT(9),
1319                 .hw.init = &(struct clk_init_data){
1320                         .name = "gsbi11_qup_clk",
1321                         .parent_names = (const char *[]){ "gsbi11_qup_src" },
1322                         .num_parents = 1,
1323                         .ops = &clk_branch_ops,
1324                         .flags = CLK_SET_RATE_PARENT,
1325                 },
1326         },
1327 };
1328
1329 static struct clk_rcg gsbi12_qup_src = {
1330         .ns_reg = 0x2b2c,
1331         .md_reg = 0x2b28,
1332         .mn = {
1333                 .mnctr_en_bit = 8,
1334                 .mnctr_reset_bit = 7,
1335                 .mnctr_mode_shift = 5,
1336                 .n_val_shift = 16,
1337                 .m_val_shift = 16,
1338                 .width = 8,
1339         },
1340         .p = {
1341                 .pre_div_shift = 3,
1342                 .pre_div_width = 2,
1343         },
1344         .s = {
1345                 .src_sel_shift = 0,
1346                 .parent_map = gcc_pxo_pll8_map,
1347         },
1348         .freq_tbl = clk_tbl_gsbi_qup,
1349         .clkr = {
1350                 .enable_reg = 0x2b2c,
1351                 .enable_mask = BIT(11),
1352                 .hw.init = &(struct clk_init_data){
1353                         .name = "gsbi12_qup_src",
1354                         .parent_names = gcc_pxo_pll8,
1355                         .num_parents = 2,
1356                         .ops = &clk_rcg_ops,
1357                         .flags = CLK_SET_PARENT_GATE,
1358                 },
1359         },
1360 };
1361
1362 static struct clk_branch gsbi12_qup_clk = {
1363         .halt_reg = 0x2fd4,
1364         .halt_bit = 11,
1365         .clkr = {
1366                 .enable_reg = 0x2b2c,
1367                 .enable_mask = BIT(9),
1368                 .hw.init = &(struct clk_init_data){
1369                         .name = "gsbi12_qup_clk",
1370                         .parent_names = (const char *[]){ "gsbi12_qup_src" },
1371                         .num_parents = 1,
1372                         .ops = &clk_branch_ops,
1373                         .flags = CLK_SET_RATE_PARENT,
1374                 },
1375         },
1376 };
1377
1378 static const struct freq_tbl clk_tbl_gp[] = {
1379         { 9600000, P_CXO,  2, 0, 0 },
1380         { 13500000, P_PXO,  2, 0, 0 },
1381         { 19200000, P_CXO,  1, 0, 0 },
1382         { 27000000, P_PXO,  1, 0, 0 },
1383         { 64000000, P_PLL8, 2, 1, 3 },
1384         { 76800000, P_PLL8, 1, 1, 5 },
1385         { 96000000, P_PLL8, 4, 0, 0 },
1386         { 128000000, P_PLL8, 3, 0, 0 },
1387         { 192000000, P_PLL8, 2, 0, 0 },
1388         { }
1389 };
1390
1391 static struct clk_rcg gp0_src = {
1392         .ns_reg = 0x2d24,
1393         .md_reg = 0x2d00,
1394         .mn = {
1395                 .mnctr_en_bit = 8,
1396                 .mnctr_reset_bit = 7,
1397                 .mnctr_mode_shift = 5,
1398                 .n_val_shift = 16,
1399                 .m_val_shift = 16,
1400                 .width = 8,
1401         },
1402         .p = {
1403                 .pre_div_shift = 3,
1404                 .pre_div_width = 2,
1405         },
1406         .s = {
1407                 .src_sel_shift = 0,
1408                 .parent_map = gcc_pxo_pll8_cxo_map,
1409         },
1410         .freq_tbl = clk_tbl_gp,
1411         .clkr = {
1412                 .enable_reg = 0x2d24,
1413                 .enable_mask = BIT(11),
1414                 .hw.init = &(struct clk_init_data){
1415                         .name = "gp0_src",
1416                         .parent_names = gcc_pxo_pll8_cxo,
1417                         .num_parents = 3,
1418                         .ops = &clk_rcg_ops,
1419                         .flags = CLK_SET_PARENT_GATE,
1420                 },
1421         }
1422 };
1423
1424 static struct clk_branch gp0_clk = {
1425         .halt_reg = 0x2fd8,
1426         .halt_bit = 7,
1427         .clkr = {
1428                 .enable_reg = 0x2d24,
1429                 .enable_mask = BIT(9),
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "gp0_clk",
1432                         .parent_names = (const char *[]){ "gp0_src" },
1433                         .num_parents = 1,
1434                         .ops = &clk_branch_ops,
1435                         .flags = CLK_SET_RATE_PARENT,
1436                 },
1437         },
1438 };
1439
1440 static struct clk_rcg gp1_src = {
1441         .ns_reg = 0x2d44,
1442         .md_reg = 0x2d40,
1443         .mn = {
1444                 .mnctr_en_bit = 8,
1445                 .mnctr_reset_bit = 7,
1446                 .mnctr_mode_shift = 5,
1447                 .n_val_shift = 16,
1448                 .m_val_shift = 16,
1449                 .width = 8,
1450         },
1451         .p = {
1452                 .pre_div_shift = 3,
1453                 .pre_div_width = 2,
1454         },
1455         .s = {
1456                 .src_sel_shift = 0,
1457                 .parent_map = gcc_pxo_pll8_cxo_map,
1458         },
1459         .freq_tbl = clk_tbl_gp,
1460         .clkr = {
1461                 .enable_reg = 0x2d44,
1462                 .enable_mask = BIT(11),
1463                 .hw.init = &(struct clk_init_data){
1464                         .name = "gp1_src",
1465                         .parent_names = gcc_pxo_pll8_cxo,
1466                         .num_parents = 3,
1467                         .ops = &clk_rcg_ops,
1468                         .flags = CLK_SET_RATE_GATE,
1469                 },
1470         }
1471 };
1472
1473 static struct clk_branch gp1_clk = {
1474         .halt_reg = 0x2fd8,
1475         .halt_bit = 6,
1476         .clkr = {
1477                 .enable_reg = 0x2d44,
1478                 .enable_mask = BIT(9),
1479                 .hw.init = &(struct clk_init_data){
1480                         .name = "gp1_clk",
1481                         .parent_names = (const char *[]){ "gp1_src" },
1482                         .num_parents = 1,
1483                         .ops = &clk_branch_ops,
1484                         .flags = CLK_SET_RATE_PARENT,
1485                 },
1486         },
1487 };
1488
1489 static struct clk_rcg gp2_src = {
1490         .ns_reg = 0x2d64,
1491         .md_reg = 0x2d60,
1492         .mn = {
1493                 .mnctr_en_bit = 8,
1494                 .mnctr_reset_bit = 7,
1495                 .mnctr_mode_shift = 5,
1496                 .n_val_shift = 16,
1497                 .m_val_shift = 16,
1498                 .width = 8,
1499         },
1500         .p = {
1501                 .pre_div_shift = 3,
1502                 .pre_div_width = 2,
1503         },
1504         .s = {
1505                 .src_sel_shift = 0,
1506                 .parent_map = gcc_pxo_pll8_cxo_map,
1507         },
1508         .freq_tbl = clk_tbl_gp,
1509         .clkr = {
1510                 .enable_reg = 0x2d64,
1511                 .enable_mask = BIT(11),
1512                 .hw.init = &(struct clk_init_data){
1513                         .name = "gp2_src",
1514                         .parent_names = gcc_pxo_pll8_cxo,
1515                         .num_parents = 3,
1516                         .ops = &clk_rcg_ops,
1517                         .flags = CLK_SET_RATE_GATE,
1518                 },
1519         }
1520 };
1521
1522 static struct clk_branch gp2_clk = {
1523         .halt_reg = 0x2fd8,
1524         .halt_bit = 5,
1525         .clkr = {
1526                 .enable_reg = 0x2d64,
1527                 .enable_mask = BIT(9),
1528                 .hw.init = &(struct clk_init_data){
1529                         .name = "gp2_clk",
1530                         .parent_names = (const char *[]){ "gp2_src" },
1531                         .num_parents = 1,
1532                         .ops = &clk_branch_ops,
1533                         .flags = CLK_SET_RATE_PARENT,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch pmem_clk = {
1539         .hwcg_reg = 0x25a0,
1540         .hwcg_bit = 6,
1541         .halt_reg = 0x2fc8,
1542         .halt_bit = 20,
1543         .clkr = {
1544                 .enable_reg = 0x25a0,
1545                 .enable_mask = BIT(4),
1546                 .hw.init = &(struct clk_init_data){
1547                         .name = "pmem_clk",
1548                         .ops = &clk_branch_ops,
1549                 },
1550         },
1551 };
1552
1553 static struct clk_rcg prng_src = {
1554         .ns_reg = 0x2e80,
1555         .p = {
1556                 .pre_div_shift = 3,
1557                 .pre_div_width = 4,
1558         },
1559         .s = {
1560                 .src_sel_shift = 0,
1561                 .parent_map = gcc_pxo_pll8_map,
1562         },
1563         .clkr = {
1564                 .hw.init = &(struct clk_init_data){
1565                         .name = "prng_src",
1566                         .parent_names = gcc_pxo_pll8,
1567                         .num_parents = 2,
1568                         .ops = &clk_rcg_ops,
1569                 },
1570         },
1571 };
1572
1573 static struct clk_branch prng_clk = {
1574         .halt_reg = 0x2fd8,
1575         .halt_check = BRANCH_HALT_VOTED,
1576         .halt_bit = 10,
1577         .clkr = {
1578                 .enable_reg = 0x3080,
1579                 .enable_mask = BIT(10),
1580                 .hw.init = &(struct clk_init_data){
1581                         .name = "prng_clk",
1582                         .parent_names = (const char *[]){ "prng_src" },
1583                         .num_parents = 1,
1584                         .ops = &clk_branch_ops,
1585                 },
1586         },
1587 };
1588
1589 static const struct freq_tbl clk_tbl_sdc[] = {
1590         {    144000, P_PXO,   3, 2, 125 },
1591         {    400000, P_PLL8,  4, 1, 240 },
1592         {  16000000, P_PLL8,  4, 1,   6 },
1593         {  17070000, P_PLL8,  1, 2,  45 },
1594         {  20210000, P_PLL8,  1, 1,  19 },
1595         {  24000000, P_PLL8,  4, 1,   4 },
1596         {  48000000, P_PLL8,  4, 1,   2 },
1597         {  64000000, P_PLL8,  3, 1,   2 },
1598         {  96000000, P_PLL8,  4, 0,   0 },
1599         { 192000000, P_PLL8,  2, 0,   0 },
1600         { }
1601 };
1602
1603 static struct clk_rcg sdc1_src = {
1604         .ns_reg = 0x282c,
1605         .md_reg = 0x2828,
1606         .mn = {
1607                 .mnctr_en_bit = 8,
1608                 .mnctr_reset_bit = 7,
1609                 .mnctr_mode_shift = 5,
1610                 .n_val_shift = 16,
1611                 .m_val_shift = 16,
1612                 .width = 8,
1613         },
1614         .p = {
1615                 .pre_div_shift = 3,
1616                 .pre_div_width = 2,
1617         },
1618         .s = {
1619                 .src_sel_shift = 0,
1620                 .parent_map = gcc_pxo_pll8_map,
1621         },
1622         .freq_tbl = clk_tbl_sdc,
1623         .clkr = {
1624                 .enable_reg = 0x282c,
1625                 .enable_mask = BIT(11),
1626                 .hw.init = &(struct clk_init_data){
1627                         .name = "sdc1_src",
1628                         .parent_names = gcc_pxo_pll8,
1629                         .num_parents = 2,
1630                         .ops = &clk_rcg_ops,
1631                 },
1632         }
1633 };
1634
1635 static struct clk_branch sdc1_clk = {
1636         .halt_reg = 0x2fc8,
1637         .halt_bit = 6,
1638         .clkr = {
1639                 .enable_reg = 0x282c,
1640                 .enable_mask = BIT(9),
1641                 .hw.init = &(struct clk_init_data){
1642                         .name = "sdc1_clk",
1643                         .parent_names = (const char *[]){ "sdc1_src" },
1644                         .num_parents = 1,
1645                         .ops = &clk_branch_ops,
1646                         .flags = CLK_SET_RATE_PARENT,
1647                 },
1648         },
1649 };
1650
1651 static struct clk_rcg sdc2_src = {
1652         .ns_reg = 0x284c,
1653         .md_reg = 0x2848,
1654         .mn = {
1655                 .mnctr_en_bit = 8,
1656                 .mnctr_reset_bit = 7,
1657                 .mnctr_mode_shift = 5,
1658                 .n_val_shift = 16,
1659                 .m_val_shift = 16,
1660                 .width = 8,
1661         },
1662         .p = {
1663                 .pre_div_shift = 3,
1664                 .pre_div_width = 2,
1665         },
1666         .s = {
1667                 .src_sel_shift = 0,
1668                 .parent_map = gcc_pxo_pll8_map,
1669         },
1670         .freq_tbl = clk_tbl_sdc,
1671         .clkr = {
1672                 .enable_reg = 0x284c,
1673                 .enable_mask = BIT(11),
1674                 .hw.init = &(struct clk_init_data){
1675                         .name = "sdc2_src",
1676                         .parent_names = gcc_pxo_pll8,
1677                         .num_parents = 2,
1678                         .ops = &clk_rcg_ops,
1679                 },
1680         }
1681 };
1682
1683 static struct clk_branch sdc2_clk = {
1684         .halt_reg = 0x2fc8,
1685         .halt_bit = 5,
1686         .clkr = {
1687                 .enable_reg = 0x284c,
1688                 .enable_mask = BIT(9),
1689                 .hw.init = &(struct clk_init_data){
1690                         .name = "sdc2_clk",
1691                         .parent_names = (const char *[]){ "sdc2_src" },
1692                         .num_parents = 1,
1693                         .ops = &clk_branch_ops,
1694                         .flags = CLK_SET_RATE_PARENT,
1695                 },
1696         },
1697 };
1698
1699 static struct clk_rcg sdc3_src = {
1700         .ns_reg = 0x286c,
1701         .md_reg = 0x2868,
1702         .mn = {
1703                 .mnctr_en_bit = 8,
1704                 .mnctr_reset_bit = 7,
1705                 .mnctr_mode_shift = 5,
1706                 .n_val_shift = 16,
1707                 .m_val_shift = 16,
1708                 .width = 8,
1709         },
1710         .p = {
1711                 .pre_div_shift = 3,
1712                 .pre_div_width = 2,
1713         },
1714         .s = {
1715                 .src_sel_shift = 0,
1716                 .parent_map = gcc_pxo_pll8_map,
1717         },
1718         .freq_tbl = clk_tbl_sdc,
1719         .clkr = {
1720                 .enable_reg = 0x286c,
1721                 .enable_mask = BIT(11),
1722                 .hw.init = &(struct clk_init_data){
1723                         .name = "sdc3_src",
1724                         .parent_names = gcc_pxo_pll8,
1725                         .num_parents = 2,
1726                         .ops = &clk_rcg_ops,
1727                 },
1728         }
1729 };
1730
1731 static struct clk_branch sdc3_clk = {
1732         .halt_reg = 0x2fc8,
1733         .halt_bit = 4,
1734         .clkr = {
1735                 .enable_reg = 0x286c,
1736                 .enable_mask = BIT(9),
1737                 .hw.init = &(struct clk_init_data){
1738                         .name = "sdc3_clk",
1739                         .parent_names = (const char *[]){ "sdc3_src" },
1740                         .num_parents = 1,
1741                         .ops = &clk_branch_ops,
1742                         .flags = CLK_SET_RATE_PARENT,
1743                 },
1744         },
1745 };
1746
1747 static struct clk_rcg sdc4_src = {
1748         .ns_reg = 0x288c,
1749         .md_reg = 0x2888,
1750         .mn = {
1751                 .mnctr_en_bit = 8,
1752                 .mnctr_reset_bit = 7,
1753                 .mnctr_mode_shift = 5,
1754                 .n_val_shift = 16,
1755                 .m_val_shift = 16,
1756                 .width = 8,
1757         },
1758         .p = {
1759                 .pre_div_shift = 3,
1760                 .pre_div_width = 2,
1761         },
1762         .s = {
1763                 .src_sel_shift = 0,
1764                 .parent_map = gcc_pxo_pll8_map,
1765         },
1766         .freq_tbl = clk_tbl_sdc,
1767         .clkr = {
1768                 .enable_reg = 0x288c,
1769                 .enable_mask = BIT(11),
1770                 .hw.init = &(struct clk_init_data){
1771                         .name = "sdc4_src",
1772                         .parent_names = gcc_pxo_pll8,
1773                         .num_parents = 2,
1774                         .ops = &clk_rcg_ops,
1775                 },
1776         }
1777 };
1778
1779 static struct clk_branch sdc4_clk = {
1780         .halt_reg = 0x2fc8,
1781         .halt_bit = 3,
1782         .clkr = {
1783                 .enable_reg = 0x288c,
1784                 .enable_mask = BIT(9),
1785                 .hw.init = &(struct clk_init_data){
1786                         .name = "sdc4_clk",
1787                         .parent_names = (const char *[]){ "sdc4_src" },
1788                         .num_parents = 1,
1789                         .ops = &clk_branch_ops,
1790                         .flags = CLK_SET_RATE_PARENT,
1791                 },
1792         },
1793 };
1794
1795 static struct clk_rcg sdc5_src = {
1796         .ns_reg = 0x28ac,
1797         .md_reg = 0x28a8,
1798         .mn = {
1799                 .mnctr_en_bit = 8,
1800                 .mnctr_reset_bit = 7,
1801                 .mnctr_mode_shift = 5,
1802                 .n_val_shift = 16,
1803                 .m_val_shift = 16,
1804                 .width = 8,
1805         },
1806         .p = {
1807                 .pre_div_shift = 3,
1808                 .pre_div_width = 2,
1809         },
1810         .s = {
1811                 .src_sel_shift = 0,
1812                 .parent_map = gcc_pxo_pll8_map,
1813         },
1814         .freq_tbl = clk_tbl_sdc,
1815         .clkr = {
1816                 .enable_reg = 0x28ac,
1817                 .enable_mask = BIT(11),
1818                 .hw.init = &(struct clk_init_data){
1819                         .name = "sdc5_src",
1820                         .parent_names = gcc_pxo_pll8,
1821                         .num_parents = 2,
1822                         .ops = &clk_rcg_ops,
1823                 },
1824         }
1825 };
1826
1827 static struct clk_branch sdc5_clk = {
1828         .halt_reg = 0x2fc8,
1829         .halt_bit = 2,
1830         .clkr = {
1831                 .enable_reg = 0x28ac,
1832                 .enable_mask = BIT(9),
1833                 .hw.init = &(struct clk_init_data){
1834                         .name = "sdc5_clk",
1835                         .parent_names = (const char *[]){ "sdc5_src" },
1836                         .num_parents = 1,
1837                         .ops = &clk_branch_ops,
1838                         .flags = CLK_SET_RATE_PARENT,
1839                 },
1840         },
1841 };
1842
1843 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1844         { 105000, P_PXO,  1, 1, 256 },
1845         { }
1846 };
1847
1848 static struct clk_rcg tsif_ref_src = {
1849         .ns_reg = 0x2710,
1850         .md_reg = 0x270c,
1851         .mn = {
1852                 .mnctr_en_bit = 8,
1853                 .mnctr_reset_bit = 7,
1854                 .mnctr_mode_shift = 5,
1855                 .n_val_shift = 16,
1856                 .m_val_shift = 16,
1857                 .width = 16,
1858         },
1859         .p = {
1860                 .pre_div_shift = 3,
1861                 .pre_div_width = 2,
1862         },
1863         .s = {
1864                 .src_sel_shift = 0,
1865                 .parent_map = gcc_pxo_pll8_map,
1866         },
1867         .freq_tbl = clk_tbl_tsif_ref,
1868         .clkr = {
1869                 .enable_reg = 0x2710,
1870                 .enable_mask = BIT(11),
1871                 .hw.init = &(struct clk_init_data){
1872                         .name = "tsif_ref_src",
1873                         .parent_names = gcc_pxo_pll8,
1874                         .num_parents = 2,
1875                         .ops = &clk_rcg_ops,
1876                         .flags = CLK_SET_RATE_GATE,
1877                 },
1878         }
1879 };
1880
1881 static struct clk_branch tsif_ref_clk = {
1882         .halt_reg = 0x2fd4,
1883         .halt_bit = 5,
1884         .clkr = {
1885                 .enable_reg = 0x2710,
1886                 .enable_mask = BIT(9),
1887                 .hw.init = &(struct clk_init_data){
1888                         .name = "tsif_ref_clk",
1889                         .parent_names = (const char *[]){ "tsif_ref_src" },
1890                         .num_parents = 1,
1891                         .ops = &clk_branch_ops,
1892                         .flags = CLK_SET_RATE_PARENT,
1893                 },
1894         },
1895 };
1896
1897 static const struct freq_tbl clk_tbl_usb[] = {
1898         { 60000000, P_PLL8, 1, 5, 32 },
1899         { }
1900 };
1901
1902 static struct clk_rcg usb_hs1_xcvr_src = {
1903         .ns_reg = 0x290c,
1904         .md_reg = 0x2908,
1905         .mn = {
1906                 .mnctr_en_bit = 8,
1907                 .mnctr_reset_bit = 7,
1908                 .mnctr_mode_shift = 5,
1909                 .n_val_shift = 16,
1910                 .m_val_shift = 16,
1911                 .width = 8,
1912         },
1913         .p = {
1914                 .pre_div_shift = 3,
1915                 .pre_div_width = 2,
1916         },
1917         .s = {
1918                 .src_sel_shift = 0,
1919                 .parent_map = gcc_pxo_pll8_map,
1920         },
1921         .freq_tbl = clk_tbl_usb,
1922         .clkr = {
1923                 .enable_reg = 0x290c,
1924                 .enable_mask = BIT(11),
1925                 .hw.init = &(struct clk_init_data){
1926                         .name = "usb_hs1_xcvr_src",
1927                         .parent_names = gcc_pxo_pll8,
1928                         .num_parents = 2,
1929                         .ops = &clk_rcg_ops,
1930                         .flags = CLK_SET_RATE_GATE,
1931                 },
1932         }
1933 };
1934
1935 static struct clk_branch usb_hs1_xcvr_clk = {
1936         .halt_reg = 0x2fc8,
1937         .halt_bit = 0,
1938         .clkr = {
1939                 .enable_reg = 0x290c,
1940                 .enable_mask = BIT(9),
1941                 .hw.init = &(struct clk_init_data){
1942                         .name = "usb_hs1_xcvr_clk",
1943                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1944                         .num_parents = 1,
1945                         .ops = &clk_branch_ops,
1946                         .flags = CLK_SET_RATE_PARENT,
1947                 },
1948         },
1949 };
1950
1951 static struct clk_rcg usb_hs3_xcvr_src = {
1952         .ns_reg = 0x370c,
1953         .md_reg = 0x3708,
1954         .mn = {
1955                 .mnctr_en_bit = 8,
1956                 .mnctr_reset_bit = 7,
1957                 .mnctr_mode_shift = 5,
1958                 .n_val_shift = 16,
1959                 .m_val_shift = 16,
1960                 .width = 8,
1961         },
1962         .p = {
1963                 .pre_div_shift = 3,
1964                 .pre_div_width = 2,
1965         },
1966         .s = {
1967                 .src_sel_shift = 0,
1968                 .parent_map = gcc_pxo_pll8_map,
1969         },
1970         .freq_tbl = clk_tbl_usb,
1971         .clkr = {
1972                 .enable_reg = 0x370c,
1973                 .enable_mask = BIT(11),
1974                 .hw.init = &(struct clk_init_data){
1975                         .name = "usb_hs3_xcvr_src",
1976                         .parent_names = gcc_pxo_pll8,
1977                         .num_parents = 2,
1978                         .ops = &clk_rcg_ops,
1979                         .flags = CLK_SET_RATE_GATE,
1980                 },
1981         }
1982 };
1983
1984 static struct clk_branch usb_hs3_xcvr_clk = {
1985         .halt_reg = 0x2fc8,
1986         .halt_bit = 30,
1987         .clkr = {
1988                 .enable_reg = 0x370c,
1989                 .enable_mask = BIT(9),
1990                 .hw.init = &(struct clk_init_data){
1991                         .name = "usb_hs3_xcvr_clk",
1992                         .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
1993                         .num_parents = 1,
1994                         .ops = &clk_branch_ops,
1995                         .flags = CLK_SET_RATE_PARENT,
1996                 },
1997         },
1998 };
1999
2000 static struct clk_rcg usb_hs4_xcvr_src = {
2001         .ns_reg = 0x372c,
2002         .md_reg = 0x3728,
2003         .mn = {
2004                 .mnctr_en_bit = 8,
2005                 .mnctr_reset_bit = 7,
2006                 .mnctr_mode_shift = 5,
2007                 .n_val_shift = 16,
2008                 .m_val_shift = 16,
2009                 .width = 8,
2010         },
2011         .p = {
2012                 .pre_div_shift = 3,
2013                 .pre_div_width = 2,
2014         },
2015         .s = {
2016                 .src_sel_shift = 0,
2017                 .parent_map = gcc_pxo_pll8_map,
2018         },
2019         .freq_tbl = clk_tbl_usb,
2020         .clkr = {
2021                 .enable_reg = 0x372c,
2022                 .enable_mask = BIT(11),
2023                 .hw.init = &(struct clk_init_data){
2024                         .name = "usb_hs4_xcvr_src",
2025                         .parent_names = gcc_pxo_pll8,
2026                         .num_parents = 2,
2027                         .ops = &clk_rcg_ops,
2028                         .flags = CLK_SET_RATE_GATE,
2029                 },
2030         }
2031 };
2032
2033 static struct clk_branch usb_hs4_xcvr_clk = {
2034         .halt_reg = 0x2fc8,
2035         .halt_bit = 2,
2036         .clkr = {
2037                 .enable_reg = 0x372c,
2038                 .enable_mask = BIT(9),
2039                 .hw.init = &(struct clk_init_data){
2040                         .name = "usb_hs4_xcvr_clk",
2041                         .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2042                         .num_parents = 1,
2043                         .ops = &clk_branch_ops,
2044                         .flags = CLK_SET_RATE_PARENT,
2045                 },
2046         },
2047 };
2048
2049 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2050         .ns_reg = 0x2928,
2051         .md_reg = 0x2924,
2052         .mn = {
2053                 .mnctr_en_bit = 8,
2054                 .mnctr_reset_bit = 7,
2055                 .mnctr_mode_shift = 5,
2056                 .n_val_shift = 16,
2057                 .m_val_shift = 16,
2058                 .width = 8,
2059         },
2060         .p = {
2061                 .pre_div_shift = 3,
2062                 .pre_div_width = 2,
2063         },
2064         .s = {
2065                 .src_sel_shift = 0,
2066                 .parent_map = gcc_pxo_pll8_map,
2067         },
2068         .freq_tbl = clk_tbl_usb,
2069         .clkr = {
2070                 .enable_reg = 0x2928,
2071                 .enable_mask = BIT(11),
2072                 .hw.init = &(struct clk_init_data){
2073                         .name = "usb_hsic_xcvr_fs_src",
2074                         .parent_names = gcc_pxo_pll8,
2075                         .num_parents = 2,
2076                         .ops = &clk_rcg_ops,
2077                         .flags = CLK_SET_RATE_GATE,
2078                 },
2079         }
2080 };
2081
2082 static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
2083
2084 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2085         .halt_reg = 0x2fc8,
2086         .halt_bit = 2,
2087         .clkr = {
2088                 .enable_reg = 0x2928,
2089                 .enable_mask = BIT(9),
2090                 .hw.init = &(struct clk_init_data){
2091                         .name = "usb_hsic_xcvr_fs_clk",
2092                         .parent_names = usb_hsic_xcvr_fs_src_p,
2093                         .num_parents = 1,
2094                         .ops = &clk_branch_ops,
2095                         .flags = CLK_SET_RATE_PARENT,
2096                 },
2097         },
2098 };
2099
2100 static struct clk_branch usb_hsic_system_clk = {
2101         .halt_reg = 0x2fcc,
2102         .halt_bit = 24,
2103         .clkr = {
2104                 .enable_reg = 0x292c,
2105                 .enable_mask = BIT(4),
2106                 .hw.init = &(struct clk_init_data){
2107                         .parent_names = usb_hsic_xcvr_fs_src_p,
2108                         .num_parents = 1,
2109                         .name = "usb_hsic_system_clk",
2110                         .ops = &clk_branch_ops,
2111                         .flags = CLK_SET_RATE_PARENT,
2112                 },
2113         },
2114 };
2115
2116 static struct clk_branch usb_hsic_hsic_clk = {
2117         .halt_reg = 0x2fcc,
2118         .halt_bit = 19,
2119         .clkr = {
2120                 .enable_reg = 0x2b44,
2121                 .enable_mask = BIT(0),
2122                 .hw.init = &(struct clk_init_data){
2123                         .parent_names = (const char *[]){ "pll14_vote" },
2124                         .num_parents = 1,
2125                         .name = "usb_hsic_hsic_clk",
2126                         .ops = &clk_branch_ops,
2127                 },
2128         },
2129 };
2130
2131 static struct clk_branch usb_hsic_hsio_cal_clk = {
2132         .halt_reg = 0x2fcc,
2133         .halt_bit = 23,
2134         .clkr = {
2135                 .enable_reg = 0x2b48,
2136                 .enable_mask = BIT(0),
2137                 .hw.init = &(struct clk_init_data){
2138                         .name = "usb_hsic_hsio_cal_clk",
2139                         .ops = &clk_branch_ops,
2140                 },
2141         },
2142 };
2143
2144 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2145         .ns_reg = 0x2968,
2146         .md_reg = 0x2964,
2147         .mn = {
2148                 .mnctr_en_bit = 8,
2149                 .mnctr_reset_bit = 7,
2150                 .mnctr_mode_shift = 5,
2151                 .n_val_shift = 16,
2152                 .m_val_shift = 16,
2153                 .width = 8,
2154         },
2155         .p = {
2156                 .pre_div_shift = 3,
2157                 .pre_div_width = 2,
2158         },
2159         .s = {
2160                 .src_sel_shift = 0,
2161                 .parent_map = gcc_pxo_pll8_map,
2162         },
2163         .freq_tbl = clk_tbl_usb,
2164         .clkr = {
2165                 .enable_reg = 0x2968,
2166                 .enable_mask = BIT(11),
2167                 .hw.init = &(struct clk_init_data){
2168                         .name = "usb_fs1_xcvr_fs_src",
2169                         .parent_names = gcc_pxo_pll8,
2170                         .num_parents = 2,
2171                         .ops = &clk_rcg_ops,
2172                         .flags = CLK_SET_RATE_GATE,
2173                 },
2174         }
2175 };
2176
2177 static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2178
2179 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2180         .halt_reg = 0x2fcc,
2181         .halt_bit = 15,
2182         .clkr = {
2183                 .enable_reg = 0x2968,
2184                 .enable_mask = BIT(9),
2185                 .hw.init = &(struct clk_init_data){
2186                         .name = "usb_fs1_xcvr_fs_clk",
2187                         .parent_names = usb_fs1_xcvr_fs_src_p,
2188                         .num_parents = 1,
2189                         .ops = &clk_branch_ops,
2190                         .flags = CLK_SET_RATE_PARENT,
2191                 },
2192         },
2193 };
2194
2195 static struct clk_branch usb_fs1_system_clk = {
2196         .halt_reg = 0x2fcc,
2197         .halt_bit = 16,
2198         .clkr = {
2199                 .enable_reg = 0x296c,
2200                 .enable_mask = BIT(4),
2201                 .hw.init = &(struct clk_init_data){
2202                         .parent_names = usb_fs1_xcvr_fs_src_p,
2203                         .num_parents = 1,
2204                         .name = "usb_fs1_system_clk",
2205                         .ops = &clk_branch_ops,
2206                         .flags = CLK_SET_RATE_PARENT,
2207                 },
2208         },
2209 };
2210
2211 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2212         .ns_reg = 0x2988,
2213         .md_reg = 0x2984,
2214         .mn = {
2215                 .mnctr_en_bit = 8,
2216                 .mnctr_reset_bit = 7,
2217                 .mnctr_mode_shift = 5,
2218                 .n_val_shift = 16,
2219                 .m_val_shift = 16,
2220                 .width = 8,
2221         },
2222         .p = {
2223                 .pre_div_shift = 3,
2224                 .pre_div_width = 2,
2225         },
2226         .s = {
2227                 .src_sel_shift = 0,
2228                 .parent_map = gcc_pxo_pll8_map,
2229         },
2230         .freq_tbl = clk_tbl_usb,
2231         .clkr = {
2232                 .enable_reg = 0x2988,
2233                 .enable_mask = BIT(11),
2234                 .hw.init = &(struct clk_init_data){
2235                         .name = "usb_fs2_xcvr_fs_src",
2236                         .parent_names = gcc_pxo_pll8,
2237                         .num_parents = 2,
2238                         .ops = &clk_rcg_ops,
2239                         .flags = CLK_SET_RATE_GATE,
2240                 },
2241         }
2242 };
2243
2244 static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2245
2246 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2247         .halt_reg = 0x2fcc,
2248         .halt_bit = 12,
2249         .clkr = {
2250                 .enable_reg = 0x2988,
2251                 .enable_mask = BIT(9),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "usb_fs2_xcvr_fs_clk",
2254                         .parent_names = usb_fs2_xcvr_fs_src_p,
2255                         .num_parents = 1,
2256                         .ops = &clk_branch_ops,
2257                         .flags = CLK_SET_RATE_PARENT,
2258                 },
2259         },
2260 };
2261
2262 static struct clk_branch usb_fs2_system_clk = {
2263         .halt_reg = 0x2fcc,
2264         .halt_bit = 13,
2265         .clkr = {
2266                 .enable_reg = 0x298c,
2267                 .enable_mask = BIT(4),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "usb_fs2_system_clk",
2270                         .parent_names = usb_fs2_xcvr_fs_src_p,
2271                         .num_parents = 1,
2272                         .ops = &clk_branch_ops,
2273                         .flags = CLK_SET_RATE_PARENT,
2274                 },
2275         },
2276 };
2277
2278 static struct clk_branch ce1_core_clk = {
2279         .hwcg_reg = 0x2724,
2280         .hwcg_bit = 6,
2281         .halt_reg = 0x2fd4,
2282         .halt_bit = 27,
2283         .clkr = {
2284                 .enable_reg = 0x2724,
2285                 .enable_mask = BIT(4),
2286                 .hw.init = &(struct clk_init_data){
2287                         .name = "ce1_core_clk",
2288                         .ops = &clk_branch_ops,
2289                 },
2290         },
2291 };
2292
2293 static struct clk_branch ce1_h_clk = {
2294         .halt_reg = 0x2fd4,
2295         .halt_bit = 1,
2296         .clkr = {
2297                 .enable_reg = 0x2720,
2298                 .enable_mask = BIT(4),
2299                 .hw.init = &(struct clk_init_data){
2300                         .name = "ce1_h_clk",
2301                         .ops = &clk_branch_ops,
2302                 },
2303         },
2304 };
2305
2306 static struct clk_branch dma_bam_h_clk = {
2307         .hwcg_reg = 0x25c0,
2308         .hwcg_bit = 6,
2309         .halt_reg = 0x2fc8,
2310         .halt_bit = 12,
2311         .clkr = {
2312                 .enable_reg = 0x25c0,
2313                 .enable_mask = BIT(4),
2314                 .hw.init = &(struct clk_init_data){
2315                         .name = "dma_bam_h_clk",
2316                         .ops = &clk_branch_ops,
2317                 },
2318         },
2319 };
2320
2321 static struct clk_branch gsbi1_h_clk = {
2322         .hwcg_reg = 0x29c0,
2323         .hwcg_bit = 6,
2324         .halt_reg = 0x2fcc,
2325         .halt_bit = 11,
2326         .clkr = {
2327                 .enable_reg = 0x29c0,
2328                 .enable_mask = BIT(4),
2329                 .hw.init = &(struct clk_init_data){
2330                         .name = "gsbi1_h_clk",
2331                         .ops = &clk_branch_ops,
2332                 },
2333         },
2334 };
2335
2336 static struct clk_branch gsbi2_h_clk = {
2337         .hwcg_reg = 0x29e0,
2338         .hwcg_bit = 6,
2339         .halt_reg = 0x2fcc,
2340         .halt_bit = 7,
2341         .clkr = {
2342                 .enable_reg = 0x29e0,
2343                 .enable_mask = BIT(4),
2344                 .hw.init = &(struct clk_init_data){
2345                         .name = "gsbi2_h_clk",
2346                         .ops = &clk_branch_ops,
2347                 },
2348         },
2349 };
2350
2351 static struct clk_branch gsbi3_h_clk = {
2352         .hwcg_reg = 0x2a00,
2353         .hwcg_bit = 6,
2354         .halt_reg = 0x2fcc,
2355         .halt_bit = 3,
2356         .clkr = {
2357                 .enable_reg = 0x2a00,
2358                 .enable_mask = BIT(4),
2359                 .hw.init = &(struct clk_init_data){
2360                         .name = "gsbi3_h_clk",
2361                         .ops = &clk_branch_ops,
2362                 },
2363         },
2364 };
2365
2366 static struct clk_branch gsbi4_h_clk = {
2367         .hwcg_reg = 0x2a20,
2368         .hwcg_bit = 6,
2369         .halt_reg = 0x2fd0,
2370         .halt_bit = 27,
2371         .clkr = {
2372                 .enable_reg = 0x2a20,
2373                 .enable_mask = BIT(4),
2374                 .hw.init = &(struct clk_init_data){
2375                         .name = "gsbi4_h_clk",
2376                         .ops = &clk_branch_ops,
2377                 },
2378         },
2379 };
2380
2381 static struct clk_branch gsbi5_h_clk = {
2382         .hwcg_reg = 0x2a40,
2383         .hwcg_bit = 6,
2384         .halt_reg = 0x2fd0,
2385         .halt_bit = 23,
2386         .clkr = {
2387                 .enable_reg = 0x2a40,
2388                 .enable_mask = BIT(4),
2389                 .hw.init = &(struct clk_init_data){
2390                         .name = "gsbi5_h_clk",
2391                         .ops = &clk_branch_ops,
2392                 },
2393         },
2394 };
2395
2396 static struct clk_branch gsbi6_h_clk = {
2397         .hwcg_reg = 0x2a60,
2398         .hwcg_bit = 6,
2399         .halt_reg = 0x2fd0,
2400         .halt_bit = 19,
2401         .clkr = {
2402                 .enable_reg = 0x2a60,
2403                 .enable_mask = BIT(4),
2404                 .hw.init = &(struct clk_init_data){
2405                         .name = "gsbi6_h_clk",
2406                         .ops = &clk_branch_ops,
2407                 },
2408         },
2409 };
2410
2411 static struct clk_branch gsbi7_h_clk = {
2412         .hwcg_reg = 0x2a80,
2413         .hwcg_bit = 6,
2414         .halt_reg = 0x2fd0,
2415         .halt_bit = 15,
2416         .clkr = {
2417                 .enable_reg = 0x2a80,
2418                 .enable_mask = BIT(4),
2419                 .hw.init = &(struct clk_init_data){
2420                         .name = "gsbi7_h_clk",
2421                         .ops = &clk_branch_ops,
2422                 },
2423         },
2424 };
2425
2426 static struct clk_branch gsbi8_h_clk = {
2427         .hwcg_reg = 0x2aa0,
2428         .hwcg_bit = 6,
2429         .halt_reg = 0x2fd0,
2430         .halt_bit = 11,
2431         .clkr = {
2432                 .enable_reg = 0x2aa0,
2433                 .enable_mask = BIT(4),
2434                 .hw.init = &(struct clk_init_data){
2435                         .name = "gsbi8_h_clk",
2436                         .ops = &clk_branch_ops,
2437                 },
2438         },
2439 };
2440
2441 static struct clk_branch gsbi9_h_clk = {
2442         .hwcg_reg = 0x2ac0,
2443         .hwcg_bit = 6,
2444         .halt_reg = 0x2fd0,
2445         .halt_bit = 7,
2446         .clkr = {
2447                 .enable_reg = 0x2ac0,
2448                 .enable_mask = BIT(4),
2449                 .hw.init = &(struct clk_init_data){
2450                         .name = "gsbi9_h_clk",
2451                         .ops = &clk_branch_ops,
2452                 },
2453         },
2454 };
2455
2456 static struct clk_branch gsbi10_h_clk = {
2457         .hwcg_reg = 0x2ae0,
2458         .hwcg_bit = 6,
2459         .halt_reg = 0x2fd0,
2460         .halt_bit = 3,
2461         .clkr = {
2462                 .enable_reg = 0x2ae0,
2463                 .enable_mask = BIT(4),
2464                 .hw.init = &(struct clk_init_data){
2465                         .name = "gsbi10_h_clk",
2466                         .ops = &clk_branch_ops,
2467                 },
2468         },
2469 };
2470
2471 static struct clk_branch gsbi11_h_clk = {
2472         .hwcg_reg = 0x2b00,
2473         .hwcg_bit = 6,
2474         .halt_reg = 0x2fd4,
2475         .halt_bit = 18,
2476         .clkr = {
2477                 .enable_reg = 0x2b00,
2478                 .enable_mask = BIT(4),
2479                 .hw.init = &(struct clk_init_data){
2480                         .name = "gsbi11_h_clk",
2481                         .ops = &clk_branch_ops,
2482                 },
2483         },
2484 };
2485
2486 static struct clk_branch gsbi12_h_clk = {
2487         .hwcg_reg = 0x2b20,
2488         .hwcg_bit = 6,
2489         .halt_reg = 0x2fd4,
2490         .halt_bit = 14,
2491         .clkr = {
2492                 .enable_reg = 0x2b20,
2493                 .enable_mask = BIT(4),
2494                 .hw.init = &(struct clk_init_data){
2495                         .name = "gsbi12_h_clk",
2496                         .ops = &clk_branch_ops,
2497                 },
2498         },
2499 };
2500
2501 static struct clk_branch tsif_h_clk = {
2502         .hwcg_reg = 0x2700,
2503         .hwcg_bit = 6,
2504         .halt_reg = 0x2fd4,
2505         .halt_bit = 7,
2506         .clkr = {
2507                 .enable_reg = 0x2700,
2508                 .enable_mask = BIT(4),
2509                 .hw.init = &(struct clk_init_data){
2510                         .name = "tsif_h_clk",
2511                         .ops = &clk_branch_ops,
2512                 },
2513         },
2514 };
2515
2516 static struct clk_branch usb_fs1_h_clk = {
2517         .halt_reg = 0x2fcc,
2518         .halt_bit = 17,
2519         .clkr = {
2520                 .enable_reg = 0x2960,
2521                 .enable_mask = BIT(4),
2522                 .hw.init = &(struct clk_init_data){
2523                         .name = "usb_fs1_h_clk",
2524                         .ops = &clk_branch_ops,
2525                 },
2526         },
2527 };
2528
2529 static struct clk_branch usb_fs2_h_clk = {
2530         .halt_reg = 0x2fcc,
2531         .halt_bit = 14,
2532         .clkr = {
2533                 .enable_reg = 0x2980,
2534                 .enable_mask = BIT(4),
2535                 .hw.init = &(struct clk_init_data){
2536                         .name = "usb_fs2_h_clk",
2537                         .ops = &clk_branch_ops,
2538                 },
2539         },
2540 };
2541
2542 static struct clk_branch usb_hs1_h_clk = {
2543         .hwcg_reg = 0x2900,
2544         .hwcg_bit = 6,
2545         .halt_reg = 0x2fc8,
2546         .halt_bit = 1,
2547         .clkr = {
2548                 .enable_reg = 0x2900,
2549                 .enable_mask = BIT(4),
2550                 .hw.init = &(struct clk_init_data){
2551                         .name = "usb_hs1_h_clk",
2552                         .ops = &clk_branch_ops,
2553                 },
2554         },
2555 };
2556
2557 static struct clk_branch usb_hs3_h_clk = {
2558         .halt_reg = 0x2fc8,
2559         .halt_bit = 31,
2560         .clkr = {
2561                 .enable_reg = 0x3700,
2562                 .enable_mask = BIT(4),
2563                 .hw.init = &(struct clk_init_data){
2564                         .name = "usb_hs3_h_clk",
2565                         .ops = &clk_branch_ops,
2566                 },
2567         },
2568 };
2569
2570 static struct clk_branch usb_hs4_h_clk = {
2571         .halt_reg = 0x2fc8,
2572         .halt_bit = 7,
2573         .clkr = {
2574                 .enable_reg = 0x3720,
2575                 .enable_mask = BIT(4),
2576                 .hw.init = &(struct clk_init_data){
2577                         .name = "usb_hs4_h_clk",
2578                         .ops = &clk_branch_ops,
2579                 },
2580         },
2581 };
2582
2583 static struct clk_branch usb_hsic_h_clk = {
2584         .halt_reg = 0x2fcc,
2585         .halt_bit = 28,
2586         .clkr = {
2587                 .enable_reg = 0x2920,
2588                 .enable_mask = BIT(4),
2589                 .hw.init = &(struct clk_init_data){
2590                         .name = "usb_hsic_h_clk",
2591                         .ops = &clk_branch_ops,
2592                 },
2593         },
2594 };
2595
2596 static struct clk_branch sdc1_h_clk = {
2597         .hwcg_reg = 0x2820,
2598         .hwcg_bit = 6,
2599         .halt_reg = 0x2fc8,
2600         .halt_bit = 11,
2601         .clkr = {
2602                 .enable_reg = 0x2820,
2603                 .enable_mask = BIT(4),
2604                 .hw.init = &(struct clk_init_data){
2605                         .name = "sdc1_h_clk",
2606                         .ops = &clk_branch_ops,
2607                 },
2608         },
2609 };
2610
2611 static struct clk_branch sdc2_h_clk = {
2612         .hwcg_reg = 0x2840,
2613         .hwcg_bit = 6,
2614         .halt_reg = 0x2fc8,
2615         .halt_bit = 10,
2616         .clkr = {
2617                 .enable_reg = 0x2840,
2618                 .enable_mask = BIT(4),
2619                 .hw.init = &(struct clk_init_data){
2620                         .name = "sdc2_h_clk",
2621                         .ops = &clk_branch_ops,
2622                 },
2623         },
2624 };
2625
2626 static struct clk_branch sdc3_h_clk = {
2627         .hwcg_reg = 0x2860,
2628         .hwcg_bit = 6,
2629         .halt_reg = 0x2fc8,
2630         .halt_bit = 9,
2631         .clkr = {
2632                 .enable_reg = 0x2860,
2633                 .enable_mask = BIT(4),
2634                 .hw.init = &(struct clk_init_data){
2635                         .name = "sdc3_h_clk",
2636                         .ops = &clk_branch_ops,
2637                 },
2638         },
2639 };
2640
2641 static struct clk_branch sdc4_h_clk = {
2642         .hwcg_reg = 0x2880,
2643         .hwcg_bit = 6,
2644         .halt_reg = 0x2fc8,
2645         .halt_bit = 8,
2646         .clkr = {
2647                 .enable_reg = 0x2880,
2648                 .enable_mask = BIT(4),
2649                 .hw.init = &(struct clk_init_data){
2650                         .name = "sdc4_h_clk",
2651                         .ops = &clk_branch_ops,
2652                 },
2653         },
2654 };
2655
2656 static struct clk_branch sdc5_h_clk = {
2657         .hwcg_reg = 0x28a0,
2658         .hwcg_bit = 6,
2659         .halt_reg = 0x2fc8,
2660         .halt_bit = 7,
2661         .clkr = {
2662                 .enable_reg = 0x28a0,
2663                 .enable_mask = BIT(4),
2664                 .hw.init = &(struct clk_init_data){
2665                         .name = "sdc5_h_clk",
2666                         .ops = &clk_branch_ops,
2667                 },
2668         },
2669 };
2670
2671 static struct clk_branch adm0_clk = {
2672         .halt_reg = 0x2fdc,
2673         .halt_check = BRANCH_HALT_VOTED,
2674         .halt_bit = 14,
2675         .clkr = {
2676                 .enable_reg = 0x3080,
2677                 .enable_mask = BIT(2),
2678                 .hw.init = &(struct clk_init_data){
2679                         .name = "adm0_clk",
2680                         .ops = &clk_branch_ops,
2681                 },
2682         },
2683 };
2684
2685 static struct clk_branch adm0_pbus_clk = {
2686         .hwcg_reg = 0x2208,
2687         .hwcg_bit = 6,
2688         .halt_reg = 0x2fdc,
2689         .halt_check = BRANCH_HALT_VOTED,
2690         .halt_bit = 13,
2691         .clkr = {
2692                 .enable_reg = 0x3080,
2693                 .enable_mask = BIT(3),
2694                 .hw.init = &(struct clk_init_data){
2695                         .name = "adm0_pbus_clk",
2696                         .ops = &clk_branch_ops,
2697                 },
2698         },
2699 };
2700
2701 static struct freq_tbl clk_tbl_ce3[] = {
2702         { 48000000, P_PLL8, 8 },
2703         { 100000000, P_PLL3, 12 },
2704         { 120000000, P_PLL3, 10 },
2705         { }
2706 };
2707
2708 static struct clk_rcg ce3_src = {
2709         .ns_reg = 0x36c0,
2710         .p = {
2711                 .pre_div_shift = 3,
2712                 .pre_div_width = 4,
2713         },
2714         .s = {
2715                 .src_sel_shift = 0,
2716                 .parent_map = gcc_pxo_pll8_pll3_map,
2717         },
2718         .freq_tbl = clk_tbl_ce3,
2719         .clkr = {
2720                 .enable_reg = 0x36c0,
2721                 .enable_mask = BIT(7),
2722                 .hw.init = &(struct clk_init_data){
2723                         .name = "ce3_src",
2724                         .parent_names = gcc_pxo_pll8_pll3,
2725                         .num_parents = 3,
2726                         .ops = &clk_rcg_ops,
2727                         .flags = CLK_SET_RATE_GATE,
2728                 },
2729         },
2730 };
2731
2732 static struct clk_branch ce3_core_clk = {
2733         .halt_reg = 0x2fdc,
2734         .halt_bit = 5,
2735         .clkr = {
2736                 .enable_reg = 0x36cc,
2737                 .enable_mask = BIT(4),
2738                 .hw.init = &(struct clk_init_data){
2739                         .name = "ce3_core_clk",
2740                         .parent_names = (const char *[]){ "ce3_src" },
2741                         .num_parents = 1,
2742                         .ops = &clk_branch_ops,
2743                         .flags = CLK_SET_RATE_PARENT,
2744                 },
2745         },
2746 };
2747
2748 static struct clk_branch ce3_h_clk = {
2749         .halt_reg = 0x2fc4,
2750         .halt_bit = 16,
2751         .clkr = {
2752                 .enable_reg = 0x36c4,
2753                 .enable_mask = BIT(4),
2754                 .hw.init = &(struct clk_init_data){
2755                         .name = "ce3_h_clk",
2756                         .parent_names = (const char *[]){ "ce3_src" },
2757                         .num_parents = 1,
2758                         .ops = &clk_branch_ops,
2759                         .flags = CLK_SET_RATE_PARENT,
2760                 },
2761         },
2762 };
2763
2764 static const struct freq_tbl clk_tbl_sata_ref[] = {
2765         { 48000000, P_PLL8, 8, 0, 0 },
2766         { 100000000, P_PLL3, 12, 0, 0 },
2767         { }
2768 };
2769
2770 static struct clk_rcg sata_clk_src = {
2771         .ns_reg = 0x2c08,
2772         .p = {
2773                 .pre_div_shift = 3,
2774                 .pre_div_width = 4,
2775         },
2776         .s = {
2777                 .src_sel_shift = 0,
2778                 .parent_map = gcc_pxo_pll8_pll3_map,
2779         },
2780         .freq_tbl = clk_tbl_sata_ref,
2781         .clkr = {
2782                 .enable_reg = 0x2c08,
2783                 .enable_mask = BIT(7),
2784                 .hw.init = &(struct clk_init_data){
2785                         .name = "sata_clk_src",
2786                         .parent_names = gcc_pxo_pll8_pll3,
2787                         .num_parents = 3,
2788                         .ops = &clk_rcg_ops,
2789                         .flags = CLK_SET_RATE_GATE,
2790                 },
2791         },
2792 };
2793
2794 static struct clk_branch sata_rxoob_clk = {
2795         .halt_reg = 0x2fdc,
2796         .halt_bit = 26,
2797         .clkr = {
2798                 .enable_reg = 0x2c0c,
2799                 .enable_mask = BIT(4),
2800                 .hw.init = &(struct clk_init_data){
2801                         .name = "sata_rxoob_clk",
2802                         .parent_names = (const char *[]){ "sata_clk_src" },
2803                         .num_parents = 1,
2804                         .ops = &clk_branch_ops,
2805                         .flags = CLK_SET_RATE_PARENT,
2806                 },
2807         },
2808 };
2809
2810 static struct clk_branch sata_pmalive_clk = {
2811         .halt_reg = 0x2fdc,
2812         .halt_bit = 25,
2813         .clkr = {
2814                 .enable_reg = 0x2c10,
2815                 .enable_mask = BIT(4),
2816                 .hw.init = &(struct clk_init_data){
2817                         .name = "sata_pmalive_clk",
2818                         .parent_names = (const char *[]){ "sata_clk_src" },
2819                         .num_parents = 1,
2820                         .ops = &clk_branch_ops,
2821                         .flags = CLK_SET_RATE_PARENT,
2822                 },
2823         },
2824 };
2825
2826 static struct clk_branch sata_phy_ref_clk = {
2827         .halt_reg = 0x2fdc,
2828         .halt_bit = 24,
2829         .clkr = {
2830                 .enable_reg = 0x2c14,
2831                 .enable_mask = BIT(4),
2832                 .hw.init = &(struct clk_init_data){
2833                         .name = "sata_phy_ref_clk",
2834                         .parent_names = (const char *[]){ "pxo" },
2835                         .num_parents = 1,
2836                         .ops = &clk_branch_ops,
2837                 },
2838         },
2839 };
2840
2841 static struct clk_branch sata_a_clk = {
2842         .halt_reg = 0x2fc0,
2843         .halt_bit = 12,
2844         .clkr = {
2845                 .enable_reg = 0x2c20,
2846                 .enable_mask = BIT(4),
2847                 .hw.init = &(struct clk_init_data){
2848                         .name = "sata_a_clk",
2849                         .ops = &clk_branch_ops,
2850                 },
2851         },
2852 };
2853
2854 static struct clk_branch sata_h_clk = {
2855         .halt_reg = 0x2fdc,
2856         .halt_bit = 27,
2857         .clkr = {
2858                 .enable_reg = 0x2c00,
2859                 .enable_mask = BIT(4),
2860                 .hw.init = &(struct clk_init_data){
2861                         .name = "sata_h_clk",
2862                         .ops = &clk_branch_ops,
2863                 },
2864         },
2865 };
2866
2867 static struct clk_branch sfab_sata_s_h_clk = {
2868         .halt_reg = 0x2fc4,
2869         .halt_bit = 14,
2870         .clkr = {
2871                 .enable_reg = 0x2480,
2872                 .enable_mask = BIT(4),
2873                 .hw.init = &(struct clk_init_data){
2874                         .name = "sfab_sata_s_h_clk",
2875                         .ops = &clk_branch_ops,
2876                 },
2877         },
2878 };
2879
2880 static struct clk_branch sata_phy_cfg_clk = {
2881         .halt_reg = 0x2fcc,
2882         .halt_bit = 12,
2883         .clkr = {
2884                 .enable_reg = 0x2c40,
2885                 .enable_mask = BIT(4),
2886                 .hw.init = &(struct clk_init_data){
2887                         .name = "sata_phy_cfg_clk",
2888                         .ops = &clk_branch_ops,
2889                 },
2890         },
2891 };
2892
2893 static struct clk_branch pcie_phy_ref_clk = {
2894         .halt_reg = 0x2fdc,
2895         .halt_bit = 29,
2896         .clkr = {
2897                 .enable_reg = 0x22d0,
2898                 .enable_mask = BIT(4),
2899                 .hw.init = &(struct clk_init_data){
2900                         .name = "pcie_phy_ref_clk",
2901                         .ops = &clk_branch_ops,
2902                 },
2903         },
2904 };
2905
2906 static struct clk_branch pcie_h_clk = {
2907         .halt_reg = 0x2fd4,
2908         .halt_bit = 8,
2909         .clkr = {
2910                 .enable_reg = 0x22cc,
2911                 .enable_mask = BIT(4),
2912                 .hw.init = &(struct clk_init_data){
2913                         .name = "pcie_h_clk",
2914                         .ops = &clk_branch_ops,
2915                 },
2916         },
2917 };
2918
2919 static struct clk_branch pcie_a_clk = {
2920         .halt_reg = 0x2fc0,
2921         .halt_bit = 13,
2922         .clkr = {
2923                 .enable_reg = 0x22c0,
2924                 .enable_mask = BIT(4),
2925                 .hw.init = &(struct clk_init_data){
2926                         .name = "pcie_a_clk",
2927                         .ops = &clk_branch_ops,
2928                 },
2929         },
2930 };
2931
2932 static struct clk_branch pmic_arb0_h_clk = {
2933         .halt_reg = 0x2fd8,
2934         .halt_check = BRANCH_HALT_VOTED,
2935         .halt_bit = 22,
2936         .clkr = {
2937                 .enable_reg = 0x3080,
2938                 .enable_mask = BIT(8),
2939                 .hw.init = &(struct clk_init_data){
2940                         .name = "pmic_arb0_h_clk",
2941                         .ops = &clk_branch_ops,
2942                 },
2943         },
2944 };
2945
2946 static struct clk_branch pmic_arb1_h_clk = {
2947         .halt_reg = 0x2fd8,
2948         .halt_check = BRANCH_HALT_VOTED,
2949         .halt_bit = 21,
2950         .clkr = {
2951                 .enable_reg = 0x3080,
2952                 .enable_mask = BIT(9),
2953                 .hw.init = &(struct clk_init_data){
2954                         .name = "pmic_arb1_h_clk",
2955                         .ops = &clk_branch_ops,
2956                 },
2957         },
2958 };
2959
2960 static struct clk_branch pmic_ssbi2_clk = {
2961         .halt_reg = 0x2fd8,
2962         .halt_check = BRANCH_HALT_VOTED,
2963         .halt_bit = 23,
2964         .clkr = {
2965                 .enable_reg = 0x3080,
2966                 .enable_mask = BIT(7),
2967                 .hw.init = &(struct clk_init_data){
2968                         .name = "pmic_ssbi2_clk",
2969                         .ops = &clk_branch_ops,
2970                 },
2971         },
2972 };
2973
2974 static struct clk_branch rpm_msg_ram_h_clk = {
2975         .hwcg_reg = 0x27e0,
2976         .hwcg_bit = 6,
2977         .halt_reg = 0x2fd8,
2978         .halt_check = BRANCH_HALT_VOTED,
2979         .halt_bit = 12,
2980         .clkr = {
2981                 .enable_reg = 0x3080,
2982                 .enable_mask = BIT(6),
2983                 .hw.init = &(struct clk_init_data){
2984                         .name = "rpm_msg_ram_h_clk",
2985                         .ops = &clk_branch_ops,
2986                 },
2987         },
2988 };
2989
2990 static struct clk_regmap *gcc_msm8960_clks[] = {
2991         [PLL3] = &pll3.clkr,
2992         [PLL4_VOTE] = &pll4_vote,
2993         [PLL8] = &pll8.clkr,
2994         [PLL8_VOTE] = &pll8_vote,
2995         [PLL14] = &pll14.clkr,
2996         [PLL14_VOTE] = &pll14_vote,
2997         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2998         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2999         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3000         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3001         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3002         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3003         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3004         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3005         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3006         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3007         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3008         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3009         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3010         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3011         [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3012         [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3013         [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3014         [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3015         [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3016         [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3017         [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3018         [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3019         [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3020         [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3021         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3022         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3023         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3024         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3025         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3026         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3027         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3028         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3029         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3030         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3031         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3032         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3033         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3034         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3035         [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3036         [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3037         [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3038         [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3039         [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3040         [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3041         [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3042         [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3043         [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3044         [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3045         [GP0_SRC] = &gp0_src.clkr,
3046         [GP0_CLK] = &gp0_clk.clkr,
3047         [GP1_SRC] = &gp1_src.clkr,
3048         [GP1_CLK] = &gp1_clk.clkr,
3049         [GP2_SRC] = &gp2_src.clkr,
3050         [GP2_CLK] = &gp2_clk.clkr,
3051         [PMEM_A_CLK] = &pmem_clk.clkr,
3052         [PRNG_SRC] = &prng_src.clkr,
3053         [PRNG_CLK] = &prng_clk.clkr,
3054         [SDC1_SRC] = &sdc1_src.clkr,
3055         [SDC1_CLK] = &sdc1_clk.clkr,
3056         [SDC2_SRC] = &sdc2_src.clkr,
3057         [SDC2_CLK] = &sdc2_clk.clkr,
3058         [SDC3_SRC] = &sdc3_src.clkr,
3059         [SDC3_CLK] = &sdc3_clk.clkr,
3060         [SDC4_SRC] = &sdc4_src.clkr,
3061         [SDC4_CLK] = &sdc4_clk.clkr,
3062         [SDC5_SRC] = &sdc5_src.clkr,
3063         [SDC5_CLK] = &sdc5_clk.clkr,
3064         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3065         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3066         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3067         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3068         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3069         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3070         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3071         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3072         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3073         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3074         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3075         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3076         [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3077         [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3078         [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3079         [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3080         [CE1_H_CLK] = &ce1_h_clk.clkr,
3081         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3082         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3083         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3084         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3085         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3086         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3087         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3088         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3089         [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3090         [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3091         [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3092         [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3093         [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3094         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3095         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3096         [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3097         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3098         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3099         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3100         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3101         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3102         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3103         [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3104         [ADM0_CLK] = &adm0_clk.clkr,
3105         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3106         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3107         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3108         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3109         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3110 };
3111
3112 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3113         [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3114         [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3115         [QDSS_STM_RESET] = { 0x2060, 6 },
3116         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3117         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3118         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3119         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3120         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3121         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3122         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3123         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3124         [ADM0_C2_RESET] = { 0x220c, 4},
3125         [ADM0_C1_RESET] = { 0x220c, 3},
3126         [ADM0_C0_RESET] = { 0x220c, 2},
3127         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3128         [ADM0_RESET] = { 0x220c },
3129         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3130         [QDSS_POR_RESET] = { 0x2260, 4 },
3131         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3132         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3133         [QDSS_AXI_RESET] = { 0x2260, 1 },
3134         [QDSS_DBG_RESET] = { 0x2260 },
3135         [PCIE_A_RESET] = { 0x22c0, 7 },
3136         [PCIE_AUX_RESET] = { 0x22c8, 7 },
3137         [PCIE_H_RESET] = { 0x22d0, 7 },
3138         [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3139         [SFAB_PCIE_S_RESET] = { 0x22d4 },
3140         [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3141         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3142         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3143         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3144         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3145         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3146         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3147         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3148         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3149         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3150         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3151         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3152         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3153         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3154         [PPSS_PROC_RESET] = { 0x2594, 1 },
3155         [PPSS_RESET] = { 0x2594},
3156         [DMA_BAM_RESET] = { 0x25c0, 7 },
3157         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3158         [SLIMBUS_H_RESET] = { 0x2620, 7 },
3159         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3160         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3161         [TSIF_H_RESET] = { 0x2700, 7 },
3162         [CE1_H_RESET] = { 0x2720, 7 },
3163         [CE1_CORE_RESET] = { 0x2724, 7 },
3164         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3165         [CE2_H_RESET] = { 0x2740, 7 },
3166         [CE2_CORE_RESET] = { 0x2744, 7 },
3167         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3168         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3169         [RPM_PROC_RESET] = { 0x27c0, 7 },
3170         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3171         [SDC1_RESET] = { 0x2830 },
3172         [SDC2_RESET] = { 0x2850 },
3173         [SDC3_RESET] = { 0x2870 },
3174         [SDC4_RESET] = { 0x2890 },
3175         [SDC5_RESET] = { 0x28b0 },
3176         [DFAB_A2_RESET] = { 0x28c0, 7 },
3177         [USB_HS1_RESET] = { 0x2910 },
3178         [USB_HSIC_RESET] = { 0x2934 },
3179         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3180         [USB_FS1_RESET] = { 0x2974 },
3181         [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3182         [USB_FS2_RESET] = { 0x2994 },
3183         [GSBI1_RESET] = { 0x29dc },
3184         [GSBI2_RESET] = { 0x29fc },
3185         [GSBI3_RESET] = { 0x2a1c },
3186         [GSBI4_RESET] = { 0x2a3c },
3187         [GSBI5_RESET] = { 0x2a5c },
3188         [GSBI6_RESET] = { 0x2a7c },
3189         [GSBI7_RESET] = { 0x2a9c },
3190         [GSBI8_RESET] = { 0x2abc },
3191         [GSBI9_RESET] = { 0x2adc },
3192         [GSBI10_RESET] = { 0x2afc },
3193         [GSBI11_RESET] = { 0x2b1c },
3194         [GSBI12_RESET] = { 0x2b3c },
3195         [SPDM_RESET] = { 0x2b6c },
3196         [TLMM_H_RESET] = { 0x2ba0, 7 },
3197         [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3198         [MSS_SLP_RESET] = { 0x2c60, 7 },
3199         [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3200         [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3201         [MSS_RESET] = { 0x2c64 },
3202         [SATA_H_RESET] = { 0x2c80, 7 },
3203         [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3204         [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3205         [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3206         [TSSC_RESET] = { 0x2ca0, 7 },
3207         [PDM_RESET] = { 0x2cc0, 12 },
3208         [MPM_H_RESET] = { 0x2da0, 7 },
3209         [MPM_RESET] = { 0x2da4 },
3210         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3211         [PRNG_RESET] = { 0x2e80, 12 },
3212         [RIVA_RESET] = { 0x35e0 },
3213 };
3214
3215 static struct clk_regmap *gcc_apq8064_clks[] = {
3216         [PLL3] = &pll3.clkr,
3217         [PLL4_VOTE] = &pll4_vote,
3218         [PLL8] = &pll8.clkr,
3219         [PLL8_VOTE] = &pll8_vote,
3220         [PLL14] = &pll14.clkr,
3221         [PLL14_VOTE] = &pll14_vote,
3222         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3223         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3224         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3225         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3226         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3227         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3228         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3229         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3230         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3231         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3232         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3233         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3234         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3235         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3236         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3237         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3238         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3239         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3240         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3241         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3242         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3243         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3244         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3245         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3246         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3247         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3248         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3249         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3250         [GP0_SRC] = &gp0_src.clkr,
3251         [GP0_CLK] = &gp0_clk.clkr,
3252         [GP1_SRC] = &gp1_src.clkr,
3253         [GP1_CLK] = &gp1_clk.clkr,
3254         [GP2_SRC] = &gp2_src.clkr,
3255         [GP2_CLK] = &gp2_clk.clkr,
3256         [PMEM_A_CLK] = &pmem_clk.clkr,
3257         [PRNG_SRC] = &prng_src.clkr,
3258         [PRNG_CLK] = &prng_clk.clkr,
3259         [SDC1_SRC] = &sdc1_src.clkr,
3260         [SDC1_CLK] = &sdc1_clk.clkr,
3261         [SDC2_SRC] = &sdc2_src.clkr,
3262         [SDC2_CLK] = &sdc2_clk.clkr,
3263         [SDC3_SRC] = &sdc3_src.clkr,
3264         [SDC3_CLK] = &sdc3_clk.clkr,
3265         [SDC4_SRC] = &sdc4_src.clkr,
3266         [SDC4_CLK] = &sdc4_clk.clkr,
3267         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3268         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3269         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3270         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3271         [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3272         [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3273         [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3274         [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3275         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3276         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3277         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3278         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3279         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3280         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3281         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3282         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3283         [SATA_H_CLK] = &sata_h_clk.clkr,
3284         [SATA_CLK_SRC] = &sata_clk_src.clkr,
3285         [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3286         [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3287         [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3288         [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3289         [SATA_A_CLK] = &sata_a_clk.clkr,
3290         [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3291         [CE3_SRC] = &ce3_src.clkr,
3292         [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3293         [CE3_H_CLK] = &ce3_h_clk.clkr,
3294         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3295         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3296         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3297         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3298         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3299         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3300         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3301         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3302         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3303         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3304         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3305         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3306         [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3307         [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3308         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3309         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3310         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3311         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3312         [ADM0_CLK] = &adm0_clk.clkr,
3313         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3314         [PCIE_A_CLK] = &pcie_a_clk.clkr,
3315         [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3316         [PCIE_H_CLK] = &pcie_h_clk.clkr,
3317         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3318         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3319         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3320         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3321 };
3322
3323 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3324         [QDSS_STM_RESET] = { 0x2060, 6 },
3325         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3326         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3327         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3328         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3329         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3330         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3331         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3332         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3333         [ADM0_C2_RESET] = { 0x220c, 4},
3334         [ADM0_C1_RESET] = { 0x220c, 3},
3335         [ADM0_C0_RESET] = { 0x220c, 2},
3336         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3337         [ADM0_RESET] = { 0x220c },
3338         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3339         [QDSS_POR_RESET] = { 0x2260, 4 },
3340         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3341         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3342         [QDSS_AXI_RESET] = { 0x2260, 1 },
3343         [QDSS_DBG_RESET] = { 0x2260 },
3344         [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3345         [SFAB_PCIE_S_RESET] = { 0x22d8 },
3346         [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3347         [PCIE_PHY_RESET] = { 0x22dc, 5 },
3348         [PCIE_PCI_RESET] = { 0x22dc, 4 },
3349         [PCIE_POR_RESET] = { 0x22dc, 3 },
3350         [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3351         [PCIE_ACLK_RESET] = { 0x22dc },
3352         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3353         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3354         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3355         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3356         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3357         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3358         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3359         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3360         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3361         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3362         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3363         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3364         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3365         [PPSS_PROC_RESET] = { 0x2594, 1 },
3366         [PPSS_RESET] = { 0x2594},
3367         [DMA_BAM_RESET] = { 0x25c0, 7 },
3368         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3369         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3370         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3371         [TSIF_H_RESET] = { 0x2700, 7 },
3372         [CE1_H_RESET] = { 0x2720, 7 },
3373         [CE1_CORE_RESET] = { 0x2724, 7 },
3374         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3375         [CE2_H_RESET] = { 0x2740, 7 },
3376         [CE2_CORE_RESET] = { 0x2744, 7 },
3377         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3378         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3379         [RPM_PROC_RESET] = { 0x27c0, 7 },
3380         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3381         [SDC1_RESET] = { 0x2830 },
3382         [SDC2_RESET] = { 0x2850 },
3383         [SDC3_RESET] = { 0x2870 },
3384         [SDC4_RESET] = { 0x2890 },
3385         [USB_HS1_RESET] = { 0x2910 },
3386         [USB_HSIC_RESET] = { 0x2934 },
3387         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3388         [USB_FS1_RESET] = { 0x2974 },
3389         [GSBI1_RESET] = { 0x29dc },
3390         [GSBI2_RESET] = { 0x29fc },
3391         [GSBI3_RESET] = { 0x2a1c },
3392         [GSBI4_RESET] = { 0x2a3c },
3393         [GSBI5_RESET] = { 0x2a5c },
3394         [GSBI6_RESET] = { 0x2a7c },
3395         [GSBI7_RESET] = { 0x2a9c },
3396         [SPDM_RESET] = { 0x2b6c },
3397         [TLMM_H_RESET] = { 0x2ba0, 7 },
3398         [SATA_SFAB_M_RESET] = { 0x2c18 },
3399         [SATA_RESET] = { 0x2c1c },
3400         [GSS_SLP_RESET] = { 0x2c60, 7 },
3401         [GSS_RESET] = { 0x2c64 },
3402         [TSSC_RESET] = { 0x2ca0, 7 },
3403         [PDM_RESET] = { 0x2cc0, 12 },
3404         [MPM_H_RESET] = { 0x2da0, 7 },
3405         [MPM_RESET] = { 0x2da4 },
3406         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3407         [PRNG_RESET] = { 0x2e80, 12 },
3408         [RIVA_RESET] = { 0x35e0 },
3409         [CE3_H_RESET] = { 0x36c4, 7 },
3410         [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3411         [SFAB_CE3_S_RESET] = { 0x36c8 },
3412         [CE3_RESET] = { 0x36cc, 7 },
3413         [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3414         [USB_HS3_RESET] = { 0x3710 },
3415         [USB_HS4_RESET] = { 0x3730 },
3416 };
3417
3418 static const struct regmap_config gcc_msm8960_regmap_config = {
3419         .reg_bits       = 32,
3420         .reg_stride     = 4,
3421         .val_bits       = 32,
3422         .max_register   = 0x3660,
3423         .fast_io        = true,
3424 };
3425
3426 static const struct regmap_config gcc_apq8064_regmap_config = {
3427         .reg_bits       = 32,
3428         .reg_stride     = 4,
3429         .val_bits       = 32,
3430         .max_register   = 0x3880,
3431         .fast_io        = true,
3432 };
3433
3434 static const struct qcom_cc_desc gcc_msm8960_desc = {
3435         .config = &gcc_msm8960_regmap_config,
3436         .clks = gcc_msm8960_clks,
3437         .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3438         .resets = gcc_msm8960_resets,
3439         .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3440 };
3441
3442 static const struct qcom_cc_desc gcc_apq8064_desc = {
3443         .config = &gcc_apq8064_regmap_config,
3444         .clks = gcc_apq8064_clks,
3445         .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3446         .resets = gcc_apq8064_resets,
3447         .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3448 };
3449
3450 static const struct of_device_id gcc_msm8960_match_table[] = {
3451         { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3452         { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3453         { }
3454 };
3455 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3456
3457 static int gcc_msm8960_probe(struct platform_device *pdev)
3458 {
3459         struct device *dev = &pdev->dev;
3460         const struct of_device_id *match;
3461         struct platform_device *tsens;
3462         int ret;
3463
3464         match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3465         if (!match)
3466                 return -EINVAL;
3467
3468         ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3469         if (ret)
3470                 return ret;
3471
3472         ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3473         if (ret)
3474                 return ret;
3475
3476         ret = qcom_cc_probe(pdev, match->data);
3477         if (ret)
3478                 return ret;
3479
3480         tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3481                                               NULL, 0);
3482         if (IS_ERR(tsens))
3483                 return PTR_ERR(tsens);
3484
3485         platform_set_drvdata(pdev, tsens);
3486
3487         return 0;
3488 }
3489
3490 static int gcc_msm8960_remove(struct platform_device *pdev)
3491 {
3492         struct platform_device *tsens = platform_get_drvdata(pdev);
3493
3494         platform_device_unregister(tsens);
3495
3496         return 0;
3497 }
3498
3499 static struct platform_driver gcc_msm8960_driver = {
3500         .probe          = gcc_msm8960_probe,
3501         .remove         = gcc_msm8960_remove,
3502         .driver         = {
3503                 .name   = "gcc-msm8960",
3504                 .of_match_table = gcc_msm8960_match_table,
3505         },
3506 };
3507
3508 static int __init gcc_msm8960_init(void)
3509 {
3510         return platform_driver_register(&gcc_msm8960_driver);
3511 }
3512 core_initcall(gcc_msm8960_init);
3513
3514 static void __exit gcc_msm8960_exit(void)
3515 {
3516         platform_driver_unregister(&gcc_msm8960_driver);
3517 }
3518 module_exit(gcc_msm8960_exit);
3519
3520 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3521 MODULE_LICENSE("GPL v2");
3522 MODULE_ALIAS("platform:gcc-msm8960");