drivers/clk/qcom/gcc-msm8974.c

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
  26 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34 #include "gdsc.h"
  35
  36 enum {
  37         P_XO,
  38         P_GPLL0,
  39         P_GPLL1,
  40         P_GPLL4,
  41 };
  42
  43 static const struct parent_map gcc_xo_gpll0_map[] = {
  44         { P_XO, 0 },
  45         { P_GPLL0, 1 }
  46 };
  47
  48 static const char * const gcc_xo_gpll0[] = {
  49         "xo",
  50         "gpll0_vote",
  51 };
  52
  53 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  54         { P_XO, 0 },
  55         { P_GPLL0, 1 },
  56         { P_GPLL4, 5 }
  57 };
  58
  59 static const char * const gcc_xo_gpll0_gpll4[] = {
  60         "xo",
  61         "gpll0_vote",
  62         "gpll4_vote",
  63 };
  64
  65 static struct clk_pll gpll0 = {
  66         .l_reg = 0x0004,
  67         .m_reg = 0x0008,
  68         .n_reg = 0x000c,
  69         .config_reg = 0x0014,
  70         .mode_reg = 0x0000,
  71         .status_reg = 0x001c,
  72         .status_bit = 17,
  73         .clkr.hw.init = &(struct clk_init_data){
  74                 .name = "gpll0",
  75                 .parent_names = (const char *[]){ "xo" },
  76                 .num_parents = 1,
  77                 .ops = &clk_pll_ops,
  78         },
  79 };
  80
  81 static struct clk_regmap gpll0_vote = {
  82         .enable_reg = 0x1480,
  83         .enable_mask = BIT(0),
  84         .hw.init = &(struct clk_init_data){
  85                 .name = "gpll0_vote",
  86                 .parent_names = (const char *[]){ "gpll0" },
  87                 .num_parents = 1,
  88                 .ops = &clk_pll_vote_ops,
  89         },
  90 };
  91
  92 static struct clk_rcg2 config_noc_clk_src = {
  93         .cmd_rcgr = 0x0150,
  94         .hid_width = 5,
  95         .parent_map = gcc_xo_gpll0_map,
  96         .clkr.hw.init = &(struct clk_init_data){
  97                 .name = "config_noc_clk_src",
  98                 .parent_names = gcc_xo_gpll0,
  99                 .num_parents = 2,
 100                 .ops = &clk_rcg2_ops,
 101         },
 102 };
 103
 104 static struct clk_rcg2 periph_noc_clk_src = {
 105         .cmd_rcgr = 0x0190,
 106         .hid_width = 5,
 107         .parent_map = gcc_xo_gpll0_map,
 108         .clkr.hw.init = &(struct clk_init_data){
 109                 .name = "periph_noc_clk_src",
 110                 .parent_names = gcc_xo_gpll0,
 111                 .num_parents = 2,
 112                 .ops = &clk_rcg2_ops,
 113         },
 114 };
 115
 116 static struct clk_rcg2 system_noc_clk_src = {
 117         .cmd_rcgr = 0x0120,
 118         .hid_width = 5,
 119         .parent_map = gcc_xo_gpll0_map,
 120         .clkr.hw.init = &(struct clk_init_data){
 121                 .name = "system_noc_clk_src",
 122                 .parent_names = gcc_xo_gpll0,
 123                 .num_parents = 2,
 124                 .ops = &clk_rcg2_ops,
 125         },
 126 };
 127
 128 static struct clk_pll gpll1 = {
 129         .l_reg = 0x0044,
 130         .m_reg = 0x0048,
 131         .n_reg = 0x004c,
 132         .config_reg = 0x0054,
 133         .mode_reg = 0x0040,
 134         .status_reg = 0x005c,
 135         .status_bit = 17,
 136         .clkr.hw.init = &(struct clk_init_data){
 137                 .name = "gpll1",
 138                 .parent_names = (const char *[]){ "xo" },
 139                 .num_parents = 1,
 140                 .ops = &clk_pll_ops,
 141         },
 142 };
 143
 144 static struct clk_regmap gpll1_vote = {
 145         .enable_reg = 0x1480,
 146         .enable_mask = BIT(1),
 147         .hw.init = &(struct clk_init_data){
 148                 .name = "gpll1_vote",
 149                 .parent_names = (const char *[]){ "gpll1" },
 150                 .num_parents = 1,
 151                 .ops = &clk_pll_vote_ops,
 152         },
 153 };
 154
 155 static struct clk_pll gpll4 = {
 156         .l_reg = 0x1dc4,
 157         .m_reg = 0x1dc8,
 158         .n_reg = 0x1dcc,
 159         .config_reg = 0x1dd4,
 160         .mode_reg = 0x1dc0,
 161         .status_reg = 0x1ddc,
 162         .status_bit = 17,
 163         .clkr.hw.init = &(struct clk_init_data){
 164                 .name = "gpll4",
 165                 .parent_names = (const char *[]){ "xo" },
 166                 .num_parents = 1,
 167                 .ops = &clk_pll_ops,
 168         },
 169 };
 170
 171 static struct clk_regmap gpll4_vote = {
 172         .enable_reg = 0x1480,
 173         .enable_mask = BIT(4),
 174         .hw.init = &(struct clk_init_data){
 175                 .name = "gpll4_vote",
 176                 .parent_names = (const char *[]){ "gpll4" },
 177                 .num_parents = 1,
 178                 .ops = &clk_pll_vote_ops,
 179         },
 180 };
 181
 182 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
 183         F(125000000, P_GPLL0, 1, 5, 24),
 184         { }
 185 };
 186
 187 static struct clk_rcg2 usb30_master_clk_src = {
 188         .cmd_rcgr = 0x03d4,
 189         .mnd_width = 8,
 190         .hid_width = 5,
 191         .parent_map = gcc_xo_gpll0_map,
 192         .freq_tbl = ftbl_gcc_usb30_master_clk,
 193         .clkr.hw.init = &(struct clk_init_data){
 194                 .name = "usb30_master_clk_src",
 195                 .parent_names = gcc_xo_gpll0,
 196                 .num_parents = 2,
 197                 .ops = &clk_rcg2_ops,
 198         },
 199 };
 200
 201 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
 202         F(19200000, P_XO, 1, 0, 0),
 203         F(37500000, P_GPLL0, 16, 0, 0),
 204         F(50000000, P_GPLL0, 12, 0, 0),
 205         { }
 206 };
 207
 208 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 209         .cmd_rcgr = 0x0660,
 210         .hid_width = 5,
 211         .parent_map = gcc_xo_gpll0_map,
 212         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 213         .clkr.hw.init = &(struct clk_init_data){
 214                 .name = "blsp1_qup1_i2c_apps_clk_src",
 215                 .parent_names = gcc_xo_gpll0,
 216                 .num_parents = 2,
 217                 .ops = &clk_rcg2_ops,
 218         },
 219 };
 220
 221 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
 222         F(960000, P_XO, 10, 1, 2),
 223         F(4800000, P_XO, 4, 0, 0),
 224         F(9600000, P_XO, 2, 0, 0),
 225         F(15000000, P_GPLL0, 10, 1, 4),
 226         F(19200000, P_XO, 1, 0, 0),
 227         F(25000000, P_GPLL0, 12, 1, 2),
 228         F(50000000, P_GPLL0, 12, 0, 0),
 229         { }
 230 };
 231
 232 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 233         .cmd_rcgr = 0x064c,
 234         .mnd_width = 8,
 235         .hid_width = 5,
 236         .parent_map = gcc_xo_gpll0_map,
 237         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 238         .clkr.hw.init = &(struct clk_init_data){
 239                 .name = "blsp1_qup1_spi_apps_clk_src",
 240                 .parent_names = gcc_xo_gpll0,
 241                 .num_parents = 2,
 242                 .ops = &clk_rcg2_ops,
 243         },
 244 };
 245
 246 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 247         .cmd_rcgr = 0x06e0,
 248         .hid_width = 5,
 249         .parent_map = gcc_xo_gpll0_map,
 250         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 251         .clkr.hw.init = &(struct clk_init_data){
 252                 .name = "blsp1_qup2_i2c_apps_clk_src",
 253                 .parent_names = gcc_xo_gpll0,
 254                 .num_parents = 2,
 255                 .ops = &clk_rcg2_ops,
 256         },
 257 };
 258
 259 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 260         .cmd_rcgr = 0x06cc,
 261         .mnd_width = 8,
 262         .hid_width = 5,
 263         .parent_map = gcc_xo_gpll0_map,
 264         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 265         .clkr.hw.init = &(struct clk_init_data){
 266                 .name = "blsp1_qup2_spi_apps_clk_src",
 267                 .parent_names = gcc_xo_gpll0,
 268                 .num_parents = 2,
 269                 .ops = &clk_rcg2_ops,
 270         },
 271 };
 272
 273 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 274         .cmd_rcgr = 0x0760,
 275         .hid_width = 5,
 276         .parent_map = gcc_xo_gpll0_map,
 277         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 278         .clkr.hw.init = &(struct clk_init_data){
 279                 .name = "blsp1_qup3_i2c_apps_clk_src",
 280                 .parent_names = gcc_xo_gpll0,
 281                 .num_parents = 2,
 282                 .ops = &clk_rcg2_ops,
 283         },
 284 };
 285
 286 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 287         .cmd_rcgr = 0x074c,
 288         .mnd_width = 8,
 289         .hid_width = 5,
 290         .parent_map = gcc_xo_gpll0_map,
 291         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 292         .clkr.hw.init = &(struct clk_init_data){
 293                 .name = "blsp1_qup3_spi_apps_clk_src",
 294                 .parent_names = gcc_xo_gpll0,
 295                 .num_parents = 2,
 296                 .ops = &clk_rcg2_ops,
 297         },
 298 };
 299
 300 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 301         .cmd_rcgr = 0x07e0,
 302         .hid_width = 5,
 303         .parent_map = gcc_xo_gpll0_map,
 304         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 305         .clkr.hw.init = &(struct clk_init_data){
 306                 .name = "blsp1_qup4_i2c_apps_clk_src",
 307                 .parent_names = gcc_xo_gpll0,
 308                 .num_parents = 2,
 309                 .ops = &clk_rcg2_ops,
 310         },
 311 };
 312
 313 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 314         .cmd_rcgr = 0x07cc,
 315         .mnd_width = 8,
 316         .hid_width = 5,
 317         .parent_map = gcc_xo_gpll0_map,
 318         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 319         .clkr.hw.init = &(struct clk_init_data){
 320                 .name = "blsp1_qup4_spi_apps_clk_src",
 321                 .parent_names = gcc_xo_gpll0,
 322                 .num_parents = 2,
 323                 .ops = &clk_rcg2_ops,
 324         },
 325 };
 326
 327 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 328         .cmd_rcgr = 0x0860,
 329         .hid_width = 5,
 330         .parent_map = gcc_xo_gpll0_map,
 331         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 332         .clkr.hw.init = &(struct clk_init_data){
 333                 .name = "blsp1_qup5_i2c_apps_clk_src",
 334                 .parent_names = gcc_xo_gpll0,
 335                 .num_parents = 2,
 336                 .ops = &clk_rcg2_ops,
 337         },
 338 };
 339
 340 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 341         .cmd_rcgr = 0x084c,
 342         .mnd_width = 8,
 343         .hid_width = 5,
 344         .parent_map = gcc_xo_gpll0_map,
 345         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 346         .clkr.hw.init = &(struct clk_init_data){
 347                 .name = "blsp1_qup5_spi_apps_clk_src",
 348                 .parent_names = gcc_xo_gpll0,
 349                 .num_parents = 2,
 350                 .ops = &clk_rcg2_ops,
 351         },
 352 };
 353
 354 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 355         .cmd_rcgr = 0x08e0,
 356         .hid_width = 5,
 357         .parent_map = gcc_xo_gpll0_map,
 358         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 359         .clkr.hw.init = &(struct clk_init_data){
 360                 .name = "blsp1_qup6_i2c_apps_clk_src",
 361                 .parent_names = gcc_xo_gpll0,
 362                 .num_parents = 2,
 363                 .ops = &clk_rcg2_ops,
 364         },
 365 };
 366
 367 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 368         .cmd_rcgr = 0x08cc,
 369         .mnd_width = 8,
 370         .hid_width = 5,
 371         .parent_map = gcc_xo_gpll0_map,
 372         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 373         .clkr.hw.init = &(struct clk_init_data){
 374                 .name = "blsp1_qup6_spi_apps_clk_src",
 375                 .parent_names = gcc_xo_gpll0,
 376                 .num_parents = 2,
 377                 .ops = &clk_rcg2_ops,
 378         },
 379 };
 380
 381 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
 382         F(3686400, P_GPLL0, 1, 96, 15625),
 383         F(7372800, P_GPLL0, 1, 192, 15625),
 384         F(14745600, P_GPLL0, 1, 384, 15625),
 385         F(16000000, P_GPLL0, 5, 2, 15),
 386         F(19200000, P_XO, 1, 0, 0),
 387         F(24000000, P_GPLL0, 5, 1, 5),
 388         F(32000000, P_GPLL0, 1, 4, 75),
 389         F(40000000, P_GPLL0, 15, 0, 0),
 390         F(46400000, P_GPLL0, 1, 29, 375),
 391         F(48000000, P_GPLL0, 12.5, 0, 0),
 392         F(51200000, P_GPLL0, 1, 32, 375),
 393         F(56000000, P_GPLL0, 1, 7, 75),
 394         F(58982400, P_GPLL0, 1, 1536, 15625),
 395         F(60000000, P_GPLL0, 10, 0, 0),
 396         F(63160000, P_GPLL0, 9.5, 0, 0),
 397         { }
 398 };
 399
 400 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 401         .cmd_rcgr = 0x068c,
 402         .mnd_width = 16,
 403         .hid_width = 5,
 404         .parent_map = gcc_xo_gpll0_map,
 405         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 406         .clkr.hw.init = &(struct clk_init_data){
 407                 .name = "blsp1_uart1_apps_clk_src",
 408                 .parent_names = gcc_xo_gpll0,
 409                 .num_parents = 2,
 410                 .ops = &clk_rcg2_ops,
 411         },
 412 };
 413
 414 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 415         .cmd_rcgr = 0x070c,
 416         .mnd_width = 16,
 417         .hid_width = 5,
 418         .parent_map = gcc_xo_gpll0_map,
 419         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 420         .clkr.hw.init = &(struct clk_init_data){
 421                 .name = "blsp1_uart2_apps_clk_src",
 422                 .parent_names = gcc_xo_gpll0,
 423                 .num_parents = 2,
 424                 .ops = &clk_rcg2_ops,
 425         },
 426 };
 427
 428 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 429         .cmd_rcgr = 0x078c,
 430         .mnd_width = 16,
 431         .hid_width = 5,
 432         .parent_map = gcc_xo_gpll0_map,
 433         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 434         .clkr.hw.init = &(struct clk_init_data){
 435                 .name = "blsp1_uart3_apps_clk_src",
 436                 .parent_names = gcc_xo_gpll0,
 437                 .num_parents = 2,
 438                 .ops = &clk_rcg2_ops,
 439         },
 440 };
 441
 442 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 443         .cmd_rcgr = 0x080c,
 444         .mnd_width = 16,
 445         .hid_width = 5,
 446         .parent_map = gcc_xo_gpll0_map,
 447         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 448         .clkr.hw.init = &(struct clk_init_data){
 449                 .name = "blsp1_uart4_apps_clk_src",
 450                 .parent_names = gcc_xo_gpll0,
 451                 .num_parents = 2,
 452                 .ops = &clk_rcg2_ops,
 453         },
 454 };
 455
 456 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 457         .cmd_rcgr = 0x088c,
 458         .mnd_width = 16,
 459         .hid_width = 5,
 460         .parent_map = gcc_xo_gpll0_map,
 461         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 462         .clkr.hw.init = &(struct clk_init_data){
 463                 .name = "blsp1_uart5_apps_clk_src",
 464                 .parent_names = gcc_xo_gpll0,
 465                 .num_parents = 2,
 466                 .ops = &clk_rcg2_ops,
 467         },
 468 };
 469
 470 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 471         .cmd_rcgr = 0x090c,
 472         .mnd_width = 16,
 473         .hid_width = 5,
 474         .parent_map = gcc_xo_gpll0_map,
 475         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 476         .clkr.hw.init = &(struct clk_init_data){
 477                 .name = "blsp1_uart6_apps_clk_src",
 478                 .parent_names = gcc_xo_gpll0,
 479                 .num_parents = 2,
 480                 .ops = &clk_rcg2_ops,
 481         },
 482 };
 483
 484 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 485         .cmd_rcgr = 0x09a0,
 486         .hid_width = 5,
 487         .parent_map = gcc_xo_gpll0_map,
 488         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 489         .clkr.hw.init = &(struct clk_init_data){
 490                 .name = "blsp2_qup1_i2c_apps_clk_src",
 491                 .parent_names = gcc_xo_gpll0,
 492                 .num_parents = 2,
 493                 .ops = &clk_rcg2_ops,
 494         },
 495 };
 496
 497 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 498         .cmd_rcgr = 0x098c,
 499         .mnd_width = 8,
 500         .hid_width = 5,
 501         .parent_map = gcc_xo_gpll0_map,
 502         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 503         .clkr.hw.init = &(struct clk_init_data){
 504                 .name = "blsp2_qup1_spi_apps_clk_src",
 505                 .parent_names = gcc_xo_gpll0,
 506                 .num_parents = 2,
 507                 .ops = &clk_rcg2_ops,
 508         },
 509 };
 510
 511 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 512         .cmd_rcgr = 0x0a20,
 513         .hid_width = 5,
 514         .parent_map = gcc_xo_gpll0_map,
 515         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 516         .clkr.hw.init = &(struct clk_init_data){
 517                 .name = "blsp2_qup2_i2c_apps_clk_src",
 518                 .parent_names = gcc_xo_gpll0,
 519                 .num_parents = 2,
 520                 .ops = &clk_rcg2_ops,
 521         },
 522 };
 523
 524 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 525         .cmd_rcgr = 0x0a0c,
 526         .mnd_width = 8,
 527         .hid_width = 5,
 528         .parent_map = gcc_xo_gpll0_map,
 529         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 530         .clkr.hw.init = &(struct clk_init_data){
 531                 .name = "blsp2_qup2_spi_apps_clk_src",
 532                 .parent_names = gcc_xo_gpll0,
 533                 .num_parents = 2,
 534                 .ops = &clk_rcg2_ops,
 535         },
 536 };
 537
 538 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 539         .cmd_rcgr = 0x0aa0,
 540         .hid_width = 5,
 541         .parent_map = gcc_xo_gpll0_map,
 542         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 543         .clkr.hw.init = &(struct clk_init_data){
 544                 .name = "blsp2_qup3_i2c_apps_clk_src",
 545                 .parent_names = gcc_xo_gpll0,
 546                 .num_parents = 2,
 547                 .ops = &clk_rcg2_ops,
 548         },
 549 };
 550
 551 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 552         .cmd_rcgr = 0x0a8c,
 553         .mnd_width = 8,
 554         .hid_width = 5,
 555         .parent_map = gcc_xo_gpll0_map,
 556         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 557         .clkr.hw.init = &(struct clk_init_data){
 558                 .name = "blsp2_qup3_spi_apps_clk_src",
 559                 .parent_names = gcc_xo_gpll0,
 560                 .num_parents = 2,
 561                 .ops = &clk_rcg2_ops,
 562         },
 563 };
 564
 565 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 566         .cmd_rcgr = 0x0b20,
 567         .hid_width = 5,
 568         .parent_map = gcc_xo_gpll0_map,
 569         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 570         .clkr.hw.init = &(struct clk_init_data){
 571                 .name = "blsp2_qup4_i2c_apps_clk_src",
 572                 .parent_names = gcc_xo_gpll0,
 573                 .num_parents = 2,
 574                 .ops = &clk_rcg2_ops,
 575         },
 576 };
 577
 578 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 579         .cmd_rcgr = 0x0b0c,
 580         .mnd_width = 8,
 581         .hid_width = 5,
 582         .parent_map = gcc_xo_gpll0_map,
 583         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 584         .clkr.hw.init = &(struct clk_init_data){
 585                 .name = "blsp2_qup4_spi_apps_clk_src",
 586                 .parent_names = gcc_xo_gpll0,
 587                 .num_parents = 2,
 588                 .ops = &clk_rcg2_ops,
 589         },
 590 };
 591
 592 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 593         .cmd_rcgr = 0x0ba0,
 594         .hid_width = 5,
 595         .parent_map = gcc_xo_gpll0_map,
 596         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 597         .clkr.hw.init = &(struct clk_init_data){
 598                 .name = "blsp2_qup5_i2c_apps_clk_src",
 599                 .parent_names = gcc_xo_gpll0,
 600                 .num_parents = 2,
 601                 .ops = &clk_rcg2_ops,
 602         },
 603 };
 604
 605 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 606         .cmd_rcgr = 0x0b8c,
 607         .mnd_width = 8,
 608         .hid_width = 5,
 609         .parent_map = gcc_xo_gpll0_map,
 610         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 611         .clkr.hw.init = &(struct clk_init_data){
 612                 .name = "blsp2_qup5_spi_apps_clk_src",
 613                 .parent_names = gcc_xo_gpll0,
 614                 .num_parents = 2,
 615                 .ops = &clk_rcg2_ops,
 616         },
 617 };
 618
 619 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 620         .cmd_rcgr = 0x0c20,
 621         .hid_width = 5,
 622         .parent_map = gcc_xo_gpll0_map,
 623         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 624         .clkr.hw.init = &(struct clk_init_data){
 625                 .name = "blsp2_qup6_i2c_apps_clk_src",
 626                 .parent_names = gcc_xo_gpll0,
 627                 .num_parents = 2,
 628                 .ops = &clk_rcg2_ops,
 629         },
 630 };
 631
 632 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 633         .cmd_rcgr = 0x0c0c,
 634         .mnd_width = 8,
 635         .hid_width = 5,
 636         .parent_map = gcc_xo_gpll0_map,
 637         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 638         .clkr.hw.init = &(struct clk_init_data){
 639                 .name = "blsp2_qup6_spi_apps_clk_src",
 640                 .parent_names = gcc_xo_gpll0,
 641                 .num_parents = 2,
 642                 .ops = &clk_rcg2_ops,
 643         },
 644 };
 645
 646 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 647         .cmd_rcgr = 0x09cc,
 648         .mnd_width = 16,
 649         .hid_width = 5,
 650         .parent_map = gcc_xo_gpll0_map,
 651         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 652         .clkr.hw.init = &(struct clk_init_data){
 653                 .name = "blsp2_uart1_apps_clk_src",
 654                 .parent_names = gcc_xo_gpll0,
 655                 .num_parents = 2,
 656                 .ops = &clk_rcg2_ops,
 657         },
 658 };
 659
 660 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 661         .cmd_rcgr = 0x0a4c,
 662         .mnd_width = 16,
 663         .hid_width = 5,
 664         .parent_map = gcc_xo_gpll0_map,
 665         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 666         .clkr.hw.init = &(struct clk_init_data){
 667                 .name = "blsp2_uart2_apps_clk_src",
 668                 .parent_names = gcc_xo_gpll0,
 669                 .num_parents = 2,
 670                 .ops = &clk_rcg2_ops,
 671         },
 672 };
 673
 674 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 675         .cmd_rcgr = 0x0acc,
 676         .mnd_width = 16,
 677         .hid_width = 5,
 678         .parent_map = gcc_xo_gpll0_map,
 679         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 680         .clkr.hw.init = &(struct clk_init_data){
 681                 .name = "blsp2_uart3_apps_clk_src",
 682                 .parent_names = gcc_xo_gpll0,
 683                 .num_parents = 2,
 684                 .ops = &clk_rcg2_ops,
 685         },
 686 };
 687
 688 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 689         .cmd_rcgr = 0x0b4c,
 690         .mnd_width = 16,
 691         .hid_width = 5,
 692         .parent_map = gcc_xo_gpll0_map,
 693         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 694         .clkr.hw.init = &(struct clk_init_data){
 695                 .name = "blsp2_uart4_apps_clk_src",
 696                 .parent_names = gcc_xo_gpll0,
 697                 .num_parents = 2,
 698                 .ops = &clk_rcg2_ops,
 699         },
 700 };
 701
 702 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 703         .cmd_rcgr = 0x0bcc,
 704         .mnd_width = 16,
 705         .hid_width = 5,
 706         .parent_map = gcc_xo_gpll0_map,
 707         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 708         .clkr.hw.init = &(struct clk_init_data){
 709                 .name = "blsp2_uart5_apps_clk_src",
 710                 .parent_names = gcc_xo_gpll0,
 711                 .num_parents = 2,
 712                 .ops = &clk_rcg2_ops,
 713         },
 714 };
 715
 716 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 717         .cmd_rcgr = 0x0c4c,
 718         .mnd_width = 16,
 719         .hid_width = 5,
 720         .parent_map = gcc_xo_gpll0_map,
 721         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 722         .clkr.hw.init = &(struct clk_init_data){
 723                 .name = "blsp2_uart6_apps_clk_src",
 724                 .parent_names = gcc_xo_gpll0,
 725                 .num_parents = 2,
 726                 .ops = &clk_rcg2_ops,
 727         },
 728 };
 729
 730 static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
 731         F(50000000, P_GPLL0, 12, 0, 0),
 732         F(75000000, P_GPLL0, 8, 0, 0),
 733         F(100000000, P_GPLL0, 6, 0, 0),
 734         F(150000000, P_GPLL0, 4, 0, 0),
 735         { }
 736 };
 737
 738 static struct clk_rcg2 ce1_clk_src = {
 739         .cmd_rcgr = 0x1050,
 740         .hid_width = 5,
 741         .parent_map = gcc_xo_gpll0_map,
 742         .freq_tbl = ftbl_gcc_ce1_clk,
 743         .clkr.hw.init = &(struct clk_init_data){
 744                 .name = "ce1_clk_src",
 745                 .parent_names = gcc_xo_gpll0,
 746                 .num_parents = 2,
 747                 .ops = &clk_rcg2_ops,
 748         },
 749 };
 750
 751 static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
 752         F(50000000, P_GPLL0, 12, 0, 0),
 753         F(75000000, P_GPLL0, 8, 0, 0),
 754         F(100000000, P_GPLL0, 6, 0, 0),
 755         F(150000000, P_GPLL0, 4, 0, 0),
 756         { }
 757 };
 758
 759 static struct clk_rcg2 ce2_clk_src = {
 760         .cmd_rcgr = 0x1090,
 761         .hid_width = 5,
 762         .parent_map = gcc_xo_gpll0_map,
 763         .freq_tbl = ftbl_gcc_ce2_clk,
 764         .clkr.hw.init = &(struct clk_init_data){
 765                 .name = "ce2_clk_src",
 766                 .parent_names = gcc_xo_gpll0,
 767                 .num_parents = 2,
 768                 .ops = &clk_rcg2_ops,
 769         },
 770 };
 771
 772 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
 773         F(4800000, P_XO, 4, 0, 0),
 774         F(6000000, P_GPLL0, 10, 1, 10),
 775         F(6750000, P_GPLL0, 1, 1, 89),
 776         F(8000000, P_GPLL0, 15, 1, 5),
 777         F(9600000, P_XO, 2, 0, 0),
 778         F(16000000, P_GPLL0, 1, 2, 75),
 779         F(19200000, P_XO, 1, 0, 0),
 780         F(24000000, P_GPLL0, 5, 1, 5),
 781         { }
 782 };
 783
 784
 785 static struct clk_rcg2 gp1_clk_src = {
 786         .cmd_rcgr = 0x1904,
 787         .mnd_width = 8,
 788         .hid_width = 5,
 789         .parent_map = gcc_xo_gpll0_map,
 790         .freq_tbl = ftbl_gcc_gp_clk,
 791         .clkr.hw.init = &(struct clk_init_data){
 792                 .name = "gp1_clk_src",
 793                 .parent_names = gcc_xo_gpll0,
 794                 .num_parents = 2,
 795                 .ops = &clk_rcg2_ops,
 796         },
 797 };
 798
 799 static struct clk_rcg2 gp2_clk_src = {
 800         .cmd_rcgr = 0x1944,
 801         .mnd_width = 8,
 802         .hid_width = 5,
 803         .parent_map = gcc_xo_gpll0_map,
 804         .freq_tbl = ftbl_gcc_gp_clk,
 805         .clkr.hw.init = &(struct clk_init_data){
 806                 .name = "gp2_clk_src",
 807                 .parent_names = gcc_xo_gpll0,
 808                 .num_parents = 2,
 809                 .ops = &clk_rcg2_ops,
 810         },
 811 };
 812
 813 static struct clk_rcg2 gp3_clk_src = {
 814         .cmd_rcgr = 0x1984,
 815         .mnd_width = 8,
 816         .hid_width = 5,
 817         .parent_map = gcc_xo_gpll0_map,
 818         .freq_tbl = ftbl_gcc_gp_clk,
 819         .clkr.hw.init = &(struct clk_init_data){
 820                 .name = "gp3_clk_src",
 821                 .parent_names = gcc_xo_gpll0,
 822                 .num_parents = 2,
 823                 .ops = &clk_rcg2_ops,
 824         },
 825 };
 826
 827 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
 828         F(60000000, P_GPLL0, 10, 0, 0),
 829         { }
 830 };
 831
 832 static struct clk_rcg2 pdm2_clk_src = {
 833         .cmd_rcgr = 0x0cd0,
 834         .hid_width = 5,
 835         .parent_map = gcc_xo_gpll0_map,
 836         .freq_tbl = ftbl_gcc_pdm2_clk,
 837         .clkr.hw.init = &(struct clk_init_data){
 838                 .name = "pdm2_clk_src",
 839                 .parent_names = gcc_xo_gpll0,
 840                 .num_parents = 2,
 841                 .ops = &clk_rcg2_ops,
 842         },
 843 };
 844
 845 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
 846         F(144000, P_XO, 16, 3, 25),
 847         F(400000, P_XO, 12, 1, 4),
 848         F(20000000, P_GPLL0, 15, 1, 2),
 849         F(25000000, P_GPLL0, 12, 1, 2),
 850         F(50000000, P_GPLL0, 12, 0, 0),
 851         F(100000000, P_GPLL0, 6, 0, 0),
 852         F(200000000, P_GPLL0, 3, 0, 0),
 853         { }
 854 };
 855
 856 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
 857         F(144000, P_XO, 16, 3, 25),
 858         F(400000, P_XO, 12, 1, 4),
 859         F(20000000, P_GPLL0, 15, 1, 2),
 860         F(25000000, P_GPLL0, 12, 1, 2),
 861         F(50000000, P_GPLL0, 12, 0, 0),
 862         F(100000000, P_GPLL0, 6, 0, 0),
 863         F(192000000, P_GPLL4, 4, 0, 0),
 864         F(200000000, P_GPLL0, 3, 0, 0),
 865         F(384000000, P_GPLL4, 2, 0, 0),
 866         { }
 867 };
 868
 869 static struct clk_init_data sdcc1_apps_clk_src_init = {
 870         .name = "sdcc1_apps_clk_src",
 871         .parent_names = gcc_xo_gpll0,
 872         .num_parents = 2,
 873         .ops = &clk_rcg2_floor_ops,
 874 };
 875
 876 static struct clk_rcg2 sdcc1_apps_clk_src = {
 877         .cmd_rcgr = 0x04d0,
 878         .mnd_width = 8,
 879         .hid_width = 5,
 880         .parent_map = gcc_xo_gpll0_map,
 881         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 882         .clkr.hw.init = &sdcc1_apps_clk_src_init,
 883 };
 884
 885 static struct clk_rcg2 sdcc2_apps_clk_src = {
 886         .cmd_rcgr = 0x0510,
 887         .mnd_width = 8,
 888         .hid_width = 5,
 889         .parent_map = gcc_xo_gpll0_map,
 890         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 891         .clkr.hw.init = &(struct clk_init_data){
 892                 .name = "sdcc2_apps_clk_src",
 893                 .parent_names = gcc_xo_gpll0,
 894                 .num_parents = 2,
 895                 .ops = &clk_rcg2_floor_ops,
 896         },
 897 };
 898
 899 static struct clk_rcg2 sdcc3_apps_clk_src = {
 900         .cmd_rcgr = 0x0550,
 901         .mnd_width = 8,
 902         .hid_width = 5,
 903         .parent_map = gcc_xo_gpll0_map,
 904         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 905         .clkr.hw.init = &(struct clk_init_data){
 906                 .name = "sdcc3_apps_clk_src",
 907                 .parent_names = gcc_xo_gpll0,
 908                 .num_parents = 2,
 909                 .ops = &clk_rcg2_floor_ops,
 910         },
 911 };
 912
 913 static struct clk_rcg2 sdcc4_apps_clk_src = {
 914         .cmd_rcgr = 0x0590,
 915         .mnd_width = 8,
 916         .hid_width = 5,
 917         .parent_map = gcc_xo_gpll0_map,
 918         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 919         .clkr.hw.init = &(struct clk_init_data){
 920                 .name = "sdcc4_apps_clk_src",
 921                 .parent_names = gcc_xo_gpll0,
 922                 .num_parents = 2,
 923                 .ops = &clk_rcg2_floor_ops,
 924         },
 925 };
 926
 927 static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
 928         F(105000, P_XO, 2, 1, 91),
 929         { }
 930 };
 931
 932 static struct clk_rcg2 tsif_ref_clk_src = {
 933         .cmd_rcgr = 0x0d90,
 934         .mnd_width = 8,
 935         .hid_width = 5,
 936         .parent_map = gcc_xo_gpll0_map,
 937         .freq_tbl = ftbl_gcc_tsif_ref_clk,
 938         .clkr.hw.init = &(struct clk_init_data){
 939                 .name = "tsif_ref_clk_src",
 940                 .parent_names = gcc_xo_gpll0,
 941                 .num_parents = 2,
 942                 .ops = &clk_rcg2_ops,
 943         },
 944 };
 945
 946 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
 947         F(60000000, P_GPLL0, 10, 0, 0),
 948         { }
 949 };
 950
 951 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 952         .cmd_rcgr = 0x03e8,
 953         .hid_width = 5,
 954         .parent_map = gcc_xo_gpll0_map,
 955         .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
 956         .clkr.hw.init = &(struct clk_init_data){
 957                 .name = "usb30_mock_utmi_clk_src",
 958                 .parent_names = gcc_xo_gpll0,
 959                 .num_parents = 2,
 960                 .ops = &clk_rcg2_ops,
 961         },
 962 };
 963
 964 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
 965         F(60000000, P_GPLL0, 10, 0, 0),
 966         F(75000000, P_GPLL0, 8, 0, 0),
 967         { }
 968 };
 969
 970 static struct clk_rcg2 usb_hs_system_clk_src = {
 971         .cmd_rcgr = 0x0490,
 972         .hid_width = 5,
 973         .parent_map = gcc_xo_gpll0_map,
 974         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
 975         .clkr.hw.init = &(struct clk_init_data){
 976                 .name = "usb_hs_system_clk_src",
 977                 .parent_names = gcc_xo_gpll0,
 978                 .num_parents = 2,
 979                 .ops = &clk_rcg2_ops,
 980         },
 981 };
 982
 983 static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
 984         F(480000000, P_GPLL1, 1, 0, 0),
 985         { }
 986 };
 987
 988 static const struct parent_map usb_hsic_clk_src_map[] = {
 989         { P_XO, 0 },
 990         { P_GPLL1, 4 }
 991 };
 992
 993 static struct clk_rcg2 usb_hsic_clk_src = {
 994         .cmd_rcgr = 0x0440,
 995         .hid_width = 5,
 996         .parent_map = usb_hsic_clk_src_map,
 997         .freq_tbl = ftbl_gcc_usb_hsic_clk,
 998         .clkr.hw.init = &(struct clk_init_data){
 999                 .name = "usb_hsic_clk_src",
1000                 .parent_names = (const char *[]){
1001                         "xo",
1002                         "gpll1_vote",
1003                 },
1004                 .num_parents = 2,
1005                 .ops = &clk_rcg2_ops,
1006         },
1007 };
1008
1009 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1010         F(9600000, P_XO, 2, 0, 0),
1011         { }
1012 };
1013
1014 static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1015         .cmd_rcgr = 0x0458,
1016         .hid_width = 5,
1017         .parent_map = gcc_xo_gpll0_map,
1018         .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1019         .clkr.hw.init = &(struct clk_init_data){
1020                 .name = "usb_hsic_io_cal_clk_src",
1021                 .parent_names = gcc_xo_gpll0,
1022                 .num_parents = 1,
1023                 .ops = &clk_rcg2_ops,
1024         },
1025 };
1026
1027 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1028         F(60000000, P_GPLL0, 10, 0, 0),
1029         F(75000000, P_GPLL0, 8, 0, 0),
1030         { }
1031 };
1032
1033 static struct clk_rcg2 usb_hsic_system_clk_src = {
1034         .cmd_rcgr = 0x041c,
1035         .hid_width = 5,
1036         .parent_map = gcc_xo_gpll0_map,
1037         .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1038         .clkr.hw.init = &(struct clk_init_data){
1039                 .name = "usb_hsic_system_clk_src",
1040                 .parent_names = gcc_xo_gpll0,
1041                 .num_parents = 2,
1042                 .ops = &clk_rcg2_ops,
1043         },
1044 };
1045
1046 static struct clk_regmap gcc_mmss_gpll0_clk_src = {
1047         .enable_reg = 0x1484,
1048         .enable_mask = BIT(26),
1049         .hw.init = &(struct clk_init_data){
1050                 .name = "mmss_gpll0_vote",
1051                 .parent_names = (const char *[]){
1052                         "gpll0_vote",
1053                 },
1054                 .num_parents = 1,
1055                 .ops = &clk_branch_simple_ops,
1056         },
1057 };
1058
1059 static struct clk_branch gcc_bam_dma_ahb_clk = {
1060         .halt_reg = 0x0d44,
1061         .halt_check = BRANCH_HALT_VOTED,
1062         .clkr = {
1063                 .enable_reg = 0x1484,
1064                 .enable_mask = BIT(12),
1065                 .hw.init = &(struct clk_init_data){
1066                         .name = "gcc_bam_dma_ahb_clk",
1067                         .parent_names = (const char *[]){
1068                                 "periph_noc_clk_src",
1069                         },
1070                         .num_parents = 1,
1071                         .ops = &clk_branch2_ops,
1072                 },
1073         },
1074 };
1075
1076 static struct clk_branch gcc_blsp1_ahb_clk = {
1077         .halt_reg = 0x05c4,
1078         .halt_check = BRANCH_HALT_VOTED,
1079         .clkr = {
1080                 .enable_reg = 0x1484,
1081                 .enable_mask = BIT(17),
1082                 .hw.init = &(struct clk_init_data){
1083                         .name = "gcc_blsp1_ahb_clk",
1084                         .parent_names = (const char *[]){
1085                                 "periph_noc_clk_src",
1086                         },
1087                         .num_parents = 1,
1088                         .ops = &clk_branch2_ops,
1089                 },
1090         },
1091 };
1092
1093 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1094         .halt_reg = 0x0648,
1095         .clkr = {
1096                 .enable_reg = 0x0648,
1097                 .enable_mask = BIT(0),
1098                 .hw.init = &(struct clk_init_data){
1099                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1100                         .parent_names = (const char *[]){
1101                                 "blsp1_qup1_i2c_apps_clk_src",
1102                         },
1103                         .num_parents = 1,
1104                         .flags = CLK_SET_RATE_PARENT,
1105                         .ops = &clk_branch2_ops,
1106                 },
1107         },
1108 };
1109
1110 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1111         .halt_reg = 0x0644,
1112         .clkr = {
1113                 .enable_reg = 0x0644,
1114                 .enable_mask = BIT(0),
1115                 .hw.init = &(struct clk_init_data){
1116                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1117                         .parent_names = (const char *[]){
1118                                 "blsp1_qup1_spi_apps_clk_src",
1119                         },
1120                         .num_parents = 1,
1121                         .flags = CLK_SET_RATE_PARENT,
1122                         .ops = &clk_branch2_ops,
1123                 },
1124         },
1125 };
1126
1127 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1128         .halt_reg = 0x06c8,
1129         .clkr = {
1130                 .enable_reg = 0x06c8,
1131                 .enable_mask = BIT(0),
1132                 .hw.init = &(struct clk_init_data){
1133                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1134                         .parent_names = (const char *[]){
1135                                 "blsp1_qup2_i2c_apps_clk_src",
1136                         },
1137                         .num_parents = 1,
1138                         .flags = CLK_SET_RATE_PARENT,
1139                         .ops = &clk_branch2_ops,
1140                 },
1141         },
1142 };
1143
1144 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1145         .halt_reg = 0x06c4,
1146         .clkr = {
1147                 .enable_reg = 0x06c4,
1148                 .enable_mask = BIT(0),
1149                 .hw.init = &(struct clk_init_data){
1150                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1151                         .parent_names = (const char *[]){
1152                                 "blsp1_qup2_spi_apps_clk_src",
1153                         },
1154                         .num_parents = 1,
1155                         .flags = CLK_SET_RATE_PARENT,
1156                         .ops = &clk_branch2_ops,
1157                 },
1158         },
1159 };
1160
1161 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1162         .halt_reg = 0x0748,
1163         .clkr = {
1164                 .enable_reg = 0x0748,
1165                 .enable_mask = BIT(0),
1166                 .hw.init = &(struct clk_init_data){
1167                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1168                         .parent_names = (const char *[]){
1169                                 "blsp1_qup3_i2c_apps_clk_src",
1170                         },
1171                         .num_parents = 1,
1172                         .flags = CLK_SET_RATE_PARENT,
1173                         .ops = &clk_branch2_ops,
1174                 },
1175         },
1176 };
1177
1178 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1179         .halt_reg = 0x0744,
1180         .clkr = {
1181                 .enable_reg = 0x0744,
1182                 .enable_mask = BIT(0),
1183                 .hw.init = &(struct clk_init_data){
1184                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1185                         .parent_names = (const char *[]){
1186                                 "blsp1_qup3_spi_apps_clk_src",
1187                         },
1188                         .num_parents = 1,
1189                         .flags = CLK_SET_RATE_PARENT,
1190                         .ops = &clk_branch2_ops,
1191                 },
1192         },
1193 };
1194
1195 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1196         .halt_reg = 0x07c8,
1197         .clkr = {
1198                 .enable_reg = 0x07c8,
1199                 .enable_mask = BIT(0),
1200                 .hw.init = &(struct clk_init_data){
1201                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1202                         .parent_names = (const char *[]){
1203                                 "blsp1_qup4_i2c_apps_clk_src",
1204                         },
1205                         .num_parents = 1,
1206                         .flags = CLK_SET_RATE_PARENT,
1207                         .ops = &clk_branch2_ops,
1208                 },
1209         },
1210 };
1211
1212 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1213         .halt_reg = 0x07c4,
1214         .clkr = {
1215                 .enable_reg = 0x07c4,
1216                 .enable_mask = BIT(0),
1217                 .hw.init = &(struct clk_init_data){
1218                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1219                         .parent_names = (const char *[]){
1220                                 "blsp1_qup4_spi_apps_clk_src",
1221                         },
1222                         .num_parents = 1,
1223                         .flags = CLK_SET_RATE_PARENT,
1224                         .ops = &clk_branch2_ops,
1225                 },
1226         },
1227 };
1228
1229 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1230         .halt_reg = 0x0848,
1231         .clkr = {
1232                 .enable_reg = 0x0848,
1233                 .enable_mask = BIT(0),
1234                 .hw.init = &(struct clk_init_data){
1235                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1236                         .parent_names = (const char *[]){
1237                                 "blsp1_qup5_i2c_apps_clk_src",
1238                         },
1239                         .num_parents = 1,
1240                         .flags = CLK_SET_RATE_PARENT,
1241                         .ops = &clk_branch2_ops,
1242                 },
1243         },
1244 };
1245
1246 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1247         .halt_reg = 0x0844,
1248         .clkr = {
1249                 .enable_reg = 0x0844,
1250                 .enable_mask = BIT(0),
1251                 .hw.init = &(struct clk_init_data){
1252                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1253                         .parent_names = (const char *[]){
1254                                 "blsp1_qup5_spi_apps_clk_src",
1255                         },
1256                         .num_parents = 1,
1257                         .flags = CLK_SET_RATE_PARENT,
1258                         .ops = &clk_branch2_ops,
1259                 },
1260         },
1261 };
1262
1263 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1264         .halt_reg = 0x08c8,
1265         .clkr = {
1266                 .enable_reg = 0x08c8,
1267                 .enable_mask = BIT(0),
1268                 .hw.init = &(struct clk_init_data){
1269                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1270                         .parent_names = (const char *[]){
1271                                 "blsp1_qup6_i2c_apps_clk_src",
1272                         },
1273                         .num_parents = 1,
1274                         .flags = CLK_SET_RATE_PARENT,
1275                         .ops = &clk_branch2_ops,
1276                 },
1277         },
1278 };
1279
1280 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1281         .halt_reg = 0x08c4,
1282         .clkr = {
1283                 .enable_reg = 0x08c4,
1284                 .enable_mask = BIT(0),
1285                 .hw.init = &(struct clk_init_data){
1286                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1287                         .parent_names = (const char *[]){
1288                                 "blsp1_qup6_spi_apps_clk_src",
1289                         },
1290                         .num_parents = 1,
1291                         .flags = CLK_SET_RATE_PARENT,
1292                         .ops = &clk_branch2_ops,
1293                 },
1294         },
1295 };
1296
1297 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1298         .halt_reg = 0x0684,
1299         .clkr = {
1300                 .enable_reg = 0x0684,
1301                 .enable_mask = BIT(0),
1302                 .hw.init = &(struct clk_init_data){
1303                         .name = "gcc_blsp1_uart1_apps_clk",
1304                         .parent_names = (const char *[]){
1305                                 "blsp1_uart1_apps_clk_src",
1306                         },
1307                         .num_parents = 1,
1308                         .flags = CLK_SET_RATE_PARENT,
1309                         .ops = &clk_branch2_ops,
1310                 },
1311         },
1312 };
1313
1314 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1315         .halt_reg = 0x0704,
1316         .clkr = {
1317                 .enable_reg = 0x0704,
1318                 .enable_mask = BIT(0),
1319                 .hw.init = &(struct clk_init_data){
1320                         .name = "gcc_blsp1_uart2_apps_clk",
1321                         .parent_names = (const char *[]){
1322                                 "blsp1_uart2_apps_clk_src",
1323                         },
1324                         .num_parents = 1,
1325                         .flags = CLK_SET_RATE_PARENT,
1326                         .ops = &clk_branch2_ops,
1327                 },
1328         },
1329 };
1330
1331 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1332         .halt_reg = 0x0784,
1333         .clkr = {
1334                 .enable_reg = 0x0784,
1335                 .enable_mask = BIT(0),
1336                 .hw.init = &(struct clk_init_data){
1337                         .name = "gcc_blsp1_uart3_apps_clk",
1338                         .parent_names = (const char *[]){
1339                                 "blsp1_uart3_apps_clk_src",
1340                         },
1341                         .num_parents = 1,
1342                         .flags = CLK_SET_RATE_PARENT,
1343                         .ops = &clk_branch2_ops,
1344                 },
1345         },
1346 };
1347
1348 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1349         .halt_reg = 0x0804,
1350         .clkr = {
1351                 .enable_reg = 0x0804,
1352                 .enable_mask = BIT(0),
1353                 .hw.init = &(struct clk_init_data){
1354                         .name = "gcc_blsp1_uart4_apps_clk",
1355                         .parent_names = (const char *[]){
1356                                 "blsp1_uart4_apps_clk_src",
1357                         },
1358                         .num_parents = 1,
1359                         .flags = CLK_SET_RATE_PARENT,
1360                         .ops = &clk_branch2_ops,
1361                 },
1362         },
1363 };
1364
1365 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1366         .halt_reg = 0x0884,
1367         .clkr = {
1368                 .enable_reg = 0x0884,
1369                 .enable_mask = BIT(0),
1370                 .hw.init = &(struct clk_init_data){
1371                         .name = "gcc_blsp1_uart5_apps_clk",
1372                         .parent_names = (const char *[]){
1373                                 "blsp1_uart5_apps_clk_src",
1374                         },
1375                         .num_parents = 1,
1376                         .flags = CLK_SET_RATE_PARENT,
1377                         .ops = &clk_branch2_ops,
1378                 },
1379         },
1380 };
1381
1382 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1383         .halt_reg = 0x0904,
1384         .clkr = {
1385                 .enable_reg = 0x0904,
1386                 .enable_mask = BIT(0),
1387                 .hw.init = &(struct clk_init_data){
1388                         .name = "gcc_blsp1_uart6_apps_clk",
1389                         .parent_names = (const char *[]){
1390                                 "blsp1_uart6_apps_clk_src",
1391                         },
1392                         .num_parents = 1,
1393                         .flags = CLK_SET_RATE_PARENT,
1394                         .ops = &clk_branch2_ops,
1395                 },
1396         },
1397 };
1398
1399 static struct clk_branch gcc_blsp2_ahb_clk = {
1400         .halt_reg = 0x0944,
1401         .halt_check = BRANCH_HALT_VOTED,
1402         .clkr = {
1403                 .enable_reg = 0x1484,
1404                 .enable_mask = BIT(15),
1405                 .hw.init = &(struct clk_init_data){
1406                         .name = "gcc_blsp2_ahb_clk",
1407                         .parent_names = (const char *[]){
1408                                 "periph_noc_clk_src",
1409                         },
1410                         .num_parents = 1,
1411                         .ops = &clk_branch2_ops,
1412                 },
1413         },
1414 };
1415
1416 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1417         .halt_reg = 0x0988,
1418         .clkr = {
1419                 .enable_reg = 0x0988,
1420                 .enable_mask = BIT(0),
1421                 .hw.init = &(struct clk_init_data){
1422                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1423                         .parent_names = (const char *[]){
1424                                 "blsp2_qup1_i2c_apps_clk_src",
1425                         },
1426                         .num_parents = 1,
1427                         .flags = CLK_SET_RATE_PARENT,
1428                         .ops = &clk_branch2_ops,
1429                 },
1430         },
1431 };
1432
1433 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1434         .halt_reg = 0x0984,
1435         .clkr = {
1436                 .enable_reg = 0x0984,
1437                 .enable_mask = BIT(0),
1438                 .hw.init = &(struct clk_init_data){
1439                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1440                         .parent_names = (const char *[]){
1441                                 "blsp2_qup1_spi_apps_clk_src",
1442                         },
1443                         .num_parents = 1,
1444                         .flags = CLK_SET_RATE_PARENT,
1445                         .ops = &clk_branch2_ops,
1446                 },
1447         },
1448 };
1449
1450 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1451         .halt_reg = 0x0a08,
1452         .clkr = {
1453                 .enable_reg = 0x0a08,
1454                 .enable_mask = BIT(0),
1455                 .hw.init = &(struct clk_init_data){
1456                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1457                         .parent_names = (const char *[]){
1458                                 "blsp2_qup2_i2c_apps_clk_src",
1459                         },
1460                         .num_parents = 1,
1461                         .flags = CLK_SET_RATE_PARENT,
1462                         .ops = &clk_branch2_ops,
1463                 },
1464         },
1465 };
1466
1467 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1468         .halt_reg = 0x0a04,
1469         .clkr = {
1470                 .enable_reg = 0x0a04,
1471                 .enable_mask = BIT(0),
1472                 .hw.init = &(struct clk_init_data){
1473                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1474                         .parent_names = (const char *[]){
1475                                 "blsp2_qup2_spi_apps_clk_src",
1476                         },
1477                         .num_parents = 1,
1478                         .flags = CLK_SET_RATE_PARENT,
1479                         .ops = &clk_branch2_ops,
1480                 },
1481         },
1482 };
1483
1484 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1485         .halt_reg = 0x0a88,
1486         .clkr = {
1487                 .enable_reg = 0x0a88,
1488                 .enable_mask = BIT(0),
1489                 .hw.init = &(struct clk_init_data){
1490                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1491                         .parent_names = (const char *[]){
1492                                 "blsp2_qup3_i2c_apps_clk_src",
1493                         },
1494                         .num_parents = 1,
1495                         .flags = CLK_SET_RATE_PARENT,
1496                         .ops = &clk_branch2_ops,
1497                 },
1498         },
1499 };
1500
1501 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1502         .halt_reg = 0x0a84,
1503         .clkr = {
1504                 .enable_reg = 0x0a84,
1505                 .enable_mask = BIT(0),
1506                 .hw.init = &(struct clk_init_data){
1507                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1508                         .parent_names = (const char *[]){
1509                                 "blsp2_qup3_spi_apps_clk_src",
1510                         },
1511                         .num_parents = 1,
1512                         .flags = CLK_SET_RATE_PARENT,
1513                         .ops = &clk_branch2_ops,
1514                 },
1515         },
1516 };
1517
1518 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1519         .halt_reg = 0x0b08,
1520         .clkr = {
1521                 .enable_reg = 0x0b08,
1522                 .enable_mask = BIT(0),
1523                 .hw.init = &(struct clk_init_data){
1524                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1525                         .parent_names = (const char *[]){
1526                                 "blsp2_qup4_i2c_apps_clk_src",
1527                         },
1528                         .num_parents = 1,
1529                         .flags = CLK_SET_RATE_PARENT,
1530                         .ops = &clk_branch2_ops,
1531                 },
1532         },
1533 };
1534
1535 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1536         .halt_reg = 0x0b04,
1537         .clkr = {
1538                 .enable_reg = 0x0b04,
1539                 .enable_mask = BIT(0),
1540                 .hw.init = &(struct clk_init_data){
1541                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1542                         .parent_names = (const char *[]){
1543                                 "blsp2_qup4_spi_apps_clk_src",
1544                         },
1545                         .num_parents = 1,
1546                         .flags = CLK_SET_RATE_PARENT,
1547                         .ops = &clk_branch2_ops,
1548                 },
1549         },
1550 };
1551
1552 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1553         .halt_reg = 0x0b88,
1554         .clkr = {
1555                 .enable_reg = 0x0b88,
1556                 .enable_mask = BIT(0),
1557                 .hw.init = &(struct clk_init_data){
1558                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1559                         .parent_names = (const char *[]){
1560                                 "blsp2_qup5_i2c_apps_clk_src",
1561                         },
1562                         .num_parents = 1,
1563                         .flags = CLK_SET_RATE_PARENT,
1564                         .ops = &clk_branch2_ops,
1565                 },
1566         },
1567 };
1568
1569 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1570         .halt_reg = 0x0b84,
1571         .clkr = {
1572                 .enable_reg = 0x0b84,
1573                 .enable_mask = BIT(0),
1574                 .hw.init = &(struct clk_init_data){
1575                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1576                         .parent_names = (const char *[]){
1577                                 "blsp2_qup5_spi_apps_clk_src",
1578                         },
1579                         .num_parents = 1,
1580                         .flags = CLK_SET_RATE_PARENT,
1581                         .ops = &clk_branch2_ops,
1582                 },
1583         },
1584 };
1585
1586 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1587         .halt_reg = 0x0c08,
1588         .clkr = {
1589                 .enable_reg = 0x0c08,
1590                 .enable_mask = BIT(0),
1591                 .hw.init = &(struct clk_init_data){
1592                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1593                         .parent_names = (const char *[]){
1594                                 "blsp2_qup6_i2c_apps_clk_src",
1595                         },
1596                         .num_parents = 1,
1597                         .flags = CLK_SET_RATE_PARENT,
1598                         .ops = &clk_branch2_ops,
1599                 },
1600         },
1601 };
1602
1603 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1604         .halt_reg = 0x0c04,
1605         .clkr = {
1606                 .enable_reg = 0x0c04,
1607                 .enable_mask = BIT(0),
1608                 .hw.init = &(struct clk_init_data){
1609                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1610                         .parent_names = (const char *[]){
1611                                 "blsp2_qup6_spi_apps_clk_src",
1612                         },
1613                         .num_parents = 1,
1614                         .flags = CLK_SET_RATE_PARENT,
1615                         .ops = &clk_branch2_ops,
1616                 },
1617         },
1618 };
1619
1620 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1621         .halt_reg = 0x09c4,
1622         .clkr = {
1623                 .enable_reg = 0x09c4,
1624                 .enable_mask = BIT(0),
1625                 .hw.init = &(struct clk_init_data){
1626                         .name = "gcc_blsp2_uart1_apps_clk",
1627                         .parent_names = (const char *[]){
1628                                 "blsp2_uart1_apps_clk_src",
1629                         },
1630                         .num_parents = 1,
1631                         .flags = CLK_SET_RATE_PARENT,
1632                         .ops = &clk_branch2_ops,
1633                 },
1634         },
1635 };
1636
1637 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1638         .halt_reg = 0x0a44,
1639         .clkr = {
1640                 .enable_reg = 0x0a44,
1641                 .enable_mask = BIT(0),
1642                 .hw.init = &(struct clk_init_data){
1643                         .name = "gcc_blsp2_uart2_apps_clk",
1644                         .parent_names = (const char *[]){
1645                                 "blsp2_uart2_apps_clk_src",
1646                         },
1647                         .num_parents = 1,
1648                         .flags = CLK_SET_RATE_PARENT,
1649                         .ops = &clk_branch2_ops,
1650                 },
1651         },
1652 };
1653
1654 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1655         .halt_reg = 0x0ac4,
1656         .clkr = {
1657                 .enable_reg = 0x0ac4,
1658                 .enable_mask = BIT(0),
1659                 .hw.init = &(struct clk_init_data){
1660                         .name = "gcc_blsp2_uart3_apps_clk",
1661                         .parent_names = (const char *[]){
1662                                 "blsp2_uart3_apps_clk_src",
1663                         },
1664                         .num_parents = 1,
1665                         .flags = CLK_SET_RATE_PARENT,
1666                         .ops = &clk_branch2_ops,
1667                 },
1668         },
1669 };
1670
1671 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1672         .halt_reg = 0x0b44,
1673         .clkr = {
1674                 .enable_reg = 0x0b44,
1675                 .enable_mask = BIT(0),
1676                 .hw.init = &(struct clk_init_data){
1677                         .name = "gcc_blsp2_uart4_apps_clk",
1678                         .parent_names = (const char *[]){
1679                                 "blsp2_uart4_apps_clk_src",
1680                         },
1681                         .num_parents = 1,
1682                         .flags = CLK_SET_RATE_PARENT,
1683                         .ops = &clk_branch2_ops,
1684                 },
1685         },
1686 };
1687
1688 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1689         .halt_reg = 0x0bc4,
1690         .clkr = {
1691                 .enable_reg = 0x0bc4,
1692                 .enable_mask = BIT(0),
1693                 .hw.init = &(struct clk_init_data){
1694                         .name = "gcc_blsp2_uart5_apps_clk",
1695                         .parent_names = (const char *[]){
1696                                 "blsp2_uart5_apps_clk_src",
1697                         },
1698                         .num_parents = 1,
1699                         .flags = CLK_SET_RATE_PARENT,
1700                         .ops = &clk_branch2_ops,
1701                 },
1702         },
1703 };
1704
1705 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1706         .halt_reg = 0x0c44,
1707         .clkr = {
1708                 .enable_reg = 0x0c44,
1709                 .enable_mask = BIT(0),
1710                 .hw.init = &(struct clk_init_data){
1711                         .name = "gcc_blsp2_uart6_apps_clk",
1712                         .parent_names = (const char *[]){
1713                                 "blsp2_uart6_apps_clk_src",
1714                         },
1715                         .num_parents = 1,
1716                         .flags = CLK_SET_RATE_PARENT,
1717                         .ops = &clk_branch2_ops,
1718                 },
1719         },
1720 };
1721
1722 static struct clk_branch gcc_boot_rom_ahb_clk = {
1723         .halt_reg = 0x0e04,
1724         .halt_check = BRANCH_HALT_VOTED,
1725         .clkr = {
1726                 .enable_reg = 0x1484,
1727                 .enable_mask = BIT(10),
1728                 .hw.init = &(struct clk_init_data){
1729                         .name = "gcc_boot_rom_ahb_clk",
1730                         .parent_names = (const char *[]){
1731                                 "config_noc_clk_src",
1732                         },
1733                         .num_parents = 1,
1734                         .ops = &clk_branch2_ops,
1735                 },
1736         },
1737 };
1738
1739 static struct clk_branch gcc_ce1_ahb_clk = {
1740         .halt_reg = 0x104c,
1741         .halt_check = BRANCH_HALT_VOTED,
1742         .clkr = {
1743                 .enable_reg = 0x1484,
1744                 .enable_mask = BIT(3),
1745                 .hw.init = &(struct clk_init_data){
1746                         .name = "gcc_ce1_ahb_clk",
1747                         .parent_names = (const char *[]){
1748                                 "config_noc_clk_src",
1749                         },
1750                         .num_parents = 1,
1751                         .ops = &clk_branch2_ops,
1752                 },
1753         },
1754 };
1755
1756 static struct clk_branch gcc_ce1_axi_clk = {
1757         .halt_reg = 0x1048,
1758         .halt_check = BRANCH_HALT_VOTED,
1759         .clkr = {
1760                 .enable_reg = 0x1484,
1761                 .enable_mask = BIT(4),
1762                 .hw.init = &(struct clk_init_data){
1763                         .name = "gcc_ce1_axi_clk",
1764                         .parent_names = (const char *[]){
1765                                 "system_noc_clk_src",
1766                         },
1767                         .num_parents = 1,
1768                         .ops = &clk_branch2_ops,
1769                 },
1770         },
1771 };
1772
1773 static struct clk_branch gcc_ce1_clk = {
1774         .halt_reg = 0x1050,
1775         .halt_check = BRANCH_HALT_VOTED,
1776         .clkr = {
1777                 .enable_reg = 0x1484,
1778                 .enable_mask = BIT(5),
1779                 .hw.init = &(struct clk_init_data){
1780                         .name = "gcc_ce1_clk",
1781                         .parent_names = (const char *[]){
1782                                 "ce1_clk_src",
1783                         },
1784                         .num_parents = 1,
1785                         .flags = CLK_SET_RATE_PARENT,
1786                         .ops = &clk_branch2_ops,
1787                 },
1788         },
1789 };
1790
1791 static struct clk_branch gcc_ce2_ahb_clk = {
1792         .halt_reg = 0x108c,
1793         .halt_check = BRANCH_HALT_VOTED,
1794         .clkr = {
1795                 .enable_reg = 0x1484,
1796                 .enable_mask = BIT(0),
1797                 .hw.init = &(struct clk_init_data){
1798                         .name = "gcc_ce2_ahb_clk",
1799                         .parent_names = (const char *[]){
1800                                 "config_noc_clk_src",
1801                         },
1802                         .num_parents = 1,
1803                         .ops = &clk_branch2_ops,
1804                 },
1805         },
1806 };
1807
1808 static struct clk_branch gcc_ce2_axi_clk = {
1809         .halt_reg = 0x1088,
1810         .halt_check = BRANCH_HALT_VOTED,
1811         .clkr = {
1812                 .enable_reg = 0x1484,
1813                 .enable_mask = BIT(1),
1814                 .hw.init = &(struct clk_init_data){
1815                         .name = "gcc_ce2_axi_clk",
1816                         .parent_names = (const char *[]){
1817                                 "system_noc_clk_src",
1818                         },
1819                         .num_parents = 1,
1820                         .ops = &clk_branch2_ops,
1821                 },
1822         },
1823 };
1824
1825 static struct clk_branch gcc_ce2_clk = {
1826         .halt_reg = 0x1090,
1827         .halt_check = BRANCH_HALT_VOTED,
1828         .clkr = {
1829                 .enable_reg = 0x1484,
1830                 .enable_mask = BIT(2),
1831                 .hw.init = &(struct clk_init_data){
1832                         .name = "gcc_ce2_clk",
1833                         .parent_names = (const char *[]){
1834                                 "ce2_clk_src",
1835                         },
1836                         .num_parents = 1,
1837                         .flags = CLK_SET_RATE_PARENT,
1838                         .ops = &clk_branch2_ops,
1839                 },
1840         },
1841 };
1842
1843 static struct clk_branch gcc_gp1_clk = {
1844         .halt_reg = 0x1900,
1845         .clkr = {
1846                 .enable_reg = 0x1900,
1847                 .enable_mask = BIT(0),
1848                 .hw.init = &(struct clk_init_data){
1849                         .name = "gcc_gp1_clk",
1850                         .parent_names = (const char *[]){
1851                                 "gp1_clk_src",
1852                         },
1853                         .num_parents = 1,
1854                         .flags = CLK_SET_RATE_PARENT,
1855                         .ops = &clk_branch2_ops,
1856                 },
1857         },
1858 };
1859
1860 static struct clk_branch gcc_gp2_clk = {
1861         .halt_reg = 0x1940,
1862         .clkr = {
1863                 .enable_reg = 0x1940,
1864                 .enable_mask = BIT(0),
1865                 .hw.init = &(struct clk_init_data){
1866                         .name = "gcc_gp2_clk",
1867                         .parent_names = (const char *[]){
1868                                 "gp2_clk_src",
1869                         },
1870                         .num_parents = 1,
1871                         .flags = CLK_SET_RATE_PARENT,
1872                         .ops = &clk_branch2_ops,
1873                 },
1874         },
1875 };
1876
1877 static struct clk_branch gcc_gp3_clk = {
1878         .halt_reg = 0x1980,
1879         .clkr = {
1880                 .enable_reg = 0x1980,
1881                 .enable_mask = BIT(0),
1882                 .hw.init = &(struct clk_init_data){
1883                         .name = "gcc_gp3_clk",
1884                         .parent_names = (const char *[]){
1885                                 "gp3_clk_src",
1886                         },
1887                         .num_parents = 1,
1888                         .flags = CLK_SET_RATE_PARENT,
1889                         .ops = &clk_branch2_ops,
1890                 },
1891         },
1892 };
1893
1894 static struct clk_branch gcc_lpass_q6_axi_clk = {
1895         .halt_reg = 0x11c0,
1896         .clkr = {
1897                 .enable_reg = 0x11c0,
1898                 .enable_mask = BIT(0),
1899                 .hw.init = &(struct clk_init_data){
1900                         .name = "gcc_lpass_q6_axi_clk",
1901                         .parent_names = (const char *[]){
1902                                 "system_noc_clk_src",
1903                         },
1904                         .num_parents = 1,
1905                         .ops = &clk_branch2_ops,
1906                 },
1907         },
1908 };
1909
1910 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1911         .halt_reg = 0x024c,
1912         .clkr = {
1913                 .enable_reg = 0x024c,
1914                 .enable_mask = BIT(0),
1915                 .hw.init = &(struct clk_init_data){
1916                         .name = "gcc_mmss_noc_cfg_ahb_clk",
1917                         .parent_names = (const char *[]){
1918                                 "config_noc_clk_src",
1919                         },
1920                         .num_parents = 1,
1921                         .ops = &clk_branch2_ops,
1922                         .flags = CLK_IGNORE_UNUSED,
1923                 },
1924         },
1925 };
1926
1927 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
1928         .halt_reg = 0x0248,
1929         .clkr = {
1930                 .enable_reg = 0x0248,
1931                 .enable_mask = BIT(0),
1932                 .hw.init = &(struct clk_init_data){
1933                         .name = "gcc_ocmem_noc_cfg_ahb_clk",
1934                         .parent_names = (const char *[]){
1935                                 "config_noc_clk_src",
1936                         },
1937                         .num_parents = 1,
1938                         .ops = &clk_branch2_ops,
1939                 },
1940         },
1941 };
1942
1943 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1944         .halt_reg = 0x0280,
1945         .clkr = {
1946                 .enable_reg = 0x0280,
1947                 .enable_mask = BIT(0),
1948                 .hw.init = &(struct clk_init_data){
1949                         .name = "gcc_mss_cfg_ahb_clk",
1950                         .parent_names = (const char *[]){
1951                                 "config_noc_clk_src",
1952                         },
1953                         .num_parents = 1,
1954                         .ops = &clk_branch2_ops,
1955                 },
1956         },
1957 };
1958
1959 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1960         .halt_reg = 0x0284,
1961         .clkr = {
1962                 .enable_reg = 0x0284,
1963                 .enable_mask = BIT(0),
1964                 .hw.init = &(struct clk_init_data){
1965                         .name = "gcc_mss_q6_bimc_axi_clk",
1966                         .ops = &clk_branch2_ops,
1967                 },
1968         },
1969 };
1970
1971 static struct clk_branch gcc_pdm2_clk = {
1972         .halt_reg = 0x0ccc,
1973         .clkr = {
1974                 .enable_reg = 0x0ccc,
1975                 .enable_mask = BIT(0),
1976                 .hw.init = &(struct clk_init_data){
1977                         .name = "gcc_pdm2_clk",
1978                         .parent_names = (const char *[]){
1979                                 "pdm2_clk_src",
1980                         },
1981                         .num_parents = 1,
1982                         .flags = CLK_SET_RATE_PARENT,
1983                         .ops = &clk_branch2_ops,
1984                 },
1985         },
1986 };
1987
1988 static struct clk_branch gcc_pdm_ahb_clk = {
1989         .halt_reg = 0x0cc4,
1990         .clkr = {
1991                 .enable_reg = 0x0cc4,
1992                 .enable_mask = BIT(0),
1993                 .hw.init = &(struct clk_init_data){
1994                         .name = "gcc_pdm_ahb_clk",
1995                         .parent_names = (const char *[]){
1996                                 "periph_noc_clk_src",
1997                         },
1998                         .num_parents = 1,
1999                         .ops = &clk_branch2_ops,
2000                 },
2001         },
2002 };
2003
2004 static struct clk_branch gcc_prng_ahb_clk = {
2005         .halt_reg = 0x0d04,
2006         .halt_check = BRANCH_HALT_VOTED,
2007         .clkr = {
2008                 .enable_reg = 0x1484,
2009                 .enable_mask = BIT(13),
2010                 .hw.init = &(struct clk_init_data){
2011                         .name = "gcc_prng_ahb_clk",
2012                         .parent_names = (const char *[]){
2013                                 "periph_noc_clk_src",
2014                         },
2015                         .num_parents = 1,
2016                         .ops = &clk_branch2_ops,
2017                 },
2018         },
2019 };
2020
2021 static struct clk_branch gcc_sdcc1_ahb_clk = {
2022         .halt_reg = 0x04c8,
2023         .clkr = {
2024                 .enable_reg = 0x04c8,
2025                 .enable_mask = BIT(0),
2026                 .hw.init = &(struct clk_init_data){
2027                         .name = "gcc_sdcc1_ahb_clk",
2028                         .parent_names = (const char *[]){
2029                                 "periph_noc_clk_src",
2030                         },
2031                         .num_parents = 1,
2032                         .ops = &clk_branch2_ops,
2033                 },
2034         },
2035 };
2036
2037 static struct clk_branch gcc_sdcc1_apps_clk = {
2038         .halt_reg = 0x04c4,
2039         .clkr = {
2040                 .enable_reg = 0x04c4,
2041                 .enable_mask = BIT(0),
2042                 .hw.init = &(struct clk_init_data){
2043                         .name = "gcc_sdcc1_apps_clk",
2044                         .parent_names = (const char *[]){
2045                                 "sdcc1_apps_clk_src",
2046                         },
2047                         .num_parents = 1,
2048                         .flags = CLK_SET_RATE_PARENT,
2049                         .ops = &clk_branch2_ops,
2050                 },
2051         },
2052 };
2053
2054 static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2055         .halt_reg = 0x04e8,
2056         .clkr = {
2057                 .enable_reg = 0x04e8,
2058                 .enable_mask = BIT(0),
2059                 .hw.init = &(struct clk_init_data){
2060                         .name = "gcc_sdcc1_cdccal_ff_clk",
2061                         .parent_names = (const char *[]){
2062                                 "xo"
2063                         },
2064                         .num_parents = 1,
2065                         .ops = &clk_branch2_ops,
2066                 },
2067         },
2068 };
2069
2070 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2071         .halt_reg = 0x04e4,
2072         .clkr = {
2073                 .enable_reg = 0x04e4,
2074                 .enable_mask = BIT(0),
2075                 .hw.init = &(struct clk_init_data){
2076                         .name = "gcc_sdcc1_cdccal_sleep_clk",
2077                         .parent_names = (const char *[]){
2078                                 "sleep_clk_src"
2079                         },
2080                         .num_parents = 1,
2081                         .ops = &clk_branch2_ops,
2082                 },
2083         },
2084 };
2085
2086 static struct clk_branch gcc_sdcc2_ahb_clk = {
2087         .halt_reg = 0x0508,
2088         .clkr = {
2089                 .enable_reg = 0x0508,
2090                 .enable_mask = BIT(0),
2091                 .hw.init = &(struct clk_init_data){
2092                         .name = "gcc_sdcc2_ahb_clk",
2093                         .parent_names = (const char *[]){
2094                                 "periph_noc_clk_src",
2095                         },
2096                         .num_parents = 1,
2097                         .ops = &clk_branch2_ops,
2098                 },
2099         },
2100 };
2101
2102 static struct clk_branch gcc_sdcc2_apps_clk = {
2103         .halt_reg = 0x0504,
2104         .clkr = {
2105                 .enable_reg = 0x0504,
2106                 .enable_mask = BIT(0),
2107                 .hw.init = &(struct clk_init_data){
2108                         .name = "gcc_sdcc2_apps_clk",
2109                         .parent_names = (const char *[]){
2110                                 "sdcc2_apps_clk_src",
2111                         },
2112                         .num_parents = 1,
2113                         .flags = CLK_SET_RATE_PARENT,
2114                         .ops = &clk_branch2_ops,
2115                 },
2116         },
2117 };
2118
2119 static struct clk_branch gcc_sdcc3_ahb_clk = {
2120         .halt_reg = 0x0548,
2121         .clkr = {
2122                 .enable_reg = 0x0548,
2123                 .enable_mask = BIT(0),
2124                 .hw.init = &(struct clk_init_data){
2125                         .name = "gcc_sdcc3_ahb_clk",
2126                         .parent_names = (const char *[]){
2127                                 "periph_noc_clk_src",
2128                         },
2129                         .num_parents = 1,
2130                         .ops = &clk_branch2_ops,
2131                 },
2132         },
2133 };
2134
2135 static struct clk_branch gcc_sdcc3_apps_clk = {
2136         .halt_reg = 0x0544,
2137         .clkr = {
2138                 .enable_reg = 0x0544,
2139                 .enable_mask = BIT(0),
2140                 .hw.init = &(struct clk_init_data){
2141                         .name = "gcc_sdcc3_apps_clk",
2142                         .parent_names = (const char *[]){
2143                                 "sdcc3_apps_clk_src",
2144                         },
2145                         .num_parents = 1,
2146                         .flags = CLK_SET_RATE_PARENT,
2147                         .ops = &clk_branch2_ops,
2148                 },
2149         },
2150 };
2151
2152 static struct clk_branch gcc_sdcc4_ahb_clk = {
2153         .halt_reg = 0x0588,
2154         .clkr = {
2155                 .enable_reg = 0x0588,
2156                 .enable_mask = BIT(0),
2157                 .hw.init = &(struct clk_init_data){
2158                         .name = "gcc_sdcc4_ahb_clk",
2159                         .parent_names = (const char *[]){
2160                                 "periph_noc_clk_src",
2161                         },
2162                         .num_parents = 1,
2163                         .ops = &clk_branch2_ops,
2164                 },
2165         },
2166 };
2167
2168 static struct clk_branch gcc_sdcc4_apps_clk = {
2169         .halt_reg = 0x0584,
2170         .clkr = {
2171                 .enable_reg = 0x0584,
2172                 .enable_mask = BIT(0),
2173                 .hw.init = &(struct clk_init_data){
2174                         .name = "gcc_sdcc4_apps_clk",
2175                         .parent_names = (const char *[]){
2176                                 "sdcc4_apps_clk_src",
2177                         },
2178                         .num_parents = 1,
2179                         .flags = CLK_SET_RATE_PARENT,
2180                         .ops = &clk_branch2_ops,
2181                 },
2182         },
2183 };
2184
2185 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2186         .halt_reg = 0x0108,
2187         .clkr = {
2188                 .enable_reg = 0x0108,
2189                 .enable_mask = BIT(0),
2190                 .hw.init = &(struct clk_init_data){
2191                         .name = "gcc_sys_noc_usb3_axi_clk",
2192                         .parent_names = (const char *[]){
2193                                 "usb30_master_clk_src",
2194                         },
2195                         .num_parents = 1,
2196                         .flags = CLK_SET_RATE_PARENT,
2197                         .ops = &clk_branch2_ops,
2198                 },
2199         },
2200 };
2201
2202 static struct clk_branch gcc_tsif_ahb_clk = {
2203         .halt_reg = 0x0d84,
2204         .clkr = {
2205                 .enable_reg = 0x0d84,
2206                 .enable_mask = BIT(0),
2207                 .hw.init = &(struct clk_init_data){
2208                         .name = "gcc_tsif_ahb_clk",
2209                         .parent_names = (const char *[]){
2210                                 "periph_noc_clk_src",
2211                         },
2212                         .num_parents = 1,
2213                         .ops = &clk_branch2_ops,
2214                 },
2215         },
2216 };
2217
2218 static struct clk_branch gcc_tsif_ref_clk = {
2219         .halt_reg = 0x0d88,
2220         .clkr = {
2221                 .enable_reg = 0x0d88,
2222                 .enable_mask = BIT(0),
2223                 .hw.init = &(struct clk_init_data){
2224                         .name = "gcc_tsif_ref_clk",
2225                         .parent_names = (const char *[]){
2226                                 "tsif_ref_clk_src",
2227                         },
2228                         .num_parents = 1,
2229                         .flags = CLK_SET_RATE_PARENT,
2230                         .ops = &clk_branch2_ops,
2231                 },
2232         },
2233 };
2234
2235 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2236         .halt_reg = 0x04ac,
2237         .clkr = {
2238                 .enable_reg = 0x04ac,
2239                 .enable_mask = BIT(0),
2240                 .hw.init = &(struct clk_init_data){
2241                         .name = "gcc_usb2a_phy_sleep_clk",
2242                         .parent_names = (const char *[]){
2243                                 "sleep_clk_src",
2244                         },
2245                         .num_parents = 1,
2246                         .ops = &clk_branch2_ops,
2247                 },
2248         },
2249 };
2250
2251 static struct clk_branch gcc_usb2b_phy_sleep_clk = {
2252         .halt_reg = 0x04b4,
2253         .clkr = {
2254                 .enable_reg = 0x04b4,
2255                 .enable_mask = BIT(0),
2256                 .hw.init = &(struct clk_init_data){
2257                         .name = "gcc_usb2b_phy_sleep_clk",
2258                         .parent_names = (const char *[]){
2259                                 "sleep_clk_src",
2260                         },
2261                         .num_parents = 1,
2262                         .ops = &clk_branch2_ops,
2263                 },
2264         },
2265 };
2266
2267 static struct clk_branch gcc_usb30_master_clk = {
2268         .halt_reg = 0x03c8,
2269         .clkr = {
2270                 .enable_reg = 0x03c8,
2271                 .enable_mask = BIT(0),
2272                 .hw.init = &(struct clk_init_data){
2273                         .name = "gcc_usb30_master_clk",
2274                         .parent_names = (const char *[]){
2275                                 "usb30_master_clk_src",
2276                         },
2277                         .num_parents = 1,
2278                         .flags = CLK_SET_RATE_PARENT,
2279                         .ops = &clk_branch2_ops,
2280                 },
2281         },
2282 };
2283
2284 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2285         .halt_reg = 0x03d0,
2286         .clkr = {
2287                 .enable_reg = 0x03d0,
2288                 .enable_mask = BIT(0),
2289                 .hw.init = &(struct clk_init_data){
2290                         .name = "gcc_usb30_mock_utmi_clk",
2291                         .parent_names = (const char *[]){
2292                                 "usb30_mock_utmi_clk_src",
2293                         },
2294                         .num_parents = 1,
2295                         .flags = CLK_SET_RATE_PARENT,
2296                         .ops = &clk_branch2_ops,
2297                 },
2298         },
2299 };
2300
2301 static struct clk_branch gcc_usb30_sleep_clk = {
2302         .halt_reg = 0x03cc,
2303         .clkr = {
2304                 .enable_reg = 0x03cc,
2305                 .enable_mask = BIT(0),
2306                 .hw.init = &(struct clk_init_data){
2307                         .name = "gcc_usb30_sleep_clk",
2308                         .parent_names = (const char *[]){
2309                                 "sleep_clk_src",
2310                         },
2311                         .num_parents = 1,
2312                         .ops = &clk_branch2_ops,
2313                 },
2314         },
2315 };
2316
2317 static struct clk_branch gcc_usb_hs_ahb_clk = {
2318         .halt_reg = 0x0488,
2319         .clkr = {
2320                 .enable_reg = 0x0488,
2321                 .enable_mask = BIT(0),
2322                 .hw.init = &(struct clk_init_data){
2323                         .name = "gcc_usb_hs_ahb_clk",
2324                         .parent_names = (const char *[]){
2325                                 "periph_noc_clk_src",
2326                         },
2327                         .num_parents = 1,
2328                         .ops = &clk_branch2_ops,
2329                 },
2330         },
2331 };
2332
2333 static struct clk_branch gcc_usb_hs_system_clk = {
2334         .halt_reg = 0x0484,
2335         .clkr = {
2336                 .enable_reg = 0x0484,
2337                 .enable_mask = BIT(0),
2338                 .hw.init = &(struct clk_init_data){
2339                         .name = "gcc_usb_hs_system_clk",
2340                         .parent_names = (const char *[]){
2341                                 "usb_hs_system_clk_src",
2342                         },
2343                         .num_parents = 1,
2344                         .flags = CLK_SET_RATE_PARENT,
2345                         .ops = &clk_branch2_ops,
2346                 },
2347         },
2348 };
2349
2350 static struct clk_branch gcc_usb_hsic_ahb_clk = {
2351         .halt_reg = 0x0408,
2352         .clkr = {
2353                 .enable_reg = 0x0408,
2354                 .enable_mask = BIT(0),
2355                 .hw.init = &(struct clk_init_data){
2356                         .name = "gcc_usb_hsic_ahb_clk",
2357                         .parent_names = (const char *[]){
2358                                 "periph_noc_clk_src",
2359                         },
2360                         .num_parents = 1,
2361                         .ops = &clk_branch2_ops,
2362                 },
2363         },
2364 };
2365
2366 static struct clk_branch gcc_usb_hsic_clk = {
2367         .halt_reg = 0x0410,
2368         .clkr = {
2369                 .enable_reg = 0x0410,
2370                 .enable_mask = BIT(0),
2371                 .hw.init = &(struct clk_init_data){
2372                         .name = "gcc_usb_hsic_clk",
2373                         .parent_names = (const char *[]){
2374                                 "usb_hsic_clk_src",
2375                         },
2376                         .num_parents = 1,
2377                         .flags = CLK_SET_RATE_PARENT,
2378                         .ops = &clk_branch2_ops,
2379                 },
2380         },
2381 };
2382
2383 static struct clk_branch gcc_usb_hsic_io_cal_clk = {
2384         .halt_reg = 0x0414,
2385         .clkr = {
2386                 .enable_reg = 0x0414,
2387                 .enable_mask = BIT(0),
2388                 .hw.init = &(struct clk_init_data){
2389                         .name = "gcc_usb_hsic_io_cal_clk",
2390                         .parent_names = (const char *[]){
2391                                 "usb_hsic_io_cal_clk_src",
2392                         },
2393                         .num_parents = 1,
2394                         .flags = CLK_SET_RATE_PARENT,
2395                         .ops = &clk_branch2_ops,
2396                 },
2397         },
2398 };
2399
2400 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
2401         .halt_reg = 0x0418,
2402         .clkr = {
2403                 .enable_reg = 0x0418,
2404                 .enable_mask = BIT(0),
2405                 .hw.init = &(struct clk_init_data){
2406                         .name = "gcc_usb_hsic_io_cal_sleep_clk",
2407                         .parent_names = (const char *[]){
2408                                 "sleep_clk_src",
2409                         },
2410                         .num_parents = 1,
2411                         .ops = &clk_branch2_ops,
2412                 },
2413         },
2414 };
2415
2416 static struct clk_branch gcc_usb_hsic_system_clk = {
2417         .halt_reg = 0x040c,
2418         .clkr = {
2419                 .enable_reg = 0x040c,
2420                 .enable_mask = BIT(0),
2421                 .hw.init = &(struct clk_init_data){
2422                         .name = "gcc_usb_hsic_system_clk",
2423                         .parent_names = (const char *[]){
2424                                 "usb_hsic_system_clk_src",
2425                         },
2426                         .num_parents = 1,
2427                         .flags = CLK_SET_RATE_PARENT,
2428                         .ops = &clk_branch2_ops,
2429                 },
2430         },
2431 };
2432
2433 static struct gdsc usb_hs_hsic_gdsc = {
2434         .gdscr = 0x404,
2435         .pd = {
2436                 .name = "usb_hs_hsic",
2437         },
2438         .pwrsts = PWRSTS_OFF_ON,
2439 };
2440
2441 static struct clk_regmap *gcc_msm8974_clocks[] = {
2442         [GPLL0] = &gpll0.clkr,
2443         [GPLL0_VOTE] = &gpll0_vote,
2444         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2445         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2446         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2447         [GPLL1] = &gpll1.clkr,
2448         [GPLL1_VOTE] = &gpll1_vote,
2449         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2450         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2451         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2452         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2453         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2454         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2455         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2456         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2457         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2458         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2459         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2460         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2461         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2462         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2463         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2464         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2465         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2466         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2467         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2468         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2469         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2470         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2471         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2472         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2473         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2474         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2475         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2476         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2477         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2478         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2479         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2480         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2481         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2482         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2483         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2484         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2485         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2486         [CE1_CLK_SRC] = &ce1_clk_src.clkr,
2487         [CE2_CLK_SRC] = &ce2_clk_src.clkr,
2488         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2489         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2490         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2491         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2492         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2493         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2494         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2495         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2496         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2497         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2498         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2499         [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2500         [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2501         [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2502         [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2503         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2504         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2505         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2506         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2507         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2508         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2509         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2510         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2511         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2512         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2513         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2514         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2515         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2516         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2517         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2518         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2519         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2520         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2521         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2522         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2523         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2524         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2525         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2526         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2527         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2528         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2529         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2530         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2531         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2532         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2533         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2534         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2535         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2536         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2537         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2538         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2539         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2540         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2541         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2542         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2543         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2544         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2545         [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
2546         [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
2547         [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
2548         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2549         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2550         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2551         [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2552         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2553         [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
2554         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2555         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2556         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2557         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2558         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2559         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2560         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2561         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2562         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2563         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2564         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2565         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2566         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2567         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2568         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2569         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2570         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2571         [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
2572         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2573         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2574         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2575         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2576         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2577         [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2578         [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2579         [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2580         [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
2581         [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2582         [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
2583         [GPLL4] = NULL,
2584         [GPLL4_VOTE] = NULL,
2585         [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL,
2586         [GCC_SDCC1_CDCCAL_FF_CLK] = NULL,
2587 };
2588
2589 static const struct qcom_reset_map gcc_msm8974_resets[] = {
2590         [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2591         [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2592         [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2593         [GCC_IMEM_BCR] = { 0x0200 },
2594         [GCC_MMSS_BCR] = { 0x0240 },
2595         [GCC_QDSS_BCR] = { 0x0300 },
2596         [GCC_USB_30_BCR] = { 0x03c0 },
2597         [GCC_USB3_PHY_BCR] = { 0x03fc },
2598         [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2599         [GCC_USB_HS_BCR] = { 0x0480 },
2600         [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2601         [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2602         [GCC_SDCC1_BCR] = { 0x04c0 },
2603         [GCC_SDCC2_BCR] = { 0x0500 },
2604         [GCC_SDCC3_BCR] = { 0x0540 },
2605         [GCC_SDCC4_BCR] = { 0x0580 },
2606         [GCC_BLSP1_BCR] = { 0x05c0 },
2607         [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2608         [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2609         [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2610         [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2611         [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2612         [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2613         [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2614         [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2615         [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2616         [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2617         [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2618         [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2619         [GCC_BLSP2_BCR] = { 0x0940 },
2620         [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2621         [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2622         [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2623         [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2624         [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2625         [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2626         [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2627         [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2628         [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2629         [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2630         [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2631         [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2632         [GCC_PDM_BCR] = { 0x0cc0 },
2633         [GCC_BAM_DMA_BCR] = { 0x0d40 },
2634         [GCC_TSIF_BCR] = { 0x0d80 },
2635         [GCC_TCSR_BCR] = { 0x0dc0 },
2636         [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2637         [GCC_MSG_RAM_BCR] = { 0x0e40 },
2638         [GCC_TLMM_BCR] = { 0x0e80 },
2639         [GCC_MPM_BCR] = { 0x0ec0 },
2640         [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2641         [GCC_SPMI_BCR] = { 0x0fc0 },
2642         [GCC_SPDM_BCR] = { 0x1000 },
2643         [GCC_CE1_BCR] = { 0x1040 },
2644         [GCC_CE2_BCR] = { 0x1080 },
2645         [GCC_BIMC_BCR] = { 0x1100 },
2646         [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2647         [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2648         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2649         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2650         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2651         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2652         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2653         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2654         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2655         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2656         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2657         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2658         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2659         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2660         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2661         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2662         [GCC_DEHR_BCR] = { 0x1300 },
2663         [GCC_RBCPR_BCR] = { 0x1380 },
2664         [GCC_MSS_RESTART] = { 0x1680 },
2665         [GCC_LPASS_RESTART] = { 0x16c0 },
2666         [GCC_WCSS_RESTART] = { 0x1700 },
2667         [GCC_VENUS_RESTART] = { 0x1740 },
2668 };
2669
2670 static struct gdsc *gcc_msm8974_gdscs[] = {
2671         [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
2672 };
2673
2674 static const struct regmap_config gcc_msm8974_regmap_config = {
2675         .reg_bits       = 32,
2676         .reg_stride     = 4,
2677         .val_bits       = 32,
2678         .max_register   = 0x1fc0,
2679         .fast_io        = true,
2680 };
2681
2682 static const struct qcom_cc_desc gcc_msm8974_desc = {
2683         .config = &gcc_msm8974_regmap_config,
2684         .clks = gcc_msm8974_clocks,
2685         .num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
2686         .resets = gcc_msm8974_resets,
2687         .num_resets = ARRAY_SIZE(gcc_msm8974_resets),
2688         .gdscs = gcc_msm8974_gdscs,
2689         .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs),
2690 };
2691
2692 static const struct of_device_id gcc_msm8974_match_table[] = {
2693         { .compatible = "qcom,gcc-msm8974" },
2694         { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL },
2695         { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL },
2696         { }
2697 };
2698 MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
2699
2700 static void msm8974_pro_clock_override(void)
2701 {
2702         sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
2703         sdcc1_apps_clk_src_init.num_parents = 3;
2704         sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro;
2705         sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map;
2706
2707         gcc_msm8974_clocks[GPLL4] = &gpll4.clkr;
2708         gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote;
2709         gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] =
2710                 &gcc_sdcc1_cdccal_sleep_clk.clkr;
2711         gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] =
2712                 &gcc_sdcc1_cdccal_ff_clk.clkr;
2713 }
2714
2715 static int gcc_msm8974_probe(struct platform_device *pdev)
2716 {
2717         int ret;
2718         struct device *dev = &pdev->dev;
2719         bool pro;
2720         const struct of_device_id *id;
2721
2722         id = of_match_device(gcc_msm8974_match_table, dev);
2723         if (!id)
2724                 return -ENODEV;
2725         pro = !!(id->data);
2726
2727         if (pro)
2728                 msm8974_pro_clock_override();
2729
2730         ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
2731         if (ret)
2732                 return ret;
2733
2734         ret = qcom_cc_register_sleep_clk(dev);
2735         if (ret)
2736                 return ret;
2737
2738         return qcom_cc_probe(pdev, &gcc_msm8974_desc);
2739 }
2740
2741 static struct platform_driver gcc_msm8974_driver = {
2742         .probe          = gcc_msm8974_probe,
2743         .driver         = {
2744                 .name   = "gcc-msm8974",
2745                 .of_match_table = gcc_msm8974_match_table,
2746         },
2747 };
2748
2749 static int __init gcc_msm8974_init(void)
2750 {
2751         return platform_driver_register(&gcc_msm8974_driver);
2752 }
2753 core_initcall(gcc_msm8974_init);
2754
2755 static void __exit gcc_msm8974_exit(void)
2756 {
2757         platform_driver_unregister(&gcc_msm8974_driver);
2758 }
2759 module_exit(gcc_msm8974_exit);
2760
2761 MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver");
2762 MODULE_LICENSE("GPL v2");
2763 MODULE_ALIAS("platform:gcc-msm8974");