drivers/clk/qcom/gcc-msm8996.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  26
  27 #include "common.h"
  28 #include "clk-regmap.h"
  29 #include "clk-alpha-pll.h"
  30 #include "clk-rcg.h"
  31 #include "clk-branch.h"
  32 #include "reset.h"
  33 #include "gdsc.h"
  34
  35 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  36
  37 enum {
  38         P_XO,
  39         P_GPLL0,
  40         P_GPLL2,
  41         P_GPLL3,
  42         P_GPLL1,
  43         P_GPLL2_EARLY,
  44         P_GPLL0_EARLY_DIV,
  45         P_SLEEP_CLK,
  46         P_GPLL4,
  47         P_AUD_REF_CLK,
  48         P_GPLL1_EARLY_DIV
  49 };
  50
  51 static const struct parent_map gcc_sleep_clk_map[] = {
  52         { P_SLEEP_CLK, 5 }
  53 };
  54
  55 static const char * const gcc_sleep_clk[] = {
  56         "sleep_clk"
  57 };
  58
  59 static const struct parent_map gcc_xo_gpll0_map[] = {
  60         { P_XO, 0 },
  61         { P_GPLL0, 1 }
  62 };
  63
  64 static const char * const gcc_xo_gpll0[] = {
  65         "xo",
  66         "gpll0"
  67 };
  68
  69 static const struct parent_map gcc_xo_sleep_clk_map[] = {
  70         { P_XO, 0 },
  71         { P_SLEEP_CLK, 5 }
  72 };
  73
  74 static const char * const gcc_xo_sleep_clk[] = {
  75         "xo",
  76         "sleep_clk"
  77 };
  78
  79 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
  80         { P_XO, 0 },
  81         { P_GPLL0, 1 },
  82         { P_GPLL0_EARLY_DIV, 6 }
  83 };
  84
  85 static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
  86         "xo",
  87         "gpll0",
  88         "gpll0_early_div"
  89 };
  90
  91 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  92         { P_XO, 0 },
  93         { P_GPLL0, 1 },
  94         { P_GPLL4, 5 }
  95 };
  96
  97 static const char * const gcc_xo_gpll0_gpll4[] = {
  98         "xo",
  99         "gpll0",
 100         "gpll4"
 101 };
 102
 103 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
 104         { P_XO, 0 },
 105         { P_GPLL0, 1 },
 106         { P_AUD_REF_CLK, 2 }
 107 };
 108
 109 static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
 110         "xo",
 111         "gpll0",
 112         "aud_ref_clk"
 113 };
 114
 115 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
 116         { P_XO, 0 },
 117         { P_GPLL0, 1 },
 118         { P_SLEEP_CLK, 5 },
 119         { P_GPLL0_EARLY_DIV, 6 }
 120 };
 121
 122 static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
 123         "xo",
 124         "gpll0",
 125         "sleep_clk",
 126         "gpll0_early_div"
 127 };
 128
 129 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 130         { P_XO, 0 },
 131         { P_GPLL0, 1 },
 132         { P_GPLL4, 5 },
 133         { P_GPLL0_EARLY_DIV, 6 }
 134 };
 135
 136 static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 137         "xo",
 138         "gpll0",
 139         "gpll4",
 140         "gpll0_early_div"
 141 };
 142
 143 static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
 144         { P_XO, 0 },
 145         { P_GPLL0, 1 },
 146         { P_GPLL1_EARLY_DIV, 3 },
 147         { P_GPLL1, 4 },
 148         { P_GPLL4, 5 },
 149         { P_GPLL0_EARLY_DIV, 6 }
 150 };
 151
 152 static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
 153         "xo",
 154         "gpll0",
 155         "gpll1_early_div",
 156         "gpll1",
 157         "gpll4",
 158         "gpll0_early_div"
 159 };
 160
 161 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
 162         { P_XO, 0 },
 163         { P_GPLL0, 1 },
 164         { P_GPLL2, 2 },
 165         { P_GPLL3, 3 },
 166         { P_GPLL1, 4 },
 167         { P_GPLL2_EARLY, 5 },
 168         { P_GPLL0_EARLY_DIV, 6 }
 169 };
 170
 171 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
 172         "xo",
 173         "gpll0",
 174         "gpll2",
 175         "gpll3",
 176         "gpll1",
 177         "gpll2_early",
 178         "gpll0_early_div"
 179 };
 180
 181 static struct clk_fixed_factor xo = {
 182         .mult = 1,
 183         .div = 1,
 184         .hw.init = &(struct clk_init_data){
 185                 .name = "xo",
 186                 .parent_names = (const char *[]){ "xo_board" },
 187                 .num_parents = 1,
 188                 .ops = &clk_fixed_factor_ops,
 189         },
 190 };
 191
 192 static struct clk_alpha_pll gpll0_early = {
 193         .offset = 0x00000,
 194         .clkr = {
 195                 .enable_reg = 0x52000,
 196                 .enable_mask = BIT(0),
 197                 .hw.init = &(struct clk_init_data){
 198                         .name = "gpll0_early",
 199                         .parent_names = (const char *[]){ "xo" },
 200                         .num_parents = 1,
 201                         .ops = &clk_alpha_pll_ops,
 202                 },
 203         },
 204 };
 205
 206 static struct clk_fixed_factor gpll0_early_div = {
 207         .mult = 1,
 208         .div = 2,
 209         .hw.init = &(struct clk_init_data){
 210                 .name = "gpll0_early_div",
 211                 .parent_names = (const char *[]){ "gpll0_early" },
 212                 .num_parents = 1,
 213                 .ops = &clk_fixed_factor_ops,
 214         },
 215 };
 216
 217 static struct clk_alpha_pll_postdiv gpll0 = {
 218         .offset = 0x00000,
 219         .clkr.hw.init = &(struct clk_init_data){
 220                 .name = "gpll0",
 221                 .parent_names = (const char *[]){ "gpll0_early" },
 222                 .num_parents = 1,
 223                 .ops = &clk_alpha_pll_postdiv_ops,
 224         },
 225 };
 226
 227 static struct clk_alpha_pll gpll4_early = {
 228         .offset = 0x77000,
 229         .clkr = {
 230                 .enable_reg = 0x52000,
 231                 .enable_mask = BIT(4),
 232                 .hw.init = &(struct clk_init_data){
 233                         .name = "gpll4_early",
 234                         .parent_names = (const char *[]){ "xo" },
 235                         .num_parents = 1,
 236                         .ops = &clk_alpha_pll_ops,
 237                 },
 238         },
 239 };
 240
 241 static struct clk_alpha_pll_postdiv gpll4 = {
 242         .offset = 0x77000,
 243         .clkr.hw.init = &(struct clk_init_data){
 244                 .name = "gpll4",
 245                 .parent_names = (const char *[]){ "gpll4_early" },
 246                 .num_parents = 1,
 247                 .ops = &clk_alpha_pll_postdiv_ops,
 248         },
 249 };
 250
 251 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 252         F(19200000, P_XO, 1, 0, 0),
 253         F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
 254         F(100000000, P_GPLL0, 6, 0, 0),
 255         F(150000000, P_GPLL0, 4, 0, 0),
 256         F(200000000, P_GPLL0, 3, 0, 0),
 257         F(240000000, P_GPLL0, 2.5, 0, 0),
 258         { }
 259 };
 260
 261 static struct clk_rcg2 system_noc_clk_src = {
 262         .cmd_rcgr = 0x0401c,
 263         .hid_width = 5,
 264         .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
 265         .freq_tbl = ftbl_system_noc_clk_src,
 266         .clkr.hw.init = &(struct clk_init_data){
 267                 .name = "system_noc_clk_src",
 268                 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
 269                 .num_parents = 7,
 270                 .ops = &clk_rcg2_ops,
 271         },
 272 };
 273
 274 static const struct freq_tbl ftbl_config_noc_clk_src[] = {
 275         F(19200000, P_XO, 1, 0, 0),
 276         F(37500000, P_GPLL0, 16, 0, 0),
 277         F(75000000, P_GPLL0, 8, 0, 0),
 278         { }
 279 };
 280
 281 static struct clk_rcg2 config_noc_clk_src = {
 282         .cmd_rcgr = 0x0500c,
 283         .hid_width = 5,
 284         .parent_map = gcc_xo_gpll0_map,
 285         .freq_tbl = ftbl_config_noc_clk_src,
 286         .clkr.hw.init = &(struct clk_init_data){
 287                 .name = "config_noc_clk_src",
 288                 .parent_names = gcc_xo_gpll0,
 289                 .num_parents = 2,
 290                 .ops = &clk_rcg2_ops,
 291         },
 292 };
 293
 294 static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
 295         F(19200000, P_XO, 1, 0, 0),
 296         F(37500000, P_GPLL0, 16, 0, 0),
 297         F(50000000, P_GPLL0, 12, 0, 0),
 298         F(75000000, P_GPLL0, 8, 0, 0),
 299         F(100000000, P_GPLL0, 6, 0, 0),
 300         { }
 301 };
 302
 303 static struct clk_rcg2 periph_noc_clk_src = {
 304         .cmd_rcgr = 0x06014,
 305         .hid_width = 5,
 306         .parent_map = gcc_xo_gpll0_map,
 307         .freq_tbl = ftbl_periph_noc_clk_src,
 308         .clkr.hw.init = &(struct clk_init_data){
 309                 .name = "periph_noc_clk_src",
 310                 .parent_names = gcc_xo_gpll0,
 311                 .num_parents = 2,
 312                 .ops = &clk_rcg2_ops,
 313         },
 314 };
 315
 316 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
 317         F(19200000, P_XO, 1, 0, 0),
 318         F(120000000, P_GPLL0, 5, 0, 0),
 319         F(150000000, P_GPLL0, 4, 0, 0),
 320         { }
 321 };
 322
 323 static struct clk_rcg2 usb30_master_clk_src = {
 324         .cmd_rcgr = 0x0f014,
 325         .mnd_width = 8,
 326         .hid_width = 5,
 327         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 328         .freq_tbl = ftbl_usb30_master_clk_src,
 329         .clkr.hw.init = &(struct clk_init_data){
 330                 .name = "usb30_master_clk_src",
 331                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 332                 .num_parents = 3,
 333                 .ops = &clk_rcg2_ops,
 334         },
 335 };
 336
 337 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 338         F(19200000, P_XO, 1, 0, 0),
 339         { }
 340 };
 341
 342 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 343         .cmd_rcgr = 0x0f028,
 344         .hid_width = 5,
 345         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 346         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 347         .clkr.hw.init = &(struct clk_init_data){
 348                 .name = "usb30_mock_utmi_clk_src",
 349                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 350                 .num_parents = 3,
 351                 .ops = &clk_rcg2_ops,
 352         },
 353 };
 354
 355 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
 356         F(1200000, P_XO, 16, 0, 0),
 357         { }
 358 };
 359
 360 static struct clk_rcg2 usb3_phy_aux_clk_src = {
 361         .cmd_rcgr = 0x5000c,
 362         .hid_width = 5,
 363         .parent_map = gcc_xo_sleep_clk_map,
 364         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
 365         .clkr.hw.init = &(struct clk_init_data){
 366                 .name = "usb3_phy_aux_clk_src",
 367                 .parent_names = gcc_xo_sleep_clk,
 368                 .num_parents = 2,
 369                 .ops = &clk_rcg2_ops,
 370         },
 371 };
 372
 373 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
 374         F(120000000, P_GPLL0, 5, 0, 0),
 375         { }
 376 };
 377
 378 static struct clk_rcg2 usb20_master_clk_src = {
 379         .cmd_rcgr = 0x12010,
 380         .mnd_width = 8,
 381         .hid_width = 5,
 382         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 383         .freq_tbl = ftbl_usb20_master_clk_src,
 384         .clkr.hw.init = &(struct clk_init_data){
 385                 .name = "usb20_master_clk_src",
 386                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 387                 .num_parents = 3,
 388                 .ops = &clk_rcg2_ops,
 389         },
 390 };
 391
 392 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 393         .cmd_rcgr = 0x12024,
 394         .hid_width = 5,
 395         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 396         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 397         .clkr.hw.init = &(struct clk_init_data){
 398                 .name = "usb20_mock_utmi_clk_src",
 399                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 400                 .num_parents = 3,
 401                 .ops = &clk_rcg2_ops,
 402         },
 403 };
 404
 405 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 406         F(144000, P_XO, 16, 3, 25),
 407         F(400000, P_XO, 12, 1, 4),
 408         F(20000000, P_GPLL0, 15, 1, 2),
 409         F(25000000, P_GPLL0, 12, 1, 2),
 410         F(50000000, P_GPLL0, 12, 0, 0),
 411         F(96000000, P_GPLL4, 4, 0, 0),
 412         F(192000000, P_GPLL4, 2, 0, 0),
 413         F(384000000, P_GPLL4, 1, 0, 0),
 414         { }
 415 };
 416
 417 static struct clk_rcg2 sdcc1_apps_clk_src = {
 418         .cmd_rcgr = 0x13010,
 419         .mnd_width = 8,
 420         .hid_width = 5,
 421         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 422         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 423         .clkr.hw.init = &(struct clk_init_data){
 424                 .name = "sdcc1_apps_clk_src",
 425                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 426                 .num_parents = 4,
 427                 .ops = &clk_rcg2_floor_ops,
 428         },
 429 };
 430
 431 static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
 432         F(19200000, P_XO, 1, 0, 0),
 433         F(150000000, P_GPLL0, 4, 0, 0),
 434         F(300000000, P_GPLL0, 2, 0, 0),
 435         { }
 436 };
 437
 438 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 439         .cmd_rcgr = 0x13024,
 440         .hid_width = 5,
 441         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 442         .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 443         .clkr.hw.init = &(struct clk_init_data){
 444                 .name = "sdcc1_ice_core_clk_src",
 445                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 446                 .num_parents = 4,
 447                 .ops = &clk_rcg2_ops,
 448         },
 449 };
 450
 451 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
 452         F(144000, P_XO, 16, 3, 25),
 453         F(400000, P_XO, 12, 1, 4),
 454         F(20000000, P_GPLL0, 15, 1, 2),
 455         F(25000000, P_GPLL0, 12, 1, 2),
 456         F(50000000, P_GPLL0, 12, 0, 0),
 457         F(100000000, P_GPLL0, 6, 0, 0),
 458         F(200000000, P_GPLL0, 3, 0, 0),
 459         { }
 460 };
 461
 462 static struct clk_rcg2 sdcc2_apps_clk_src = {
 463         .cmd_rcgr = 0x14010,
 464         .mnd_width = 8,
 465         .hid_width = 5,
 466         .parent_map = gcc_xo_gpll0_gpll4_map,
 467         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 468         .clkr.hw.init = &(struct clk_init_data){
 469                 .name = "sdcc2_apps_clk_src",
 470                 .parent_names = gcc_xo_gpll0_gpll4,
 471                 .num_parents = 3,
 472                 .ops = &clk_rcg2_floor_ops,
 473         },
 474 };
 475
 476 static struct clk_rcg2 sdcc3_apps_clk_src = {
 477         .cmd_rcgr = 0x15010,
 478         .mnd_width = 8,
 479         .hid_width = 5,
 480         .parent_map = gcc_xo_gpll0_gpll4_map,
 481         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 482         .clkr.hw.init = &(struct clk_init_data){
 483                 .name = "sdcc3_apps_clk_src",
 484                 .parent_names = gcc_xo_gpll0_gpll4,
 485                 .num_parents = 3,
 486                 .ops = &clk_rcg2_floor_ops,
 487         },
 488 };
 489
 490 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
 491         F(144000, P_XO, 16, 3, 25),
 492         F(400000, P_XO, 12, 1, 4),
 493         F(20000000, P_GPLL0, 15, 1, 2),
 494         F(25000000, P_GPLL0, 12, 1, 2),
 495         F(50000000, P_GPLL0, 12, 0, 0),
 496         F(100000000, P_GPLL0, 6, 0, 0),
 497         { }
 498 };
 499
 500 static struct clk_rcg2 sdcc4_apps_clk_src = {
 501         .cmd_rcgr = 0x16010,
 502         .mnd_width = 8,
 503         .hid_width = 5,
 504         .parent_map = gcc_xo_gpll0_map,
 505         .freq_tbl = ftbl_sdcc4_apps_clk_src,
 506         .clkr.hw.init = &(struct clk_init_data){
 507                 .name = "sdcc4_apps_clk_src",
 508                 .parent_names = gcc_xo_gpll0,
 509                 .num_parents = 2,
 510                 .ops = &clk_rcg2_floor_ops,
 511         },
 512 };
 513
 514 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 515         F(960000, P_XO, 10, 1, 2),
 516         F(4800000, P_XO, 4, 0, 0),
 517         F(9600000, P_XO, 2, 0, 0),
 518         F(15000000, P_GPLL0, 10, 1, 4),
 519         F(19200000, P_XO, 1, 0, 0),
 520         F(25000000, P_GPLL0, 12, 1, 2),
 521         F(50000000, P_GPLL0, 12, 0, 0),
 522         { }
 523 };
 524
 525 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 526         .cmd_rcgr = 0x1900c,
 527         .mnd_width = 8,
 528         .hid_width = 5,
 529         .parent_map = gcc_xo_gpll0_map,
 530         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 531         .clkr.hw.init = &(struct clk_init_data){
 532                 .name = "blsp1_qup1_spi_apps_clk_src",
 533                 .parent_names = gcc_xo_gpll0,
 534                 .num_parents = 2,
 535                 .ops = &clk_rcg2_ops,
 536         },
 537 };
 538
 539 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 540         F(19200000, P_XO, 1, 0, 0),
 541         F(50000000, P_GPLL0, 12, 0, 0),
 542         { }
 543 };
 544
 545 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 546         .cmd_rcgr = 0x19020,
 547         .hid_width = 5,
 548         .parent_map = gcc_xo_gpll0_map,
 549         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 550         .clkr.hw.init = &(struct clk_init_data){
 551                 .name = "blsp1_qup1_i2c_apps_clk_src",
 552                 .parent_names = gcc_xo_gpll0,
 553                 .num_parents = 2,
 554                 .ops = &clk_rcg2_ops,
 555         },
 556 };
 557
 558 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 559         F(3686400, P_GPLL0, 1, 96, 15625),
 560         F(7372800, P_GPLL0, 1, 192, 15625),
 561         F(14745600, P_GPLL0, 1, 384, 15625),
 562         F(16000000, P_GPLL0, 5, 2, 15),
 563         F(19200000, P_XO, 1, 0, 0),
 564         F(24000000, P_GPLL0, 5, 1, 5),
 565         F(32000000, P_GPLL0, 1, 4, 75),
 566         F(40000000, P_GPLL0, 15, 0, 0),
 567         F(46400000, P_GPLL0, 1, 29, 375),
 568         F(48000000, P_GPLL0, 12.5, 0, 0),
 569         F(51200000, P_GPLL0, 1, 32, 375),
 570         F(56000000, P_GPLL0, 1, 7, 75),
 571         F(58982400, P_GPLL0, 1, 1536, 15625),
 572         F(60000000, P_GPLL0, 10, 0, 0),
 573         F(63157895, P_GPLL0, 9.5, 0, 0),
 574         { }
 575 };
 576
 577 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 578         .cmd_rcgr = 0x1a00c,
 579         .mnd_width = 16,
 580         .hid_width = 5,
 581         .parent_map = gcc_xo_gpll0_map,
 582         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 583         .clkr.hw.init = &(struct clk_init_data){
 584                 .name = "blsp1_uart1_apps_clk_src",
 585                 .parent_names = gcc_xo_gpll0,
 586                 .num_parents = 2,
 587                 .ops = &clk_rcg2_ops,
 588         },
 589 };
 590
 591 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 592         .cmd_rcgr = 0x1b00c,
 593         .mnd_width = 8,
 594         .hid_width = 5,
 595         .parent_map = gcc_xo_gpll0_map,
 596         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 597         .clkr.hw.init = &(struct clk_init_data){
 598                 .name = "blsp1_qup2_spi_apps_clk_src",
 599                 .parent_names = gcc_xo_gpll0,
 600                 .num_parents = 2,
 601                 .ops = &clk_rcg2_ops,
 602         },
 603 };
 604
 605 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 606         .cmd_rcgr = 0x1b020,
 607         .hid_width = 5,
 608         .parent_map = gcc_xo_gpll0_map,
 609         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 610         .clkr.hw.init = &(struct clk_init_data){
 611                 .name = "blsp1_qup2_i2c_apps_clk_src",
 612                 .parent_names = gcc_xo_gpll0,
 613                 .num_parents = 2,
 614                 .ops = &clk_rcg2_ops,
 615         },
 616 };
 617
 618 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 619         .cmd_rcgr = 0x1c00c,
 620         .mnd_width = 16,
 621         .hid_width = 5,
 622         .parent_map = gcc_xo_gpll0_map,
 623         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 624         .clkr.hw.init = &(struct clk_init_data){
 625                 .name = "blsp1_uart2_apps_clk_src",
 626                 .parent_names = gcc_xo_gpll0,
 627                 .num_parents = 2,
 628                 .ops = &clk_rcg2_ops,
 629         },
 630 };
 631
 632 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 633         .cmd_rcgr = 0x1d00c,
 634         .mnd_width = 8,
 635         .hid_width = 5,
 636         .parent_map = gcc_xo_gpll0_map,
 637         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 638         .clkr.hw.init = &(struct clk_init_data){
 639                 .name = "blsp1_qup3_spi_apps_clk_src",
 640                 .parent_names = gcc_xo_gpll0,
 641                 .num_parents = 2,
 642                 .ops = &clk_rcg2_ops,
 643         },
 644 };
 645
 646 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 647         .cmd_rcgr = 0x1d020,
 648         .hid_width = 5,
 649         .parent_map = gcc_xo_gpll0_map,
 650         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 651         .clkr.hw.init = &(struct clk_init_data){
 652                 .name = "blsp1_qup3_i2c_apps_clk_src",
 653                 .parent_names = gcc_xo_gpll0,
 654                 .num_parents = 2,
 655                 .ops = &clk_rcg2_ops,
 656         },
 657 };
 658
 659 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 660         .cmd_rcgr = 0x1e00c,
 661         .mnd_width = 16,
 662         .hid_width = 5,
 663         .parent_map = gcc_xo_gpll0_map,
 664         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 665         .clkr.hw.init = &(struct clk_init_data){
 666                 .name = "blsp1_uart3_apps_clk_src",
 667                 .parent_names = gcc_xo_gpll0,
 668                 .num_parents = 2,
 669                 .ops = &clk_rcg2_ops,
 670         },
 671 };
 672
 673 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 674         .cmd_rcgr = 0x1f00c,
 675         .mnd_width = 8,
 676         .hid_width = 5,
 677         .parent_map = gcc_xo_gpll0_map,
 678         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 679         .clkr.hw.init = &(struct clk_init_data){
 680                 .name = "blsp1_qup4_spi_apps_clk_src",
 681                 .parent_names = gcc_xo_gpll0,
 682                 .num_parents = 2,
 683                 .ops = &clk_rcg2_ops,
 684         },
 685 };
 686
 687 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 688         .cmd_rcgr = 0x1f020,
 689         .hid_width = 5,
 690         .parent_map = gcc_xo_gpll0_map,
 691         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 692         .clkr.hw.init = &(struct clk_init_data){
 693                 .name = "blsp1_qup4_i2c_apps_clk_src",
 694                 .parent_names = gcc_xo_gpll0,
 695                 .num_parents = 2,
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 701         .cmd_rcgr = 0x2000c,
 702         .mnd_width = 16,
 703         .hid_width = 5,
 704         .parent_map = gcc_xo_gpll0_map,
 705         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 706         .clkr.hw.init = &(struct clk_init_data){
 707                 .name = "blsp1_uart4_apps_clk_src",
 708                 .parent_names = gcc_xo_gpll0,
 709                 .num_parents = 2,
 710                 .ops = &clk_rcg2_ops,
 711         },
 712 };
 713
 714 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 715         .cmd_rcgr = 0x2100c,
 716         .mnd_width = 8,
 717         .hid_width = 5,
 718         .parent_map = gcc_xo_gpll0_map,
 719         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 720         .clkr.hw.init = &(struct clk_init_data){
 721                 .name = "blsp1_qup5_spi_apps_clk_src",
 722                 .parent_names = gcc_xo_gpll0,
 723                 .num_parents = 2,
 724                 .ops = &clk_rcg2_ops,
 725         },
 726 };
 727
 728 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 729         .cmd_rcgr = 0x21020,
 730         .hid_width = 5,
 731         .parent_map = gcc_xo_gpll0_map,
 732         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 733         .clkr.hw.init = &(struct clk_init_data){
 734                 .name = "blsp1_qup5_i2c_apps_clk_src",
 735                 .parent_names = gcc_xo_gpll0,
 736                 .num_parents = 2,
 737                 .ops = &clk_rcg2_ops,
 738         },
 739 };
 740
 741 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 742         .cmd_rcgr = 0x2200c,
 743         .mnd_width = 16,
 744         .hid_width = 5,
 745         .parent_map = gcc_xo_gpll0_map,
 746         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 747         .clkr.hw.init = &(struct clk_init_data){
 748                 .name = "blsp1_uart5_apps_clk_src",
 749                 .parent_names = gcc_xo_gpll0,
 750                 .num_parents = 2,
 751                 .ops = &clk_rcg2_ops,
 752         },
 753 };
 754
 755 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 756         .cmd_rcgr = 0x2300c,
 757         .mnd_width = 8,
 758         .hid_width = 5,
 759         .parent_map = gcc_xo_gpll0_map,
 760         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 761         .clkr.hw.init = &(struct clk_init_data){
 762                 .name = "blsp1_qup6_spi_apps_clk_src",
 763                 .parent_names = gcc_xo_gpll0,
 764                 .num_parents = 2,
 765                 .ops = &clk_rcg2_ops,
 766         },
 767 };
 768
 769 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 770         .cmd_rcgr = 0x23020,
 771         .hid_width = 5,
 772         .parent_map = gcc_xo_gpll0_map,
 773         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 774         .clkr.hw.init = &(struct clk_init_data){
 775                 .name = "blsp1_qup6_i2c_apps_clk_src",
 776                 .parent_names = gcc_xo_gpll0,
 777                 .num_parents = 2,
 778                 .ops = &clk_rcg2_ops,
 779         },
 780 };
 781
 782 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 783         .cmd_rcgr = 0x2400c,
 784         .mnd_width = 16,
 785         .hid_width = 5,
 786         .parent_map = gcc_xo_gpll0_map,
 787         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 788         .clkr.hw.init = &(struct clk_init_data){
 789                 .name = "blsp1_uart6_apps_clk_src",
 790                 .parent_names = gcc_xo_gpll0,
 791                 .num_parents = 2,
 792                 .ops = &clk_rcg2_ops,
 793         },
 794 };
 795
 796 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 797         .cmd_rcgr = 0x2600c,
 798         .mnd_width = 8,
 799         .hid_width = 5,
 800         .parent_map = gcc_xo_gpll0_map,
 801         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 802         .clkr.hw.init = &(struct clk_init_data){
 803                 .name = "blsp2_qup1_spi_apps_clk_src",
 804                 .parent_names = gcc_xo_gpll0,
 805                 .num_parents = 2,
 806                 .ops = &clk_rcg2_ops,
 807         },
 808 };
 809
 810 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 811         .cmd_rcgr = 0x26020,
 812         .hid_width = 5,
 813         .parent_map = gcc_xo_gpll0_map,
 814         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 815         .clkr.hw.init = &(struct clk_init_data){
 816                 .name = "blsp2_qup1_i2c_apps_clk_src",
 817                 .parent_names = gcc_xo_gpll0,
 818                 .num_parents = 2,
 819                 .ops = &clk_rcg2_ops,
 820         },
 821 };
 822
 823 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 824         .cmd_rcgr = 0x2700c,
 825         .mnd_width = 16,
 826         .hid_width = 5,
 827         .parent_map = gcc_xo_gpll0_map,
 828         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 829         .clkr.hw.init = &(struct clk_init_data){
 830                 .name = "blsp2_uart1_apps_clk_src",
 831                 .parent_names = gcc_xo_gpll0,
 832                 .num_parents = 2,
 833                 .ops = &clk_rcg2_ops,
 834         },
 835 };
 836
 837 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 838         .cmd_rcgr = 0x2800c,
 839         .mnd_width = 8,
 840         .hid_width = 5,
 841         .parent_map = gcc_xo_gpll0_map,
 842         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 843         .clkr.hw.init = &(struct clk_init_data){
 844                 .name = "blsp2_qup2_spi_apps_clk_src",
 845                 .parent_names = gcc_xo_gpll0,
 846                 .num_parents = 2,
 847                 .ops = &clk_rcg2_ops,
 848         },
 849 };
 850
 851 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 852         .cmd_rcgr = 0x28020,
 853         .hid_width = 5,
 854         .parent_map = gcc_xo_gpll0_map,
 855         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 856         .clkr.hw.init = &(struct clk_init_data){
 857                 .name = "blsp2_qup2_i2c_apps_clk_src",
 858                 .parent_names = gcc_xo_gpll0,
 859                 .num_parents = 2,
 860                 .ops = &clk_rcg2_ops,
 861         },
 862 };
 863
 864 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 865         .cmd_rcgr = 0x2900c,
 866         .mnd_width = 16,
 867         .hid_width = 5,
 868         .parent_map = gcc_xo_gpll0_map,
 869         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 870         .clkr.hw.init = &(struct clk_init_data){
 871                 .name = "blsp2_uart2_apps_clk_src",
 872                 .parent_names = gcc_xo_gpll0,
 873                 .num_parents = 2,
 874                 .ops = &clk_rcg2_ops,
 875         },
 876 };
 877
 878 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 879         .cmd_rcgr = 0x2a00c,
 880         .mnd_width = 8,
 881         .hid_width = 5,
 882         .parent_map = gcc_xo_gpll0_map,
 883         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 884         .clkr.hw.init = &(struct clk_init_data){
 885                 .name = "blsp2_qup3_spi_apps_clk_src",
 886                 .parent_names = gcc_xo_gpll0,
 887                 .num_parents = 2,
 888                 .ops = &clk_rcg2_ops,
 889         },
 890 };
 891
 892 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 893         .cmd_rcgr = 0x2a020,
 894         .hid_width = 5,
 895         .parent_map = gcc_xo_gpll0_map,
 896         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 897         .clkr.hw.init = &(struct clk_init_data){
 898                 .name = "blsp2_qup3_i2c_apps_clk_src",
 899                 .parent_names = gcc_xo_gpll0,
 900                 .num_parents = 2,
 901                 .ops = &clk_rcg2_ops,
 902         },
 903 };
 904
 905 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 906         .cmd_rcgr = 0x2b00c,
 907         .mnd_width = 16,
 908         .hid_width = 5,
 909         .parent_map = gcc_xo_gpll0_map,
 910         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 911         .clkr.hw.init = &(struct clk_init_data){
 912                 .name = "blsp2_uart3_apps_clk_src",
 913                 .parent_names = gcc_xo_gpll0,
 914                 .num_parents = 2,
 915                 .ops = &clk_rcg2_ops,
 916         },
 917 };
 918
 919 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 920         .cmd_rcgr = 0x2c00c,
 921         .mnd_width = 8,
 922         .hid_width = 5,
 923         .parent_map = gcc_xo_gpll0_map,
 924         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 925         .clkr.hw.init = &(struct clk_init_data){
 926                 .name = "blsp2_qup4_spi_apps_clk_src",
 927                 .parent_names = gcc_xo_gpll0,
 928                 .num_parents = 2,
 929                 .ops = &clk_rcg2_ops,
 930         },
 931 };
 932
 933 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 934         .cmd_rcgr = 0x2c020,
 935         .hid_width = 5,
 936         .parent_map = gcc_xo_gpll0_map,
 937         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 938         .clkr.hw.init = &(struct clk_init_data){
 939                 .name = "blsp2_qup4_i2c_apps_clk_src",
 940                 .parent_names = gcc_xo_gpll0,
 941                 .num_parents = 2,
 942                 .ops = &clk_rcg2_ops,
 943         },
 944 };
 945
 946 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 947         .cmd_rcgr = 0x2d00c,
 948         .mnd_width = 16,
 949         .hid_width = 5,
 950         .parent_map = gcc_xo_gpll0_map,
 951         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 952         .clkr.hw.init = &(struct clk_init_data){
 953                 .name = "blsp2_uart4_apps_clk_src",
 954                 .parent_names = gcc_xo_gpll0,
 955                 .num_parents = 2,
 956                 .ops = &clk_rcg2_ops,
 957         },
 958 };
 959
 960 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 961         .cmd_rcgr = 0x2e00c,
 962         .mnd_width = 8,
 963         .hid_width = 5,
 964         .parent_map = gcc_xo_gpll0_map,
 965         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 966         .clkr.hw.init = &(struct clk_init_data){
 967                 .name = "blsp2_qup5_spi_apps_clk_src",
 968                 .parent_names = gcc_xo_gpll0,
 969                 .num_parents = 2,
 970                 .ops = &clk_rcg2_ops,
 971         },
 972 };
 973
 974 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 975         .cmd_rcgr = 0x2e020,
 976         .hid_width = 5,
 977         .parent_map = gcc_xo_gpll0_map,
 978         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 979         .clkr.hw.init = &(struct clk_init_data){
 980                 .name = "blsp2_qup5_i2c_apps_clk_src",
 981                 .parent_names = gcc_xo_gpll0,
 982                 .num_parents = 2,
 983                 .ops = &clk_rcg2_ops,
 984         },
 985 };
 986
 987 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 988         .cmd_rcgr = 0x2f00c,
 989         .mnd_width = 16,
 990         .hid_width = 5,
 991         .parent_map = gcc_xo_gpll0_map,
 992         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 993         .clkr.hw.init = &(struct clk_init_data){
 994                 .name = "blsp2_uart5_apps_clk_src",
 995                 .parent_names = gcc_xo_gpll0,
 996                 .num_parents = 2,
 997                 .ops = &clk_rcg2_ops,
 998         },
 999 };
1000
1001 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1002         .cmd_rcgr = 0x3000c,
1003         .mnd_width = 8,
1004         .hid_width = 5,
1005         .parent_map = gcc_xo_gpll0_map,
1006         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1007         .clkr.hw.init = &(struct clk_init_data){
1008                 .name = "blsp2_qup6_spi_apps_clk_src",
1009                 .parent_names = gcc_xo_gpll0,
1010                 .num_parents = 2,
1011                 .ops = &clk_rcg2_ops,
1012         },
1013 };
1014
1015 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1016         .cmd_rcgr = 0x30020,
1017         .hid_width = 5,
1018         .parent_map = gcc_xo_gpll0_map,
1019         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1020         .clkr.hw.init = &(struct clk_init_data){
1021                 .name = "blsp2_qup6_i2c_apps_clk_src",
1022                 .parent_names = gcc_xo_gpll0,
1023                 .num_parents = 2,
1024                 .ops = &clk_rcg2_ops,
1025         },
1026 };
1027
1028 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1029         .cmd_rcgr = 0x3100c,
1030         .mnd_width = 16,
1031         .hid_width = 5,
1032         .parent_map = gcc_xo_gpll0_map,
1033         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1034         .clkr.hw.init = &(struct clk_init_data){
1035                 .name = "blsp2_uart6_apps_clk_src",
1036                 .parent_names = gcc_xo_gpll0,
1037                 .num_parents = 2,
1038                 .ops = &clk_rcg2_ops,
1039         },
1040 };
1041
1042 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1043         F(60000000, P_GPLL0, 10, 0, 0),
1044         { }
1045 };
1046
1047 static struct clk_rcg2 pdm2_clk_src = {
1048         .cmd_rcgr = 0x33010,
1049         .hid_width = 5,
1050         .parent_map = gcc_xo_gpll0_map,
1051         .freq_tbl = ftbl_pdm2_clk_src,
1052         .clkr.hw.init = &(struct clk_init_data){
1053                 .name = "pdm2_clk_src",
1054                 .parent_names = gcc_xo_gpll0,
1055                 .num_parents = 2,
1056                 .ops = &clk_rcg2_ops,
1057         },
1058 };
1059
1060 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1061         F(105495, P_XO, 1, 1, 182),
1062         { }
1063 };
1064
1065 static struct clk_rcg2 tsif_ref_clk_src = {
1066         .cmd_rcgr = 0x36010,
1067         .mnd_width = 8,
1068         .hid_width = 5,
1069         .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1070         .freq_tbl = ftbl_tsif_ref_clk_src,
1071         .clkr.hw.init = &(struct clk_init_data){
1072                 .name = "tsif_ref_clk_src",
1073                 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1074                 .num_parents = 3,
1075                 .ops = &clk_rcg2_ops,
1076         },
1077 };
1078
1079 static struct clk_rcg2 gcc_sleep_clk_src = {
1080         .cmd_rcgr = 0x43014,
1081         .hid_width = 5,
1082         .parent_map = gcc_sleep_clk_map,
1083         .clkr.hw.init = &(struct clk_init_data){
1084                 .name = "gcc_sleep_clk_src",
1085                 .parent_names = gcc_sleep_clk,
1086                 .num_parents = 1,
1087                 .ops = &clk_rcg2_ops,
1088         },
1089 };
1090
1091 static struct clk_rcg2 hmss_rbcpr_clk_src = {
1092         .cmd_rcgr = 0x48040,
1093         .hid_width = 5,
1094         .parent_map = gcc_xo_gpll0_map,
1095         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1096         .clkr.hw.init = &(struct clk_init_data){
1097                 .name = "hmss_rbcpr_clk_src",
1098                 .parent_names = gcc_xo_gpll0,
1099                 .num_parents = 2,
1100                 .ops = &clk_rcg2_ops,
1101         },
1102 };
1103
1104 static struct clk_rcg2 hmss_gpll0_clk_src = {
1105         .cmd_rcgr = 0x48058,
1106         .hid_width = 5,
1107         .parent_map = gcc_xo_gpll0_map,
1108         .clkr.hw.init = &(struct clk_init_data){
1109                 .name = "hmss_gpll0_clk_src",
1110                 .parent_names = gcc_xo_gpll0,
1111                 .num_parents = 2,
1112                 .ops = &clk_rcg2_ops,
1113         },
1114 };
1115
1116 static const struct freq_tbl ftbl_gp1_clk_src[] = {
1117         F(19200000, P_XO, 1, 0, 0),
1118         F(100000000, P_GPLL0, 6, 0, 0),
1119         F(200000000, P_GPLL0, 3, 0, 0),
1120         { }
1121 };
1122
1123 static struct clk_rcg2 gp1_clk_src = {
1124         .cmd_rcgr = 0x64004,
1125         .mnd_width = 8,
1126         .hid_width = 5,
1127         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1128         .freq_tbl = ftbl_gp1_clk_src,
1129         .clkr.hw.init = &(struct clk_init_data){
1130                 .name = "gp1_clk_src",
1131                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1132                 .num_parents = 4,
1133                 .ops = &clk_rcg2_ops,
1134         },
1135 };
1136
1137 static struct clk_rcg2 gp2_clk_src = {
1138         .cmd_rcgr = 0x65004,
1139         .mnd_width = 8,
1140         .hid_width = 5,
1141         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1142         .freq_tbl = ftbl_gp1_clk_src,
1143         .clkr.hw.init = &(struct clk_init_data){
1144                 .name = "gp2_clk_src",
1145                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1146                 .num_parents = 4,
1147                 .ops = &clk_rcg2_ops,
1148         },
1149 };
1150
1151 static struct clk_rcg2 gp3_clk_src = {
1152         .cmd_rcgr = 0x66004,
1153         .mnd_width = 8,
1154         .hid_width = 5,
1155         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1156         .freq_tbl = ftbl_gp1_clk_src,
1157         .clkr.hw.init = &(struct clk_init_data){
1158                 .name = "gp3_clk_src",
1159                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1160                 .num_parents = 4,
1161                 .ops = &clk_rcg2_ops,
1162         },
1163 };
1164
1165 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1166         F(1010526, P_XO, 1, 1, 19),
1167         { }
1168 };
1169
1170 static struct clk_rcg2 pcie_aux_clk_src = {
1171         .cmd_rcgr = 0x6c000,
1172         .mnd_width = 16,
1173         .hid_width = 5,
1174         .parent_map = gcc_xo_sleep_clk_map,
1175         .freq_tbl = ftbl_pcie_aux_clk_src,
1176         .clkr.hw.init = &(struct clk_init_data){
1177                 .name = "pcie_aux_clk_src",
1178                 .parent_names = gcc_xo_sleep_clk,
1179                 .num_parents = 2,
1180                 .ops = &clk_rcg2_ops,
1181         },
1182 };
1183
1184 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1185         F(100000000, P_GPLL0, 6, 0, 0),
1186         F(200000000, P_GPLL0, 3, 0, 0),
1187         F(240000000, P_GPLL0, 2.5, 0, 0),
1188         { }
1189 };
1190
1191 static struct clk_rcg2 ufs_axi_clk_src = {
1192         .cmd_rcgr = 0x75024,
1193         .mnd_width = 8,
1194         .hid_width = 5,
1195         .parent_map = gcc_xo_gpll0_map,
1196         .freq_tbl = ftbl_ufs_axi_clk_src,
1197         .clkr.hw.init = &(struct clk_init_data){
1198                 .name = "ufs_axi_clk_src",
1199                 .parent_names = gcc_xo_gpll0,
1200                 .num_parents = 2,
1201                 .ops = &clk_rcg2_ops,
1202         },
1203 };
1204
1205 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
1206         F(19200000, P_XO, 1, 0, 0),
1207         F(150000000, P_GPLL0, 4, 0, 0),
1208         F(300000000, P_GPLL0, 2, 0, 0),
1209         { }
1210 };
1211
1212 static struct clk_rcg2 ufs_ice_core_clk_src = {
1213         .cmd_rcgr = 0x76014,
1214         .hid_width = 5,
1215         .parent_map = gcc_xo_gpll0_map,
1216         .freq_tbl = ftbl_ufs_ice_core_clk_src,
1217         .clkr.hw.init = &(struct clk_init_data){
1218                 .name = "ufs_ice_core_clk_src",
1219                 .parent_names = gcc_xo_gpll0,
1220                 .num_parents = 2,
1221                 .ops = &clk_rcg2_ops,
1222         },
1223 };
1224
1225 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
1226         F(75000000, P_GPLL0, 8, 0, 0),
1227         F(150000000, P_GPLL0, 4, 0, 0),
1228         F(256000000, P_GPLL4, 1.5, 0, 0),
1229         F(300000000, P_GPLL0, 2, 0, 0),
1230         { }
1231 };
1232
1233 static struct clk_rcg2 qspi_ser_clk_src = {
1234         .cmd_rcgr = 0x8b00c,
1235         .hid_width = 5,
1236         .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1237         .freq_tbl = ftbl_qspi_ser_clk_src,
1238         .clkr.hw.init = &(struct clk_init_data){
1239                 .name = "qspi_ser_clk_src",
1240                 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1241                 .num_parents = 6,
1242                 .ops = &clk_rcg2_ops,
1243         },
1244 };
1245
1246 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1247         .halt_reg = 0x0f03c,
1248         .clkr = {
1249                 .enable_reg = 0x0f03c,
1250                 .enable_mask = BIT(0),
1251                 .hw.init = &(struct clk_init_data){
1252                         .name = "gcc_sys_noc_usb3_axi_clk",
1253                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1254                         .num_parents = 1,
1255                         .flags = CLK_SET_RATE_PARENT,
1256                         .ops = &clk_branch2_ops,
1257                 },
1258         },
1259 };
1260
1261 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1262         .halt_reg = 0x75038,
1263         .clkr = {
1264                 .enable_reg = 0x75038,
1265                 .enable_mask = BIT(0),
1266                 .hw.init = &(struct clk_init_data){
1267                         .name = "gcc_sys_noc_ufs_axi_clk",
1268                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1269                         .num_parents = 1,
1270                         .flags = CLK_SET_RATE_PARENT,
1271                         .ops = &clk_branch2_ops,
1272                 },
1273         },
1274 };
1275
1276 static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1277         .halt_reg = 0x6010,
1278         .clkr = {
1279                 .enable_reg = 0x6010,
1280                 .enable_mask = BIT(0),
1281                 .hw.init = &(struct clk_init_data){
1282                         .name = "gcc_periph_noc_usb20_ahb_clk",
1283                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1284                         .num_parents = 1,
1285                         .flags = CLK_SET_RATE_PARENT,
1286                         .ops = &clk_branch2_ops,
1287                 },
1288         },
1289 };
1290
1291 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1292         .halt_reg = 0x9008,
1293         .clkr = {
1294                 .enable_reg = 0x9008,
1295                 .enable_mask = BIT(0),
1296                 .hw.init = &(struct clk_init_data){
1297                         .name = "gcc_mmss_noc_cfg_ahb_clk",
1298                         .parent_names = (const char *[]){ "config_noc_clk_src" },
1299                         .num_parents = 1,
1300                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1301                         .ops = &clk_branch2_ops,
1302                 },
1303         },
1304 };
1305
1306 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1307         .halt_reg = 0x9010,
1308         .clkr = {
1309                 .enable_reg = 0x9010,
1310                 .enable_mask = BIT(0),
1311                 .hw.init = &(struct clk_init_data){
1312                         .name = "gcc_mmss_bimc_gfx_clk",
1313                         .flags = CLK_SET_RATE_PARENT,
1314                         .ops = &clk_branch2_ops,
1315                 },
1316         },
1317 };
1318
1319 static struct clk_branch gcc_usb30_master_clk = {
1320         .halt_reg = 0x0f008,
1321         .clkr = {
1322                 .enable_reg = 0x0f008,
1323                 .enable_mask = BIT(0),
1324                 .hw.init = &(struct clk_init_data){
1325                         .name = "gcc_usb30_master_clk",
1326                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1327                         .num_parents = 1,
1328                         .flags = CLK_SET_RATE_PARENT,
1329                         .ops = &clk_branch2_ops,
1330                 },
1331         },
1332 };
1333
1334 static struct clk_branch gcc_usb30_sleep_clk = {
1335         .halt_reg = 0x0f00c,
1336         .clkr = {
1337                 .enable_reg = 0x0f00c,
1338                 .enable_mask = BIT(0),
1339                 .hw.init = &(struct clk_init_data){
1340                         .name = "gcc_usb30_sleep_clk",
1341                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1342                         .num_parents = 1,
1343                         .flags = CLK_SET_RATE_PARENT,
1344                         .ops = &clk_branch2_ops,
1345                 },
1346         },
1347 };
1348
1349 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1350         .halt_reg = 0x0f010,
1351         .clkr = {
1352                 .enable_reg = 0x0f010,
1353                 .enable_mask = BIT(0),
1354                 .hw.init = &(struct clk_init_data){
1355                         .name = "gcc_usb30_mock_utmi_clk",
1356                         .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1357                         .num_parents = 1,
1358                         .flags = CLK_SET_RATE_PARENT,
1359                         .ops = &clk_branch2_ops,
1360                 },
1361         },
1362 };
1363
1364 static struct clk_branch gcc_usb3_phy_aux_clk = {
1365         .halt_reg = 0x50000,
1366         .clkr = {
1367                 .enable_reg = 0x50000,
1368                 .enable_mask = BIT(0),
1369                 .hw.init = &(struct clk_init_data){
1370                         .name = "gcc_usb3_phy_aux_clk",
1371                         .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1372                         .num_parents = 1,
1373                         .flags = CLK_SET_RATE_PARENT,
1374                         .ops = &clk_branch2_ops,
1375                 },
1376         },
1377 };
1378
1379 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1380         .halt_reg = 0x50004,
1381         .clkr = {
1382                 .enable_reg = 0x50004,
1383                 .enable_mask = BIT(0),
1384                 .hw.init = &(struct clk_init_data){
1385                         .name = "gcc_usb3_phy_pipe_clk",
1386                         .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1387                         .num_parents = 1,
1388                         .flags = CLK_SET_RATE_PARENT,
1389                         .ops = &clk_branch2_ops,
1390                 },
1391         },
1392 };
1393
1394 static struct clk_branch gcc_usb20_master_clk = {
1395         .halt_reg = 0x12004,
1396         .clkr = {
1397                 .enable_reg = 0x12004,
1398                 .enable_mask = BIT(0),
1399                 .hw.init = &(struct clk_init_data){
1400                         .name = "gcc_usb20_master_clk",
1401                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1402                         .num_parents = 1,
1403                         .flags = CLK_SET_RATE_PARENT,
1404                         .ops = &clk_branch2_ops,
1405                 },
1406         },
1407 };
1408
1409 static struct clk_branch gcc_usb20_sleep_clk = {
1410         .halt_reg = 0x12008,
1411         .clkr = {
1412                 .enable_reg = 0x12008,
1413                 .enable_mask = BIT(0),
1414                 .hw.init = &(struct clk_init_data){
1415                         .name = "gcc_usb20_sleep_clk",
1416                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1417                         .num_parents = 1,
1418                         .flags = CLK_SET_RATE_PARENT,
1419                         .ops = &clk_branch2_ops,
1420                 },
1421         },
1422 };
1423
1424 static struct clk_branch gcc_usb20_mock_utmi_clk = {
1425         .halt_reg = 0x1200c,
1426         .clkr = {
1427                 .enable_reg = 0x1200c,
1428                 .enable_mask = BIT(0),
1429                 .hw.init = &(struct clk_init_data){
1430                         .name = "gcc_usb20_mock_utmi_clk",
1431                         .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1432                         .num_parents = 1,
1433                         .flags = CLK_SET_RATE_PARENT,
1434                         .ops = &clk_branch2_ops,
1435                 },
1436         },
1437 };
1438
1439 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1440         .halt_reg = 0x6a004,
1441         .clkr = {
1442                 .enable_reg = 0x6a004,
1443                 .enable_mask = BIT(0),
1444                 .hw.init = &(struct clk_init_data){
1445                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1446                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1447                         .num_parents = 1,
1448                         .flags = CLK_SET_RATE_PARENT,
1449                         .ops = &clk_branch2_ops,
1450                 },
1451         },
1452 };
1453
1454 static struct clk_branch gcc_sdcc1_apps_clk = {
1455         .halt_reg = 0x13004,
1456         .clkr = {
1457                 .enable_reg = 0x13004,
1458                 .enable_mask = BIT(0),
1459                 .hw.init = &(struct clk_init_data){
1460                         .name = "gcc_sdcc1_apps_clk",
1461                         .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1462                         .num_parents = 1,
1463                         .flags = CLK_SET_RATE_PARENT,
1464                         .ops = &clk_branch2_ops,
1465                 },
1466         },
1467 };
1468
1469 static struct clk_branch gcc_sdcc1_ahb_clk = {
1470         .halt_reg = 0x13008,
1471         .clkr = {
1472                 .enable_reg = 0x13008,
1473                 .enable_mask = BIT(0),
1474                 .hw.init = &(struct clk_init_data){
1475                         .name = "gcc_sdcc1_ahb_clk",
1476                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1477                         .num_parents = 1,
1478                         .flags = CLK_SET_RATE_PARENT,
1479                         .ops = &clk_branch2_ops,
1480                 },
1481         },
1482 };
1483
1484 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1485         .halt_reg = 0x13038,
1486         .clkr = {
1487                 .enable_reg = 0x13038,
1488                 .enable_mask = BIT(0),
1489                 .hw.init = &(struct clk_init_data){
1490                         .name = "gcc_sdcc1_ice_core_clk",
1491                         .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1492                         .num_parents = 1,
1493                         .flags = CLK_SET_RATE_PARENT,
1494                         .ops = &clk_branch2_ops,
1495                 },
1496         },
1497 };
1498
1499 static struct clk_branch gcc_sdcc2_apps_clk = {
1500         .halt_reg = 0x14004,
1501         .clkr = {
1502                 .enable_reg = 0x14004,
1503                 .enable_mask = BIT(0),
1504                 .hw.init = &(struct clk_init_data){
1505                         .name = "gcc_sdcc2_apps_clk",
1506                         .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1507                         .num_parents = 1,
1508                         .flags = CLK_SET_RATE_PARENT,
1509                         .ops = &clk_branch2_ops,
1510                 },
1511         },
1512 };
1513
1514 static struct clk_branch gcc_sdcc2_ahb_clk = {
1515         .halt_reg = 0x14008,
1516         .clkr = {
1517                 .enable_reg = 0x14008,
1518                 .enable_mask = BIT(0),
1519                 .hw.init = &(struct clk_init_data){
1520                         .name = "gcc_sdcc2_ahb_clk",
1521                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1522                         .num_parents = 1,
1523                         .flags = CLK_SET_RATE_PARENT,
1524                         .ops = &clk_branch2_ops,
1525                 },
1526         },
1527 };
1528
1529 static struct clk_branch gcc_sdcc3_apps_clk = {
1530         .halt_reg = 0x15004,
1531         .clkr = {
1532                 .enable_reg = 0x15004,
1533                 .enable_mask = BIT(0),
1534                 .hw.init = &(struct clk_init_data){
1535                         .name = "gcc_sdcc3_apps_clk",
1536                         .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1537                         .num_parents = 1,
1538                         .flags = CLK_SET_RATE_PARENT,
1539                         .ops = &clk_branch2_ops,
1540                 },
1541         },
1542 };
1543
1544 static struct clk_branch gcc_sdcc3_ahb_clk = {
1545         .halt_reg = 0x15008,
1546         .clkr = {
1547                 .enable_reg = 0x15008,
1548                 .enable_mask = BIT(0),
1549                 .hw.init = &(struct clk_init_data){
1550                         .name = "gcc_sdcc3_ahb_clk",
1551                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1552                         .num_parents = 1,
1553                         .flags = CLK_SET_RATE_PARENT,
1554                         .ops = &clk_branch2_ops,
1555                 },
1556         },
1557 };
1558
1559 static struct clk_branch gcc_sdcc4_apps_clk = {
1560         .halt_reg = 0x16004,
1561         .clkr = {
1562                 .enable_reg = 0x16004,
1563                 .enable_mask = BIT(0),
1564                 .hw.init = &(struct clk_init_data){
1565                         .name = "gcc_sdcc4_apps_clk",
1566                         .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1567                         .num_parents = 1,
1568                         .flags = CLK_SET_RATE_PARENT,
1569                         .ops = &clk_branch2_ops,
1570                 },
1571         },
1572 };
1573
1574 static struct clk_branch gcc_sdcc4_ahb_clk = {
1575         .halt_reg = 0x16008,
1576         .clkr = {
1577                 .enable_reg = 0x16008,
1578                 .enable_mask = BIT(0),
1579                 .hw.init = &(struct clk_init_data){
1580                         .name = "gcc_sdcc4_ahb_clk",
1581                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1582                         .num_parents = 1,
1583                         .flags = CLK_SET_RATE_PARENT,
1584                         .ops = &clk_branch2_ops,
1585                 },
1586         },
1587 };
1588
1589 static struct clk_branch gcc_blsp1_ahb_clk = {
1590         .halt_reg = 0x17004,
1591         .halt_check = BRANCH_HALT_VOTED,
1592         .clkr = {
1593                 .enable_reg = 0x52004,
1594                 .enable_mask = BIT(17),
1595                 .hw.init = &(struct clk_init_data){
1596                         .name = "gcc_blsp1_ahb_clk",
1597                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1598                         .num_parents = 1,
1599                         .flags = CLK_SET_RATE_PARENT,
1600                         .ops = &clk_branch2_ops,
1601                 },
1602         },
1603 };
1604
1605 static struct clk_branch gcc_blsp1_sleep_clk = {
1606         .halt_reg = 0x17008,
1607         .halt_check = BRANCH_HALT_VOTED,
1608         .clkr = {
1609                 .enable_reg = 0x52004,
1610                 .enable_mask = BIT(16),
1611                 .hw.init = &(struct clk_init_data){
1612                         .name = "gcc_blsp1_sleep_clk",
1613                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1614                         .num_parents = 1,
1615                         .flags = CLK_SET_RATE_PARENT,
1616                         .ops = &clk_branch2_ops,
1617                 },
1618         },
1619 };
1620
1621 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1622         .halt_reg = 0x19004,
1623         .clkr = {
1624                 .enable_reg = 0x19004,
1625                 .enable_mask = BIT(0),
1626                 .hw.init = &(struct clk_init_data){
1627                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1628                         .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1629                         .num_parents = 1,
1630                         .flags = CLK_SET_RATE_PARENT,
1631                         .ops = &clk_branch2_ops,
1632                 },
1633         },
1634 };
1635
1636 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1637         .halt_reg = 0x19008,
1638         .clkr = {
1639                 .enable_reg = 0x19008,
1640                 .enable_mask = BIT(0),
1641                 .hw.init = &(struct clk_init_data){
1642                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1643                         .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1644                         .num_parents = 1,
1645                         .flags = CLK_SET_RATE_PARENT,
1646                         .ops = &clk_branch2_ops,
1647                 },
1648         },
1649 };
1650
1651 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1652         .halt_reg = 0x1a004,
1653         .clkr = {
1654                 .enable_reg = 0x1a004,
1655                 .enable_mask = BIT(0),
1656                 .hw.init = &(struct clk_init_data){
1657                         .name = "gcc_blsp1_uart1_apps_clk",
1658                         .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1659                         .num_parents = 1,
1660                         .flags = CLK_SET_RATE_PARENT,
1661                         .ops = &clk_branch2_ops,
1662                 },
1663         },
1664 };
1665
1666 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1667         .halt_reg = 0x1b004,
1668         .clkr = {
1669                 .enable_reg = 0x1b004,
1670                 .enable_mask = BIT(0),
1671                 .hw.init = &(struct clk_init_data){
1672                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1673                         .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1674                         .num_parents = 1,
1675                         .flags = CLK_SET_RATE_PARENT,
1676                         .ops = &clk_branch2_ops,
1677                 },
1678         },
1679 };
1680
1681 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1682         .halt_reg = 0x1b008,
1683         .clkr = {
1684                 .enable_reg = 0x1b008,
1685                 .enable_mask = BIT(0),
1686                 .hw.init = &(struct clk_init_data){
1687                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1688                         .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1689                         .num_parents = 1,
1690                         .flags = CLK_SET_RATE_PARENT,
1691                         .ops = &clk_branch2_ops,
1692                 },
1693         },
1694 };
1695
1696 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1697         .halt_reg = 0x1c004,
1698         .clkr = {
1699                 .enable_reg = 0x1c004,
1700                 .enable_mask = BIT(0),
1701                 .hw.init = &(struct clk_init_data){
1702                         .name = "gcc_blsp1_uart2_apps_clk",
1703                         .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1704                         .num_parents = 1,
1705                         .flags = CLK_SET_RATE_PARENT,
1706                         .ops = &clk_branch2_ops,
1707                 },
1708         },
1709 };
1710
1711 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1712         .halt_reg = 0x1d004,
1713         .clkr = {
1714                 .enable_reg = 0x1d004,
1715                 .enable_mask = BIT(0),
1716                 .hw.init = &(struct clk_init_data){
1717                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1718                         .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1719                         .num_parents = 1,
1720                         .flags = CLK_SET_RATE_PARENT,
1721                         .ops = &clk_branch2_ops,
1722                 },
1723         },
1724 };
1725
1726 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1727         .halt_reg = 0x1d008,
1728         .clkr = {
1729                 .enable_reg = 0x1d008,
1730                 .enable_mask = BIT(0),
1731                 .hw.init = &(struct clk_init_data){
1732                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1733                         .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1734                         .num_parents = 1,
1735                         .flags = CLK_SET_RATE_PARENT,
1736                         .ops = &clk_branch2_ops,
1737                 },
1738         },
1739 };
1740
1741 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1742         .halt_reg = 0x1e004,
1743         .clkr = {
1744                 .enable_reg = 0x1e004,
1745                 .enable_mask = BIT(0),
1746                 .hw.init = &(struct clk_init_data){
1747                         .name = "gcc_blsp1_uart3_apps_clk",
1748                         .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1749                         .num_parents = 1,
1750                         .flags = CLK_SET_RATE_PARENT,
1751                         .ops = &clk_branch2_ops,
1752                 },
1753         },
1754 };
1755
1756 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1757         .halt_reg = 0x1f004,
1758         .clkr = {
1759                 .enable_reg = 0x1f004,
1760                 .enable_mask = BIT(0),
1761                 .hw.init = &(struct clk_init_data){
1762                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1763                         .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1764                         .num_parents = 1,
1765                         .flags = CLK_SET_RATE_PARENT,
1766                         .ops = &clk_branch2_ops,
1767                 },
1768         },
1769 };
1770
1771 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1772         .halt_reg = 0x1f008,
1773         .clkr = {
1774                 .enable_reg = 0x1f008,
1775                 .enable_mask = BIT(0),
1776                 .hw.init = &(struct clk_init_data){
1777                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1778                         .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1779                         .num_parents = 1,
1780                         .flags = CLK_SET_RATE_PARENT,
1781                         .ops = &clk_branch2_ops,
1782                 },
1783         },
1784 };
1785
1786 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1787         .halt_reg = 0x20004,
1788         .clkr = {
1789                 .enable_reg = 0x20004,
1790                 .enable_mask = BIT(0),
1791                 .hw.init = &(struct clk_init_data){
1792                         .name = "gcc_blsp1_uart4_apps_clk",
1793                         .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1794                         .num_parents = 1,
1795                         .flags = CLK_SET_RATE_PARENT,
1796                         .ops = &clk_branch2_ops,
1797                 },
1798         },
1799 };
1800
1801 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1802         .halt_reg = 0x21004,
1803         .clkr = {
1804                 .enable_reg = 0x21004,
1805                 .enable_mask = BIT(0),
1806                 .hw.init = &(struct clk_init_data){
1807                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1808                         .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1809                         .num_parents = 1,
1810                         .flags = CLK_SET_RATE_PARENT,
1811                         .ops = &clk_branch2_ops,
1812                 },
1813         },
1814 };
1815
1816 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1817         .halt_reg = 0x21008,
1818         .clkr = {
1819                 .enable_reg = 0x21008,
1820                 .enable_mask = BIT(0),
1821                 .hw.init = &(struct clk_init_data){
1822                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1823                         .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1824                         .num_parents = 1,
1825                         .flags = CLK_SET_RATE_PARENT,
1826                         .ops = &clk_branch2_ops,
1827                 },
1828         },
1829 };
1830
1831 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1832         .halt_reg = 0x22004,
1833         .clkr = {
1834                 .enable_reg = 0x22004,
1835                 .enable_mask = BIT(0),
1836                 .hw.init = &(struct clk_init_data){
1837                         .name = "gcc_blsp1_uart5_apps_clk",
1838                         .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1839                         .num_parents = 1,
1840                         .flags = CLK_SET_RATE_PARENT,
1841                         .ops = &clk_branch2_ops,
1842                 },
1843         },
1844 };
1845
1846 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1847         .halt_reg = 0x23004,
1848         .clkr = {
1849                 .enable_reg = 0x23004,
1850                 .enable_mask = BIT(0),
1851                 .hw.init = &(struct clk_init_data){
1852                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1853                         .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1854                         .num_parents = 1,
1855                         .flags = CLK_SET_RATE_PARENT,
1856                         .ops = &clk_branch2_ops,
1857                 },
1858         },
1859 };
1860
1861 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1862         .halt_reg = 0x23008,
1863         .clkr = {
1864                 .enable_reg = 0x23008,
1865                 .enable_mask = BIT(0),
1866                 .hw.init = &(struct clk_init_data){
1867                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1868                         .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1869                         .num_parents = 1,
1870                         .flags = CLK_SET_RATE_PARENT,
1871                         .ops = &clk_branch2_ops,
1872                 },
1873         },
1874 };
1875
1876 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1877         .halt_reg = 0x24004,
1878         .clkr = {
1879                 .enable_reg = 0x24004,
1880                 .enable_mask = BIT(0),
1881                 .hw.init = &(struct clk_init_data){
1882                         .name = "gcc_blsp1_uart6_apps_clk",
1883                         .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1884                         .num_parents = 1,
1885                         .flags = CLK_SET_RATE_PARENT,
1886                         .ops = &clk_branch2_ops,
1887                 },
1888         },
1889 };
1890
1891 static struct clk_branch gcc_blsp2_ahb_clk = {
1892         .halt_reg = 0x25004,
1893         .halt_check = BRANCH_HALT_VOTED,
1894         .clkr = {
1895                 .enable_reg = 0x52004,
1896                 .enable_mask = BIT(15),
1897                 .hw.init = &(struct clk_init_data){
1898                         .name = "gcc_blsp2_ahb_clk",
1899                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1900                         .num_parents = 1,
1901                         .flags = CLK_SET_RATE_PARENT,
1902                         .ops = &clk_branch2_ops,
1903                 },
1904         },
1905 };
1906
1907 static struct clk_branch gcc_blsp2_sleep_clk = {
1908         .halt_reg = 0x25008,
1909         .halt_check = BRANCH_HALT_VOTED,
1910         .clkr = {
1911                 .enable_reg = 0x52004,
1912                 .enable_mask = BIT(14),
1913                 .hw.init = &(struct clk_init_data){
1914                         .name = "gcc_blsp2_sleep_clk",
1915                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1916                         .num_parents = 1,
1917                         .flags = CLK_SET_RATE_PARENT,
1918                         .ops = &clk_branch2_ops,
1919                 },
1920         },
1921 };
1922
1923 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1924         .halt_reg = 0x26004,
1925         .clkr = {
1926                 .enable_reg = 0x26004,
1927                 .enable_mask = BIT(0),
1928                 .hw.init = &(struct clk_init_data){
1929                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1930                         .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1931                         .num_parents = 1,
1932                         .flags = CLK_SET_RATE_PARENT,
1933                         .ops = &clk_branch2_ops,
1934                 },
1935         },
1936 };
1937
1938 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1939         .halt_reg = 0x26008,
1940         .clkr = {
1941                 .enable_reg = 0x26008,
1942                 .enable_mask = BIT(0),
1943                 .hw.init = &(struct clk_init_data){
1944                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1945                         .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1946                         .num_parents = 1,
1947                         .flags = CLK_SET_RATE_PARENT,
1948                         .ops = &clk_branch2_ops,
1949                 },
1950         },
1951 };
1952
1953 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1954         .halt_reg = 0x27004,
1955         .clkr = {
1956                 .enable_reg = 0x27004,
1957                 .enable_mask = BIT(0),
1958                 .hw.init = &(struct clk_init_data){
1959                         .name = "gcc_blsp2_uart1_apps_clk",
1960                         .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
1961                         .num_parents = 1,
1962                         .flags = CLK_SET_RATE_PARENT,
1963                         .ops = &clk_branch2_ops,
1964                 },
1965         },
1966 };
1967
1968 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1969         .halt_reg = 0x28004,
1970         .clkr = {
1971                 .enable_reg = 0x28004,
1972                 .enable_mask = BIT(0),
1973                 .hw.init = &(struct clk_init_data){
1974                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1975                         .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
1976                         .num_parents = 1,
1977                         .flags = CLK_SET_RATE_PARENT,
1978                         .ops = &clk_branch2_ops,
1979                 },
1980         },
1981 };
1982
1983 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1984         .halt_reg = 0x28008,
1985         .clkr = {
1986                 .enable_reg = 0x28008,
1987                 .enable_mask = BIT(0),
1988                 .hw.init = &(struct clk_init_data){
1989                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1990                         .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
1991                         .num_parents = 1,
1992                         .flags = CLK_SET_RATE_PARENT,
1993                         .ops = &clk_branch2_ops,
1994                 },
1995         },
1996 };
1997
1998 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1999         .halt_reg = 0x29004,
2000         .clkr = {
2001                 .enable_reg = 0x29004,
2002                 .enable_mask = BIT(0),
2003                 .hw.init = &(struct clk_init_data){
2004                         .name = "gcc_blsp2_uart2_apps_clk",
2005                         .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2006                         .num_parents = 1,
2007                         .flags = CLK_SET_RATE_PARENT,
2008                         .ops = &clk_branch2_ops,
2009                 },
2010         },
2011 };
2012
2013 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2014         .halt_reg = 0x2a004,
2015         .clkr = {
2016                 .enable_reg = 0x2a004,
2017                 .enable_mask = BIT(0),
2018                 .hw.init = &(struct clk_init_data){
2019                         .name = "gcc_blsp2_qup3_spi_apps_clk",
2020                         .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2021                         .num_parents = 1,
2022                         .flags = CLK_SET_RATE_PARENT,
2023                         .ops = &clk_branch2_ops,
2024                 },
2025         },
2026 };
2027
2028 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2029         .halt_reg = 0x2a008,
2030         .clkr = {
2031                 .enable_reg = 0x2a008,
2032                 .enable_mask = BIT(0),
2033                 .hw.init = &(struct clk_init_data){
2034                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
2035                         .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2036                         .num_parents = 1,
2037                         .flags = CLK_SET_RATE_PARENT,
2038                         .ops = &clk_branch2_ops,
2039                 },
2040         },
2041 };
2042
2043 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2044         .halt_reg = 0x2b004,
2045         .clkr = {
2046                 .enable_reg = 0x2b004,
2047                 .enable_mask = BIT(0),
2048                 .hw.init = &(struct clk_init_data){
2049                         .name = "gcc_blsp2_uart3_apps_clk",
2050                         .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2051                         .num_parents = 1,
2052                         .flags = CLK_SET_RATE_PARENT,
2053                         .ops = &clk_branch2_ops,
2054                 },
2055         },
2056 };
2057
2058 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2059         .halt_reg = 0x2c004,
2060         .clkr = {
2061                 .enable_reg = 0x2c004,
2062                 .enable_mask = BIT(0),
2063                 .hw.init = &(struct clk_init_data){
2064                         .name = "gcc_blsp2_qup4_spi_apps_clk",
2065                         .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2066                         .num_parents = 1,
2067                         .flags = CLK_SET_RATE_PARENT,
2068                         .ops = &clk_branch2_ops,
2069                 },
2070         },
2071 };
2072
2073 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2074         .halt_reg = 0x2c008,
2075         .clkr = {
2076                 .enable_reg = 0x2c008,
2077                 .enable_mask = BIT(0),
2078                 .hw.init = &(struct clk_init_data){
2079                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
2080                         .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2081                         .num_parents = 1,
2082                         .flags = CLK_SET_RATE_PARENT,
2083                         .ops = &clk_branch2_ops,
2084                 },
2085         },
2086 };
2087
2088 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2089         .halt_reg = 0x2d004,
2090         .clkr = {
2091                 .enable_reg = 0x2d004,
2092                 .enable_mask = BIT(0),
2093                 .hw.init = &(struct clk_init_data){
2094                         .name = "gcc_blsp2_uart4_apps_clk",
2095                         .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2096                         .num_parents = 1,
2097                         .flags = CLK_SET_RATE_PARENT,
2098                         .ops = &clk_branch2_ops,
2099                 },
2100         },
2101 };
2102
2103 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2104         .halt_reg = 0x2e004,
2105         .clkr = {
2106                 .enable_reg = 0x2e004,
2107                 .enable_mask = BIT(0),
2108                 .hw.init = &(struct clk_init_data){
2109                         .name = "gcc_blsp2_qup5_spi_apps_clk",
2110                         .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2111                         .num_parents = 1,
2112                         .flags = CLK_SET_RATE_PARENT,
2113                         .ops = &clk_branch2_ops,
2114                 },
2115         },
2116 };
2117
2118 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2119         .halt_reg = 0x2e008,
2120         .clkr = {
2121                 .enable_reg = 0x2e008,
2122                 .enable_mask = BIT(0),
2123                 .hw.init = &(struct clk_init_data){
2124                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
2125                         .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2126                         .num_parents = 1,
2127                         .flags = CLK_SET_RATE_PARENT,
2128                         .ops = &clk_branch2_ops,
2129                 },
2130         },
2131 };
2132
2133 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2134         .halt_reg = 0x2f004,
2135         .clkr = {
2136                 .enable_reg = 0x2f004,
2137                 .enable_mask = BIT(0),
2138                 .hw.init = &(struct clk_init_data){
2139                         .name = "gcc_blsp2_uart5_apps_clk",
2140                         .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2141                         .num_parents = 1,
2142                         .flags = CLK_SET_RATE_PARENT,
2143                         .ops = &clk_branch2_ops,
2144                 },
2145         },
2146 };
2147
2148 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2149         .halt_reg = 0x30004,
2150         .clkr = {
2151                 .enable_reg = 0x30004,
2152                 .enable_mask = BIT(0),
2153                 .hw.init = &(struct clk_init_data){
2154                         .name = "gcc_blsp2_qup6_spi_apps_clk",
2155                         .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2156                         .num_parents = 1,
2157                         .flags = CLK_SET_RATE_PARENT,
2158                         .ops = &clk_branch2_ops,
2159                 },
2160         },
2161 };
2162
2163 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2164         .halt_reg = 0x30008,
2165         .clkr = {
2166                 .enable_reg = 0x30008,
2167                 .enable_mask = BIT(0),
2168                 .hw.init = &(struct clk_init_data){
2169                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
2170                         .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2171                         .num_parents = 1,
2172                         .flags = CLK_SET_RATE_PARENT,
2173                         .ops = &clk_branch2_ops,
2174                 },
2175         },
2176 };
2177
2178 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2179         .halt_reg = 0x31004,
2180         .clkr = {
2181                 .enable_reg = 0x31004,
2182                 .enable_mask = BIT(0),
2183                 .hw.init = &(struct clk_init_data){
2184                         .name = "gcc_blsp2_uart6_apps_clk",
2185                         .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2186                         .num_parents = 1,
2187                         .flags = CLK_SET_RATE_PARENT,
2188                         .ops = &clk_branch2_ops,
2189                 },
2190         },
2191 };
2192
2193 static struct clk_branch gcc_pdm_ahb_clk = {
2194         .halt_reg = 0x33004,
2195         .clkr = {
2196                 .enable_reg = 0x33004,
2197                 .enable_mask = BIT(0),
2198                 .hw.init = &(struct clk_init_data){
2199                         .name = "gcc_pdm_ahb_clk",
2200                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2201                         .num_parents = 1,
2202                         .flags = CLK_SET_RATE_PARENT,
2203                         .ops = &clk_branch2_ops,
2204                 },
2205         },
2206 };
2207
2208 static struct clk_branch gcc_pdm2_clk = {
2209         .halt_reg = 0x3300c,
2210         .clkr = {
2211                 .enable_reg = 0x3300c,
2212                 .enable_mask = BIT(0),
2213                 .hw.init = &(struct clk_init_data){
2214                         .name = "gcc_pdm2_clk",
2215                         .parent_names = (const char *[]){ "pdm2_clk_src" },
2216                         .num_parents = 1,
2217                         .flags = CLK_SET_RATE_PARENT,
2218                         .ops = &clk_branch2_ops,
2219                 },
2220         },
2221 };
2222
2223 static struct clk_branch gcc_prng_ahb_clk = {
2224         .halt_reg = 0x34004,
2225         .halt_check = BRANCH_HALT_VOTED,
2226         .clkr = {
2227                 .enable_reg = 0x52004,
2228                 .enable_mask = BIT(13),
2229                 .hw.init = &(struct clk_init_data){
2230                         .name = "gcc_prng_ahb_clk",
2231                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2232                         .num_parents = 1,
2233                         .flags = CLK_SET_RATE_PARENT,
2234                         .ops = &clk_branch2_ops,
2235                 },
2236         },
2237 };
2238
2239 static struct clk_branch gcc_tsif_ahb_clk = {
2240         .halt_reg = 0x36004,
2241         .clkr = {
2242                 .enable_reg = 0x36004,
2243                 .enable_mask = BIT(0),
2244                 .hw.init = &(struct clk_init_data){
2245                         .name = "gcc_tsif_ahb_clk",
2246                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2247                         .num_parents = 1,
2248                         .flags = CLK_SET_RATE_PARENT,
2249                         .ops = &clk_branch2_ops,
2250                 },
2251         },
2252 };
2253
2254 static struct clk_branch gcc_tsif_ref_clk = {
2255         .halt_reg = 0x36008,
2256         .clkr = {
2257                 .enable_reg = 0x36008,
2258                 .enable_mask = BIT(0),
2259                 .hw.init = &(struct clk_init_data){
2260                         .name = "gcc_tsif_ref_clk",
2261                         .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2262                         .num_parents = 1,
2263                         .flags = CLK_SET_RATE_PARENT,
2264                         .ops = &clk_branch2_ops,
2265                 },
2266         },
2267 };
2268
2269 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2270         .halt_reg = 0x3600c,
2271         .clkr = {
2272                 .enable_reg = 0x3600c,
2273                 .enable_mask = BIT(0),
2274                 .hw.init = &(struct clk_init_data){
2275                         .name = "gcc_tsif_inactivity_timers_clk",
2276                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2277                         .num_parents = 1,
2278                         .flags = CLK_SET_RATE_PARENT,
2279                         .ops = &clk_branch2_ops,
2280                 },
2281         },
2282 };
2283
2284 static struct clk_branch gcc_boot_rom_ahb_clk = {
2285         .halt_reg = 0x38004,
2286         .halt_check = BRANCH_HALT_VOTED,
2287         .clkr = {
2288                 .enable_reg = 0x52004,
2289                 .enable_mask = BIT(10),
2290                 .hw.init = &(struct clk_init_data){
2291                         .name = "gcc_boot_rom_ahb_clk",
2292                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2293                         .num_parents = 1,
2294                         .flags = CLK_SET_RATE_PARENT,
2295                         .ops = &clk_branch2_ops,
2296                 },
2297         },
2298 };
2299
2300 static struct clk_branch gcc_bimc_gfx_clk = {
2301         .halt_reg = 0x46018,
2302         .clkr = {
2303                 .enable_reg = 0x46018,
2304                 .enable_mask = BIT(0),
2305                 .hw.init = &(struct clk_init_data){
2306                         .name = "gcc_bimc_gfx_clk",
2307                         .flags = CLK_SET_RATE_PARENT,
2308                         .ops = &clk_branch2_ops,
2309                 },
2310         },
2311 };
2312
2313 static struct clk_branch gcc_hmss_rbcpr_clk = {
2314         .halt_reg = 0x4800c,
2315         .clkr = {
2316                 .enable_reg = 0x4800c,
2317                 .enable_mask = BIT(0),
2318                 .hw.init = &(struct clk_init_data){
2319                         .name = "gcc_hmss_rbcpr_clk",
2320                         .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2321                         .num_parents = 1,
2322                         .flags = CLK_SET_RATE_PARENT,
2323                         .ops = &clk_branch2_ops,
2324                 },
2325         },
2326 };
2327
2328 static struct clk_branch gcc_gp1_clk = {
2329         .halt_reg = 0x64000,
2330         .clkr = {
2331                 .enable_reg = 0x64000,
2332                 .enable_mask = BIT(0),
2333                 .hw.init = &(struct clk_init_data){
2334                         .name = "gcc_gp1_clk",
2335                         .parent_names = (const char *[]){ "gp1_clk_src" },
2336                         .num_parents = 1,
2337                         .flags = CLK_SET_RATE_PARENT,
2338                         .ops = &clk_branch2_ops,
2339                 },
2340         },
2341 };
2342
2343 static struct clk_branch gcc_gp2_clk = {
2344         .halt_reg = 0x65000,
2345         .clkr = {
2346                 .enable_reg = 0x65000,
2347                 .enable_mask = BIT(0),
2348                 .hw.init = &(struct clk_init_data){
2349                         .name = "gcc_gp2_clk",
2350                         .parent_names = (const char *[]){ "gp2_clk_src" },
2351                         .num_parents = 1,
2352                         .flags = CLK_SET_RATE_PARENT,
2353                         .ops = &clk_branch2_ops,
2354                 },
2355         },
2356 };
2357
2358 static struct clk_branch gcc_gp3_clk = {
2359         .halt_reg = 0x66000,
2360         .clkr = {
2361                 .enable_reg = 0x66000,
2362                 .enable_mask = BIT(0),
2363                 .hw.init = &(struct clk_init_data){
2364                         .name = "gcc_gp3_clk",
2365                         .parent_names = (const char *[]){ "gp3_clk_src" },
2366                         .num_parents = 1,
2367                         .flags = CLK_SET_RATE_PARENT,
2368                         .ops = &clk_branch2_ops,
2369                 },
2370         },
2371 };
2372
2373 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2374         .halt_reg = 0x6b008,
2375         .clkr = {
2376                 .enable_reg = 0x6b008,
2377                 .enable_mask = BIT(0),
2378                 .hw.init = &(struct clk_init_data){
2379                         .name = "gcc_pcie_0_slv_axi_clk",
2380                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2381                         .num_parents = 1,
2382                         .flags = CLK_SET_RATE_PARENT,
2383                         .ops = &clk_branch2_ops,
2384                 },
2385         },
2386 };
2387
2388 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2389         .halt_reg = 0x6b00c,
2390         .clkr = {
2391                 .enable_reg = 0x6b00c,
2392                 .enable_mask = BIT(0),
2393                 .hw.init = &(struct clk_init_data){
2394                         .name = "gcc_pcie_0_mstr_axi_clk",
2395                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2396                         .num_parents = 1,
2397                         .flags = CLK_SET_RATE_PARENT,
2398                         .ops = &clk_branch2_ops,
2399                 },
2400         },
2401 };
2402
2403 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2404         .halt_reg = 0x6b010,
2405         .clkr = {
2406                 .enable_reg = 0x6b010,
2407                 .enable_mask = BIT(0),
2408                 .hw.init = &(struct clk_init_data){
2409                         .name = "gcc_pcie_0_cfg_ahb_clk",
2410                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2411                         .num_parents = 1,
2412                         .flags = CLK_SET_RATE_PARENT,
2413                         .ops = &clk_branch2_ops,
2414                 },
2415         },
2416 };
2417
2418 static struct clk_branch gcc_pcie_0_aux_clk = {
2419         .halt_reg = 0x6b014,
2420         .clkr = {
2421                 .enable_reg = 0x6b014,
2422                 .enable_mask = BIT(0),
2423                 .hw.init = &(struct clk_init_data){
2424                         .name = "gcc_pcie_0_aux_clk",
2425                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2426                         .num_parents = 1,
2427                         .flags = CLK_SET_RATE_PARENT,
2428                         .ops = &clk_branch2_ops,
2429                 },
2430         },
2431 };
2432
2433 static struct clk_branch gcc_pcie_0_pipe_clk = {
2434         .halt_reg = 0x6b018,
2435         .clkr = {
2436                 .enable_reg = 0x6b018,
2437                 .enable_mask = BIT(0),
2438                 .hw.init = &(struct clk_init_data){
2439                         .name = "gcc_pcie_0_pipe_clk",
2440                         .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2441                         .num_parents = 1,
2442                         .flags = CLK_SET_RATE_PARENT,
2443                         .ops = &clk_branch2_ops,
2444                 },
2445         },
2446 };
2447
2448 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2449         .halt_reg = 0x6d008,
2450         .clkr = {
2451                 .enable_reg = 0x6d008,
2452                 .enable_mask = BIT(0),
2453                 .hw.init = &(struct clk_init_data){
2454                         .name = "gcc_pcie_1_slv_axi_clk",
2455                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2456                         .num_parents = 1,
2457                         .flags = CLK_SET_RATE_PARENT,
2458                         .ops = &clk_branch2_ops,
2459                 },
2460         },
2461 };
2462
2463 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2464         .halt_reg = 0x6d00c,
2465         .clkr = {
2466                 .enable_reg = 0x6d00c,
2467                 .enable_mask = BIT(0),
2468                 .hw.init = &(struct clk_init_data){
2469                         .name = "gcc_pcie_1_mstr_axi_clk",
2470                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2471                         .num_parents = 1,
2472                         .flags = CLK_SET_RATE_PARENT,
2473                         .ops = &clk_branch2_ops,
2474                 },
2475         },
2476 };
2477
2478 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2479         .halt_reg = 0x6d010,
2480         .clkr = {
2481                 .enable_reg = 0x6d010,
2482                 .enable_mask = BIT(0),
2483                 .hw.init = &(struct clk_init_data){
2484                         .name = "gcc_pcie_1_cfg_ahb_clk",
2485                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2486                         .num_parents = 1,
2487                         .flags = CLK_SET_RATE_PARENT,
2488                         .ops = &clk_branch2_ops,
2489                 },
2490         },
2491 };
2492
2493 static struct clk_branch gcc_pcie_1_aux_clk = {
2494         .halt_reg = 0x6d014,
2495         .clkr = {
2496                 .enable_reg = 0x6d014,
2497                 .enable_mask = BIT(0),
2498                 .hw.init = &(struct clk_init_data){
2499                         .name = "gcc_pcie_1_aux_clk",
2500                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2501                         .num_parents = 1,
2502                         .flags = CLK_SET_RATE_PARENT,
2503                         .ops = &clk_branch2_ops,
2504                 },
2505         },
2506 };
2507
2508 static struct clk_branch gcc_pcie_1_pipe_clk = {
2509         .halt_reg = 0x6d018,
2510         .clkr = {
2511                 .enable_reg = 0x6d018,
2512                 .enable_mask = BIT(0),
2513                 .hw.init = &(struct clk_init_data){
2514                         .name = "gcc_pcie_1_pipe_clk",
2515                         .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2516                         .num_parents = 1,
2517                         .flags = CLK_SET_RATE_PARENT,
2518                         .ops = &clk_branch2_ops,
2519                 },
2520         },
2521 };
2522
2523 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2524         .halt_reg = 0x6e008,
2525         .clkr = {
2526                 .enable_reg = 0x6e008,
2527                 .enable_mask = BIT(0),
2528                 .hw.init = &(struct clk_init_data){
2529                         .name = "gcc_pcie_2_slv_axi_clk",
2530                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2531                         .num_parents = 1,
2532                         .flags = CLK_SET_RATE_PARENT,
2533                         .ops = &clk_branch2_ops,
2534                 },
2535         },
2536 };
2537
2538 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2539         .halt_reg = 0x6e00c,
2540         .clkr = {
2541                 .enable_reg = 0x6e00c,
2542                 .enable_mask = BIT(0),
2543                 .hw.init = &(struct clk_init_data){
2544                         .name = "gcc_pcie_2_mstr_axi_clk",
2545                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2546                         .num_parents = 1,
2547                         .flags = CLK_SET_RATE_PARENT,
2548                         .ops = &clk_branch2_ops,
2549                 },
2550         },
2551 };
2552
2553 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2554         .halt_reg = 0x6e010,
2555         .clkr = {
2556                 .enable_reg = 0x6e010,
2557                 .enable_mask = BIT(0),
2558                 .hw.init = &(struct clk_init_data){
2559                         .name = "gcc_pcie_2_cfg_ahb_clk",
2560                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2561                         .num_parents = 1,
2562                         .flags = CLK_SET_RATE_PARENT,
2563                         .ops = &clk_branch2_ops,
2564                 },
2565         },
2566 };
2567
2568 static struct clk_branch gcc_pcie_2_aux_clk = {
2569         .halt_reg = 0x6e014,
2570         .clkr = {
2571                 .enable_reg = 0x6e014,
2572                 .enable_mask = BIT(0),
2573                 .hw.init = &(struct clk_init_data){
2574                         .name = "gcc_pcie_2_aux_clk",
2575                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2576                         .num_parents = 1,
2577                         .flags = CLK_SET_RATE_PARENT,
2578                         .ops = &clk_branch2_ops,
2579                 },
2580         },
2581 };
2582
2583 static struct clk_branch gcc_pcie_2_pipe_clk = {
2584         .halt_reg = 0x6e018,
2585         .clkr = {
2586                 .enable_reg = 0x6e018,
2587                 .enable_mask = BIT(0),
2588                 .hw.init = &(struct clk_init_data){
2589                         .name = "gcc_pcie_2_pipe_clk",
2590                         .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2591                         .num_parents = 1,
2592                         .flags = CLK_SET_RATE_PARENT,
2593                         .ops = &clk_branch2_ops,
2594                 },
2595         },
2596 };
2597
2598 static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2599         .halt_reg = 0x6f004,
2600         .clkr = {
2601                 .enable_reg = 0x6f004,
2602                 .enable_mask = BIT(0),
2603                 .hw.init = &(struct clk_init_data){
2604                         .name = "gcc_pcie_phy_cfg_ahb_clk",
2605                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2606                         .num_parents = 1,
2607                         .flags = CLK_SET_RATE_PARENT,
2608                         .ops = &clk_branch2_ops,
2609                 },
2610         },
2611 };
2612
2613 static struct clk_branch gcc_pcie_phy_aux_clk = {
2614         .halt_reg = 0x6f008,
2615         .clkr = {
2616                 .enable_reg = 0x6f008,
2617                 .enable_mask = BIT(0),
2618                 .hw.init = &(struct clk_init_data){
2619                         .name = "gcc_pcie_phy_aux_clk",
2620                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2621                         .num_parents = 1,
2622                         .flags = CLK_SET_RATE_PARENT,
2623                         .ops = &clk_branch2_ops,
2624                 },
2625         },
2626 };
2627
2628 static struct clk_branch gcc_ufs_axi_clk = {
2629         .halt_reg = 0x75008,
2630         .clkr = {
2631                 .enable_reg = 0x75008,
2632                 .enable_mask = BIT(0),
2633                 .hw.init = &(struct clk_init_data){
2634                         .name = "gcc_ufs_axi_clk",
2635                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2636                         .num_parents = 1,
2637                         .flags = CLK_SET_RATE_PARENT,
2638                         .ops = &clk_branch2_ops,
2639                 },
2640         },
2641 };
2642
2643 static struct clk_branch gcc_ufs_ahb_clk = {
2644         .halt_reg = 0x7500c,
2645         .clkr = {
2646                 .enable_reg = 0x7500c,
2647                 .enable_mask = BIT(0),
2648                 .hw.init = &(struct clk_init_data){
2649                         .name = "gcc_ufs_ahb_clk",
2650                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2651                         .num_parents = 1,
2652                         .flags = CLK_SET_RATE_PARENT,
2653                         .ops = &clk_branch2_ops,
2654                 },
2655         },
2656 };
2657
2658 static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2659         .mult = 1,
2660         .div = 16,
2661         .hw.init = &(struct clk_init_data){
2662                 .name = "ufs_tx_cfg_clk_src",
2663                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2664                 .num_parents = 1,
2665                 .flags = CLK_SET_RATE_PARENT,
2666                 .ops = &clk_fixed_factor_ops,
2667         },
2668 };
2669
2670 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2671         .halt_reg = 0x75010,
2672         .clkr = {
2673                 .enable_reg = 0x75010,
2674                 .enable_mask = BIT(0),
2675                 .hw.init = &(struct clk_init_data){
2676                         .name = "gcc_ufs_tx_cfg_clk",
2677                         .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2678                         .num_parents = 1,
2679                         .flags = CLK_SET_RATE_PARENT,
2680                         .ops = &clk_branch2_ops,
2681                 },
2682         },
2683 };
2684
2685 static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2686         .mult = 1,
2687         .div = 16,
2688         .hw.init = &(struct clk_init_data){
2689                 .name = "ufs_rx_cfg_clk_src",
2690                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2691                 .num_parents = 1,
2692                 .flags = CLK_SET_RATE_PARENT,
2693                 .ops = &clk_fixed_factor_ops,
2694         },
2695 };
2696
2697 static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
2698         .halt_reg = 0x7d010,
2699         .halt_check = BRANCH_HALT_VOTED,
2700         .clkr = {
2701                 .enable_reg = 0x7d010,
2702                 .enable_mask = BIT(0),
2703                 .hw.init = &(struct clk_init_data){
2704                         .name = "hlos1_vote_lpass_core_smmu_clk",
2705                         .ops = &clk_branch2_ops,
2706                 },
2707         },
2708 };
2709
2710 static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
2711         .halt_reg = 0x7d014,
2712         .halt_check = BRANCH_HALT_VOTED,
2713         .clkr = {
2714                 .enable_reg = 0x7d014,
2715                 .enable_mask = BIT(0),
2716                 .hw.init = &(struct clk_init_data){
2717                         .name = "hlos1_vote_lpass_adsp_smmu_clk",
2718                         .ops = &clk_branch2_ops,
2719                 },
2720         },
2721 };
2722
2723 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2724         .halt_reg = 0x75014,
2725         .clkr = {
2726                 .enable_reg = 0x75014,
2727                 .enable_mask = BIT(0),
2728                 .hw.init = &(struct clk_init_data){
2729                         .name = "gcc_ufs_rx_cfg_clk",
2730                         .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2731                         .num_parents = 1,
2732                         .flags = CLK_SET_RATE_PARENT,
2733                         .ops = &clk_branch2_ops,
2734                 },
2735         },
2736 };
2737
2738 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2739         .halt_reg = 0x75018,
2740         .clkr = {
2741                 .enable_reg = 0x75018,
2742                 .enable_mask = BIT(0),
2743                 .hw.init = &(struct clk_init_data){
2744                         .name = "gcc_ufs_tx_symbol_0_clk",
2745                         .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2746                         .num_parents = 1,
2747                         .flags = CLK_SET_RATE_PARENT,
2748                         .ops = &clk_branch2_ops,
2749                 },
2750         },
2751 };
2752
2753 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2754         .halt_reg = 0x7501c,
2755         .clkr = {
2756                 .enable_reg = 0x7501c,
2757                 .enable_mask = BIT(0),
2758                 .hw.init = &(struct clk_init_data){
2759                         .name = "gcc_ufs_rx_symbol_0_clk",
2760                         .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2761                         .num_parents = 1,
2762                         .flags = CLK_SET_RATE_PARENT,
2763                         .ops = &clk_branch2_ops,
2764                 },
2765         },
2766 };
2767
2768 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2769         .halt_reg = 0x75020,
2770         .clkr = {
2771                 .enable_reg = 0x75020,
2772                 .enable_mask = BIT(0),
2773                 .hw.init = &(struct clk_init_data){
2774                         .name = "gcc_ufs_rx_symbol_1_clk",
2775                         .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2776                         .num_parents = 1,
2777                         .flags = CLK_SET_RATE_PARENT,
2778                         .ops = &clk_branch2_ops,
2779                 },
2780         },
2781 };
2782
2783 static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2784         .mult = 1,
2785         .div = 2,
2786         .hw.init = &(struct clk_init_data){
2787                 .name = "ufs_ice_core_postdiv_clk_src",
2788                 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2789                 .num_parents = 1,
2790                 .flags = CLK_SET_RATE_PARENT,
2791                 .ops = &clk_fixed_factor_ops,
2792         },
2793 };
2794
2795 static struct clk_branch gcc_ufs_unipro_core_clk = {
2796         .halt_reg = 0x7600c,
2797         .clkr = {
2798                 .enable_reg = 0x7600c,
2799                 .enable_mask = BIT(0),
2800                 .hw.init = &(struct clk_init_data){
2801                         .name = "gcc_ufs_unipro_core_clk",
2802                         .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2803                         .num_parents = 1,
2804                         .flags = CLK_SET_RATE_PARENT,
2805                         .ops = &clk_branch2_ops,
2806                 },
2807         },
2808 };
2809
2810 static struct clk_branch gcc_ufs_ice_core_clk = {
2811         .halt_reg = 0x76010,
2812         .clkr = {
2813                 .enable_reg = 0x76010,
2814                 .enable_mask = BIT(0),
2815                 .hw.init = &(struct clk_init_data){
2816                         .name = "gcc_ufs_ice_core_clk",
2817                         .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2818                         .num_parents = 1,
2819                         .flags = CLK_SET_RATE_PARENT,
2820                         .ops = &clk_branch2_ops,
2821                 },
2822         },
2823 };
2824
2825 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2826         .halt_check = BRANCH_HALT_DELAY,
2827         .clkr = {
2828                 .enable_reg = 0x76030,
2829                 .enable_mask = BIT(0),
2830                 .hw.init = &(struct clk_init_data){
2831                         .name = "gcc_ufs_sys_clk_core_clk",
2832                         .ops = &clk_branch2_ops,
2833                 },
2834         },
2835 };
2836
2837 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2838         .halt_check = BRANCH_HALT_DELAY,
2839         .clkr = {
2840                 .enable_reg = 0x76034,
2841                 .enable_mask = BIT(0),
2842                 .hw.init = &(struct clk_init_data){
2843                         .name = "gcc_ufs_tx_symbol_clk_core_clk",
2844                         .ops = &clk_branch2_ops,
2845                 },
2846         },
2847 };
2848
2849 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2850         .halt_reg = 0x81008,
2851         .clkr = {
2852                 .enable_reg = 0x81008,
2853                 .enable_mask = BIT(0),
2854                 .hw.init = &(struct clk_init_data){
2855                         .name = "gcc_aggre0_snoc_axi_clk",
2856                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2857                         .num_parents = 1,
2858                         .flags = CLK_SET_RATE_PARENT,
2859                         .ops = &clk_branch2_ops,
2860                 },
2861         },
2862 };
2863
2864 static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2865         .halt_reg = 0x8100c,
2866         .clkr = {
2867                 .enable_reg = 0x8100c,
2868                 .enable_mask = BIT(0),
2869                 .hw.init = &(struct clk_init_data){
2870                         .name = "gcc_aggre0_cnoc_ahb_clk",
2871                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2872                         .num_parents = 1,
2873                         .flags = CLK_SET_RATE_PARENT,
2874                         .ops = &clk_branch2_ops,
2875                 },
2876         },
2877 };
2878
2879 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2880         .halt_reg = 0x81014,
2881         .clkr = {
2882                 .enable_reg = 0x81014,
2883                 .enable_mask = BIT(0),
2884                 .hw.init = &(struct clk_init_data){
2885                         .name = "gcc_smmu_aggre0_axi_clk",
2886                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2887                         .num_parents = 1,
2888                         .flags = CLK_SET_RATE_PARENT,
2889                         .ops = &clk_branch2_ops,
2890                 },
2891         },
2892 };
2893
2894 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2895         .halt_reg = 0x81018,
2896         .clkr = {
2897                 .enable_reg = 0x81018,
2898                 .enable_mask = BIT(0),
2899                 .hw.init = &(struct clk_init_data){
2900                         .name = "gcc_smmu_aggre0_ahb_clk",
2901                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2902                         .num_parents = 1,
2903                         .flags = CLK_SET_RATE_PARENT,
2904                         .ops = &clk_branch2_ops,
2905                 },
2906         },
2907 };
2908
2909 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2910         .halt_reg = 0x83014,
2911         .clkr = {
2912                 .enable_reg = 0x83014,
2913                 .enable_mask = BIT(0),
2914                 .hw.init = &(struct clk_init_data){
2915                         .name = "gcc_aggre2_ufs_axi_clk",
2916                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2917                         .num_parents = 1,
2918                         .flags = CLK_SET_RATE_PARENT,
2919                         .ops = &clk_branch2_ops,
2920                 },
2921         },
2922 };
2923
2924 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2925         .halt_reg = 0x83018,
2926         .clkr = {
2927                 .enable_reg = 0x83018,
2928                 .enable_mask = BIT(0),
2929                 .hw.init = &(struct clk_init_data){
2930                         .name = "gcc_aggre2_usb3_axi_clk",
2931                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
2932                         .num_parents = 1,
2933                         .flags = CLK_SET_RATE_PARENT,
2934                         .ops = &clk_branch2_ops,
2935                 },
2936         },
2937 };
2938
2939 static struct clk_branch gcc_qspi_ahb_clk = {
2940         .halt_reg = 0x8b004,
2941         .clkr = {
2942                 .enable_reg = 0x8b004,
2943                 .enable_mask = BIT(0),
2944                 .hw.init = &(struct clk_init_data){
2945                         .name = "gcc_qspi_ahb_clk",
2946                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2947                         .num_parents = 1,
2948                         .flags = CLK_SET_RATE_PARENT,
2949                         .ops = &clk_branch2_ops,
2950                 },
2951         },
2952 };
2953
2954 static struct clk_branch gcc_qspi_ser_clk = {
2955         .halt_reg = 0x8b008,
2956         .clkr = {
2957                 .enable_reg = 0x8b008,
2958                 .enable_mask = BIT(0),
2959                 .hw.init = &(struct clk_init_data){
2960                         .name = "gcc_qspi_ser_clk",
2961                         .parent_names = (const char *[]){ "qspi_ser_clk_src" },
2962                         .num_parents = 1,
2963                         .flags = CLK_SET_RATE_PARENT,
2964                         .ops = &clk_branch2_ops,
2965                 },
2966         },
2967 };
2968
2969 static struct clk_branch gcc_usb3_clkref_clk = {
2970         .halt_reg = 0x8800C,
2971         .clkr = {
2972                 .enable_reg = 0x8800C,
2973                 .enable_mask = BIT(0),
2974                 .hw.init = &(struct clk_init_data){
2975                         .name = "gcc_usb3_clkref_clk",
2976                         .parent_names = (const char *[]){ "xo" },
2977                         .num_parents = 1,
2978                         .ops = &clk_branch2_ops,
2979                 },
2980         },
2981 };
2982
2983 static struct clk_branch gcc_hdmi_clkref_clk = {
2984         .halt_reg = 0x88000,
2985         .clkr = {
2986                 .enable_reg = 0x88000,
2987                 .enable_mask = BIT(0),
2988                 .hw.init = &(struct clk_init_data){
2989                         .name = "gcc_hdmi_clkref_clk",
2990                         .parent_names = (const char *[]){ "xo" },
2991                         .num_parents = 1,
2992                         .ops = &clk_branch2_ops,
2993                 },
2994         },
2995 };
2996
2997 static struct clk_branch gcc_ufs_clkref_clk = {
2998         .halt_reg = 0x88008,
2999         .clkr = {
3000                 .enable_reg = 0x88008,
3001                 .enable_mask = BIT(0),
3002                 .hw.init = &(struct clk_init_data){
3003                         .name = "gcc_ufs_clkref_clk",
3004                         .parent_names = (const char *[]){ "xo" },
3005                         .num_parents = 1,
3006                         .ops = &clk_branch2_ops,
3007                 },
3008         },
3009 };
3010
3011 static struct clk_branch gcc_pcie_clkref_clk = {
3012         .halt_reg = 0x88010,
3013         .clkr = {
3014                 .enable_reg = 0x88010,
3015                 .enable_mask = BIT(0),
3016                 .hw.init = &(struct clk_init_data){
3017                         .name = "gcc_pcie_clkref_clk",
3018                         .parent_names = (const char *[]){ "xo" },
3019                         .num_parents = 1,
3020                         .ops = &clk_branch2_ops,
3021                 },
3022         },
3023 };
3024
3025 static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3026         .halt_reg = 0x88014,
3027         .clkr = {
3028                 .enable_reg = 0x88014,
3029                 .enable_mask = BIT(0),
3030                 .hw.init = &(struct clk_init_data){
3031                         .name = "gcc_rx2_usb2_clkref_clk",
3032                         .parent_names = (const char *[]){ "xo" },
3033                         .num_parents = 1,
3034                         .ops = &clk_branch2_ops,
3035                 },
3036         },
3037 };
3038
3039 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3040         .halt_reg = 0x88018,
3041         .clkr = {
3042                 .enable_reg = 0x88018,
3043                 .enable_mask = BIT(0),
3044                 .hw.init = &(struct clk_init_data){
3045                         .name = "gcc_rx1_usb2_clkref_clk",
3046                         .parent_names = (const char *[]){ "xo" },
3047                         .num_parents = 1,
3048                         .ops = &clk_branch2_ops,
3049                 },
3050         },
3051 };
3052
3053 static struct clk_hw *gcc_msm8996_hws[] = {
3054         &xo.hw,
3055         &gpll0_early_div.hw,
3056         &ufs_tx_cfg_clk_src.hw,
3057         &ufs_rx_cfg_clk_src.hw,
3058         &ufs_ice_core_postdiv_clk_src.hw,
3059 };
3060
3061 static struct gdsc aggre0_noc_gdsc = {
3062         .gdscr = 0x81004,
3063         .gds_hw_ctrl = 0x81028,
3064         .pd = {
3065                 .name = "aggre0_noc",
3066         },
3067         .pwrsts = PWRSTS_OFF_ON,
3068         .flags = VOTABLE,
3069 };
3070
3071 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3072         .gdscr = 0x7d024,
3073         .pd = {
3074                 .name = "hlos1_vote_aggre0_noc",
3075         },
3076         .pwrsts = PWRSTS_OFF_ON,
3077         .flags = VOTABLE,
3078 };
3079
3080 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3081         .gdscr = 0x7d034,
3082         .pd = {
3083                 .name = "hlos1_vote_lpass_adsp",
3084         },
3085         .pwrsts = PWRSTS_OFF_ON,
3086         .flags = VOTABLE,
3087 };
3088
3089 static struct gdsc hlos1_vote_lpass_core_gdsc = {
3090         .gdscr = 0x7d038,
3091         .pd = {
3092                 .name = "hlos1_vote_lpass_core",
3093         },
3094         .pwrsts = PWRSTS_OFF_ON,
3095         .flags = VOTABLE,
3096 };
3097
3098 static struct gdsc usb30_gdsc = {
3099         .gdscr = 0xf004,
3100         .pd = {
3101                 .name = "usb30",
3102         },
3103         .pwrsts = PWRSTS_OFF_ON,
3104 };
3105
3106 static struct gdsc pcie0_gdsc = {
3107         .gdscr = 0x6b004,
3108         .pd = {
3109                 .name = "pcie0",
3110         },
3111         .pwrsts = PWRSTS_OFF_ON,
3112 };
3113
3114 static struct gdsc pcie1_gdsc = {
3115         .gdscr = 0x6d004,
3116         .pd = {
3117                 .name = "pcie1",
3118         },
3119         .pwrsts = PWRSTS_OFF_ON,
3120 };
3121
3122 static struct gdsc pcie2_gdsc = {
3123         .gdscr = 0x6e004,
3124         .pd = {
3125                 .name = "pcie2",
3126         },
3127         .pwrsts = PWRSTS_OFF_ON,
3128 };
3129
3130 static struct gdsc ufs_gdsc = {
3131         .gdscr = 0x75004,
3132         .pd = {
3133                 .name = "ufs",
3134         },
3135         .pwrsts = PWRSTS_OFF_ON,
3136 };
3137
3138 static struct clk_regmap *gcc_msm8996_clocks[] = {
3139         [GPLL0_EARLY] = &gpll0_early.clkr,
3140         [GPLL0] = &gpll0.clkr,
3141         [GPLL4_EARLY] = &gpll4_early.clkr,
3142         [GPLL4] = &gpll4.clkr,
3143         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3144         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3145         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3146         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3147         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3148         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3149         [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3150         [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3151         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3152         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3153         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3154         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3155         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3156         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3157         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3158         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3159         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3160         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3161         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3162         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3163         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3164         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3165         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3166         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3167         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3168         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3169         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3170         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3171         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3172         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3173         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3174         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3175         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3176         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3177         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3178         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3179         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3180         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3181         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3182         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3183         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3184         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3185         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3186         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3187         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3188         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3189         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3190         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3191         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3192         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3193         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3194         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3195         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3196         [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3197         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3198         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3199         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3200         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3201         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3202         [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3203         [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3204         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3205         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3206         [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3207         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3208         [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3209         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3210         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3211         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3212         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3213         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3214         [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3215         [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3216         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3217         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3218         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3219         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3220         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3221         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3222         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3223         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3224         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3225         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3226         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3227         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3228         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3229         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3230         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3231         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3232         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3233         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3234         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3235         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3236         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3237         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3238         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3239         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3240         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3241         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3242         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3243         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3244         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3245         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3246         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3247         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3248         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3249         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3250         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3251         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3252         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3253         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3254         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3255         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3256         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3257         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3258         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3259         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3260         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3261         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3262         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3263         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3264         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3265         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3266         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3267         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3268         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3269         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3270         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3271         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3272         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3273         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3274         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3275         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3276         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3277         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3278         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3279         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3280         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3281         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3282         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3283         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3284         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3285         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3286         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3287         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3288         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3289         [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3290         [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3291         [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3292         [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3293         [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3294         [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3295         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3296         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3297         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3298         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3299         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3300         [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
3301         [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
3302         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3303         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3304         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3305         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3306         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3307         [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3308         [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3309         [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3310         [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3311         [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3312         [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3313         [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3314         [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3315         [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3316         [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3317         [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3318         [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3319         [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3320         [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3321         [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3322         [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3323 };
3324
3325 static struct gdsc *gcc_msm8996_gdscs[] = {
3326         [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3327         [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3328         [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3329         [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3330         [USB30_GDSC] = &usb30_gdsc,
3331         [PCIE0_GDSC] = &pcie0_gdsc,
3332         [PCIE1_GDSC] = &pcie1_gdsc,
3333         [PCIE2_GDSC] = &pcie2_gdsc,
3334         [UFS_GDSC] = &ufs_gdsc,
3335 };
3336
3337 static const struct qcom_reset_map gcc_msm8996_resets[] = {
3338         [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3339         [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3340         [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3341         [GCC_IMEM_BCR] = { 0x8000 },
3342         [GCC_MMSS_BCR] = { 0x9000 },
3343         [GCC_PIMEM_BCR] = { 0x0a000 },
3344         [GCC_QDSS_BCR] = { 0x0c000 },
3345         [GCC_USB_30_BCR] = { 0x0f000 },
3346         [GCC_USB_20_BCR] = { 0x12000 },
3347         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3348         [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3349         [GCC_USB3_PHY_BCR] = { 0x50020 },
3350         [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3351         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3352         [GCC_SDCC1_BCR] = { 0x13000 },
3353         [GCC_SDCC2_BCR] = { 0x14000 },
3354         [GCC_SDCC3_BCR] = { 0x15000 },
3355         [GCC_SDCC4_BCR] = { 0x16000 },
3356         [GCC_BLSP1_BCR] = { 0x17000 },
3357         [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3358         [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3359         [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3360         [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3361         [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3362         [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3363         [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3364         [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3365         [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3366         [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3367         [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3368         [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3369         [GCC_BLSP2_BCR] = { 0x25000 },
3370         [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3371         [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3372         [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3373         [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3374         [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3375         [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3376         [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3377         [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3378         [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3379         [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3380         [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3381         [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3382         [GCC_PDM_BCR] = { 0x33000 },
3383         [GCC_PRNG_BCR] = { 0x34000 },
3384         [GCC_TSIF_BCR] = { 0x36000 },
3385         [GCC_TCSR_BCR] = { 0x37000 },
3386         [GCC_BOOT_ROM_BCR] = { 0x38000 },
3387         [GCC_MSG_RAM_BCR] = { 0x39000 },
3388         [GCC_TLMM_BCR] = { 0x3a000 },
3389         [GCC_MPM_BCR] = { 0x3b000 },
3390         [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3391         [GCC_SPMI_BCR] = { 0x3f000 },
3392         [GCC_SPDM_BCR] = { 0x40000 },
3393         [GCC_CE1_BCR] = { 0x41000 },
3394         [GCC_BIMC_BCR] = { 0x44000 },
3395         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3396         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3397         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3398         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3399         [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3400         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3401         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3402         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3403         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3404         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3405         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3406         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3407         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3408         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3409         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3410         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3411         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3412         [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3413         [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3414         [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3415         [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3416         [GCC_APB2JTAG_BCR] = { 0x4c000 },
3417         [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3418         [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3419         [GCC_PCIE_0_BCR] = { 0x6b000 },
3420         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3421         [GCC_PCIE_1_BCR] = { 0x6d000 },
3422         [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3423         [GCC_PCIE_2_BCR] = { 0x6e000 },
3424         [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3425         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3426         [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3427         [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3428         [GCC_DCD_BCR] = { 0x70000 },
3429         [GCC_OBT_ODT_BCR] = { 0x73000 },
3430         [GCC_UFS_BCR] = { 0x75000 },
3431         [GCC_SSC_BCR] = { 0x63000 },
3432         [GCC_VS_BCR] = { 0x7a000 },
3433         [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3434         [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3435         [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3436         [GCC_DCC_BCR] = { 0x84000 },
3437         [GCC_IPA_BCR] = { 0x89000 },
3438         [GCC_QSPI_BCR] = { 0x8b000 },
3439         [GCC_SKL_BCR] = { 0x8c000 },
3440         [GCC_MSMPU_BCR] = { 0x8d000 },
3441         [GCC_MSS_Q6_BCR] = { 0x8e000 },
3442         [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3443         [GCC_MSS_RESTART] = { 0x8f008 },
3444 };
3445
3446 static const struct regmap_config gcc_msm8996_regmap_config = {
3447         .reg_bits       = 32,
3448         .reg_stride     = 4,
3449         .val_bits       = 32,
3450         .max_register   = 0x8f010,
3451         .fast_io        = true,
3452 };
3453
3454 static const struct qcom_cc_desc gcc_msm8996_desc = {
3455         .config = &gcc_msm8996_regmap_config,
3456         .clks = gcc_msm8996_clocks,
3457         .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3458         .resets = gcc_msm8996_resets,
3459         .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3460         .gdscs = gcc_msm8996_gdscs,
3461         .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3462 };
3463
3464 static const struct of_device_id gcc_msm8996_match_table[] = {
3465         { .compatible = "qcom,gcc-msm8996" },
3466         { }
3467 };
3468 MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3469
3470 static int gcc_msm8996_probe(struct platform_device *pdev)
3471 {
3472         struct device *dev = &pdev->dev;
3473         int i, ret;
3474         struct regmap *regmap;
3475
3476         regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3477         if (IS_ERR(regmap))
3478                 return PTR_ERR(regmap);
3479
3480         /*
3481          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3482          * turned off by hardware during certain apps low power modes.
3483          */
3484         regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3485
3486         for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3487                 ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
3488                 if (ret)
3489                         return ret;
3490         }
3491
3492         return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3493 }
3494
3495 static struct platform_driver gcc_msm8996_driver = {
3496         .probe          = gcc_msm8996_probe,
3497         .driver         = {
3498                 .name   = "gcc-msm8996",
3499                 .of_match_table = gcc_msm8996_match_table,
3500         },
3501 };
3502
3503 static int __init gcc_msm8996_init(void)
3504 {
3505         return platform_driver_register(&gcc_msm8996_driver);
3506 }
3507 core_initcall(gcc_msm8996_init);
3508
3509 static void __exit gcc_msm8996_exit(void)
3510 {
3511         platform_driver_unregister(&gcc_msm8996_driver);
3512 }
3513 module_exit(gcc_msm8996_exit);
3514
3515 MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3516 MODULE_LICENSE("GPL v2");
3517 MODULE_ALIAS("platform:gcc-msm8996");