drivers/clk/qcom/gcc-msm8996.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  26
  27 #include "common.h"
  28 #include "clk-regmap.h"
  29 #include "clk-alpha-pll.h"
  30 #include "clk-rcg.h"
  31 #include "clk-branch.h"
  32 #include "reset.h"
  33 #include "gdsc.h"
  34
  35 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  36
  37 enum {
  38         P_XO,
  39         P_GPLL0,
  40         P_GPLL2,
  41         P_GPLL3,
  42         P_GPLL1,
  43         P_GPLL2_EARLY,
  44         P_GPLL0_EARLY_DIV,
  45         P_SLEEP_CLK,
  46         P_GPLL4,
  47         P_AUD_REF_CLK,
  48         P_GPLL1_EARLY_DIV
  49 };
  50
  51 static const struct parent_map gcc_sleep_clk_map[] = {
  52         { P_SLEEP_CLK, 5 }
  53 };
  54
  55 static const char * const gcc_sleep_clk[] = {
  56         "sleep_clk"
  57 };
  58
  59 static const struct parent_map gcc_xo_gpll0_map[] = {
  60         { P_XO, 0 },
  61         { P_GPLL0, 1 }
  62 };
  63
  64 static const char * const gcc_xo_gpll0[] = {
  65         "xo",
  66         "gpll0"
  67 };
  68
  69 static const struct parent_map gcc_xo_sleep_clk_map[] = {
  70         { P_XO, 0 },
  71         { P_SLEEP_CLK, 5 }
  72 };
  73
  74 static const char * const gcc_xo_sleep_clk[] = {
  75         "xo",
  76         "sleep_clk"
  77 };
  78
  79 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
  80         { P_XO, 0 },
  81         { P_GPLL0, 1 },
  82         { P_GPLL0_EARLY_DIV, 6 }
  83 };
  84
  85 static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
  86         "xo",
  87         "gpll0",
  88         "gpll0_early_div"
  89 };
  90
  91 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  92         { P_XO, 0 },
  93         { P_GPLL0, 1 },
  94         { P_GPLL4, 5 }
  95 };
  96
  97 static const char * const gcc_xo_gpll0_gpll4[] = {
  98         "xo",
  99         "gpll0",
 100         "gpll4"
 101 };
 102
 103 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
 104         { P_XO, 0 },
 105         { P_GPLL0, 1 },
 106         { P_AUD_REF_CLK, 2 }
 107 };
 108
 109 static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
 110         "xo",
 111         "gpll0",
 112         "aud_ref_clk"
 113 };
 114
 115 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
 116         { P_XO, 0 },
 117         { P_GPLL0, 1 },
 118         { P_SLEEP_CLK, 5 },
 119         { P_GPLL0_EARLY_DIV, 6 }
 120 };
 121
 122 static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
 123         "xo",
 124         "gpll0",
 125         "sleep_clk",
 126         "gpll0_early_div"
 127 };
 128
 129 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 130         { P_XO, 0 },
 131         { P_GPLL0, 1 },
 132         { P_GPLL4, 5 },
 133         { P_GPLL0_EARLY_DIV, 6 }
 134 };
 135
 136 static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 137         "xo",
 138         "gpll0",
 139         "gpll4",
 140         "gpll0_early_div"
 141 };
 142
 143 static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
 144         { P_XO, 0 },
 145         { P_GPLL0, 1 },
 146         { P_GPLL1_EARLY_DIV, 3 },
 147         { P_GPLL1, 4 },
 148         { P_GPLL4, 5 },
 149         { P_GPLL0_EARLY_DIV, 6 }
 150 };
 151
 152 static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
 153         "xo",
 154         "gpll0",
 155         "gpll1_early_div",
 156         "gpll1",
 157         "gpll4",
 158         "gpll0_early_div"
 159 };
 160
 161 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
 162         { P_XO, 0 },
 163         { P_GPLL0, 1 },
 164         { P_GPLL2, 2 },
 165         { P_GPLL3, 3 },
 166         { P_GPLL1, 4 },
 167         { P_GPLL2_EARLY, 5 },
 168         { P_GPLL0_EARLY_DIV, 6 }
 169 };
 170
 171 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
 172         "xo",
 173         "gpll0",
 174         "gpll2",
 175         "gpll3",
 176         "gpll1",
 177         "gpll2_early",
 178         "gpll0_early_div"
 179 };
 180
 181 static struct clk_fixed_factor xo = {
 182         .mult = 1,
 183         .div = 1,
 184         .hw.init = &(struct clk_init_data){
 185                 .name = "xo",
 186                 .parent_names = (const char *[]){ "xo_board" },
 187                 .num_parents = 1,
 188                 .ops = &clk_fixed_factor_ops,
 189         },
 190 };
 191
 192 static struct clk_alpha_pll gpll0_early = {
 193         .offset = 0x00000,
 194         .clkr = {
 195                 .enable_reg = 0x52000,
 196                 .enable_mask = BIT(0),
 197                 .hw.init = &(struct clk_init_data){
 198                         .name = "gpll0_early",
 199                         .parent_names = (const char *[]){ "xo" },
 200                         .num_parents = 1,
 201                         .ops = &clk_alpha_pll_ops,
 202                 },
 203         },
 204 };
 205
 206 static struct clk_fixed_factor gpll0_early_div = {
 207         .mult = 1,
 208         .div = 2,
 209         .hw.init = &(struct clk_init_data){
 210                 .name = "gpll0_early_div",
 211                 .parent_names = (const char *[]){ "gpll0_early" },
 212                 .num_parents = 1,
 213                 .ops = &clk_fixed_factor_ops,
 214         },
 215 };
 216
 217 static struct clk_alpha_pll_postdiv gpll0 = {
 218         .offset = 0x00000,
 219         .clkr.hw.init = &(struct clk_init_data){
 220                 .name = "gpll0",
 221                 .parent_names = (const char *[]){ "gpll0_early" },
 222                 .num_parents = 1,
 223                 .ops = &clk_alpha_pll_postdiv_ops,
 224         },
 225 };
 226
 227 static struct clk_alpha_pll gpll4_early = {
 228         .offset = 0x77000,
 229         .clkr = {
 230                 .enable_reg = 0x52000,
 231                 .enable_mask = BIT(4),
 232                 .hw.init = &(struct clk_init_data){
 233                         .name = "gpll4_early",
 234                         .parent_names = (const char *[]){ "xo" },
 235                         .num_parents = 1,
 236                         .ops = &clk_alpha_pll_ops,
 237                 },
 238         },
 239 };
 240
 241 static struct clk_alpha_pll_postdiv gpll4 = {
 242         .offset = 0x77000,
 243         .clkr.hw.init = &(struct clk_init_data){
 244                 .name = "gpll4",
 245                 .parent_names = (const char *[]){ "gpll4_early" },
 246                 .num_parents = 1,
 247                 .ops = &clk_alpha_pll_postdiv_ops,
 248         },
 249 };
 250
 251 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 252         F(19200000, P_XO, 1, 0, 0),
 253         F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
 254         F(100000000, P_GPLL0, 6, 0, 0),
 255         F(150000000, P_GPLL0, 4, 0, 0),
 256         F(200000000, P_GPLL0, 3, 0, 0),
 257         F(240000000, P_GPLL0, 2.5, 0, 0),
 258         { }
 259 };
 260
 261 static struct clk_rcg2 system_noc_clk_src = {
 262         .cmd_rcgr = 0x0401c,
 263         .hid_width = 5,
 264         .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
 265         .freq_tbl = ftbl_system_noc_clk_src,
 266         .clkr.hw.init = &(struct clk_init_data){
 267                 .name = "system_noc_clk_src",
 268                 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
 269                 .num_parents = 7,
 270                 .ops = &clk_rcg2_ops,
 271         },
 272 };
 273
 274 static const struct freq_tbl ftbl_config_noc_clk_src[] = {
 275         F(19200000, P_XO, 1, 0, 0),
 276         F(37500000, P_GPLL0, 16, 0, 0),
 277         F(75000000, P_GPLL0, 8, 0, 0),
 278         { }
 279 };
 280
 281 static struct clk_rcg2 config_noc_clk_src = {
 282         .cmd_rcgr = 0x0500c,
 283         .hid_width = 5,
 284         .parent_map = gcc_xo_gpll0_map,
 285         .freq_tbl = ftbl_config_noc_clk_src,
 286         .clkr.hw.init = &(struct clk_init_data){
 287                 .name = "config_noc_clk_src",
 288                 .parent_names = gcc_xo_gpll0,
 289                 .num_parents = 2,
 290                 .ops = &clk_rcg2_ops,
 291         },
 292 };
 293
 294 static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
 295         F(19200000, P_XO, 1, 0, 0),
 296         F(37500000, P_GPLL0, 16, 0, 0),
 297         F(50000000, P_GPLL0, 12, 0, 0),
 298         F(75000000, P_GPLL0, 8, 0, 0),
 299         F(100000000, P_GPLL0, 6, 0, 0),
 300         { }
 301 };
 302
 303 static struct clk_rcg2 periph_noc_clk_src = {
 304         .cmd_rcgr = 0x06014,
 305         .hid_width = 5,
 306         .parent_map = gcc_xo_gpll0_map,
 307         .freq_tbl = ftbl_periph_noc_clk_src,
 308         .clkr.hw.init = &(struct clk_init_data){
 309                 .name = "periph_noc_clk_src",
 310                 .parent_names = gcc_xo_gpll0,
 311                 .num_parents = 2,
 312                 .ops = &clk_rcg2_ops,
 313         },
 314 };
 315
 316 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
 317         F(19200000, P_XO, 1, 0, 0),
 318         F(120000000, P_GPLL0, 5, 0, 0),
 319         F(150000000, P_GPLL0, 4, 0, 0),
 320         { }
 321 };
 322
 323 static struct clk_rcg2 usb30_master_clk_src = {
 324         .cmd_rcgr = 0x0f014,
 325         .mnd_width = 8,
 326         .hid_width = 5,
 327         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 328         .freq_tbl = ftbl_usb30_master_clk_src,
 329         .clkr.hw.init = &(struct clk_init_data){
 330                 .name = "usb30_master_clk_src",
 331                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 332                 .num_parents = 3,
 333                 .ops = &clk_rcg2_ops,
 334         },
 335 };
 336
 337 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 338         F(19200000, P_XO, 1, 0, 0),
 339         { }
 340 };
 341
 342 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 343         .cmd_rcgr = 0x0f028,
 344         .hid_width = 5,
 345         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 346         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 347         .clkr.hw.init = &(struct clk_init_data){
 348                 .name = "usb30_mock_utmi_clk_src",
 349                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 350                 .num_parents = 3,
 351                 .ops = &clk_rcg2_ops,
 352         },
 353 };
 354
 355 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
 356         F(1200000, P_XO, 16, 0, 0),
 357         { }
 358 };
 359
 360 static struct clk_rcg2 usb3_phy_aux_clk_src = {
 361         .cmd_rcgr = 0x5000c,
 362         .hid_width = 5,
 363         .parent_map = gcc_xo_sleep_clk_map,
 364         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
 365         .clkr.hw.init = &(struct clk_init_data){
 366                 .name = "usb3_phy_aux_clk_src",
 367                 .parent_names = gcc_xo_sleep_clk,
 368                 .num_parents = 2,
 369                 .ops = &clk_rcg2_ops,
 370         },
 371 };
 372
 373 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
 374         F(120000000, P_GPLL0, 5, 0, 0),
 375         { }
 376 };
 377
 378 static struct clk_rcg2 usb20_master_clk_src = {
 379         .cmd_rcgr = 0x12010,
 380         .mnd_width = 8,
 381         .hid_width = 5,
 382         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 383         .freq_tbl = ftbl_usb20_master_clk_src,
 384         .clkr.hw.init = &(struct clk_init_data){
 385                 .name = "usb20_master_clk_src",
 386                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 387                 .num_parents = 3,
 388                 .ops = &clk_rcg2_ops,
 389         },
 390 };
 391
 392 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 393         .cmd_rcgr = 0x12024,
 394         .hid_width = 5,
 395         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 396         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 397         .clkr.hw.init = &(struct clk_init_data){
 398                 .name = "usb20_mock_utmi_clk_src",
 399                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 400                 .num_parents = 3,
 401                 .ops = &clk_rcg2_ops,
 402         },
 403 };
 404
 405 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 406         F(144000, P_XO, 16, 3, 25),
 407         F(400000, P_XO, 12, 1, 4),
 408         F(20000000, P_GPLL0, 15, 1, 2),
 409         F(25000000, P_GPLL0, 12, 1, 2),
 410         F(50000000, P_GPLL0, 12, 0, 0),
 411         F(96000000, P_GPLL4, 4, 0, 0),
 412         F(192000000, P_GPLL4, 2, 0, 0),
 413         F(384000000, P_GPLL4, 1, 0, 0),
 414         { }
 415 };
 416
 417 static struct clk_rcg2 sdcc1_apps_clk_src = {
 418         .cmd_rcgr = 0x13010,
 419         .mnd_width = 8,
 420         .hid_width = 5,
 421         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 422         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 423         .clkr.hw.init = &(struct clk_init_data){
 424                 .name = "sdcc1_apps_clk_src",
 425                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 426                 .num_parents = 4,
 427                 .ops = &clk_rcg2_ops,
 428         },
 429 };
 430
 431 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 432         .cmd_rcgr = 0x13024,
 433         .hid_width = 5,
 434         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 435         .clkr.hw.init = &(struct clk_init_data){
 436                 .name = "sdcc1_ice_core_clk_src",
 437                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 438                 .num_parents = 4,
 439                 .ops = &clk_rcg2_ops,
 440         },
 441 };
 442
 443 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
 444         F(144000, P_XO, 16, 3, 25),
 445         F(400000, P_XO, 12, 1, 4),
 446         F(20000000, P_GPLL0, 15, 1, 2),
 447         F(25000000, P_GPLL0, 12, 1, 2),
 448         F(50000000, P_GPLL0, 12, 0, 0),
 449         F(100000000, P_GPLL0, 6, 0, 0),
 450         F(200000000, P_GPLL0, 3, 0, 0),
 451         { }
 452 };
 453
 454 static struct clk_rcg2 sdcc2_apps_clk_src = {
 455         .cmd_rcgr = 0x14010,
 456         .mnd_width = 8,
 457         .hid_width = 5,
 458         .parent_map = gcc_xo_gpll0_gpll4_map,
 459         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 460         .clkr.hw.init = &(struct clk_init_data){
 461                 .name = "sdcc2_apps_clk_src",
 462                 .parent_names = gcc_xo_gpll0_gpll4,
 463                 .num_parents = 3,
 464                 .ops = &clk_rcg2_ops,
 465         },
 466 };
 467
 468 static struct clk_rcg2 sdcc3_apps_clk_src = {
 469         .cmd_rcgr = 0x15010,
 470         .mnd_width = 8,
 471         .hid_width = 5,
 472         .parent_map = gcc_xo_gpll0_gpll4_map,
 473         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 474         .clkr.hw.init = &(struct clk_init_data){
 475                 .name = "sdcc3_apps_clk_src",
 476                 .parent_names = gcc_xo_gpll0_gpll4,
 477                 .num_parents = 3,
 478                 .ops = &clk_rcg2_ops,
 479         },
 480 };
 481
 482 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
 483         F(144000, P_XO, 16, 3, 25),
 484         F(400000, P_XO, 12, 1, 4),
 485         F(20000000, P_GPLL0, 15, 1, 2),
 486         F(25000000, P_GPLL0, 12, 1, 2),
 487         F(50000000, P_GPLL0, 12, 0, 0),
 488         F(100000000, P_GPLL0, 6, 0, 0),
 489         { }
 490 };
 491
 492 static struct clk_rcg2 sdcc4_apps_clk_src = {
 493         .cmd_rcgr = 0x16010,
 494         .mnd_width = 8,
 495         .hid_width = 5,
 496         .parent_map = gcc_xo_gpll0_map,
 497         .freq_tbl = ftbl_sdcc4_apps_clk_src,
 498         .clkr.hw.init = &(struct clk_init_data){
 499                 .name = "sdcc4_apps_clk_src",
 500                 .parent_names = gcc_xo_gpll0,
 501                 .num_parents = 2,
 502                 .ops = &clk_rcg2_ops,
 503         },
 504 };
 505
 506 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 507         F(960000, P_XO, 10, 1, 2),
 508         F(4800000, P_XO, 4, 0, 0),
 509         F(9600000, P_XO, 2, 0, 0),
 510         F(15000000, P_GPLL0, 10, 1, 4),
 511         F(19200000, P_XO, 1, 0, 0),
 512         F(25000000, P_GPLL0, 12, 1, 2),
 513         F(50000000, P_GPLL0, 12, 0, 0),
 514         { }
 515 };
 516
 517 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 518         .cmd_rcgr = 0x1900c,
 519         .mnd_width = 8,
 520         .hid_width = 5,
 521         .parent_map = gcc_xo_gpll0_map,
 522         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 523         .clkr.hw.init = &(struct clk_init_data){
 524                 .name = "blsp1_qup1_spi_apps_clk_src",
 525                 .parent_names = gcc_xo_gpll0,
 526                 .num_parents = 2,
 527                 .ops = &clk_rcg2_ops,
 528         },
 529 };
 530
 531 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 532         F(19200000, P_XO, 1, 0, 0),
 533         F(50000000, P_GPLL0, 12, 0, 0),
 534         { }
 535 };
 536
 537 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 538         .cmd_rcgr = 0x19020,
 539         .hid_width = 5,
 540         .parent_map = gcc_xo_gpll0_map,
 541         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 542         .clkr.hw.init = &(struct clk_init_data){
 543                 .name = "blsp1_qup1_i2c_apps_clk_src",
 544                 .parent_names = gcc_xo_gpll0,
 545                 .num_parents = 2,
 546                 .ops = &clk_rcg2_ops,
 547         },
 548 };
 549
 550 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 551         F(3686400, P_GPLL0, 1, 96, 15625),
 552         F(7372800, P_GPLL0, 1, 192, 15625),
 553         F(14745600, P_GPLL0, 1, 384, 15625),
 554         F(16000000, P_GPLL0, 5, 2, 15),
 555         F(19200000, P_XO, 1, 0, 0),
 556         F(24000000, P_GPLL0, 5, 1, 5),
 557         F(32000000, P_GPLL0, 1, 4, 75),
 558         F(40000000, P_GPLL0, 15, 0, 0),
 559         F(46400000, P_GPLL0, 1, 29, 375),
 560         F(48000000, P_GPLL0, 12.5, 0, 0),
 561         F(51200000, P_GPLL0, 1, 32, 375),
 562         F(56000000, P_GPLL0, 1, 7, 75),
 563         F(58982400, P_GPLL0, 1, 1536, 15625),
 564         F(60000000, P_GPLL0, 10, 0, 0),
 565         F(63157895, P_GPLL0, 9.5, 0, 0),
 566         { }
 567 };
 568
 569 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 570         .cmd_rcgr = 0x1a00c,
 571         .mnd_width = 16,
 572         .hid_width = 5,
 573         .parent_map = gcc_xo_gpll0_map,
 574         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 575         .clkr.hw.init = &(struct clk_init_data){
 576                 .name = "blsp1_uart1_apps_clk_src",
 577                 .parent_names = gcc_xo_gpll0,
 578                 .num_parents = 2,
 579                 .ops = &clk_rcg2_ops,
 580         },
 581 };
 582
 583 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 584         .cmd_rcgr = 0x1b00c,
 585         .mnd_width = 8,
 586         .hid_width = 5,
 587         .parent_map = gcc_xo_gpll0_map,
 588         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 589         .clkr.hw.init = &(struct clk_init_data){
 590                 .name = "blsp1_qup2_spi_apps_clk_src",
 591                 .parent_names = gcc_xo_gpll0,
 592                 .num_parents = 2,
 593                 .ops = &clk_rcg2_ops,
 594         },
 595 };
 596
 597 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 598         .cmd_rcgr = 0x1b020,
 599         .hid_width = 5,
 600         .parent_map = gcc_xo_gpll0_map,
 601         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 602         .clkr.hw.init = &(struct clk_init_data){
 603                 .name = "blsp1_qup2_i2c_apps_clk_src",
 604                 .parent_names = gcc_xo_gpll0,
 605                 .num_parents = 2,
 606                 .ops = &clk_rcg2_ops,
 607         },
 608 };
 609
 610 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 611         .cmd_rcgr = 0x1c00c,
 612         .mnd_width = 16,
 613         .hid_width = 5,
 614         .parent_map = gcc_xo_gpll0_map,
 615         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 616         .clkr.hw.init = &(struct clk_init_data){
 617                 .name = "blsp1_uart2_apps_clk_src",
 618                 .parent_names = gcc_xo_gpll0,
 619                 .num_parents = 2,
 620                 .ops = &clk_rcg2_ops,
 621         },
 622 };
 623
 624 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 625         .cmd_rcgr = 0x1d00c,
 626         .mnd_width = 8,
 627         .hid_width = 5,
 628         .parent_map = gcc_xo_gpll0_map,
 629         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 630         .clkr.hw.init = &(struct clk_init_data){
 631                 .name = "blsp1_qup3_spi_apps_clk_src",
 632                 .parent_names = gcc_xo_gpll0,
 633                 .num_parents = 2,
 634                 .ops = &clk_rcg2_ops,
 635         },
 636 };
 637
 638 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 639         .cmd_rcgr = 0x1d020,
 640         .hid_width = 5,
 641         .parent_map = gcc_xo_gpll0_map,
 642         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 643         .clkr.hw.init = &(struct clk_init_data){
 644                 .name = "blsp1_qup3_i2c_apps_clk_src",
 645                 .parent_names = gcc_xo_gpll0,
 646                 .num_parents = 2,
 647                 .ops = &clk_rcg2_ops,
 648         },
 649 };
 650
 651 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 652         .cmd_rcgr = 0x1e00c,
 653         .mnd_width = 16,
 654         .hid_width = 5,
 655         .parent_map = gcc_xo_gpll0_map,
 656         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 657         .clkr.hw.init = &(struct clk_init_data){
 658                 .name = "blsp1_uart3_apps_clk_src",
 659                 .parent_names = gcc_xo_gpll0,
 660                 .num_parents = 2,
 661                 .ops = &clk_rcg2_ops,
 662         },
 663 };
 664
 665 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 666         .cmd_rcgr = 0x1f00c,
 667         .mnd_width = 8,
 668         .hid_width = 5,
 669         .parent_map = gcc_xo_gpll0_map,
 670         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 671         .clkr.hw.init = &(struct clk_init_data){
 672                 .name = "blsp1_qup4_spi_apps_clk_src",
 673                 .parent_names = gcc_xo_gpll0,
 674                 .num_parents = 2,
 675                 .ops = &clk_rcg2_ops,
 676         },
 677 };
 678
 679 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 680         .cmd_rcgr = 0x1f020,
 681         .hid_width = 5,
 682         .parent_map = gcc_xo_gpll0_map,
 683         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 684         .clkr.hw.init = &(struct clk_init_data){
 685                 .name = "blsp1_qup4_i2c_apps_clk_src",
 686                 .parent_names = gcc_xo_gpll0,
 687                 .num_parents = 2,
 688                 .ops = &clk_rcg2_ops,
 689         },
 690 };
 691
 692 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 693         .cmd_rcgr = 0x2000c,
 694         .mnd_width = 16,
 695         .hid_width = 5,
 696         .parent_map = gcc_xo_gpll0_map,
 697         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 698         .clkr.hw.init = &(struct clk_init_data){
 699                 .name = "blsp1_uart4_apps_clk_src",
 700                 .parent_names = gcc_xo_gpll0,
 701                 .num_parents = 2,
 702                 .ops = &clk_rcg2_ops,
 703         },
 704 };
 705
 706 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 707         .cmd_rcgr = 0x2100c,
 708         .mnd_width = 8,
 709         .hid_width = 5,
 710         .parent_map = gcc_xo_gpll0_map,
 711         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 712         .clkr.hw.init = &(struct clk_init_data){
 713                 .name = "blsp1_qup5_spi_apps_clk_src",
 714                 .parent_names = gcc_xo_gpll0,
 715                 .num_parents = 2,
 716                 .ops = &clk_rcg2_ops,
 717         },
 718 };
 719
 720 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 721         .cmd_rcgr = 0x21020,
 722         .hid_width = 5,
 723         .parent_map = gcc_xo_gpll0_map,
 724         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 725         .clkr.hw.init = &(struct clk_init_data){
 726                 .name = "blsp1_qup5_i2c_apps_clk_src",
 727                 .parent_names = gcc_xo_gpll0,
 728                 .num_parents = 2,
 729                 .ops = &clk_rcg2_ops,
 730         },
 731 };
 732
 733 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 734         .cmd_rcgr = 0x2200c,
 735         .mnd_width = 16,
 736         .hid_width = 5,
 737         .parent_map = gcc_xo_gpll0_map,
 738         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 739         .clkr.hw.init = &(struct clk_init_data){
 740                 .name = "blsp1_uart5_apps_clk_src",
 741                 .parent_names = gcc_xo_gpll0,
 742                 .num_parents = 2,
 743                 .ops = &clk_rcg2_ops,
 744         },
 745 };
 746
 747 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 748         .cmd_rcgr = 0x2300c,
 749         .mnd_width = 8,
 750         .hid_width = 5,
 751         .parent_map = gcc_xo_gpll0_map,
 752         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 753         .clkr.hw.init = &(struct clk_init_data){
 754                 .name = "blsp1_qup6_spi_apps_clk_src",
 755                 .parent_names = gcc_xo_gpll0,
 756                 .num_parents = 2,
 757                 .ops = &clk_rcg2_ops,
 758         },
 759 };
 760
 761 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 762         .cmd_rcgr = 0x23020,
 763         .hid_width = 5,
 764         .parent_map = gcc_xo_gpll0_map,
 765         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 766         .clkr.hw.init = &(struct clk_init_data){
 767                 .name = "blsp1_qup6_i2c_apps_clk_src",
 768                 .parent_names = gcc_xo_gpll0,
 769                 .num_parents = 2,
 770                 .ops = &clk_rcg2_ops,
 771         },
 772 };
 773
 774 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 775         .cmd_rcgr = 0x2400c,
 776         .mnd_width = 16,
 777         .hid_width = 5,
 778         .parent_map = gcc_xo_gpll0_map,
 779         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 780         .clkr.hw.init = &(struct clk_init_data){
 781                 .name = "blsp1_uart6_apps_clk_src",
 782                 .parent_names = gcc_xo_gpll0,
 783                 .num_parents = 2,
 784                 .ops = &clk_rcg2_ops,
 785         },
 786 };
 787
 788 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 789         .cmd_rcgr = 0x2600c,
 790         .mnd_width = 8,
 791         .hid_width = 5,
 792         .parent_map = gcc_xo_gpll0_map,
 793         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 794         .clkr.hw.init = &(struct clk_init_data){
 795                 .name = "blsp2_qup1_spi_apps_clk_src",
 796                 .parent_names = gcc_xo_gpll0,
 797                 .num_parents = 2,
 798                 .ops = &clk_rcg2_ops,
 799         },
 800 };
 801
 802 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 803         .cmd_rcgr = 0x26020,
 804         .hid_width = 5,
 805         .parent_map = gcc_xo_gpll0_map,
 806         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 807         .clkr.hw.init = &(struct clk_init_data){
 808                 .name = "blsp2_qup1_i2c_apps_clk_src",
 809                 .parent_names = gcc_xo_gpll0,
 810                 .num_parents = 2,
 811                 .ops = &clk_rcg2_ops,
 812         },
 813 };
 814
 815 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 816         .cmd_rcgr = 0x2700c,
 817         .mnd_width = 16,
 818         .hid_width = 5,
 819         .parent_map = gcc_xo_gpll0_map,
 820         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 821         .clkr.hw.init = &(struct clk_init_data){
 822                 .name = "blsp2_uart1_apps_clk_src",
 823                 .parent_names = gcc_xo_gpll0,
 824                 .num_parents = 2,
 825                 .ops = &clk_rcg2_ops,
 826         },
 827 };
 828
 829 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 830         .cmd_rcgr = 0x2800c,
 831         .mnd_width = 8,
 832         .hid_width = 5,
 833         .parent_map = gcc_xo_gpll0_map,
 834         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 835         .clkr.hw.init = &(struct clk_init_data){
 836                 .name = "blsp2_qup2_spi_apps_clk_src",
 837                 .parent_names = gcc_xo_gpll0,
 838                 .num_parents = 2,
 839                 .ops = &clk_rcg2_ops,
 840         },
 841 };
 842
 843 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 844         .cmd_rcgr = 0x28020,
 845         .hid_width = 5,
 846         .parent_map = gcc_xo_gpll0_map,
 847         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 848         .clkr.hw.init = &(struct clk_init_data){
 849                 .name = "blsp2_qup2_i2c_apps_clk_src",
 850                 .parent_names = gcc_xo_gpll0,
 851                 .num_parents = 2,
 852                 .ops = &clk_rcg2_ops,
 853         },
 854 };
 855
 856 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 857         .cmd_rcgr = 0x2900c,
 858         .mnd_width = 16,
 859         .hid_width = 5,
 860         .parent_map = gcc_xo_gpll0_map,
 861         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 862         .clkr.hw.init = &(struct clk_init_data){
 863                 .name = "blsp2_uart2_apps_clk_src",
 864                 .parent_names = gcc_xo_gpll0,
 865                 .num_parents = 2,
 866                 .ops = &clk_rcg2_ops,
 867         },
 868 };
 869
 870 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 871         .cmd_rcgr = 0x2a00c,
 872         .mnd_width = 8,
 873         .hid_width = 5,
 874         .parent_map = gcc_xo_gpll0_map,
 875         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 876         .clkr.hw.init = &(struct clk_init_data){
 877                 .name = "blsp2_qup3_spi_apps_clk_src",
 878                 .parent_names = gcc_xo_gpll0,
 879                 .num_parents = 2,
 880                 .ops = &clk_rcg2_ops,
 881         },
 882 };
 883
 884 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 885         .cmd_rcgr = 0x2a020,
 886         .hid_width = 5,
 887         .parent_map = gcc_xo_gpll0_map,
 888         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 889         .clkr.hw.init = &(struct clk_init_data){
 890                 .name = "blsp2_qup3_i2c_apps_clk_src",
 891                 .parent_names = gcc_xo_gpll0,
 892                 .num_parents = 2,
 893                 .ops = &clk_rcg2_ops,
 894         },
 895 };
 896
 897 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 898         .cmd_rcgr = 0x2b00c,
 899         .mnd_width = 16,
 900         .hid_width = 5,
 901         .parent_map = gcc_xo_gpll0_map,
 902         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 903         .clkr.hw.init = &(struct clk_init_data){
 904                 .name = "blsp2_uart3_apps_clk_src",
 905                 .parent_names = gcc_xo_gpll0,
 906                 .num_parents = 2,
 907                 .ops = &clk_rcg2_ops,
 908         },
 909 };
 910
 911 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 912         .cmd_rcgr = 0x2c00c,
 913         .mnd_width = 8,
 914         .hid_width = 5,
 915         .parent_map = gcc_xo_gpll0_map,
 916         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 917         .clkr.hw.init = &(struct clk_init_data){
 918                 .name = "blsp2_qup4_spi_apps_clk_src",
 919                 .parent_names = gcc_xo_gpll0,
 920                 .num_parents = 2,
 921                 .ops = &clk_rcg2_ops,
 922         },
 923 };
 924
 925 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 926         .cmd_rcgr = 0x2c020,
 927         .hid_width = 5,
 928         .parent_map = gcc_xo_gpll0_map,
 929         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 930         .clkr.hw.init = &(struct clk_init_data){
 931                 .name = "blsp2_qup4_i2c_apps_clk_src",
 932                 .parent_names = gcc_xo_gpll0,
 933                 .num_parents = 2,
 934                 .ops = &clk_rcg2_ops,
 935         },
 936 };
 937
 938 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 939         .cmd_rcgr = 0x2d00c,
 940         .mnd_width = 16,
 941         .hid_width = 5,
 942         .parent_map = gcc_xo_gpll0_map,
 943         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 944         .clkr.hw.init = &(struct clk_init_data){
 945                 .name = "blsp2_uart4_apps_clk_src",
 946                 .parent_names = gcc_xo_gpll0,
 947                 .num_parents = 2,
 948                 .ops = &clk_rcg2_ops,
 949         },
 950 };
 951
 952 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 953         .cmd_rcgr = 0x2e00c,
 954         .mnd_width = 8,
 955         .hid_width = 5,
 956         .parent_map = gcc_xo_gpll0_map,
 957         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 958         .clkr.hw.init = &(struct clk_init_data){
 959                 .name = "blsp2_qup5_spi_apps_clk_src",
 960                 .parent_names = gcc_xo_gpll0,
 961                 .num_parents = 2,
 962                 .ops = &clk_rcg2_ops,
 963         },
 964 };
 965
 966 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 967         .cmd_rcgr = 0x2e020,
 968         .hid_width = 5,
 969         .parent_map = gcc_xo_gpll0_map,
 970         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 971         .clkr.hw.init = &(struct clk_init_data){
 972                 .name = "blsp2_qup5_i2c_apps_clk_src",
 973                 .parent_names = gcc_xo_gpll0,
 974                 .num_parents = 2,
 975                 .ops = &clk_rcg2_ops,
 976         },
 977 };
 978
 979 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 980         .cmd_rcgr = 0x2f00c,
 981         .mnd_width = 16,
 982         .hid_width = 5,
 983         .parent_map = gcc_xo_gpll0_map,
 984         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 985         .clkr.hw.init = &(struct clk_init_data){
 986                 .name = "blsp2_uart5_apps_clk_src",
 987                 .parent_names = gcc_xo_gpll0,
 988                 .num_parents = 2,
 989                 .ops = &clk_rcg2_ops,
 990         },
 991 };
 992
 993 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 994         .cmd_rcgr = 0x3000c,
 995         .mnd_width = 8,
 996         .hid_width = 5,
 997         .parent_map = gcc_xo_gpll0_map,
 998         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 999         .clkr.hw.init = &(struct clk_init_data){
1000                 .name = "blsp2_qup6_spi_apps_clk_src",
1001                 .parent_names = gcc_xo_gpll0,
1002                 .num_parents = 2,
1003                 .ops = &clk_rcg2_ops,
1004         },
1005 };
1006
1007 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1008         .cmd_rcgr = 0x30020,
1009         .hid_width = 5,
1010         .parent_map = gcc_xo_gpll0_map,
1011         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1012         .clkr.hw.init = &(struct clk_init_data){
1013                 .name = "blsp2_qup6_i2c_apps_clk_src",
1014                 .parent_names = gcc_xo_gpll0,
1015                 .num_parents = 2,
1016                 .ops = &clk_rcg2_ops,
1017         },
1018 };
1019
1020 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1021         .cmd_rcgr = 0x3100c,
1022         .mnd_width = 16,
1023         .hid_width = 5,
1024         .parent_map = gcc_xo_gpll0_map,
1025         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1026         .clkr.hw.init = &(struct clk_init_data){
1027                 .name = "blsp2_uart6_apps_clk_src",
1028                 .parent_names = gcc_xo_gpll0,
1029                 .num_parents = 2,
1030                 .ops = &clk_rcg2_ops,
1031         },
1032 };
1033
1034 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1035         F(60000000, P_GPLL0, 10, 0, 0),
1036         { }
1037 };
1038
1039 static struct clk_rcg2 pdm2_clk_src = {
1040         .cmd_rcgr = 0x33010,
1041         .hid_width = 5,
1042         .parent_map = gcc_xo_gpll0_map,
1043         .freq_tbl = ftbl_pdm2_clk_src,
1044         .clkr.hw.init = &(struct clk_init_data){
1045                 .name = "pdm2_clk_src",
1046                 .parent_names = gcc_xo_gpll0,
1047                 .num_parents = 2,
1048                 .ops = &clk_rcg2_ops,
1049         },
1050 };
1051
1052 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1053         F(105495, P_XO, 1, 1, 182),
1054         { }
1055 };
1056
1057 static struct clk_rcg2 tsif_ref_clk_src = {
1058         .cmd_rcgr = 0x36010,
1059         .mnd_width = 8,
1060         .hid_width = 5,
1061         .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1062         .freq_tbl = ftbl_tsif_ref_clk_src,
1063         .clkr.hw.init = &(struct clk_init_data){
1064                 .name = "tsif_ref_clk_src",
1065                 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1066                 .num_parents = 3,
1067                 .ops = &clk_rcg2_ops,
1068         },
1069 };
1070
1071 static struct clk_rcg2 gcc_sleep_clk_src = {
1072         .cmd_rcgr = 0x43014,
1073         .hid_width = 5,
1074         .parent_map = gcc_sleep_clk_map,
1075         .clkr.hw.init = &(struct clk_init_data){
1076                 .name = "gcc_sleep_clk_src",
1077                 .parent_names = gcc_sleep_clk,
1078                 .num_parents = 1,
1079                 .ops = &clk_rcg2_ops,
1080         },
1081 };
1082
1083 static struct clk_rcg2 hmss_rbcpr_clk_src = {
1084         .cmd_rcgr = 0x48040,
1085         .hid_width = 5,
1086         .parent_map = gcc_xo_gpll0_map,
1087         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1088         .clkr.hw.init = &(struct clk_init_data){
1089                 .name = "hmss_rbcpr_clk_src",
1090                 .parent_names = gcc_xo_gpll0,
1091                 .num_parents = 2,
1092                 .ops = &clk_rcg2_ops,
1093         },
1094 };
1095
1096 static struct clk_rcg2 hmss_gpll0_clk_src = {
1097         .cmd_rcgr = 0x48058,
1098         .hid_width = 5,
1099         .parent_map = gcc_xo_gpll0_map,
1100         .clkr.hw.init = &(struct clk_init_data){
1101                 .name = "hmss_gpll0_clk_src",
1102                 .parent_names = gcc_xo_gpll0,
1103                 .num_parents = 2,
1104                 .ops = &clk_rcg2_ops,
1105         },
1106 };
1107
1108 static const struct freq_tbl ftbl_gp1_clk_src[] = {
1109         F(19200000, P_XO, 1, 0, 0),
1110         F(100000000, P_GPLL0, 6, 0, 0),
1111         F(200000000, P_GPLL0, 3, 0, 0),
1112         { }
1113 };
1114
1115 static struct clk_rcg2 gp1_clk_src = {
1116         .cmd_rcgr = 0x64004,
1117         .mnd_width = 8,
1118         .hid_width = 5,
1119         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1120         .freq_tbl = ftbl_gp1_clk_src,
1121         .clkr.hw.init = &(struct clk_init_data){
1122                 .name = "gp1_clk_src",
1123                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1124                 .num_parents = 4,
1125                 .ops = &clk_rcg2_ops,
1126         },
1127 };
1128
1129 static struct clk_rcg2 gp2_clk_src = {
1130         .cmd_rcgr = 0x65004,
1131         .mnd_width = 8,
1132         .hid_width = 5,
1133         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1134         .freq_tbl = ftbl_gp1_clk_src,
1135         .clkr.hw.init = &(struct clk_init_data){
1136                 .name = "gp2_clk_src",
1137                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1138                 .num_parents = 4,
1139                 .ops = &clk_rcg2_ops,
1140         },
1141 };
1142
1143 static struct clk_rcg2 gp3_clk_src = {
1144         .cmd_rcgr = 0x66004,
1145         .mnd_width = 8,
1146         .hid_width = 5,
1147         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1148         .freq_tbl = ftbl_gp1_clk_src,
1149         .clkr.hw.init = &(struct clk_init_data){
1150                 .name = "gp3_clk_src",
1151                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1152                 .num_parents = 4,
1153                 .ops = &clk_rcg2_ops,
1154         },
1155 };
1156
1157 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1158         F(1010526, P_XO, 1, 1, 19),
1159         { }
1160 };
1161
1162 static struct clk_rcg2 pcie_aux_clk_src = {
1163         .cmd_rcgr = 0x6c000,
1164         .mnd_width = 16,
1165         .hid_width = 5,
1166         .parent_map = gcc_xo_sleep_clk_map,
1167         .freq_tbl = ftbl_pcie_aux_clk_src,
1168         .clkr.hw.init = &(struct clk_init_data){
1169                 .name = "pcie_aux_clk_src",
1170                 .parent_names = gcc_xo_sleep_clk,
1171                 .num_parents = 2,
1172                 .ops = &clk_rcg2_ops,
1173         },
1174 };
1175
1176 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1177         F(100000000, P_GPLL0, 6, 0, 0),
1178         F(200000000, P_GPLL0, 3, 0, 0),
1179         F(240000000, P_GPLL0, 2.5, 0, 0),
1180         { }
1181 };
1182
1183 static struct clk_rcg2 ufs_axi_clk_src = {
1184         .cmd_rcgr = 0x75024,
1185         .mnd_width = 8,
1186         .hid_width = 5,
1187         .parent_map = gcc_xo_gpll0_map,
1188         .freq_tbl = ftbl_ufs_axi_clk_src,
1189         .clkr.hw.init = &(struct clk_init_data){
1190                 .name = "ufs_axi_clk_src",
1191                 .parent_names = gcc_xo_gpll0,
1192                 .num_parents = 2,
1193                 .ops = &clk_rcg2_ops,
1194         },
1195 };
1196
1197 static struct clk_rcg2 ufs_ice_core_clk_src = {
1198         .cmd_rcgr = 0x76014,
1199         .hid_width = 5,
1200         .parent_map = gcc_xo_gpll0_map,
1201         .clkr.hw.init = &(struct clk_init_data){
1202                 .name = "ufs_ice_core_clk_src",
1203                 .parent_names = gcc_xo_gpll0,
1204                 .num_parents = 2,
1205                 .ops = &clk_rcg2_ops,
1206         },
1207 };
1208
1209 static struct clk_rcg2 qspi_ser_clk_src = {
1210         .cmd_rcgr = 0x8b00c,
1211         .hid_width = 5,
1212         .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1213         .clkr.hw.init = &(struct clk_init_data){
1214                 .name = "qspi_ser_clk_src",
1215                 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1216                 .num_parents = 6,
1217                 .ops = &clk_rcg2_ops,
1218         },
1219 };
1220
1221 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1222         .halt_reg = 0x0f03c,
1223         .clkr = {
1224                 .enable_reg = 0x0f03c,
1225                 .enable_mask = BIT(0),
1226                 .hw.init = &(struct clk_init_data){
1227                         .name = "gcc_sys_noc_usb3_axi_clk",
1228                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1229                         .num_parents = 1,
1230                         .flags = CLK_SET_RATE_PARENT,
1231                         .ops = &clk_branch2_ops,
1232                 },
1233         },
1234 };
1235
1236 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1237         .halt_reg = 0x75038,
1238         .clkr = {
1239                 .enable_reg = 0x75038,
1240                 .enable_mask = BIT(0),
1241                 .hw.init = &(struct clk_init_data){
1242                         .name = "gcc_sys_noc_ufs_axi_clk",
1243                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1244                         .num_parents = 1,
1245                         .flags = CLK_SET_RATE_PARENT,
1246                         .ops = &clk_branch2_ops,
1247                 },
1248         },
1249 };
1250
1251 static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1252         .halt_reg = 0x6010,
1253         .clkr = {
1254                 .enable_reg = 0x6010,
1255                 .enable_mask = BIT(0),
1256                 .hw.init = &(struct clk_init_data){
1257                         .name = "gcc_periph_noc_usb20_ahb_clk",
1258                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1259                         .num_parents = 1,
1260                         .flags = CLK_SET_RATE_PARENT,
1261                         .ops = &clk_branch2_ops,
1262                 },
1263         },
1264 };
1265
1266 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1267         .halt_reg = 0x9008,
1268         .clkr = {
1269                 .enable_reg = 0x9008,
1270                 .enable_mask = BIT(0),
1271                 .hw.init = &(struct clk_init_data){
1272                         .name = "gcc_mmss_noc_cfg_ahb_clk",
1273                         .parent_names = (const char *[]){ "config_noc_clk_src" },
1274                         .num_parents = 1,
1275                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1276                         .ops = &clk_branch2_ops,
1277                 },
1278         },
1279 };
1280
1281 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1282         .halt_reg = 0x9010,
1283         .clkr = {
1284                 .enable_reg = 0x9010,
1285                 .enable_mask = BIT(0),
1286                 .hw.init = &(struct clk_init_data){
1287                         .name = "gcc_mmss_bimc_gfx_clk",
1288                         .flags = CLK_SET_RATE_PARENT,
1289                         .ops = &clk_branch2_ops,
1290                 },
1291         },
1292 };
1293
1294 static struct clk_branch gcc_usb30_master_clk = {
1295         .halt_reg = 0x0f008,
1296         .clkr = {
1297                 .enable_reg = 0x0f008,
1298                 .enable_mask = BIT(0),
1299                 .hw.init = &(struct clk_init_data){
1300                         .name = "gcc_usb30_master_clk",
1301                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1302                         .num_parents = 1,
1303                         .flags = CLK_SET_RATE_PARENT,
1304                         .ops = &clk_branch2_ops,
1305                 },
1306         },
1307 };
1308
1309 static struct clk_branch gcc_usb30_sleep_clk = {
1310         .halt_reg = 0x0f00c,
1311         .clkr = {
1312                 .enable_reg = 0x0f00c,
1313                 .enable_mask = BIT(0),
1314                 .hw.init = &(struct clk_init_data){
1315                         .name = "gcc_usb30_sleep_clk",
1316                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1317                         .num_parents = 1,
1318                         .flags = CLK_SET_RATE_PARENT,
1319                         .ops = &clk_branch2_ops,
1320                 },
1321         },
1322 };
1323
1324 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1325         .halt_reg = 0x0f010,
1326         .clkr = {
1327                 .enable_reg = 0x0f010,
1328                 .enable_mask = BIT(0),
1329                 .hw.init = &(struct clk_init_data){
1330                         .name = "gcc_usb30_mock_utmi_clk",
1331                         .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1332                         .num_parents = 1,
1333                         .flags = CLK_SET_RATE_PARENT,
1334                         .ops = &clk_branch2_ops,
1335                 },
1336         },
1337 };
1338
1339 static struct clk_branch gcc_usb3_phy_aux_clk = {
1340         .halt_reg = 0x50000,
1341         .clkr = {
1342                 .enable_reg = 0x50000,
1343                 .enable_mask = BIT(0),
1344                 .hw.init = &(struct clk_init_data){
1345                         .name = "gcc_usb3_phy_aux_clk",
1346                         .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1347                         .num_parents = 1,
1348                         .flags = CLK_SET_RATE_PARENT,
1349                         .ops = &clk_branch2_ops,
1350                 },
1351         },
1352 };
1353
1354 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1355         .halt_reg = 0x50004,
1356         .clkr = {
1357                 .enable_reg = 0x50004,
1358                 .enable_mask = BIT(0),
1359                 .hw.init = &(struct clk_init_data){
1360                         .name = "gcc_usb3_phy_pipe_clk",
1361                         .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1362                         .num_parents = 1,
1363                         .flags = CLK_SET_RATE_PARENT,
1364                         .ops = &clk_branch2_ops,
1365                 },
1366         },
1367 };
1368
1369 static struct clk_branch gcc_usb20_master_clk = {
1370         .halt_reg = 0x12004,
1371         .clkr = {
1372                 .enable_reg = 0x12004,
1373                 .enable_mask = BIT(0),
1374                 .hw.init = &(struct clk_init_data){
1375                         .name = "gcc_usb20_master_clk",
1376                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1377                         .num_parents = 1,
1378                         .flags = CLK_SET_RATE_PARENT,
1379                         .ops = &clk_branch2_ops,
1380                 },
1381         },
1382 };
1383
1384 static struct clk_branch gcc_usb20_sleep_clk = {
1385         .halt_reg = 0x12008,
1386         .clkr = {
1387                 .enable_reg = 0x12008,
1388                 .enable_mask = BIT(0),
1389                 .hw.init = &(struct clk_init_data){
1390                         .name = "gcc_usb20_sleep_clk",
1391                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1392                         .num_parents = 1,
1393                         .flags = CLK_SET_RATE_PARENT,
1394                         .ops = &clk_branch2_ops,
1395                 },
1396         },
1397 };
1398
1399 static struct clk_branch gcc_usb20_mock_utmi_clk = {
1400         .halt_reg = 0x1200c,
1401         .clkr = {
1402                 .enable_reg = 0x1200c,
1403                 .enable_mask = BIT(0),
1404                 .hw.init = &(struct clk_init_data){
1405                         .name = "gcc_usb20_mock_utmi_clk",
1406                         .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1407                         .num_parents = 1,
1408                         .flags = CLK_SET_RATE_PARENT,
1409                         .ops = &clk_branch2_ops,
1410                 },
1411         },
1412 };
1413
1414 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1415         .halt_reg = 0x6a004,
1416         .clkr = {
1417                 .enable_reg = 0x6a004,
1418                 .enable_mask = BIT(0),
1419                 .hw.init = &(struct clk_init_data){
1420                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1421                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1422                         .num_parents = 1,
1423                         .flags = CLK_SET_RATE_PARENT,
1424                         .ops = &clk_branch2_ops,
1425                 },
1426         },
1427 };
1428
1429 static struct clk_branch gcc_sdcc1_apps_clk = {
1430         .halt_reg = 0x13004,
1431         .clkr = {
1432                 .enable_reg = 0x13004,
1433                 .enable_mask = BIT(0),
1434                 .hw.init = &(struct clk_init_data){
1435                         .name = "gcc_sdcc1_apps_clk",
1436                         .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1437                         .num_parents = 1,
1438                         .flags = CLK_SET_RATE_PARENT,
1439                         .ops = &clk_branch2_ops,
1440                 },
1441         },
1442 };
1443
1444 static struct clk_branch gcc_sdcc1_ahb_clk = {
1445         .halt_reg = 0x13008,
1446         .clkr = {
1447                 .enable_reg = 0x13008,
1448                 .enable_mask = BIT(0),
1449                 .hw.init = &(struct clk_init_data){
1450                         .name = "gcc_sdcc1_ahb_clk",
1451                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1452                         .num_parents = 1,
1453                         .flags = CLK_SET_RATE_PARENT,
1454                         .ops = &clk_branch2_ops,
1455                 },
1456         },
1457 };
1458
1459 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1460         .halt_reg = 0x13038,
1461         .clkr = {
1462                 .enable_reg = 0x13038,
1463                 .enable_mask = BIT(0),
1464                 .hw.init = &(struct clk_init_data){
1465                         .name = "gcc_sdcc1_ice_core_clk",
1466                         .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1467                         .num_parents = 1,
1468                         .flags = CLK_SET_RATE_PARENT,
1469                         .ops = &clk_branch2_ops,
1470                 },
1471         },
1472 };
1473
1474 static struct clk_branch gcc_sdcc2_apps_clk = {
1475         .halt_reg = 0x14004,
1476         .clkr = {
1477                 .enable_reg = 0x14004,
1478                 .enable_mask = BIT(0),
1479                 .hw.init = &(struct clk_init_data){
1480                         .name = "gcc_sdcc2_apps_clk",
1481                         .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1482                         .num_parents = 1,
1483                         .flags = CLK_SET_RATE_PARENT,
1484                         .ops = &clk_branch2_ops,
1485                 },
1486         },
1487 };
1488
1489 static struct clk_branch gcc_sdcc2_ahb_clk = {
1490         .halt_reg = 0x14008,
1491         .clkr = {
1492                 .enable_reg = 0x14008,
1493                 .enable_mask = BIT(0),
1494                 .hw.init = &(struct clk_init_data){
1495                         .name = "gcc_sdcc2_ahb_clk",
1496                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1497                         .num_parents = 1,
1498                         .flags = CLK_SET_RATE_PARENT,
1499                         .ops = &clk_branch2_ops,
1500                 },
1501         },
1502 };
1503
1504 static struct clk_branch gcc_sdcc3_apps_clk = {
1505         .halt_reg = 0x15004,
1506         .clkr = {
1507                 .enable_reg = 0x15004,
1508                 .enable_mask = BIT(0),
1509                 .hw.init = &(struct clk_init_data){
1510                         .name = "gcc_sdcc3_apps_clk",
1511                         .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1512                         .num_parents = 1,
1513                         .flags = CLK_SET_RATE_PARENT,
1514                         .ops = &clk_branch2_ops,
1515                 },
1516         },
1517 };
1518
1519 static struct clk_branch gcc_sdcc3_ahb_clk = {
1520         .halt_reg = 0x15008,
1521         .clkr = {
1522                 .enable_reg = 0x15008,
1523                 .enable_mask = BIT(0),
1524                 .hw.init = &(struct clk_init_data){
1525                         .name = "gcc_sdcc3_ahb_clk",
1526                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1527                         .num_parents = 1,
1528                         .flags = CLK_SET_RATE_PARENT,
1529                         .ops = &clk_branch2_ops,
1530                 },
1531         },
1532 };
1533
1534 static struct clk_branch gcc_sdcc4_apps_clk = {
1535         .halt_reg = 0x16004,
1536         .clkr = {
1537                 .enable_reg = 0x16004,
1538                 .enable_mask = BIT(0),
1539                 .hw.init = &(struct clk_init_data){
1540                         .name = "gcc_sdcc4_apps_clk",
1541                         .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1542                         .num_parents = 1,
1543                         .flags = CLK_SET_RATE_PARENT,
1544                         .ops = &clk_branch2_ops,
1545                 },
1546         },
1547 };
1548
1549 static struct clk_branch gcc_sdcc4_ahb_clk = {
1550         .halt_reg = 0x16008,
1551         .clkr = {
1552                 .enable_reg = 0x16008,
1553                 .enable_mask = BIT(0),
1554                 .hw.init = &(struct clk_init_data){
1555                         .name = "gcc_sdcc4_ahb_clk",
1556                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1557                         .num_parents = 1,
1558                         .flags = CLK_SET_RATE_PARENT,
1559                         .ops = &clk_branch2_ops,
1560                 },
1561         },
1562 };
1563
1564 static struct clk_branch gcc_blsp1_ahb_clk = {
1565         .halt_reg = 0x17004,
1566         .halt_check = BRANCH_HALT_VOTED,
1567         .clkr = {
1568                 .enable_reg = 0x52004,
1569                 .enable_mask = BIT(17),
1570                 .hw.init = &(struct clk_init_data){
1571                         .name = "gcc_blsp1_ahb_clk",
1572                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1573                         .num_parents = 1,
1574                         .flags = CLK_SET_RATE_PARENT,
1575                         .ops = &clk_branch2_ops,
1576                 },
1577         },
1578 };
1579
1580 static struct clk_branch gcc_blsp1_sleep_clk = {
1581         .halt_reg = 0x17008,
1582         .halt_check = BRANCH_HALT_VOTED,
1583         .clkr = {
1584                 .enable_reg = 0x52004,
1585                 .enable_mask = BIT(16),
1586                 .hw.init = &(struct clk_init_data){
1587                         .name = "gcc_blsp1_sleep_clk",
1588                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1589                         .num_parents = 1,
1590                         .flags = CLK_SET_RATE_PARENT,
1591                         .ops = &clk_branch2_ops,
1592                 },
1593         },
1594 };
1595
1596 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1597         .halt_reg = 0x19004,
1598         .clkr = {
1599                 .enable_reg = 0x19004,
1600                 .enable_mask = BIT(0),
1601                 .hw.init = &(struct clk_init_data){
1602                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1603                         .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1604                         .num_parents = 1,
1605                         .flags = CLK_SET_RATE_PARENT,
1606                         .ops = &clk_branch2_ops,
1607                 },
1608         },
1609 };
1610
1611 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1612         .halt_reg = 0x19008,
1613         .clkr = {
1614                 .enable_reg = 0x19008,
1615                 .enable_mask = BIT(0),
1616                 .hw.init = &(struct clk_init_data){
1617                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1618                         .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1619                         .num_parents = 1,
1620                         .flags = CLK_SET_RATE_PARENT,
1621                         .ops = &clk_branch2_ops,
1622                 },
1623         },
1624 };
1625
1626 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1627         .halt_reg = 0x1a004,
1628         .clkr = {
1629                 .enable_reg = 0x1a004,
1630                 .enable_mask = BIT(0),
1631                 .hw.init = &(struct clk_init_data){
1632                         .name = "gcc_blsp1_uart1_apps_clk",
1633                         .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1634                         .num_parents = 1,
1635                         .flags = CLK_SET_RATE_PARENT,
1636                         .ops = &clk_branch2_ops,
1637                 },
1638         },
1639 };
1640
1641 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1642         .halt_reg = 0x1b004,
1643         .clkr = {
1644                 .enable_reg = 0x1b004,
1645                 .enable_mask = BIT(0),
1646                 .hw.init = &(struct clk_init_data){
1647                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1648                         .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1649                         .num_parents = 1,
1650                         .flags = CLK_SET_RATE_PARENT,
1651                         .ops = &clk_branch2_ops,
1652                 },
1653         },
1654 };
1655
1656 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1657         .halt_reg = 0x1b008,
1658         .clkr = {
1659                 .enable_reg = 0x1b008,
1660                 .enable_mask = BIT(0),
1661                 .hw.init = &(struct clk_init_data){
1662                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1663                         .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1664                         .num_parents = 1,
1665                         .flags = CLK_SET_RATE_PARENT,
1666                         .ops = &clk_branch2_ops,
1667                 },
1668         },
1669 };
1670
1671 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1672         .halt_reg = 0x1c004,
1673         .clkr = {
1674                 .enable_reg = 0x1c004,
1675                 .enable_mask = BIT(0),
1676                 .hw.init = &(struct clk_init_data){
1677                         .name = "gcc_blsp1_uart2_apps_clk",
1678                         .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1679                         .num_parents = 1,
1680                         .flags = CLK_SET_RATE_PARENT,
1681                         .ops = &clk_branch2_ops,
1682                 },
1683         },
1684 };
1685
1686 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1687         .halt_reg = 0x1d004,
1688         .clkr = {
1689                 .enable_reg = 0x1d004,
1690                 .enable_mask = BIT(0),
1691                 .hw.init = &(struct clk_init_data){
1692                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1693                         .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1694                         .num_parents = 1,
1695                         .flags = CLK_SET_RATE_PARENT,
1696                         .ops = &clk_branch2_ops,
1697                 },
1698         },
1699 };
1700
1701 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1702         .halt_reg = 0x1d008,
1703         .clkr = {
1704                 .enable_reg = 0x1d008,
1705                 .enable_mask = BIT(0),
1706                 .hw.init = &(struct clk_init_data){
1707                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1708                         .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1709                         .num_parents = 1,
1710                         .flags = CLK_SET_RATE_PARENT,
1711                         .ops = &clk_branch2_ops,
1712                 },
1713         },
1714 };
1715
1716 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1717         .halt_reg = 0x1e004,
1718         .clkr = {
1719                 .enable_reg = 0x1e004,
1720                 .enable_mask = BIT(0),
1721                 .hw.init = &(struct clk_init_data){
1722                         .name = "gcc_blsp1_uart3_apps_clk",
1723                         .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1724                         .num_parents = 1,
1725                         .flags = CLK_SET_RATE_PARENT,
1726                         .ops = &clk_branch2_ops,
1727                 },
1728         },
1729 };
1730
1731 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1732         .halt_reg = 0x1f004,
1733         .clkr = {
1734                 .enable_reg = 0x1f004,
1735                 .enable_mask = BIT(0),
1736                 .hw.init = &(struct clk_init_data){
1737                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1738                         .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1739                         .num_parents = 1,
1740                         .flags = CLK_SET_RATE_PARENT,
1741                         .ops = &clk_branch2_ops,
1742                 },
1743         },
1744 };
1745
1746 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1747         .halt_reg = 0x1f008,
1748         .clkr = {
1749                 .enable_reg = 0x1f008,
1750                 .enable_mask = BIT(0),
1751                 .hw.init = &(struct clk_init_data){
1752                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1753                         .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1754                         .num_parents = 1,
1755                         .flags = CLK_SET_RATE_PARENT,
1756                         .ops = &clk_branch2_ops,
1757                 },
1758         },
1759 };
1760
1761 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1762         .halt_reg = 0x20004,
1763         .clkr = {
1764                 .enable_reg = 0x20004,
1765                 .enable_mask = BIT(0),
1766                 .hw.init = &(struct clk_init_data){
1767                         .name = "gcc_blsp1_uart4_apps_clk",
1768                         .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1769                         .num_parents = 1,
1770                         .flags = CLK_SET_RATE_PARENT,
1771                         .ops = &clk_branch2_ops,
1772                 },
1773         },
1774 };
1775
1776 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1777         .halt_reg = 0x21004,
1778         .clkr = {
1779                 .enable_reg = 0x21004,
1780                 .enable_mask = BIT(0),
1781                 .hw.init = &(struct clk_init_data){
1782                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1783                         .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1784                         .num_parents = 1,
1785                         .flags = CLK_SET_RATE_PARENT,
1786                         .ops = &clk_branch2_ops,
1787                 },
1788         },
1789 };
1790
1791 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1792         .halt_reg = 0x21008,
1793         .clkr = {
1794                 .enable_reg = 0x21008,
1795                 .enable_mask = BIT(0),
1796                 .hw.init = &(struct clk_init_data){
1797                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1798                         .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1799                         .num_parents = 1,
1800                         .flags = CLK_SET_RATE_PARENT,
1801                         .ops = &clk_branch2_ops,
1802                 },
1803         },
1804 };
1805
1806 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1807         .halt_reg = 0x22004,
1808         .clkr = {
1809                 .enable_reg = 0x22004,
1810                 .enable_mask = BIT(0),
1811                 .hw.init = &(struct clk_init_data){
1812                         .name = "gcc_blsp1_uart5_apps_clk",
1813                         .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1814                         .num_parents = 1,
1815                         .flags = CLK_SET_RATE_PARENT,
1816                         .ops = &clk_branch2_ops,
1817                 },
1818         },
1819 };
1820
1821 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1822         .halt_reg = 0x23004,
1823         .clkr = {
1824                 .enable_reg = 0x23004,
1825                 .enable_mask = BIT(0),
1826                 .hw.init = &(struct clk_init_data){
1827                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1828                         .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1829                         .num_parents = 1,
1830                         .flags = CLK_SET_RATE_PARENT,
1831                         .ops = &clk_branch2_ops,
1832                 },
1833         },
1834 };
1835
1836 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1837         .halt_reg = 0x23008,
1838         .clkr = {
1839                 .enable_reg = 0x23008,
1840                 .enable_mask = BIT(0),
1841                 .hw.init = &(struct clk_init_data){
1842                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1843                         .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1844                         .num_parents = 1,
1845                         .flags = CLK_SET_RATE_PARENT,
1846                         .ops = &clk_branch2_ops,
1847                 },
1848         },
1849 };
1850
1851 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1852         .halt_reg = 0x24004,
1853         .clkr = {
1854                 .enable_reg = 0x24004,
1855                 .enable_mask = BIT(0),
1856                 .hw.init = &(struct clk_init_data){
1857                         .name = "gcc_blsp1_uart6_apps_clk",
1858                         .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1859                         .num_parents = 1,
1860                         .flags = CLK_SET_RATE_PARENT,
1861                         .ops = &clk_branch2_ops,
1862                 },
1863         },
1864 };
1865
1866 static struct clk_branch gcc_blsp2_ahb_clk = {
1867         .halt_reg = 0x25004,
1868         .halt_check = BRANCH_HALT_VOTED,
1869         .clkr = {
1870                 .enable_reg = 0x52004,
1871                 .enable_mask = BIT(15),
1872                 .hw.init = &(struct clk_init_data){
1873                         .name = "gcc_blsp2_ahb_clk",
1874                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1875                         .num_parents = 1,
1876                         .flags = CLK_SET_RATE_PARENT,
1877                         .ops = &clk_branch2_ops,
1878                 },
1879         },
1880 };
1881
1882 static struct clk_branch gcc_blsp2_sleep_clk = {
1883         .halt_reg = 0x25008,
1884         .halt_check = BRANCH_HALT_VOTED,
1885         .clkr = {
1886                 .enable_reg = 0x52004,
1887                 .enable_mask = BIT(14),
1888                 .hw.init = &(struct clk_init_data){
1889                         .name = "gcc_blsp2_sleep_clk",
1890                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1891                         .num_parents = 1,
1892                         .flags = CLK_SET_RATE_PARENT,
1893                         .ops = &clk_branch2_ops,
1894                 },
1895         },
1896 };
1897
1898 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1899         .halt_reg = 0x26004,
1900         .clkr = {
1901                 .enable_reg = 0x26004,
1902                 .enable_mask = BIT(0),
1903                 .hw.init = &(struct clk_init_data){
1904                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1905                         .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1906                         .num_parents = 1,
1907                         .flags = CLK_SET_RATE_PARENT,
1908                         .ops = &clk_branch2_ops,
1909                 },
1910         },
1911 };
1912
1913 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1914         .halt_reg = 0x26008,
1915         .clkr = {
1916                 .enable_reg = 0x26008,
1917                 .enable_mask = BIT(0),
1918                 .hw.init = &(struct clk_init_data){
1919                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1920                         .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1921                         .num_parents = 1,
1922                         .flags = CLK_SET_RATE_PARENT,
1923                         .ops = &clk_branch2_ops,
1924                 },
1925         },
1926 };
1927
1928 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1929         .halt_reg = 0x27004,
1930         .clkr = {
1931                 .enable_reg = 0x27004,
1932                 .enable_mask = BIT(0),
1933                 .hw.init = &(struct clk_init_data){
1934                         .name = "gcc_blsp2_uart1_apps_clk",
1935                         .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
1936                         .num_parents = 1,
1937                         .flags = CLK_SET_RATE_PARENT,
1938                         .ops = &clk_branch2_ops,
1939                 },
1940         },
1941 };
1942
1943 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1944         .halt_reg = 0x28004,
1945         .clkr = {
1946                 .enable_reg = 0x28004,
1947                 .enable_mask = BIT(0),
1948                 .hw.init = &(struct clk_init_data){
1949                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1950                         .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
1951                         .num_parents = 1,
1952                         .flags = CLK_SET_RATE_PARENT,
1953                         .ops = &clk_branch2_ops,
1954                 },
1955         },
1956 };
1957
1958 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1959         .halt_reg = 0x28008,
1960         .clkr = {
1961                 .enable_reg = 0x28008,
1962                 .enable_mask = BIT(0),
1963                 .hw.init = &(struct clk_init_data){
1964                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1965                         .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
1966                         .num_parents = 1,
1967                         .flags = CLK_SET_RATE_PARENT,
1968                         .ops = &clk_branch2_ops,
1969                 },
1970         },
1971 };
1972
1973 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1974         .halt_reg = 0x29004,
1975         .clkr = {
1976                 .enable_reg = 0x29004,
1977                 .enable_mask = BIT(0),
1978                 .hw.init = &(struct clk_init_data){
1979                         .name = "gcc_blsp2_uart2_apps_clk",
1980                         .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
1981                         .num_parents = 1,
1982                         .flags = CLK_SET_RATE_PARENT,
1983                         .ops = &clk_branch2_ops,
1984                 },
1985         },
1986 };
1987
1988 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1989         .halt_reg = 0x2a004,
1990         .clkr = {
1991                 .enable_reg = 0x2a004,
1992                 .enable_mask = BIT(0),
1993                 .hw.init = &(struct clk_init_data){
1994                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1995                         .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
1996                         .num_parents = 1,
1997                         .flags = CLK_SET_RATE_PARENT,
1998                         .ops = &clk_branch2_ops,
1999                 },
2000         },
2001 };
2002
2003 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2004         .halt_reg = 0x2a008,
2005         .clkr = {
2006                 .enable_reg = 0x2a008,
2007                 .enable_mask = BIT(0),
2008                 .hw.init = &(struct clk_init_data){
2009                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
2010                         .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2011                         .num_parents = 1,
2012                         .flags = CLK_SET_RATE_PARENT,
2013                         .ops = &clk_branch2_ops,
2014                 },
2015         },
2016 };
2017
2018 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2019         .halt_reg = 0x2b004,
2020         .clkr = {
2021                 .enable_reg = 0x2b004,
2022                 .enable_mask = BIT(0),
2023                 .hw.init = &(struct clk_init_data){
2024                         .name = "gcc_blsp2_uart3_apps_clk",
2025                         .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2026                         .num_parents = 1,
2027                         .flags = CLK_SET_RATE_PARENT,
2028                         .ops = &clk_branch2_ops,
2029                 },
2030         },
2031 };
2032
2033 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2034         .halt_reg = 0x2c004,
2035         .clkr = {
2036                 .enable_reg = 0x2c004,
2037                 .enable_mask = BIT(0),
2038                 .hw.init = &(struct clk_init_data){
2039                         .name = "gcc_blsp2_qup4_spi_apps_clk",
2040                         .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2041                         .num_parents = 1,
2042                         .flags = CLK_SET_RATE_PARENT,
2043                         .ops = &clk_branch2_ops,
2044                 },
2045         },
2046 };
2047
2048 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2049         .halt_reg = 0x2c008,
2050         .clkr = {
2051                 .enable_reg = 0x2c008,
2052                 .enable_mask = BIT(0),
2053                 .hw.init = &(struct clk_init_data){
2054                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
2055                         .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2056                         .num_parents = 1,
2057                         .flags = CLK_SET_RATE_PARENT,
2058                         .ops = &clk_branch2_ops,
2059                 },
2060         },
2061 };
2062
2063 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2064         .halt_reg = 0x2d004,
2065         .clkr = {
2066                 .enable_reg = 0x2d004,
2067                 .enable_mask = BIT(0),
2068                 .hw.init = &(struct clk_init_data){
2069                         .name = "gcc_blsp2_uart4_apps_clk",
2070                         .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2071                         .num_parents = 1,
2072                         .flags = CLK_SET_RATE_PARENT,
2073                         .ops = &clk_branch2_ops,
2074                 },
2075         },
2076 };
2077
2078 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2079         .halt_reg = 0x2e004,
2080         .clkr = {
2081                 .enable_reg = 0x2e004,
2082                 .enable_mask = BIT(0),
2083                 .hw.init = &(struct clk_init_data){
2084                         .name = "gcc_blsp2_qup5_spi_apps_clk",
2085                         .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2086                         .num_parents = 1,
2087                         .flags = CLK_SET_RATE_PARENT,
2088                         .ops = &clk_branch2_ops,
2089                 },
2090         },
2091 };
2092
2093 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2094         .halt_reg = 0x2e008,
2095         .clkr = {
2096                 .enable_reg = 0x2e008,
2097                 .enable_mask = BIT(0),
2098                 .hw.init = &(struct clk_init_data){
2099                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
2100                         .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2101                         .num_parents = 1,
2102                         .flags = CLK_SET_RATE_PARENT,
2103                         .ops = &clk_branch2_ops,
2104                 },
2105         },
2106 };
2107
2108 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2109         .halt_reg = 0x2f004,
2110         .clkr = {
2111                 .enable_reg = 0x2f004,
2112                 .enable_mask = BIT(0),
2113                 .hw.init = &(struct clk_init_data){
2114                         .name = "gcc_blsp2_uart5_apps_clk",
2115                         .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2116                         .num_parents = 1,
2117                         .flags = CLK_SET_RATE_PARENT,
2118                         .ops = &clk_branch2_ops,
2119                 },
2120         },
2121 };
2122
2123 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2124         .halt_reg = 0x30004,
2125         .clkr = {
2126                 .enable_reg = 0x30004,
2127                 .enable_mask = BIT(0),
2128                 .hw.init = &(struct clk_init_data){
2129                         .name = "gcc_blsp2_qup6_spi_apps_clk",
2130                         .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2131                         .num_parents = 1,
2132                         .flags = CLK_SET_RATE_PARENT,
2133                         .ops = &clk_branch2_ops,
2134                 },
2135         },
2136 };
2137
2138 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2139         .halt_reg = 0x30008,
2140         .clkr = {
2141                 .enable_reg = 0x30008,
2142                 .enable_mask = BIT(0),
2143                 .hw.init = &(struct clk_init_data){
2144                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
2145                         .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2146                         .num_parents = 1,
2147                         .flags = CLK_SET_RATE_PARENT,
2148                         .ops = &clk_branch2_ops,
2149                 },
2150         },
2151 };
2152
2153 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2154         .halt_reg = 0x31004,
2155         .clkr = {
2156                 .enable_reg = 0x31004,
2157                 .enable_mask = BIT(0),
2158                 .hw.init = &(struct clk_init_data){
2159                         .name = "gcc_blsp2_uart6_apps_clk",
2160                         .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2161                         .num_parents = 1,
2162                         .flags = CLK_SET_RATE_PARENT,
2163                         .ops = &clk_branch2_ops,
2164                 },
2165         },
2166 };
2167
2168 static struct clk_branch gcc_pdm_ahb_clk = {
2169         .halt_reg = 0x33004,
2170         .clkr = {
2171                 .enable_reg = 0x33004,
2172                 .enable_mask = BIT(0),
2173                 .hw.init = &(struct clk_init_data){
2174                         .name = "gcc_pdm_ahb_clk",
2175                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2176                         .num_parents = 1,
2177                         .flags = CLK_SET_RATE_PARENT,
2178                         .ops = &clk_branch2_ops,
2179                 },
2180         },
2181 };
2182
2183 static struct clk_branch gcc_pdm2_clk = {
2184         .halt_reg = 0x3300c,
2185         .clkr = {
2186                 .enable_reg = 0x3300c,
2187                 .enable_mask = BIT(0),
2188                 .hw.init = &(struct clk_init_data){
2189                         .name = "gcc_pdm2_clk",
2190                         .parent_names = (const char *[]){ "pdm2_clk_src" },
2191                         .num_parents = 1,
2192                         .flags = CLK_SET_RATE_PARENT,
2193                         .ops = &clk_branch2_ops,
2194                 },
2195         },
2196 };
2197
2198 static struct clk_branch gcc_prng_ahb_clk = {
2199         .halt_reg = 0x34004,
2200         .halt_check = BRANCH_HALT_VOTED,
2201         .clkr = {
2202                 .enable_reg = 0x52004,
2203                 .enable_mask = BIT(13),
2204                 .hw.init = &(struct clk_init_data){
2205                         .name = "gcc_prng_ahb_clk",
2206                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2207                         .num_parents = 1,
2208                         .flags = CLK_SET_RATE_PARENT,
2209                         .ops = &clk_branch2_ops,
2210                 },
2211         },
2212 };
2213
2214 static struct clk_branch gcc_tsif_ahb_clk = {
2215         .halt_reg = 0x36004,
2216         .clkr = {
2217                 .enable_reg = 0x36004,
2218                 .enable_mask = BIT(0),
2219                 .hw.init = &(struct clk_init_data){
2220                         .name = "gcc_tsif_ahb_clk",
2221                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2222                         .num_parents = 1,
2223                         .flags = CLK_SET_RATE_PARENT,
2224                         .ops = &clk_branch2_ops,
2225                 },
2226         },
2227 };
2228
2229 static struct clk_branch gcc_tsif_ref_clk = {
2230         .halt_reg = 0x36008,
2231         .clkr = {
2232                 .enable_reg = 0x36008,
2233                 .enable_mask = BIT(0),
2234                 .hw.init = &(struct clk_init_data){
2235                         .name = "gcc_tsif_ref_clk",
2236                         .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2237                         .num_parents = 1,
2238                         .flags = CLK_SET_RATE_PARENT,
2239                         .ops = &clk_branch2_ops,
2240                 },
2241         },
2242 };
2243
2244 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2245         .halt_reg = 0x3600c,
2246         .clkr = {
2247                 .enable_reg = 0x3600c,
2248                 .enable_mask = BIT(0),
2249                 .hw.init = &(struct clk_init_data){
2250                         .name = "gcc_tsif_inactivity_timers_clk",
2251                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2252                         .num_parents = 1,
2253                         .flags = CLK_SET_RATE_PARENT,
2254                         .ops = &clk_branch2_ops,
2255                 },
2256         },
2257 };
2258
2259 static struct clk_branch gcc_boot_rom_ahb_clk = {
2260         .halt_reg = 0x38004,
2261         .halt_check = BRANCH_HALT_VOTED,
2262         .clkr = {
2263                 .enable_reg = 0x52004,
2264                 .enable_mask = BIT(10),
2265                 .hw.init = &(struct clk_init_data){
2266                         .name = "gcc_boot_rom_ahb_clk",
2267                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2268                         .num_parents = 1,
2269                         .flags = CLK_SET_RATE_PARENT,
2270                         .ops = &clk_branch2_ops,
2271                 },
2272         },
2273 };
2274
2275 static struct clk_branch gcc_bimc_gfx_clk = {
2276         .halt_reg = 0x46018,
2277         .clkr = {
2278                 .enable_reg = 0x46018,
2279                 .enable_mask = BIT(0),
2280                 .hw.init = &(struct clk_init_data){
2281                         .name = "gcc_bimc_gfx_clk",
2282                         .flags = CLK_SET_RATE_PARENT,
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_hmss_rbcpr_clk = {
2289         .halt_reg = 0x4800c,
2290         .clkr = {
2291                 .enable_reg = 0x4800c,
2292                 .enable_mask = BIT(0),
2293                 .hw.init = &(struct clk_init_data){
2294                         .name = "gcc_hmss_rbcpr_clk",
2295                         .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2296                         .num_parents = 1,
2297                         .flags = CLK_SET_RATE_PARENT,
2298                         .ops = &clk_branch2_ops,
2299                 },
2300         },
2301 };
2302
2303 static struct clk_branch gcc_gp1_clk = {
2304         .halt_reg = 0x64000,
2305         .clkr = {
2306                 .enable_reg = 0x64000,
2307                 .enable_mask = BIT(0),
2308                 .hw.init = &(struct clk_init_data){
2309                         .name = "gcc_gp1_clk",
2310                         .parent_names = (const char *[]){ "gp1_clk_src" },
2311                         .num_parents = 1,
2312                         .flags = CLK_SET_RATE_PARENT,
2313                         .ops = &clk_branch2_ops,
2314                 },
2315         },
2316 };
2317
2318 static struct clk_branch gcc_gp2_clk = {
2319         .halt_reg = 0x65000,
2320         .clkr = {
2321                 .enable_reg = 0x65000,
2322                 .enable_mask = BIT(0),
2323                 .hw.init = &(struct clk_init_data){
2324                         .name = "gcc_gp2_clk",
2325                         .parent_names = (const char *[]){ "gp2_clk_src" },
2326                         .num_parents = 1,
2327                         .flags = CLK_SET_RATE_PARENT,
2328                         .ops = &clk_branch2_ops,
2329                 },
2330         },
2331 };
2332
2333 static struct clk_branch gcc_gp3_clk = {
2334         .halt_reg = 0x66000,
2335         .clkr = {
2336                 .enable_reg = 0x66000,
2337                 .enable_mask = BIT(0),
2338                 .hw.init = &(struct clk_init_data){
2339                         .name = "gcc_gp3_clk",
2340                         .parent_names = (const char *[]){ "gp3_clk_src" },
2341                         .num_parents = 1,
2342                         .flags = CLK_SET_RATE_PARENT,
2343                         .ops = &clk_branch2_ops,
2344                 },
2345         },
2346 };
2347
2348 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2349         .halt_reg = 0x6b008,
2350         .clkr = {
2351                 .enable_reg = 0x6b008,
2352                 .enable_mask = BIT(0),
2353                 .hw.init = &(struct clk_init_data){
2354                         .name = "gcc_pcie_0_slv_axi_clk",
2355                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2356                         .num_parents = 1,
2357                         .flags = CLK_SET_RATE_PARENT,
2358                         .ops = &clk_branch2_ops,
2359                 },
2360         },
2361 };
2362
2363 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2364         .halt_reg = 0x6b00c,
2365         .clkr = {
2366                 .enable_reg = 0x6b00c,
2367                 .enable_mask = BIT(0),
2368                 .hw.init = &(struct clk_init_data){
2369                         .name = "gcc_pcie_0_mstr_axi_clk",
2370                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2371                         .num_parents = 1,
2372                         .flags = CLK_SET_RATE_PARENT,
2373                         .ops = &clk_branch2_ops,
2374                 },
2375         },
2376 };
2377
2378 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2379         .halt_reg = 0x6b010,
2380         .clkr = {
2381                 .enable_reg = 0x6b010,
2382                 .enable_mask = BIT(0),
2383                 .hw.init = &(struct clk_init_data){
2384                         .name = "gcc_pcie_0_cfg_ahb_clk",
2385                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2386                         .num_parents = 1,
2387                         .flags = CLK_SET_RATE_PARENT,
2388                         .ops = &clk_branch2_ops,
2389                 },
2390         },
2391 };
2392
2393 static struct clk_branch gcc_pcie_0_aux_clk = {
2394         .halt_reg = 0x6b014,
2395         .clkr = {
2396                 .enable_reg = 0x6b014,
2397                 .enable_mask = BIT(0),
2398                 .hw.init = &(struct clk_init_data){
2399                         .name = "gcc_pcie_0_aux_clk",
2400                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2401                         .num_parents = 1,
2402                         .flags = CLK_SET_RATE_PARENT,
2403                         .ops = &clk_branch2_ops,
2404                 },
2405         },
2406 };
2407
2408 static struct clk_branch gcc_pcie_0_pipe_clk = {
2409         .halt_reg = 0x6b018,
2410         .clkr = {
2411                 .enable_reg = 0x6b018,
2412                 .enable_mask = BIT(0),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "gcc_pcie_0_pipe_clk",
2415                         .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2416                         .num_parents = 1,
2417                         .flags = CLK_SET_RATE_PARENT,
2418                         .ops = &clk_branch2_ops,
2419                 },
2420         },
2421 };
2422
2423 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2424         .halt_reg = 0x6d008,
2425         .clkr = {
2426                 .enable_reg = 0x6d008,
2427                 .enable_mask = BIT(0),
2428                 .hw.init = &(struct clk_init_data){
2429                         .name = "gcc_pcie_1_slv_axi_clk",
2430                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2431                         .num_parents = 1,
2432                         .flags = CLK_SET_RATE_PARENT,
2433                         .ops = &clk_branch2_ops,
2434                 },
2435         },
2436 };
2437
2438 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2439         .halt_reg = 0x6d00c,
2440         .clkr = {
2441                 .enable_reg = 0x6d00c,
2442                 .enable_mask = BIT(0),
2443                 .hw.init = &(struct clk_init_data){
2444                         .name = "gcc_pcie_1_mstr_axi_clk",
2445                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2446                         .num_parents = 1,
2447                         .flags = CLK_SET_RATE_PARENT,
2448                         .ops = &clk_branch2_ops,
2449                 },
2450         },
2451 };
2452
2453 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2454         .halt_reg = 0x6d010,
2455         .clkr = {
2456                 .enable_reg = 0x6d010,
2457                 .enable_mask = BIT(0),
2458                 .hw.init = &(struct clk_init_data){
2459                         .name = "gcc_pcie_1_cfg_ahb_clk",
2460                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2461                         .num_parents = 1,
2462                         .flags = CLK_SET_RATE_PARENT,
2463                         .ops = &clk_branch2_ops,
2464                 },
2465         },
2466 };
2467
2468 static struct clk_branch gcc_pcie_1_aux_clk = {
2469         .halt_reg = 0x6d014,
2470         .clkr = {
2471                 .enable_reg = 0x6d014,
2472                 .enable_mask = BIT(0),
2473                 .hw.init = &(struct clk_init_data){
2474                         .name = "gcc_pcie_1_aux_clk",
2475                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2476                         .num_parents = 1,
2477                         .flags = CLK_SET_RATE_PARENT,
2478                         .ops = &clk_branch2_ops,
2479                 },
2480         },
2481 };
2482
2483 static struct clk_branch gcc_pcie_1_pipe_clk = {
2484         .halt_reg = 0x6d018,
2485         .clkr = {
2486                 .enable_reg = 0x6d018,
2487                 .enable_mask = BIT(0),
2488                 .hw.init = &(struct clk_init_data){
2489                         .name = "gcc_pcie_1_pipe_clk",
2490                         .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2491                         .num_parents = 1,
2492                         .flags = CLK_SET_RATE_PARENT,
2493                         .ops = &clk_branch2_ops,
2494                 },
2495         },
2496 };
2497
2498 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2499         .halt_reg = 0x6e008,
2500         .clkr = {
2501                 .enable_reg = 0x6e008,
2502                 .enable_mask = BIT(0),
2503                 .hw.init = &(struct clk_init_data){
2504                         .name = "gcc_pcie_2_slv_axi_clk",
2505                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2506                         .num_parents = 1,
2507                         .flags = CLK_SET_RATE_PARENT,
2508                         .ops = &clk_branch2_ops,
2509                 },
2510         },
2511 };
2512
2513 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2514         .halt_reg = 0x6e00c,
2515         .clkr = {
2516                 .enable_reg = 0x6e00c,
2517                 .enable_mask = BIT(0),
2518                 .hw.init = &(struct clk_init_data){
2519                         .name = "gcc_pcie_2_mstr_axi_clk",
2520                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2521                         .num_parents = 1,
2522                         .flags = CLK_SET_RATE_PARENT,
2523                         .ops = &clk_branch2_ops,
2524                 },
2525         },
2526 };
2527
2528 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2529         .halt_reg = 0x6e010,
2530         .clkr = {
2531                 .enable_reg = 0x6e010,
2532                 .enable_mask = BIT(0),
2533                 .hw.init = &(struct clk_init_data){
2534                         .name = "gcc_pcie_2_cfg_ahb_clk",
2535                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2536                         .num_parents = 1,
2537                         .flags = CLK_SET_RATE_PARENT,
2538                         .ops = &clk_branch2_ops,
2539                 },
2540         },
2541 };
2542
2543 static struct clk_branch gcc_pcie_2_aux_clk = {
2544         .halt_reg = 0x6e014,
2545         .clkr = {
2546                 .enable_reg = 0x6e014,
2547                 .enable_mask = BIT(0),
2548                 .hw.init = &(struct clk_init_data){
2549                         .name = "gcc_pcie_2_aux_clk",
2550                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2551                         .num_parents = 1,
2552                         .flags = CLK_SET_RATE_PARENT,
2553                         .ops = &clk_branch2_ops,
2554                 },
2555         },
2556 };
2557
2558 static struct clk_branch gcc_pcie_2_pipe_clk = {
2559         .halt_reg = 0x6e018,
2560         .clkr = {
2561                 .enable_reg = 0x6e018,
2562                 .enable_mask = BIT(0),
2563                 .hw.init = &(struct clk_init_data){
2564                         .name = "gcc_pcie_2_pipe_clk",
2565                         .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2566                         .num_parents = 1,
2567                         .flags = CLK_SET_RATE_PARENT,
2568                         .ops = &clk_branch2_ops,
2569                 },
2570         },
2571 };
2572
2573 static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2574         .halt_reg = 0x6f004,
2575         .clkr = {
2576                 .enable_reg = 0x6f004,
2577                 .enable_mask = BIT(0),
2578                 .hw.init = &(struct clk_init_data){
2579                         .name = "gcc_pcie_phy_cfg_ahb_clk",
2580                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2581                         .num_parents = 1,
2582                         .flags = CLK_SET_RATE_PARENT,
2583                         .ops = &clk_branch2_ops,
2584                 },
2585         },
2586 };
2587
2588 static struct clk_branch gcc_pcie_phy_aux_clk = {
2589         .halt_reg = 0x6f008,
2590         .clkr = {
2591                 .enable_reg = 0x6f008,
2592                 .enable_mask = BIT(0),
2593                 .hw.init = &(struct clk_init_data){
2594                         .name = "gcc_pcie_phy_aux_clk",
2595                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2596                         .num_parents = 1,
2597                         .flags = CLK_SET_RATE_PARENT,
2598                         .ops = &clk_branch2_ops,
2599                 },
2600         },
2601 };
2602
2603 static struct clk_branch gcc_ufs_axi_clk = {
2604         .halt_reg = 0x75008,
2605         .clkr = {
2606                 .enable_reg = 0x75008,
2607                 .enable_mask = BIT(0),
2608                 .hw.init = &(struct clk_init_data){
2609                         .name = "gcc_ufs_axi_clk",
2610                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2611                         .num_parents = 1,
2612                         .flags = CLK_SET_RATE_PARENT,
2613                         .ops = &clk_branch2_ops,
2614                 },
2615         },
2616 };
2617
2618 static struct clk_branch gcc_ufs_ahb_clk = {
2619         .halt_reg = 0x7500c,
2620         .clkr = {
2621                 .enable_reg = 0x7500c,
2622                 .enable_mask = BIT(0),
2623                 .hw.init = &(struct clk_init_data){
2624                         .name = "gcc_ufs_ahb_clk",
2625                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2626                         .num_parents = 1,
2627                         .flags = CLK_SET_RATE_PARENT,
2628                         .ops = &clk_branch2_ops,
2629                 },
2630         },
2631 };
2632
2633 static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2634         .mult = 1,
2635         .div = 16,
2636         .hw.init = &(struct clk_init_data){
2637                 .name = "ufs_tx_cfg_clk_src",
2638                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2639                 .num_parents = 1,
2640                 .flags = CLK_SET_RATE_PARENT,
2641                 .ops = &clk_fixed_factor_ops,
2642         },
2643 };
2644
2645 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2646         .halt_reg = 0x75010,
2647         .clkr = {
2648                 .enable_reg = 0x75010,
2649                 .enable_mask = BIT(0),
2650                 .hw.init = &(struct clk_init_data){
2651                         .name = "gcc_ufs_tx_cfg_clk",
2652                         .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2653                         .num_parents = 1,
2654                         .flags = CLK_SET_RATE_PARENT,
2655                         .ops = &clk_branch2_ops,
2656                 },
2657         },
2658 };
2659
2660 static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2661         .mult = 1,
2662         .div = 16,
2663         .hw.init = &(struct clk_init_data){
2664                 .name = "ufs_rx_cfg_clk_src",
2665                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2666                 .num_parents = 1,
2667                 .flags = CLK_SET_RATE_PARENT,
2668                 .ops = &clk_fixed_factor_ops,
2669         },
2670 };
2671
2672 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2673         .halt_reg = 0x75014,
2674         .clkr = {
2675                 .enable_reg = 0x75014,
2676                 .enable_mask = BIT(0),
2677                 .hw.init = &(struct clk_init_data){
2678                         .name = "gcc_ufs_rx_cfg_clk",
2679                         .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2680                         .num_parents = 1,
2681                         .flags = CLK_SET_RATE_PARENT,
2682                         .ops = &clk_branch2_ops,
2683                 },
2684         },
2685 };
2686
2687 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2688         .halt_reg = 0x75018,
2689         .clkr = {
2690                 .enable_reg = 0x75018,
2691                 .enable_mask = BIT(0),
2692                 .hw.init = &(struct clk_init_data){
2693                         .name = "gcc_ufs_tx_symbol_0_clk",
2694                         .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2695                         .num_parents = 1,
2696                         .flags = CLK_SET_RATE_PARENT,
2697                         .ops = &clk_branch2_ops,
2698                 },
2699         },
2700 };
2701
2702 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2703         .halt_reg = 0x7501c,
2704         .clkr = {
2705                 .enable_reg = 0x7501c,
2706                 .enable_mask = BIT(0),
2707                 .hw.init = &(struct clk_init_data){
2708                         .name = "gcc_ufs_rx_symbol_0_clk",
2709                         .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2710                         .num_parents = 1,
2711                         .flags = CLK_SET_RATE_PARENT,
2712                         .ops = &clk_branch2_ops,
2713                 },
2714         },
2715 };
2716
2717 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2718         .halt_reg = 0x75020,
2719         .clkr = {
2720                 .enable_reg = 0x75020,
2721                 .enable_mask = BIT(0),
2722                 .hw.init = &(struct clk_init_data){
2723                         .name = "gcc_ufs_rx_symbol_1_clk",
2724                         .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2725                         .num_parents = 1,
2726                         .flags = CLK_SET_RATE_PARENT,
2727                         .ops = &clk_branch2_ops,
2728                 },
2729         },
2730 };
2731
2732 static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2733         .mult = 1,
2734         .div = 2,
2735         .hw.init = &(struct clk_init_data){
2736                 .name = "ufs_ice_core_postdiv_clk_src",
2737                 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2738                 .num_parents = 1,
2739                 .flags = CLK_SET_RATE_PARENT,
2740                 .ops = &clk_fixed_factor_ops,
2741         },
2742 };
2743
2744 static struct clk_branch gcc_ufs_unipro_core_clk = {
2745         .halt_reg = 0x7600c,
2746         .clkr = {
2747                 .enable_reg = 0x7600c,
2748                 .enable_mask = BIT(0),
2749                 .hw.init = &(struct clk_init_data){
2750                         .name = "gcc_ufs_unipro_core_clk",
2751                         .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2752                         .num_parents = 1,
2753                         .flags = CLK_SET_RATE_PARENT,
2754                         .ops = &clk_branch2_ops,
2755                 },
2756         },
2757 };
2758
2759 static struct clk_branch gcc_ufs_ice_core_clk = {
2760         .halt_reg = 0x76010,
2761         .clkr = {
2762                 .enable_reg = 0x76010,
2763                 .enable_mask = BIT(0),
2764                 .hw.init = &(struct clk_init_data){
2765                         .name = "gcc_ufs_ice_core_clk",
2766                         .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2767                         .num_parents = 1,
2768                         .flags = CLK_SET_RATE_PARENT,
2769                         .ops = &clk_branch2_ops,
2770                 },
2771         },
2772 };
2773
2774 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2775         .halt_check = BRANCH_HALT_DELAY,
2776         .clkr = {
2777                 .enable_reg = 0x76030,
2778                 .enable_mask = BIT(0),
2779                 .hw.init = &(struct clk_init_data){
2780                         .name = "gcc_ufs_sys_clk_core_clk",
2781                         .ops = &clk_branch2_ops,
2782                 },
2783         },
2784 };
2785
2786 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2787         .halt_check = BRANCH_HALT_DELAY,
2788         .clkr = {
2789                 .enable_reg = 0x76034,
2790                 .enable_mask = BIT(0),
2791                 .hw.init = &(struct clk_init_data){
2792                         .name = "gcc_ufs_tx_symbol_clk_core_clk",
2793                         .ops = &clk_branch2_ops,
2794                 },
2795         },
2796 };
2797
2798 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2799         .halt_reg = 0x81008,
2800         .clkr = {
2801                 .enable_reg = 0x81008,
2802                 .enable_mask = BIT(0),
2803                 .hw.init = &(struct clk_init_data){
2804                         .name = "gcc_aggre0_snoc_axi_clk",
2805                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2806                         .num_parents = 1,
2807                         .flags = CLK_SET_RATE_PARENT,
2808                         .ops = &clk_branch2_ops,
2809                 },
2810         },
2811 };
2812
2813 static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2814         .halt_reg = 0x8100c,
2815         .clkr = {
2816                 .enable_reg = 0x8100c,
2817                 .enable_mask = BIT(0),
2818                 .hw.init = &(struct clk_init_data){
2819                         .name = "gcc_aggre0_cnoc_ahb_clk",
2820                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2821                         .num_parents = 1,
2822                         .flags = CLK_SET_RATE_PARENT,
2823                         .ops = &clk_branch2_ops,
2824                 },
2825         },
2826 };
2827
2828 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2829         .halt_reg = 0x81014,
2830         .clkr = {
2831                 .enable_reg = 0x81014,
2832                 .enable_mask = BIT(0),
2833                 .hw.init = &(struct clk_init_data){
2834                         .name = "gcc_smmu_aggre0_axi_clk",
2835                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2836                         .num_parents = 1,
2837                         .flags = CLK_SET_RATE_PARENT,
2838                         .ops = &clk_branch2_ops,
2839                 },
2840         },
2841 };
2842
2843 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2844         .halt_reg = 0x81018,
2845         .clkr = {
2846                 .enable_reg = 0x81018,
2847                 .enable_mask = BIT(0),
2848                 .hw.init = &(struct clk_init_data){
2849                         .name = "gcc_smmu_aggre0_ahb_clk",
2850                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2851                         .num_parents = 1,
2852                         .flags = CLK_SET_RATE_PARENT,
2853                         .ops = &clk_branch2_ops,
2854                 },
2855         },
2856 };
2857
2858 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2859         .halt_reg = 0x83014,
2860         .clkr = {
2861                 .enable_reg = 0x83014,
2862                 .enable_mask = BIT(0),
2863                 .hw.init = &(struct clk_init_data){
2864                         .name = "gcc_aggre2_ufs_axi_clk",
2865                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2866                         .num_parents = 1,
2867                         .flags = CLK_SET_RATE_PARENT,
2868                         .ops = &clk_branch2_ops,
2869                 },
2870         },
2871 };
2872
2873 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2874         .halt_reg = 0x83018,
2875         .clkr = {
2876                 .enable_reg = 0x83018,
2877                 .enable_mask = BIT(0),
2878                 .hw.init = &(struct clk_init_data){
2879                         .name = "gcc_aggre2_usb3_axi_clk",
2880                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
2881                         .num_parents = 1,
2882                         .flags = CLK_SET_RATE_PARENT,
2883                         .ops = &clk_branch2_ops,
2884                 },
2885         },
2886 };
2887
2888 static struct clk_branch gcc_qspi_ahb_clk = {
2889         .halt_reg = 0x8b004,
2890         .clkr = {
2891                 .enable_reg = 0x8b004,
2892                 .enable_mask = BIT(0),
2893                 .hw.init = &(struct clk_init_data){
2894                         .name = "gcc_qspi_ahb_clk",
2895                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2896                         .num_parents = 1,
2897                         .flags = CLK_SET_RATE_PARENT,
2898                         .ops = &clk_branch2_ops,
2899                 },
2900         },
2901 };
2902
2903 static struct clk_branch gcc_qspi_ser_clk = {
2904         .halt_reg = 0x8b008,
2905         .clkr = {
2906                 .enable_reg = 0x8b008,
2907                 .enable_mask = BIT(0),
2908                 .hw.init = &(struct clk_init_data){
2909                         .name = "gcc_qspi_ser_clk",
2910                         .parent_names = (const char *[]){ "qspi_ser_clk_src" },
2911                         .num_parents = 1,
2912                         .flags = CLK_SET_RATE_PARENT,
2913                         .ops = &clk_branch2_ops,
2914                 },
2915         },
2916 };
2917
2918 static struct clk_branch gcc_usb3_clkref_clk = {
2919         .halt_reg = 0x8800C,
2920         .clkr = {
2921                 .enable_reg = 0x8800C,
2922                 .enable_mask = BIT(0),
2923                 .hw.init = &(struct clk_init_data){
2924                         .name = "gcc_usb3_clkref_clk",
2925                         .parent_names = (const char *[]){ "xo" },
2926                         .num_parents = 1,
2927                         .ops = &clk_branch2_ops,
2928                 },
2929         },
2930 };
2931
2932 static struct clk_branch gcc_hdmi_clkref_clk = {
2933         .halt_reg = 0x88000,
2934         .clkr = {
2935                 .enable_reg = 0x88000,
2936                 .enable_mask = BIT(0),
2937                 .hw.init = &(struct clk_init_data){
2938                         .name = "gcc_hdmi_clkref_clk",
2939                         .parent_names = (const char *[]){ "xo" },
2940                         .num_parents = 1,
2941                         .ops = &clk_branch2_ops,
2942                 },
2943         },
2944 };
2945
2946 static struct clk_branch gcc_ufs_clkref_clk = {
2947         .halt_reg = 0x88008,
2948         .clkr = {
2949                 .enable_reg = 0x88008,
2950                 .enable_mask = BIT(0),
2951                 .hw.init = &(struct clk_init_data){
2952                         .name = "gcc_ufs_clkref_clk",
2953                         .parent_names = (const char *[]){ "xo" },
2954                         .num_parents = 1,
2955                         .ops = &clk_branch2_ops,
2956                 },
2957         },
2958 };
2959
2960 static struct clk_branch gcc_pcie_clkref_clk = {
2961         .halt_reg = 0x88010,
2962         .clkr = {
2963                 .enable_reg = 0x88010,
2964                 .enable_mask = BIT(0),
2965                 .hw.init = &(struct clk_init_data){
2966                         .name = "gcc_pcie_clkref_clk",
2967                         .parent_names = (const char *[]){ "xo" },
2968                         .num_parents = 1,
2969                         .ops = &clk_branch2_ops,
2970                 },
2971         },
2972 };
2973
2974 static struct clk_branch gcc_rx2_usb2_clkref_clk = {
2975         .halt_reg = 0x88014,
2976         .clkr = {
2977                 .enable_reg = 0x88014,
2978                 .enable_mask = BIT(0),
2979                 .hw.init = &(struct clk_init_data){
2980                         .name = "gcc_rx2_usb2_clkref_clk",
2981                         .parent_names = (const char *[]){ "xo" },
2982                         .num_parents = 1,
2983                         .ops = &clk_branch2_ops,
2984                 },
2985         },
2986 };
2987
2988 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
2989         .halt_reg = 0x88018,
2990         .clkr = {
2991                 .enable_reg = 0x88018,
2992                 .enable_mask = BIT(0),
2993                 .hw.init = &(struct clk_init_data){
2994                         .name = "gcc_rx1_usb2_clkref_clk",
2995                         .parent_names = (const char *[]){ "xo" },
2996                         .num_parents = 1,
2997                         .ops = &clk_branch2_ops,
2998                 },
2999         },
3000 };
3001
3002 static struct clk_hw *gcc_msm8996_hws[] = {
3003         &xo.hw,
3004         &gpll0_early_div.hw,
3005         &ufs_tx_cfg_clk_src.hw,
3006         &ufs_rx_cfg_clk_src.hw,
3007         &ufs_ice_core_postdiv_clk_src.hw,
3008 };
3009
3010 static struct gdsc aggre0_noc_gdsc = {
3011         .gdscr = 0x81004,
3012         .gds_hw_ctrl = 0x81028,
3013         .pd = {
3014                 .name = "aggre0_noc",
3015         },
3016         .pwrsts = PWRSTS_OFF_ON,
3017         .flags = VOTABLE,
3018 };
3019
3020 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3021         .gdscr = 0x7d024,
3022         .pd = {
3023                 .name = "hlos1_vote_aggre0_noc",
3024         },
3025         .pwrsts = PWRSTS_OFF_ON,
3026         .flags = VOTABLE,
3027 };
3028
3029 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3030         .gdscr = 0x7d034,
3031         .pd = {
3032                 .name = "hlos1_vote_lpass_adsp",
3033         },
3034         .pwrsts = PWRSTS_OFF_ON,
3035         .flags = VOTABLE,
3036 };
3037
3038 static struct gdsc hlos1_vote_lpass_core_gdsc = {
3039         .gdscr = 0x7d038,
3040         .pd = {
3041                 .name = "hlos1_vote_lpass_core",
3042         },
3043         .pwrsts = PWRSTS_OFF_ON,
3044         .flags = VOTABLE,
3045 };
3046
3047 static struct gdsc usb30_gdsc = {
3048         .gdscr = 0xf004,
3049         .pd = {
3050                 .name = "usb30",
3051         },
3052         .pwrsts = PWRSTS_OFF_ON,
3053 };
3054
3055 static struct gdsc pcie0_gdsc = {
3056         .gdscr = 0x6b004,
3057         .pd = {
3058                 .name = "pcie0",
3059         },
3060         .pwrsts = PWRSTS_OFF_ON,
3061 };
3062
3063 static struct gdsc pcie1_gdsc = {
3064         .gdscr = 0x6d004,
3065         .pd = {
3066                 .name = "pcie1",
3067         },
3068         .pwrsts = PWRSTS_OFF_ON,
3069 };
3070
3071 static struct gdsc pcie2_gdsc = {
3072         .gdscr = 0x6e004,
3073         .pd = {
3074                 .name = "pcie2",
3075         },
3076         .pwrsts = PWRSTS_OFF_ON,
3077 };
3078
3079 static struct gdsc ufs_gdsc = {
3080         .gdscr = 0x75004,
3081         .pd = {
3082                 .name = "ufs",
3083         },
3084         .pwrsts = PWRSTS_OFF_ON,
3085 };
3086
3087 static struct clk_regmap *gcc_msm8996_clocks[] = {
3088         [GPLL0_EARLY] = &gpll0_early.clkr,
3089         [GPLL0] = &gpll0.clkr,
3090         [GPLL4_EARLY] = &gpll4_early.clkr,
3091         [GPLL4] = &gpll4.clkr,
3092         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3093         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3094         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3095         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3096         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3097         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3098         [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3099         [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3100         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3101         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3102         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3103         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3104         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3105         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3106         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3107         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3108         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3109         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3110         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3111         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3112         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3113         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3114         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3115         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3116         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3117         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3118         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3119         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3120         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3121         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3122         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3123         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3124         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3125         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3126         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3127         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3128         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3129         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3130         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3131         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3132         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3133         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3134         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3135         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3136         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3137         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3138         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3139         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3140         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3141         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3142         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3143         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3144         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3145         [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3146         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3147         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3148         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3149         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3150         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3151         [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3152         [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3153         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3154         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3155         [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3156         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3157         [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3158         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3159         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3160         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3161         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3162         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3163         [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3164         [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3165         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3166         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3167         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3168         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3169         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3170         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3171         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3172         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3173         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3174         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3175         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3176         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3177         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3178         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3179         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3180         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3181         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3182         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3183         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3184         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3185         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3186         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3187         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3188         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3189         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3190         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3191         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3192         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3193         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3194         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3195         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3196         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3197         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3198         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3199         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3200         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3201         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3202         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3203         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3204         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3205         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3206         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3207         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3208         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3209         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3210         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3211         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3212         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3213         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3214         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3215         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3216         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3217         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3218         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3219         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3220         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3221         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3222         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3223         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3224         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3225         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3226         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3227         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3228         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3229         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3230         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3231         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3232         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3233         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3234         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3235         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3236         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3237         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3238         [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3239         [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3240         [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3241         [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3242         [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3243         [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3244         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3245         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3246         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3247         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3248         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3249         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3250         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3251         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3252         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3253         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3254         [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3255         [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3256         [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3257         [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3258         [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3259         [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3260         [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3261         [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3262         [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3263         [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3264         [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3265         [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3266         [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3267         [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3268         [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3269         [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3270 };
3271
3272 static struct gdsc *gcc_msm8996_gdscs[] = {
3273         [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3274         [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3275         [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3276         [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3277         [USB30_GDSC] = &usb30_gdsc,
3278         [PCIE0_GDSC] = &pcie0_gdsc,
3279         [PCIE1_GDSC] = &pcie1_gdsc,
3280         [PCIE2_GDSC] = &pcie2_gdsc,
3281         [UFS_GDSC] = &ufs_gdsc,
3282 };
3283
3284 static const struct qcom_reset_map gcc_msm8996_resets[] = {
3285         [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3286         [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3287         [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3288         [GCC_IMEM_BCR] = { 0x8000 },
3289         [GCC_MMSS_BCR] = { 0x9000 },
3290         [GCC_PIMEM_BCR] = { 0x0a000 },
3291         [GCC_QDSS_BCR] = { 0x0c000 },
3292         [GCC_USB_30_BCR] = { 0x0f000 },
3293         [GCC_USB_20_BCR] = { 0x12000 },
3294         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3295         [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3296         [GCC_USB3_PHY_BCR] = { 0x50020 },
3297         [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3298         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3299         [GCC_SDCC1_BCR] = { 0x13000 },
3300         [GCC_SDCC2_BCR] = { 0x14000 },
3301         [GCC_SDCC3_BCR] = { 0x15000 },
3302         [GCC_SDCC4_BCR] = { 0x16000 },
3303         [GCC_BLSP1_BCR] = { 0x17000 },
3304         [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3305         [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3306         [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3307         [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3308         [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3309         [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3310         [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3311         [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3312         [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3313         [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3314         [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3315         [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3316         [GCC_BLSP2_BCR] = { 0x25000 },
3317         [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3318         [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3319         [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3320         [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3321         [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3322         [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3323         [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3324         [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3325         [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3326         [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3327         [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3328         [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3329         [GCC_PDM_BCR] = { 0x33000 },
3330         [GCC_PRNG_BCR] = { 0x34000 },
3331         [GCC_TSIF_BCR] = { 0x36000 },
3332         [GCC_TCSR_BCR] = { 0x37000 },
3333         [GCC_BOOT_ROM_BCR] = { 0x38000 },
3334         [GCC_MSG_RAM_BCR] = { 0x39000 },
3335         [GCC_TLMM_BCR] = { 0x3a000 },
3336         [GCC_MPM_BCR] = { 0x3b000 },
3337         [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3338         [GCC_SPMI_BCR] = { 0x3f000 },
3339         [GCC_SPDM_BCR] = { 0x40000 },
3340         [GCC_CE1_BCR] = { 0x41000 },
3341         [GCC_BIMC_BCR] = { 0x44000 },
3342         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3343         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3344         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3345         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3346         [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3347         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3348         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3349         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3350         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3351         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3352         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3353         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3354         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3355         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3356         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3357         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3358         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3359         [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3360         [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3361         [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3362         [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3363         [GCC_APB2JTAG_BCR] = { 0x4c000 },
3364         [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3365         [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3366         [GCC_PCIE_0_BCR] = { 0x6b000 },
3367         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3368         [GCC_PCIE_1_BCR] = { 0x6d000 },
3369         [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3370         [GCC_PCIE_2_BCR] = { 0x6e000 },
3371         [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3372         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3373         [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3374         [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3375         [GCC_DCD_BCR] = { 0x70000 },
3376         [GCC_OBT_ODT_BCR] = { 0x73000 },
3377         [GCC_UFS_BCR] = { 0x75000 },
3378         [GCC_SSC_BCR] = { 0x63000 },
3379         [GCC_VS_BCR] = { 0x7a000 },
3380         [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3381         [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3382         [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3383         [GCC_DCC_BCR] = { 0x84000 },
3384         [GCC_IPA_BCR] = { 0x89000 },
3385         [GCC_QSPI_BCR] = { 0x8b000 },
3386         [GCC_SKL_BCR] = { 0x8c000 },
3387         [GCC_MSMPU_BCR] = { 0x8d000 },
3388         [GCC_MSS_Q6_BCR] = { 0x8e000 },
3389         [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3390 };
3391
3392 static const struct regmap_config gcc_msm8996_regmap_config = {
3393         .reg_bits       = 32,
3394         .reg_stride     = 4,
3395         .val_bits       = 32,
3396         .max_register   = 0x8f010,
3397         .fast_io        = true,
3398 };
3399
3400 static const struct qcom_cc_desc gcc_msm8996_desc = {
3401         .config = &gcc_msm8996_regmap_config,
3402         .clks = gcc_msm8996_clocks,
3403         .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3404         .resets = gcc_msm8996_resets,
3405         .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3406         .gdscs = gcc_msm8996_gdscs,
3407         .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3408 };
3409
3410 static const struct of_device_id gcc_msm8996_match_table[] = {
3411         { .compatible = "qcom,gcc-msm8996" },
3412         { }
3413 };
3414 MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3415
3416 static int gcc_msm8996_probe(struct platform_device *pdev)
3417 {
3418         struct device *dev = &pdev->dev;
3419         int i, ret;
3420         struct regmap *regmap;
3421
3422         regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3423         if (IS_ERR(regmap))
3424                 return PTR_ERR(regmap);
3425
3426         /*
3427          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3428          * turned off by hardware during certain apps low power modes.
3429          */
3430         regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3431
3432         for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3433                 ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
3434                 if (ret)
3435                         return ret;
3436         }
3437
3438         return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3439 }
3440
3441 static struct platform_driver gcc_msm8996_driver = {
3442         .probe          = gcc_msm8996_probe,
3443         .driver         = {
3444                 .name   = "gcc-msm8996",
3445                 .of_match_table = gcc_msm8996_match_table,
3446         },
3447 };
3448
3449 static int __init gcc_msm8996_init(void)
3450 {
3451         return platform_driver_register(&gcc_msm8996_driver);
3452 }
3453 core_initcall(gcc_msm8996_init);
3454
3455 static void __exit gcc_msm8996_exit(void)
3456 {
3457         platform_driver_unregister(&gcc_msm8996_driver);
3458 }
3459 module_exit(gcc_msm8996_exit);
3460
3461 MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3462 MODULE_LICENSE("GPL v2");
3463 MODULE_ALIAS("platform:gcc-msm8996");