drivers/clk/qcom/gcc-msm8998.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-alpha-pll.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_AUD_REF_CLK,
  30         P_CORE_BI_PLL_TEST_SE,
  31         P_GPLL0_OUT_MAIN,
  32         P_GPLL4_OUT_MAIN,
  33         P_PLL0_EARLY_DIV_CLK_SRC,
  34         P_SLEEP_CLK,
  35         P_XO,
  36 };
  37
  38 static const struct parent_map gcc_parent_map_0[] = {
  39         { P_XO, 0 },
  40         { P_GPLL0_OUT_MAIN, 1 },
  41         { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  42         { P_CORE_BI_PLL_TEST_SE, 7 },
  43 };
  44
  45 static const char * const gcc_parent_names_0[] = {
  46         "xo",
  47         "gpll0_out_main",
  48         "gpll0_out_main",
  49         "core_bi_pll_test_se",
  50 };
  51
  52 static const struct parent_map gcc_parent_map_1[] = {
  53         { P_XO, 0 },
  54         { P_GPLL0_OUT_MAIN, 1 },
  55         { P_CORE_BI_PLL_TEST_SE, 7 },
  56 };
  57
  58 static const char * const gcc_parent_names_1[] = {
  59         "xo",
  60         "gpll0_out_main",
  61         "core_bi_pll_test_se",
  62 };
  63
  64 static const struct parent_map gcc_parent_map_2[] = {
  65         { P_XO, 0 },
  66         { P_GPLL0_OUT_MAIN, 1 },
  67         { P_SLEEP_CLK, 5 },
  68         { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  69         { P_CORE_BI_PLL_TEST_SE, 7 },
  70 };
  71
  72 static const char * const gcc_parent_names_2[] = {
  73         "xo",
  74         "gpll0_out_main",
  75         "core_pi_sleep_clk",
  76         "gpll0_out_main",
  77         "core_bi_pll_test_se",
  78 };
  79
  80 static const struct parent_map gcc_parent_map_3[] = {
  81         { P_XO, 0 },
  82         { P_SLEEP_CLK, 5 },
  83         { P_CORE_BI_PLL_TEST_SE, 7 },
  84 };
  85
  86 static const char * const gcc_parent_names_3[] = {
  87         "xo",
  88         "core_pi_sleep_clk",
  89         "core_bi_pll_test_se",
  90 };
  91
  92 static const struct parent_map gcc_parent_map_4[] = {
  93         { P_XO, 0 },
  94         { P_GPLL0_OUT_MAIN, 1 },
  95         { P_GPLL4_OUT_MAIN, 5 },
  96         { P_CORE_BI_PLL_TEST_SE, 7 },
  97 };
  98
  99 static const char * const gcc_parent_names_4[] = {
 100         "xo",
 101         "gpll0_out_main",
 102         "gpll4_out_main",
 103         "core_bi_pll_test_se",
 104 };
 105
 106 static const struct parent_map gcc_parent_map_5[] = {
 107         { P_XO, 0 },
 108         { P_GPLL0_OUT_MAIN, 1 },
 109         { P_AUD_REF_CLK, 2 },
 110         { P_CORE_BI_PLL_TEST_SE, 7 },
 111 };
 112
 113 static const char * const gcc_parent_names_5[] = {
 114         "xo",
 115         "gpll0_out_main",
 116         "aud_ref_clk",
 117         "core_bi_pll_test_se",
 118 };
 119
 120 static struct pll_vco fabia_vco[] = {
 121         { 250000000, 2000000000, 0 },
 122         { 125000000, 1000000000, 1 },
 123 };
 124
 125 static struct clk_alpha_pll gpll0 = {
 126         .offset = 0x0,
 127         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 128         .vco_table = fabia_vco,
 129         .num_vco = ARRAY_SIZE(fabia_vco),
 130         .clkr = {
 131                 .enable_reg = 0x52000,
 132                 .enable_mask = BIT(0),
 133                 .hw.init = &(struct clk_init_data){
 134                         .name = "gpll0",
 135                         .parent_names = (const char *[]){ "xo" },
 136                         .num_parents = 1,
 137                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 138                 }
 139         },
 140 };
 141
 142 static struct clk_alpha_pll_postdiv gpll0_out_even = {
 143         .offset = 0x0,
 144         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 145         .clkr.hw.init = &(struct clk_init_data){
 146                 .name = "gpll0_out_even",
 147                 .parent_names = (const char *[]){ "gpll0" },
 148                 .num_parents = 1,
 149                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 150         },
 151 };
 152
 153 static struct clk_alpha_pll_postdiv gpll0_out_main = {
 154         .offset = 0x0,
 155         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 156         .clkr.hw.init = &(struct clk_init_data){
 157                 .name = "gpll0_out_main",
 158                 .parent_names = (const char *[]){ "gpll0" },
 159                 .num_parents = 1,
 160                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 161         },
 162 };
 163
 164 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
 165         .offset = 0x0,
 166         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 167         .clkr.hw.init = &(struct clk_init_data){
 168                 .name = "gpll0_out_odd",
 169                 .parent_names = (const char *[]){ "gpll0" },
 170                 .num_parents = 1,
 171                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 172         },
 173 };
 174
 175 static struct clk_alpha_pll_postdiv gpll0_out_test = {
 176         .offset = 0x0,
 177         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 178         .clkr.hw.init = &(struct clk_init_data){
 179                 .name = "gpll0_out_test",
 180                 .parent_names = (const char *[]){ "gpll0" },
 181                 .num_parents = 1,
 182                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 183         },
 184 };
 185
 186 static struct clk_alpha_pll gpll1 = {
 187         .offset = 0x1000,
 188         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 189         .vco_table = fabia_vco,
 190         .num_vco = ARRAY_SIZE(fabia_vco),
 191         .clkr = {
 192                 .enable_reg = 0x52000,
 193                 .enable_mask = BIT(1),
 194                 .hw.init = &(struct clk_init_data){
 195                         .name = "gpll1",
 196                         .parent_names = (const char *[]){ "xo" },
 197                         .num_parents = 1,
 198                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 199                 }
 200         },
 201 };
 202
 203 static struct clk_alpha_pll_postdiv gpll1_out_even = {
 204         .offset = 0x1000,
 205         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 206         .clkr.hw.init = &(struct clk_init_data){
 207                 .name = "gpll1_out_even",
 208                 .parent_names = (const char *[]){ "gpll1" },
 209                 .num_parents = 1,
 210                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 211         },
 212 };
 213
 214 static struct clk_alpha_pll_postdiv gpll1_out_main = {
 215         .offset = 0x1000,
 216         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 217         .clkr.hw.init = &(struct clk_init_data){
 218                 .name = "gpll1_out_main",
 219                 .parent_names = (const char *[]){ "gpll1" },
 220                 .num_parents = 1,
 221                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 222         },
 223 };
 224
 225 static struct clk_alpha_pll_postdiv gpll1_out_odd = {
 226         .offset = 0x1000,
 227         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 228         .clkr.hw.init = &(struct clk_init_data){
 229                 .name = "gpll1_out_odd",
 230                 .parent_names = (const char *[]){ "gpll1" },
 231                 .num_parents = 1,
 232                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 233         },
 234 };
 235
 236 static struct clk_alpha_pll_postdiv gpll1_out_test = {
 237         .offset = 0x1000,
 238         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 239         .clkr.hw.init = &(struct clk_init_data){
 240                 .name = "gpll1_out_test",
 241                 .parent_names = (const char *[]){ "gpll1" },
 242                 .num_parents = 1,
 243                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 244         },
 245 };
 246
 247 static struct clk_alpha_pll gpll2 = {
 248         .offset = 0x2000,
 249         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 250         .vco_table = fabia_vco,
 251         .num_vco = ARRAY_SIZE(fabia_vco),
 252         .clkr = {
 253                 .enable_reg = 0x52000,
 254                 .enable_mask = BIT(2),
 255                 .hw.init = &(struct clk_init_data){
 256                         .name = "gpll2",
 257                         .parent_names = (const char *[]){ "xo" },
 258                         .num_parents = 1,
 259                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 260                 }
 261         },
 262 };
 263
 264 static struct clk_alpha_pll_postdiv gpll2_out_even = {
 265         .offset = 0x2000,
 266         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 267         .clkr.hw.init = &(struct clk_init_data){
 268                 .name = "gpll2_out_even",
 269                 .parent_names = (const char *[]){ "gpll2" },
 270                 .num_parents = 1,
 271                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 272         },
 273 };
 274
 275 static struct clk_alpha_pll_postdiv gpll2_out_main = {
 276         .offset = 0x2000,
 277         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 278         .clkr.hw.init = &(struct clk_init_data){
 279                 .name = "gpll2_out_main",
 280                 .parent_names = (const char *[]){ "gpll2" },
 281                 .num_parents = 1,
 282                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 283         },
 284 };
 285
 286 static struct clk_alpha_pll_postdiv gpll2_out_odd = {
 287         .offset = 0x2000,
 288         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 289         .clkr.hw.init = &(struct clk_init_data){
 290                 .name = "gpll2_out_odd",
 291                 .parent_names = (const char *[]){ "gpll2" },
 292                 .num_parents = 1,
 293                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 294         },
 295 };
 296
 297 static struct clk_alpha_pll_postdiv gpll2_out_test = {
 298         .offset = 0x2000,
 299         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 300         .clkr.hw.init = &(struct clk_init_data){
 301                 .name = "gpll2_out_test",
 302                 .parent_names = (const char *[]){ "gpll2" },
 303                 .num_parents = 1,
 304                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 305         },
 306 };
 307
 308 static struct clk_alpha_pll gpll3 = {
 309         .offset = 0x3000,
 310         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 311         .vco_table = fabia_vco,
 312         .num_vco = ARRAY_SIZE(fabia_vco),
 313         .clkr = {
 314                 .enable_reg = 0x52000,
 315                 .enable_mask = BIT(3),
 316                 .hw.init = &(struct clk_init_data){
 317                         .name = "gpll3",
 318                         .parent_names = (const char *[]){ "xo" },
 319                         .num_parents = 1,
 320                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 321                 }
 322         },
 323 };
 324
 325 static struct clk_alpha_pll_postdiv gpll3_out_even = {
 326         .offset = 0x3000,
 327         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 328         .clkr.hw.init = &(struct clk_init_data){
 329                 .name = "gpll3_out_even",
 330                 .parent_names = (const char *[]){ "gpll3" },
 331                 .num_parents = 1,
 332                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 333         },
 334 };
 335
 336 static struct clk_alpha_pll_postdiv gpll3_out_main = {
 337         .offset = 0x3000,
 338         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 339         .clkr.hw.init = &(struct clk_init_data){
 340                 .name = "gpll3_out_main",
 341                 .parent_names = (const char *[]){ "gpll3" },
 342                 .num_parents = 1,
 343                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 344         },
 345 };
 346
 347 static struct clk_alpha_pll_postdiv gpll3_out_odd = {
 348         .offset = 0x3000,
 349         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 350         .clkr.hw.init = &(struct clk_init_data){
 351                 .name = "gpll3_out_odd",
 352                 .parent_names = (const char *[]){ "gpll3" },
 353                 .num_parents = 1,
 354                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 355         },
 356 };
 357
 358 static struct clk_alpha_pll_postdiv gpll3_out_test = {
 359         .offset = 0x3000,
 360         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 361         .clkr.hw.init = &(struct clk_init_data){
 362                 .name = "gpll3_out_test",
 363                 .parent_names = (const char *[]){ "gpll3" },
 364                 .num_parents = 1,
 365                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 366         },
 367 };
 368
 369 static struct clk_alpha_pll gpll4 = {
 370         .offset = 0x77000,
 371         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 372         .vco_table = fabia_vco,
 373         .num_vco = ARRAY_SIZE(fabia_vco),
 374         .clkr = {
 375                 .enable_reg = 0x52000,
 376                 .enable_mask = BIT(4),
 377                 .hw.init = &(struct clk_init_data){
 378                         .name = "gpll4",
 379                         .parent_names = (const char *[]){ "xo" },
 380                         .num_parents = 1,
 381                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 382                 }
 383         },
 384 };
 385
 386 static struct clk_alpha_pll_postdiv gpll4_out_even = {
 387         .offset = 0x77000,
 388         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 389         .clkr.hw.init = &(struct clk_init_data){
 390                 .name = "gpll4_out_even",
 391                 .parent_names = (const char *[]){ "gpll4" },
 392                 .num_parents = 1,
 393                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 394         },
 395 };
 396
 397 static struct clk_alpha_pll_postdiv gpll4_out_main = {
 398         .offset = 0x77000,
 399         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 400         .clkr.hw.init = &(struct clk_init_data){
 401                 .name = "gpll4_out_main",
 402                 .parent_names = (const char *[]){ "gpll4" },
 403                 .num_parents = 1,
 404                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 405         },
 406 };
 407
 408 static struct clk_alpha_pll_postdiv gpll4_out_odd = {
 409         .offset = 0x77000,
 410         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 411         .clkr.hw.init = &(struct clk_init_data){
 412                 .name = "gpll4_out_odd",
 413                 .parent_names = (const char *[]){ "gpll4" },
 414                 .num_parents = 1,
 415                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 416         },
 417 };
 418
 419 static struct clk_alpha_pll_postdiv gpll4_out_test = {
 420         .offset = 0x77000,
 421         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 422         .clkr.hw.init = &(struct clk_init_data){
 423                 .name = "gpll4_out_test",
 424                 .parent_names = (const char *[]){ "gpll4" },
 425                 .num_parents = 1,
 426                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 427         },
 428 };
 429
 430 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 431         F(19200000, P_XO, 1, 0, 0),
 432         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 433         { }
 434 };
 435
 436 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 437         .cmd_rcgr = 0x19020,
 438         .mnd_width = 0,
 439         .hid_width = 5,
 440         .parent_map = gcc_parent_map_1,
 441         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 442         .clkr.hw.init = &(struct clk_init_data){
 443                 .name = "blsp1_qup1_i2c_apps_clk_src",
 444                 .parent_names = gcc_parent_names_1,
 445                 .num_parents = 3,
 446                 .ops = &clk_rcg2_ops,
 447         },
 448 };
 449
 450 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 451         F(960000, P_XO, 10, 1, 2),
 452         F(4800000, P_XO, 4, 0, 0),
 453         F(9600000, P_XO, 2, 0, 0),
 454         F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
 455         F(19200000, P_XO, 1, 0, 0),
 456         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 457         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 458         { }
 459 };
 460
 461 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 462         .cmd_rcgr = 0x1900c,
 463         .mnd_width = 8,
 464         .hid_width = 5,
 465         .parent_map = gcc_parent_map_0,
 466         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 467         .clkr.hw.init = &(struct clk_init_data){
 468                 .name = "blsp1_qup1_spi_apps_clk_src",
 469                 .parent_names = gcc_parent_names_0,
 470                 .num_parents = 4,
 471                 .ops = &clk_rcg2_ops,
 472         },
 473 };
 474
 475 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 476         .cmd_rcgr = 0x1b020,
 477         .mnd_width = 0,
 478         .hid_width = 5,
 479         .parent_map = gcc_parent_map_1,
 480         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 481         .clkr.hw.init = &(struct clk_init_data){
 482                 .name = "blsp1_qup2_i2c_apps_clk_src",
 483                 .parent_names = gcc_parent_names_1,
 484                 .num_parents = 3,
 485                 .ops = &clk_rcg2_ops,
 486         },
 487 };
 488
 489 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 490         .cmd_rcgr = 0x1b00c,
 491         .mnd_width = 8,
 492         .hid_width = 5,
 493         .parent_map = gcc_parent_map_0,
 494         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 495         .clkr.hw.init = &(struct clk_init_data){
 496                 .name = "blsp1_qup2_spi_apps_clk_src",
 497                 .parent_names = gcc_parent_names_0,
 498                 .num_parents = 4,
 499                 .ops = &clk_rcg2_ops,
 500         },
 501 };
 502
 503 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 504         .cmd_rcgr = 0x1d020,
 505         .mnd_width = 0,
 506         .hid_width = 5,
 507         .parent_map = gcc_parent_map_1,
 508         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 509         .clkr.hw.init = &(struct clk_init_data){
 510                 .name = "blsp1_qup3_i2c_apps_clk_src",
 511                 .parent_names = gcc_parent_names_1,
 512                 .num_parents = 3,
 513                 .ops = &clk_rcg2_ops,
 514         },
 515 };
 516
 517 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 518         .cmd_rcgr = 0x1d00c,
 519         .mnd_width = 8,
 520         .hid_width = 5,
 521         .parent_map = gcc_parent_map_0,
 522         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 523         .clkr.hw.init = &(struct clk_init_data){
 524                 .name = "blsp1_qup3_spi_apps_clk_src",
 525                 .parent_names = gcc_parent_names_0,
 526                 .num_parents = 4,
 527                 .ops = &clk_rcg2_ops,
 528         },
 529 };
 530
 531 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 532         .cmd_rcgr = 0x1f020,
 533         .mnd_width = 0,
 534         .hid_width = 5,
 535         .parent_map = gcc_parent_map_1,
 536         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 537         .clkr.hw.init = &(struct clk_init_data){
 538                 .name = "blsp1_qup4_i2c_apps_clk_src",
 539                 .parent_names = gcc_parent_names_1,
 540                 .num_parents = 3,
 541                 .ops = &clk_rcg2_ops,
 542         },
 543 };
 544
 545 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 546         .cmd_rcgr = 0x1f00c,
 547         .mnd_width = 8,
 548         .hid_width = 5,
 549         .parent_map = gcc_parent_map_0,
 550         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 551         .clkr.hw.init = &(struct clk_init_data){
 552                 .name = "blsp1_qup4_spi_apps_clk_src",
 553                 .parent_names = gcc_parent_names_0,
 554                 .num_parents = 4,
 555                 .ops = &clk_rcg2_ops,
 556         },
 557 };
 558
 559 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 560         .cmd_rcgr = 0x21020,
 561         .mnd_width = 0,
 562         .hid_width = 5,
 563         .parent_map = gcc_parent_map_1,
 564         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 565         .clkr.hw.init = &(struct clk_init_data){
 566                 .name = "blsp1_qup5_i2c_apps_clk_src",
 567                 .parent_names = gcc_parent_names_1,
 568                 .num_parents = 3,
 569                 .ops = &clk_rcg2_ops,
 570         },
 571 };
 572
 573 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 574         .cmd_rcgr = 0x2100c,
 575         .mnd_width = 8,
 576         .hid_width = 5,
 577         .parent_map = gcc_parent_map_0,
 578         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 579         .clkr.hw.init = &(struct clk_init_data){
 580                 .name = "blsp1_qup5_spi_apps_clk_src",
 581                 .parent_names = gcc_parent_names_0,
 582                 .num_parents = 4,
 583                 .ops = &clk_rcg2_ops,
 584         },
 585 };
 586
 587 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 588         .cmd_rcgr = 0x23020,
 589         .mnd_width = 0,
 590         .hid_width = 5,
 591         .parent_map = gcc_parent_map_1,
 592         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 593         .clkr.hw.init = &(struct clk_init_data){
 594                 .name = "blsp1_qup6_i2c_apps_clk_src",
 595                 .parent_names = gcc_parent_names_1,
 596                 .num_parents = 3,
 597                 .ops = &clk_rcg2_ops,
 598         },
 599 };
 600
 601 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 602         .cmd_rcgr = 0x2300c,
 603         .mnd_width = 8,
 604         .hid_width = 5,
 605         .parent_map = gcc_parent_map_0,
 606         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 607         .clkr.hw.init = &(struct clk_init_data){
 608                 .name = "blsp1_qup6_spi_apps_clk_src",
 609                 .parent_names = gcc_parent_names_0,
 610                 .num_parents = 4,
 611                 .ops = &clk_rcg2_ops,
 612         },
 613 };
 614
 615 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 616         F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
 617         F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
 618         F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
 619         F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
 620         F(19200000, P_XO, 1, 0, 0),
 621         F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
 622         F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
 623         F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
 624         F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
 625         F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
 626         F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
 627         F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
 628         F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
 629         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 630         F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
 631         { }
 632 };
 633
 634 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 635         .cmd_rcgr = 0x1a00c,
 636         .mnd_width = 16,
 637         .hid_width = 5,
 638         .parent_map = gcc_parent_map_0,
 639         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 640         .clkr.hw.init = &(struct clk_init_data){
 641                 .name = "blsp1_uart1_apps_clk_src",
 642                 .parent_names = gcc_parent_names_0,
 643                 .num_parents = 4,
 644                 .ops = &clk_rcg2_ops,
 645         },
 646 };
 647
 648 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 649         .cmd_rcgr = 0x1c00c,
 650         .mnd_width = 16,
 651         .hid_width = 5,
 652         .parent_map = gcc_parent_map_0,
 653         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 654         .clkr.hw.init = &(struct clk_init_data){
 655                 .name = "blsp1_uart2_apps_clk_src",
 656                 .parent_names = gcc_parent_names_0,
 657                 .num_parents = 4,
 658                 .ops = &clk_rcg2_ops,
 659         },
 660 };
 661
 662 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 663         .cmd_rcgr = 0x1e00c,
 664         .mnd_width = 16,
 665         .hid_width = 5,
 666         .parent_map = gcc_parent_map_0,
 667         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 668         .clkr.hw.init = &(struct clk_init_data){
 669                 .name = "blsp1_uart3_apps_clk_src",
 670                 .parent_names = gcc_parent_names_0,
 671                 .num_parents = 4,
 672                 .ops = &clk_rcg2_ops,
 673         },
 674 };
 675
 676 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 677         .cmd_rcgr = 0x26020,
 678         .mnd_width = 0,
 679         .hid_width = 5,
 680         .parent_map = gcc_parent_map_1,
 681         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 682         .clkr.hw.init = &(struct clk_init_data){
 683                 .name = "blsp2_qup1_i2c_apps_clk_src",
 684                 .parent_names = gcc_parent_names_1,
 685                 .num_parents = 3,
 686                 .ops = &clk_rcg2_ops,
 687         },
 688 };
 689
 690 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 691         .cmd_rcgr = 0x2600c,
 692         .mnd_width = 8,
 693         .hid_width = 5,
 694         .parent_map = gcc_parent_map_0,
 695         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 696         .clkr.hw.init = &(struct clk_init_data){
 697                 .name = "blsp2_qup1_spi_apps_clk_src",
 698                 .parent_names = gcc_parent_names_0,
 699                 .num_parents = 4,
 700                 .ops = &clk_rcg2_ops,
 701         },
 702 };
 703
 704 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 705         .cmd_rcgr = 0x28020,
 706         .mnd_width = 0,
 707         .hid_width = 5,
 708         .parent_map = gcc_parent_map_1,
 709         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 710         .clkr.hw.init = &(struct clk_init_data){
 711                 .name = "blsp2_qup2_i2c_apps_clk_src",
 712                 .parent_names = gcc_parent_names_1,
 713                 .num_parents = 3,
 714                 .ops = &clk_rcg2_ops,
 715         },
 716 };
 717
 718 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 719         .cmd_rcgr = 0x2800c,
 720         .mnd_width = 8,
 721         .hid_width = 5,
 722         .parent_map = gcc_parent_map_0,
 723         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 724         .clkr.hw.init = &(struct clk_init_data){
 725                 .name = "blsp2_qup2_spi_apps_clk_src",
 726                 .parent_names = gcc_parent_names_0,
 727                 .num_parents = 4,
 728                 .ops = &clk_rcg2_ops,
 729         },
 730 };
 731
 732 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 733         .cmd_rcgr = 0x2a020,
 734         .mnd_width = 0,
 735         .hid_width = 5,
 736         .parent_map = gcc_parent_map_1,
 737         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 738         .clkr.hw.init = &(struct clk_init_data){
 739                 .name = "blsp2_qup3_i2c_apps_clk_src",
 740                 .parent_names = gcc_parent_names_1,
 741                 .num_parents = 3,
 742                 .ops = &clk_rcg2_ops,
 743         },
 744 };
 745
 746 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 747         .cmd_rcgr = 0x2a00c,
 748         .mnd_width = 8,
 749         .hid_width = 5,
 750         .parent_map = gcc_parent_map_0,
 751         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 752         .clkr.hw.init = &(struct clk_init_data){
 753                 .name = "blsp2_qup3_spi_apps_clk_src",
 754                 .parent_names = gcc_parent_names_0,
 755                 .num_parents = 4,
 756                 .ops = &clk_rcg2_ops,
 757         },
 758 };
 759
 760 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 761         .cmd_rcgr = 0x2c020,
 762         .mnd_width = 0,
 763         .hid_width = 5,
 764         .parent_map = gcc_parent_map_1,
 765         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 766         .clkr.hw.init = &(struct clk_init_data){
 767                 .name = "blsp2_qup4_i2c_apps_clk_src",
 768                 .parent_names = gcc_parent_names_1,
 769                 .num_parents = 3,
 770                 .ops = &clk_rcg2_ops,
 771         },
 772 };
 773
 774 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 775         .cmd_rcgr = 0x2c00c,
 776         .mnd_width = 8,
 777         .hid_width = 5,
 778         .parent_map = gcc_parent_map_0,
 779         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 780         .clkr.hw.init = &(struct clk_init_data){
 781                 .name = "blsp2_qup4_spi_apps_clk_src",
 782                 .parent_names = gcc_parent_names_0,
 783                 .num_parents = 4,
 784                 .ops = &clk_rcg2_ops,
 785         },
 786 };
 787
 788 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 789         .cmd_rcgr = 0x2e020,
 790         .mnd_width = 0,
 791         .hid_width = 5,
 792         .parent_map = gcc_parent_map_1,
 793         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 794         .clkr.hw.init = &(struct clk_init_data){
 795                 .name = "blsp2_qup5_i2c_apps_clk_src",
 796                 .parent_names = gcc_parent_names_1,
 797                 .num_parents = 3,
 798                 .ops = &clk_rcg2_ops,
 799         },
 800 };
 801
 802 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 803         .cmd_rcgr = 0x2e00c,
 804         .mnd_width = 8,
 805         .hid_width = 5,
 806         .parent_map = gcc_parent_map_0,
 807         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 808         .clkr.hw.init = &(struct clk_init_data){
 809                 .name = "blsp2_qup5_spi_apps_clk_src",
 810                 .parent_names = gcc_parent_names_0,
 811                 .num_parents = 4,
 812                 .ops = &clk_rcg2_ops,
 813         },
 814 };
 815
 816 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 817         .cmd_rcgr = 0x30020,
 818         .mnd_width = 0,
 819         .hid_width = 5,
 820         .parent_map = gcc_parent_map_1,
 821         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 822         .clkr.hw.init = &(struct clk_init_data){
 823                 .name = "blsp2_qup6_i2c_apps_clk_src",
 824                 .parent_names = gcc_parent_names_1,
 825                 .num_parents = 3,
 826                 .ops = &clk_rcg2_ops,
 827         },
 828 };
 829
 830 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 831         .cmd_rcgr = 0x3000c,
 832         .mnd_width = 8,
 833         .hid_width = 5,
 834         .parent_map = gcc_parent_map_0,
 835         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 836         .clkr.hw.init = &(struct clk_init_data){
 837                 .name = "blsp2_qup6_spi_apps_clk_src",
 838                 .parent_names = gcc_parent_names_0,
 839                 .num_parents = 4,
 840                 .ops = &clk_rcg2_ops,
 841         },
 842 };
 843
 844 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 845         .cmd_rcgr = 0x2700c,
 846         .mnd_width = 16,
 847         .hid_width = 5,
 848         .parent_map = gcc_parent_map_0,
 849         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 850         .clkr.hw.init = &(struct clk_init_data){
 851                 .name = "blsp2_uart1_apps_clk_src",
 852                 .parent_names = gcc_parent_names_0,
 853                 .num_parents = 4,
 854                 .ops = &clk_rcg2_ops,
 855         },
 856 };
 857
 858 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 859         .cmd_rcgr = 0x2900c,
 860         .mnd_width = 16,
 861         .hid_width = 5,
 862         .parent_map = gcc_parent_map_0,
 863         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 864         .clkr.hw.init = &(struct clk_init_data){
 865                 .name = "blsp2_uart2_apps_clk_src",
 866                 .parent_names = gcc_parent_names_0,
 867                 .num_parents = 4,
 868                 .ops = &clk_rcg2_ops,
 869         },
 870 };
 871
 872 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 873         .cmd_rcgr = 0x2b00c,
 874         .mnd_width = 16,
 875         .hid_width = 5,
 876         .parent_map = gcc_parent_map_0,
 877         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 878         .clkr.hw.init = &(struct clk_init_data){
 879                 .name = "blsp2_uart3_apps_clk_src",
 880                 .parent_names = gcc_parent_names_0,
 881                 .num_parents = 4,
 882                 .ops = &clk_rcg2_ops,
 883         },
 884 };
 885
 886 static const struct freq_tbl ftbl_gp1_clk_src[] = {
 887         F(19200000, P_XO, 1, 0, 0),
 888         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 889         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 890         { }
 891 };
 892
 893 static struct clk_rcg2 gp1_clk_src = {
 894         .cmd_rcgr = 0x64004,
 895         .mnd_width = 8,
 896         .hid_width = 5,
 897         .parent_map = gcc_parent_map_2,
 898         .freq_tbl = ftbl_gp1_clk_src,
 899         .clkr.hw.init = &(struct clk_init_data){
 900                 .name = "gp1_clk_src",
 901                 .parent_names = gcc_parent_names_2,
 902                 .num_parents = 5,
 903                 .ops = &clk_rcg2_ops,
 904         },
 905 };
 906
 907 static struct clk_rcg2 gp2_clk_src = {
 908         .cmd_rcgr = 0x65004,
 909         .mnd_width = 8,
 910         .hid_width = 5,
 911         .parent_map = gcc_parent_map_2,
 912         .freq_tbl = ftbl_gp1_clk_src,
 913         .clkr.hw.init = &(struct clk_init_data){
 914                 .name = "gp2_clk_src",
 915                 .parent_names = gcc_parent_names_2,
 916                 .num_parents = 5,
 917                 .ops = &clk_rcg2_ops,
 918         },
 919 };
 920
 921 static struct clk_rcg2 gp3_clk_src = {
 922         .cmd_rcgr = 0x66004,
 923         .mnd_width = 8,
 924         .hid_width = 5,
 925         .parent_map = gcc_parent_map_2,
 926         .freq_tbl = ftbl_gp1_clk_src,
 927         .clkr.hw.init = &(struct clk_init_data){
 928                 .name = "gp3_clk_src",
 929                 .parent_names = gcc_parent_names_2,
 930                 .num_parents = 5,
 931                 .ops = &clk_rcg2_ops,
 932         },
 933 };
 934
 935 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
 936         F(19200000, P_XO, 1, 0, 0),
 937         F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 938         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 939         { }
 940 };
 941
 942 static struct clk_rcg2 hmss_ahb_clk_src = {
 943         .cmd_rcgr = 0x48014,
 944         .mnd_width = 0,
 945         .hid_width = 5,
 946         .parent_map = gcc_parent_map_1,
 947         .freq_tbl = ftbl_hmss_ahb_clk_src,
 948         .clkr.hw.init = &(struct clk_init_data){
 949                 .name = "hmss_ahb_clk_src",
 950                 .parent_names = gcc_parent_names_1,
 951                 .num_parents = 3,
 952                 .ops = &clk_rcg2_ops,
 953         },
 954 };
 955
 956 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
 957         F(19200000, P_XO, 1, 0, 0),
 958         { }
 959 };
 960
 961 static struct clk_rcg2 hmss_rbcpr_clk_src = {
 962         .cmd_rcgr = 0x48044,
 963         .mnd_width = 0,
 964         .hid_width = 5,
 965         .parent_map = gcc_parent_map_1,
 966         .freq_tbl = ftbl_hmss_rbcpr_clk_src,
 967         .clkr.hw.init = &(struct clk_init_data){
 968                 .name = "hmss_rbcpr_clk_src",
 969                 .parent_names = gcc_parent_names_1,
 970                 .num_parents = 3,
 971                 .ops = &clk_rcg2_ops,
 972         },
 973 };
 974
 975 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 976         F(1010526, P_XO, 1, 1, 19),
 977         { }
 978 };
 979
 980 static struct clk_rcg2 pcie_aux_clk_src = {
 981         .cmd_rcgr = 0x6c000,
 982         .mnd_width = 16,
 983         .hid_width = 5,
 984         .parent_map = gcc_parent_map_3,
 985         .freq_tbl = ftbl_pcie_aux_clk_src,
 986         .clkr.hw.init = &(struct clk_init_data){
 987                 .name = "pcie_aux_clk_src",
 988                 .parent_names = gcc_parent_names_3,
 989                 .num_parents = 3,
 990                 .ops = &clk_rcg2_ops,
 991         },
 992 };
 993
 994 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
 995         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 996         { }
 997 };
 998
 999 static struct clk_rcg2 pdm2_clk_src = {
1000         .cmd_rcgr = 0x33010,
1001         .mnd_width = 0,
1002         .hid_width = 5,
1003         .parent_map = gcc_parent_map_1,
1004         .freq_tbl = ftbl_pdm2_clk_src,
1005         .clkr.hw.init = &(struct clk_init_data){
1006                 .name = "pdm2_clk_src",
1007                 .parent_names = gcc_parent_names_1,
1008                 .num_parents = 3,
1009                 .ops = &clk_rcg2_ops,
1010         },
1011 };
1012
1013 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1014         F(144000, P_XO, 16, 3, 25),
1015         F(400000, P_XO, 12, 1, 4),
1016         F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1017         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1018         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1019         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1020         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1021         { }
1022 };
1023
1024 static struct clk_rcg2 sdcc2_apps_clk_src = {
1025         .cmd_rcgr = 0x14010,
1026         .mnd_width = 8,
1027         .hid_width = 5,
1028         .parent_map = gcc_parent_map_4,
1029         .freq_tbl = ftbl_sdcc2_apps_clk_src,
1030         .clkr.hw.init = &(struct clk_init_data){
1031                 .name = "sdcc2_apps_clk_src",
1032                 .parent_names = gcc_parent_names_4,
1033                 .num_parents = 4,
1034                 .ops = &clk_rcg2_ops,
1035         },
1036 };
1037
1038 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
1039         F(144000, P_XO, 16, 3, 25),
1040         F(400000, P_XO, 12, 1, 4),
1041         F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1042         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1043         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1044         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1045         { }
1046 };
1047
1048 static struct clk_rcg2 sdcc4_apps_clk_src = {
1049         .cmd_rcgr = 0x16010,
1050         .mnd_width = 8,
1051         .hid_width = 5,
1052         .parent_map = gcc_parent_map_1,
1053         .freq_tbl = ftbl_sdcc4_apps_clk_src,
1054         .clkr.hw.init = &(struct clk_init_data){
1055                 .name = "sdcc4_apps_clk_src",
1056                 .parent_names = gcc_parent_names_1,
1057                 .num_parents = 3,
1058                 .ops = &clk_rcg2_ops,
1059         },
1060 };
1061
1062 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1063         F(105495, P_XO, 1, 1, 182),
1064         { }
1065 };
1066
1067 static struct clk_rcg2 tsif_ref_clk_src = {
1068         .cmd_rcgr = 0x36010,
1069         .mnd_width = 8,
1070         .hid_width = 5,
1071         .parent_map = gcc_parent_map_5,
1072         .freq_tbl = ftbl_tsif_ref_clk_src,
1073         .clkr.hw.init = &(struct clk_init_data){
1074                 .name = "tsif_ref_clk_src",
1075                 .parent_names = gcc_parent_names_5,
1076                 .num_parents = 4,
1077                 .ops = &clk_rcg2_ops,
1078         },
1079 };
1080
1081 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1082         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1083         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1084         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1085         { }
1086 };
1087
1088 static struct clk_rcg2 ufs_axi_clk_src = {
1089         .cmd_rcgr = 0x75018,
1090         .mnd_width = 8,
1091         .hid_width = 5,
1092         .parent_map = gcc_parent_map_0,
1093         .freq_tbl = ftbl_ufs_axi_clk_src,
1094         .clkr.hw.init = &(struct clk_init_data){
1095                 .name = "ufs_axi_clk_src",
1096                 .parent_names = gcc_parent_names_0,
1097                 .num_parents = 4,
1098                 .ops = &clk_rcg2_ops,
1099         },
1100 };
1101
1102 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1103         F(19200000, P_XO, 1, 0, 0),
1104         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1105         F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1106         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1107         { }
1108 };
1109
1110 static struct clk_rcg2 usb30_master_clk_src = {
1111         .cmd_rcgr = 0xf014,
1112         .mnd_width = 8,
1113         .hid_width = 5,
1114         .parent_map = gcc_parent_map_0,
1115         .freq_tbl = ftbl_usb30_master_clk_src,
1116         .clkr.hw.init = &(struct clk_init_data){
1117                 .name = "usb30_master_clk_src",
1118                 .parent_names = gcc_parent_names_0,
1119                 .num_parents = 4,
1120                 .ops = &clk_rcg2_ops,
1121         },
1122 };
1123
1124 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1125         .cmd_rcgr = 0xf028,
1126         .mnd_width = 0,
1127         .hid_width = 5,
1128         .parent_map = gcc_parent_map_0,
1129         .freq_tbl = ftbl_hmss_rbcpr_clk_src,
1130         .clkr.hw.init = &(struct clk_init_data){
1131                 .name = "usb30_mock_utmi_clk_src",
1132                 .parent_names = gcc_parent_names_0,
1133                 .num_parents = 4,
1134                 .ops = &clk_rcg2_ops,
1135         },
1136 };
1137
1138 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1139         F(1200000, P_XO, 16, 0, 0),
1140         { }
1141 };
1142
1143 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1144         .cmd_rcgr = 0x5000c,
1145         .mnd_width = 0,
1146         .hid_width = 5,
1147         .parent_map = gcc_parent_map_3,
1148         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1149         .clkr.hw.init = &(struct clk_init_data){
1150                 .name = "usb3_phy_aux_clk_src",
1151                 .parent_names = gcc_parent_names_3,
1152                 .num_parents = 3,
1153                 .ops = &clk_rcg2_ops,
1154         },
1155 };
1156
1157 static struct clk_branch gcc_aggre1_noc_xo_clk = {
1158         .halt_reg = 0x8202c,
1159         .halt_check = BRANCH_HALT,
1160         .clkr = {
1161                 .enable_reg = 0x8202c,
1162                 .enable_mask = BIT(0),
1163                 .hw.init = &(struct clk_init_data){
1164                         .name = "gcc_aggre1_noc_xo_clk",
1165                         .ops = &clk_branch2_ops,
1166                 },
1167         },
1168 };
1169
1170 static struct clk_branch gcc_aggre1_ufs_axi_clk = {
1171         .halt_reg = 0x82028,
1172         .halt_check = BRANCH_HALT,
1173         .clkr = {
1174                 .enable_reg = 0x82028,
1175                 .enable_mask = BIT(0),
1176                 .hw.init = &(struct clk_init_data){
1177                         .name = "gcc_aggre1_ufs_axi_clk",
1178                         .parent_names = (const char *[]){
1179                                 "ufs_axi_clk_src",
1180                         },
1181                         .num_parents = 1,
1182                         .ops = &clk_branch2_ops,
1183                 },
1184         },
1185 };
1186
1187 static struct clk_branch gcc_aggre1_usb3_axi_clk = {
1188         .halt_reg = 0x82024,
1189         .halt_check = BRANCH_HALT,
1190         .clkr = {
1191                 .enable_reg = 0x82024,
1192                 .enable_mask = BIT(0),
1193                 .hw.init = &(struct clk_init_data){
1194                         .name = "gcc_aggre1_usb3_axi_clk",
1195                         .parent_names = (const char *[]){
1196                                 "usb30_master_clk_src",
1197                         },
1198                         .num_parents = 1,
1199                         .ops = &clk_branch2_ops,
1200                 },
1201         },
1202 };
1203
1204 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
1205         .halt_reg = 0x48090,
1206         .halt_check = BRANCH_HALT,
1207         .clkr = {
1208                 .enable_reg = 0x48090,
1209                 .enable_mask = BIT(0),
1210                 .hw.init = &(struct clk_init_data){
1211                         .name = "gcc_apss_qdss_tsctr_div2_clk",
1212                         .ops = &clk_branch2_ops,
1213                 },
1214         },
1215 };
1216
1217 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
1218         .halt_reg = 0x48094,
1219         .halt_check = BRANCH_HALT,
1220         .clkr = {
1221                 .enable_reg = 0x48094,
1222                 .enable_mask = BIT(0),
1223                 .hw.init = &(struct clk_init_data){
1224                         .name = "gcc_apss_qdss_tsctr_div8_clk",
1225                         .ops = &clk_branch2_ops,
1226                 },
1227         },
1228 };
1229
1230 static struct clk_branch gcc_bimc_hmss_axi_clk = {
1231         .halt_reg = 0x48004,
1232         .halt_check = BRANCH_HALT_VOTED,
1233         .clkr = {
1234                 .enable_reg = 0x52004,
1235                 .enable_mask = BIT(22),
1236                 .hw.init = &(struct clk_init_data){
1237                         .name = "gcc_bimc_hmss_axi_clk",
1238                         .ops = &clk_branch2_ops,
1239                 },
1240         },
1241 };
1242
1243 static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1244         .halt_reg = 0x4401c,
1245         .halt_check = BRANCH_HALT,
1246         .clkr = {
1247                 .enable_reg = 0x4401c,
1248                 .enable_mask = BIT(0),
1249                 .hw.init = &(struct clk_init_data){
1250                         .name = "gcc_bimc_mss_q6_axi_clk",
1251                         .ops = &clk_branch2_ops,
1252                 },
1253         },
1254 };
1255
1256 static struct clk_branch gcc_blsp1_ahb_clk = {
1257         .halt_reg = 0x17004,
1258         .halt_check = BRANCH_HALT_VOTED,
1259         .clkr = {
1260                 .enable_reg = 0x52004,
1261                 .enable_mask = BIT(17),
1262                 .hw.init = &(struct clk_init_data){
1263                         .name = "gcc_blsp1_ahb_clk",
1264                         .ops = &clk_branch2_ops,
1265                 },
1266         },
1267 };
1268
1269 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1270         .halt_reg = 0x19008,
1271         .halt_check = BRANCH_HALT,
1272         .clkr = {
1273                 .enable_reg = 0x19008,
1274                 .enable_mask = BIT(0),
1275                 .hw.init = &(struct clk_init_data){
1276                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1277                         .parent_names = (const char *[]){
1278                                 "blsp1_qup1_i2c_apps_clk_src",
1279                         },
1280                         .num_parents = 1,
1281                         .ops = &clk_branch2_ops,
1282                 },
1283         },
1284 };
1285
1286 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1287         .halt_reg = 0x19004,
1288         .halt_check = BRANCH_HALT,
1289         .clkr = {
1290                 .enable_reg = 0x19004,
1291                 .enable_mask = BIT(0),
1292                 .hw.init = &(struct clk_init_data){
1293                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1294                         .parent_names = (const char *[]){
1295                                 "blsp1_qup1_spi_apps_clk_src",
1296                         },
1297                         .num_parents = 1,
1298                         .ops = &clk_branch2_ops,
1299                 },
1300         },
1301 };
1302
1303 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1304         .halt_reg = 0x1b008,
1305         .halt_check = BRANCH_HALT,
1306         .clkr = {
1307                 .enable_reg = 0x1b008,
1308                 .enable_mask = BIT(0),
1309                 .hw.init = &(struct clk_init_data){
1310                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1311                         .parent_names = (const char *[]){
1312                                 "blsp1_qup2_i2c_apps_clk_src",
1313                         },
1314                         .num_parents = 1,
1315                         .ops = &clk_branch2_ops,
1316                 },
1317         },
1318 };
1319
1320 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1321         .halt_reg = 0x1b004,
1322         .halt_check = BRANCH_HALT,
1323         .clkr = {
1324                 .enable_reg = 0x1b004,
1325                 .enable_mask = BIT(0),
1326                 .hw.init = &(struct clk_init_data){
1327                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1328                         .parent_names = (const char *[]){
1329                                 "blsp1_qup2_spi_apps_clk_src",
1330                         },
1331                         .num_parents = 1,
1332                         .ops = &clk_branch2_ops,
1333                 },
1334         },
1335 };
1336
1337 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1338         .halt_reg = 0x1d008,
1339         .halt_check = BRANCH_HALT,
1340         .clkr = {
1341                 .enable_reg = 0x1d008,
1342                 .enable_mask = BIT(0),
1343                 .hw.init = &(struct clk_init_data){
1344                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1345                         .parent_names = (const char *[]){
1346                                 "blsp1_qup3_i2c_apps_clk_src",
1347                         },
1348                         .num_parents = 1,
1349                         .ops = &clk_branch2_ops,
1350                 },
1351         },
1352 };
1353
1354 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1355         .halt_reg = 0x1d004,
1356         .halt_check = BRANCH_HALT,
1357         .clkr = {
1358                 .enable_reg = 0x1d004,
1359                 .enable_mask = BIT(0),
1360                 .hw.init = &(struct clk_init_data){
1361                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1362                         .parent_names = (const char *[]){
1363                                 "blsp1_qup3_spi_apps_clk_src",
1364                         },
1365                         .num_parents = 1,
1366                         .ops = &clk_branch2_ops,
1367                 },
1368         },
1369 };
1370
1371 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1372         .halt_reg = 0x1f008,
1373         .halt_check = BRANCH_HALT,
1374         .clkr = {
1375                 .enable_reg = 0x1f008,
1376                 .enable_mask = BIT(0),
1377                 .hw.init = &(struct clk_init_data){
1378                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1379                         .parent_names = (const char *[]){
1380                                 "blsp1_qup4_i2c_apps_clk_src",
1381                         },
1382                         .num_parents = 1,
1383                         .ops = &clk_branch2_ops,
1384                 },
1385         },
1386 };
1387
1388 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1389         .halt_reg = 0x1f004,
1390         .halt_check = BRANCH_HALT,
1391         .clkr = {
1392                 .enable_reg = 0x1f004,
1393                 .enable_mask = BIT(0),
1394                 .hw.init = &(struct clk_init_data){
1395                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1396                         .parent_names = (const char *[]){
1397                                 "blsp1_qup4_spi_apps_clk_src",
1398                         },
1399                         .num_parents = 1,
1400                         .ops = &clk_branch2_ops,
1401                 },
1402         },
1403 };
1404
1405 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1406         .halt_reg = 0x21008,
1407         .halt_check = BRANCH_HALT,
1408         .clkr = {
1409                 .enable_reg = 0x21008,
1410                 .enable_mask = BIT(0),
1411                 .hw.init = &(struct clk_init_data){
1412                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1413                         .parent_names = (const char *[]){
1414                                 "blsp1_qup5_i2c_apps_clk_src",
1415                         },
1416                         .num_parents = 1,
1417                         .ops = &clk_branch2_ops,
1418                 },
1419         },
1420 };
1421
1422 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1423         .halt_reg = 0x21004,
1424         .halt_check = BRANCH_HALT,
1425         .clkr = {
1426                 .enable_reg = 0x21004,
1427                 .enable_mask = BIT(0),
1428                 .hw.init = &(struct clk_init_data){
1429                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1430                         .parent_names = (const char *[]){
1431                                 "blsp1_qup5_spi_apps_clk_src",
1432                         },
1433                         .num_parents = 1,
1434                         .ops = &clk_branch2_ops,
1435                 },
1436         },
1437 };
1438
1439 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1440         .halt_reg = 0x23008,
1441         .halt_check = BRANCH_HALT,
1442         .clkr = {
1443                 .enable_reg = 0x23008,
1444                 .enable_mask = BIT(0),
1445                 .hw.init = &(struct clk_init_data){
1446                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1447                         .parent_names = (const char *[]){
1448                                 "blsp1_qup6_i2c_apps_clk_src",
1449                         },
1450                         .num_parents = 1,
1451                         .ops = &clk_branch2_ops,
1452                 },
1453         },
1454 };
1455
1456 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1457         .halt_reg = 0x23004,
1458         .halt_check = BRANCH_HALT,
1459         .clkr = {
1460                 .enable_reg = 0x23004,
1461                 .enable_mask = BIT(0),
1462                 .hw.init = &(struct clk_init_data){
1463                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1464                         .parent_names = (const char *[]){
1465                                 "blsp1_qup6_spi_apps_clk_src",
1466                         },
1467                         .num_parents = 1,
1468                         .ops = &clk_branch2_ops,
1469                 },
1470         },
1471 };
1472
1473 static struct clk_branch gcc_blsp1_sleep_clk = {
1474         .halt_reg = 0x17008,
1475         .halt_check = BRANCH_HALT_VOTED,
1476         .clkr = {
1477                 .enable_reg = 0x52004,
1478                 .enable_mask = BIT(16),
1479                 .hw.init = &(struct clk_init_data){
1480                         .name = "gcc_blsp1_sleep_clk",
1481                         .ops = &clk_branch2_ops,
1482                 },
1483         },
1484 };
1485
1486 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1487         .halt_reg = 0x1a004,
1488         .halt_check = BRANCH_HALT,
1489         .clkr = {
1490                 .enable_reg = 0x1a004,
1491                 .enable_mask = BIT(0),
1492                 .hw.init = &(struct clk_init_data){
1493                         .name = "gcc_blsp1_uart1_apps_clk",
1494                         .parent_names = (const char *[]){
1495                                 "blsp1_uart1_apps_clk_src",
1496                         },
1497                         .num_parents = 1,
1498                         .ops = &clk_branch2_ops,
1499                 },
1500         },
1501 };
1502
1503 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1504         .halt_reg = 0x1c004,
1505         .halt_check = BRANCH_HALT,
1506         .clkr = {
1507                 .enable_reg = 0x1c004,
1508                 .enable_mask = BIT(0),
1509                 .hw.init = &(struct clk_init_data){
1510                         .name = "gcc_blsp1_uart2_apps_clk",
1511                         .parent_names = (const char *[]){
1512                                 "blsp1_uart2_apps_clk_src",
1513                         },
1514                         .num_parents = 1,
1515                         .ops = &clk_branch2_ops,
1516                 },
1517         },
1518 };
1519
1520 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1521         .halt_reg = 0x1e004,
1522         .halt_check = BRANCH_HALT,
1523         .clkr = {
1524                 .enable_reg = 0x1e004,
1525                 .enable_mask = BIT(0),
1526                 .hw.init = &(struct clk_init_data){
1527                         .name = "gcc_blsp1_uart3_apps_clk",
1528                         .parent_names = (const char *[]){
1529                                 "blsp1_uart3_apps_clk_src",
1530                         },
1531                         .num_parents = 1,
1532                         .ops = &clk_branch2_ops,
1533                 },
1534         },
1535 };
1536
1537 static struct clk_branch gcc_blsp2_ahb_clk = {
1538         .halt_reg = 0x25004,
1539         .halt_check = BRANCH_HALT_VOTED,
1540         .clkr = {
1541                 .enable_reg = 0x52004,
1542                 .enable_mask = BIT(15),
1543                 .hw.init = &(struct clk_init_data){
1544                         .name = "gcc_blsp2_ahb_clk",
1545                         .ops = &clk_branch2_ops,
1546                 },
1547         },
1548 };
1549
1550 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1551         .halt_reg = 0x26008,
1552         .halt_check = BRANCH_HALT,
1553         .clkr = {
1554                 .enable_reg = 0x26008,
1555                 .enable_mask = BIT(0),
1556                 .hw.init = &(struct clk_init_data){
1557                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1558                         .parent_names = (const char *[]){
1559                                 "blsp2_qup1_i2c_apps_clk_src",
1560                         },
1561                         .num_parents = 1,
1562                         .ops = &clk_branch2_ops,
1563                 },
1564         },
1565 };
1566
1567 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1568         .halt_reg = 0x26004,
1569         .halt_check = BRANCH_HALT,
1570         .clkr = {
1571                 .enable_reg = 0x26004,
1572                 .enable_mask = BIT(0),
1573                 .hw.init = &(struct clk_init_data){
1574                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1575                         .parent_names = (const char *[]){
1576                                 "blsp2_qup1_spi_apps_clk_src",
1577                         },
1578                         .num_parents = 1,
1579                         .ops = &clk_branch2_ops,
1580                 },
1581         },
1582 };
1583
1584 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1585         .halt_reg = 0x28008,
1586         .halt_check = BRANCH_HALT,
1587         .clkr = {
1588                 .enable_reg = 0x28008,
1589                 .enable_mask = BIT(0),
1590                 .hw.init = &(struct clk_init_data){
1591                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1592                         .parent_names = (const char *[]){
1593                                 "blsp2_qup2_i2c_apps_clk_src",
1594                         },
1595                         .num_parents = 1,
1596                         .ops = &clk_branch2_ops,
1597                 },
1598         },
1599 };
1600
1601 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1602         .halt_reg = 0x28004,
1603         .halt_check = BRANCH_HALT,
1604         .clkr = {
1605                 .enable_reg = 0x28004,
1606                 .enable_mask = BIT(0),
1607                 .hw.init = &(struct clk_init_data){
1608                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1609                         .parent_names = (const char *[]){
1610                                 "blsp2_qup2_spi_apps_clk_src",
1611                         },
1612                         .num_parents = 1,
1613                         .ops = &clk_branch2_ops,
1614                 },
1615         },
1616 };
1617
1618 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1619         .halt_reg = 0x2a008,
1620         .halt_check = BRANCH_HALT,
1621         .clkr = {
1622                 .enable_reg = 0x2a008,
1623                 .enable_mask = BIT(0),
1624                 .hw.init = &(struct clk_init_data){
1625                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1626                         .parent_names = (const char *[]){
1627                                 "blsp2_qup3_i2c_apps_clk_src",
1628                         },
1629                         .num_parents = 1,
1630                         .ops = &clk_branch2_ops,
1631                 },
1632         },
1633 };
1634
1635 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1636         .halt_reg = 0x2a004,
1637         .halt_check = BRANCH_HALT,
1638         .clkr = {
1639                 .enable_reg = 0x2a004,
1640                 .enable_mask = BIT(0),
1641                 .hw.init = &(struct clk_init_data){
1642                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1643                         .parent_names = (const char *[]){
1644                                 "blsp2_qup3_spi_apps_clk_src",
1645                         },
1646                         .num_parents = 1,
1647                         .ops = &clk_branch2_ops,
1648                 },
1649         },
1650 };
1651
1652 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1653         .halt_reg = 0x2c008,
1654         .halt_check = BRANCH_HALT,
1655         .clkr = {
1656                 .enable_reg = 0x2c008,
1657                 .enable_mask = BIT(0),
1658                 .hw.init = &(struct clk_init_data){
1659                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1660                         .parent_names = (const char *[]){
1661                                 "blsp2_qup4_i2c_apps_clk_src",
1662                         },
1663                         .num_parents = 1,
1664                         .ops = &clk_branch2_ops,
1665                 },
1666         },
1667 };
1668
1669 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1670         .halt_reg = 0x2c004,
1671         .halt_check = BRANCH_HALT,
1672         .clkr = {
1673                 .enable_reg = 0x2c004,
1674                 .enable_mask = BIT(0),
1675                 .hw.init = &(struct clk_init_data){
1676                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1677                         .parent_names = (const char *[]){
1678                                 "blsp2_qup4_spi_apps_clk_src",
1679                         },
1680                         .num_parents = 1,
1681                         .ops = &clk_branch2_ops,
1682                 },
1683         },
1684 };
1685
1686 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1687         .halt_reg = 0x2e008,
1688         .halt_check = BRANCH_HALT,
1689         .clkr = {
1690                 .enable_reg = 0x2e008,
1691                 .enable_mask = BIT(0),
1692                 .hw.init = &(struct clk_init_data){
1693                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1694                         .parent_names = (const char *[]){
1695                                 "blsp2_qup5_i2c_apps_clk_src",
1696                         },
1697                         .num_parents = 1,
1698                         .ops = &clk_branch2_ops,
1699                 },
1700         },
1701 };
1702
1703 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1704         .halt_reg = 0x2e004,
1705         .halt_check = BRANCH_HALT,
1706         .clkr = {
1707                 .enable_reg = 0x2e004,
1708                 .enable_mask = BIT(0),
1709                 .hw.init = &(struct clk_init_data){
1710                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1711                         .parent_names = (const char *[]){
1712                                 "blsp2_qup5_spi_apps_clk_src",
1713                         },
1714                         .num_parents = 1,
1715                         .ops = &clk_branch2_ops,
1716                 },
1717         },
1718 };
1719
1720 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1721         .halt_reg = 0x30008,
1722         .halt_check = BRANCH_HALT,
1723         .clkr = {
1724                 .enable_reg = 0x30008,
1725                 .enable_mask = BIT(0),
1726                 .hw.init = &(struct clk_init_data){
1727                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1728                         .parent_names = (const char *[]){
1729                                 "blsp2_qup6_i2c_apps_clk_src",
1730                         },
1731                         .num_parents = 1,
1732                         .ops = &clk_branch2_ops,
1733                 },
1734         },
1735 };
1736
1737 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1738         .halt_reg = 0x30004,
1739         .halt_check = BRANCH_HALT,
1740         .clkr = {
1741                 .enable_reg = 0x30004,
1742                 .enable_mask = BIT(0),
1743                 .hw.init = &(struct clk_init_data){
1744                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1745                         .parent_names = (const char *[]){
1746                                 "blsp2_qup6_spi_apps_clk_src",
1747                         },
1748                         .num_parents = 1,
1749                         .ops = &clk_branch2_ops,
1750                 },
1751         },
1752 };
1753
1754 static struct clk_branch gcc_blsp2_sleep_clk = {
1755         .halt_reg = 0x25008,
1756         .halt_check = BRANCH_HALT_VOTED,
1757         .clkr = {
1758                 .enable_reg = 0x52004,
1759                 .enable_mask = BIT(14),
1760                 .hw.init = &(struct clk_init_data){
1761                         .name = "gcc_blsp2_sleep_clk",
1762                         .ops = &clk_branch2_ops,
1763                 },
1764         },
1765 };
1766
1767 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1768         .halt_reg = 0x27004,
1769         .halt_check = BRANCH_HALT,
1770         .clkr = {
1771                 .enable_reg = 0x27004,
1772                 .enable_mask = BIT(0),
1773                 .hw.init = &(struct clk_init_data){
1774                         .name = "gcc_blsp2_uart1_apps_clk",
1775                         .parent_names = (const char *[]){
1776                                 "blsp2_uart1_apps_clk_src",
1777                         },
1778                         .num_parents = 1,
1779                         .ops = &clk_branch2_ops,
1780                 },
1781         },
1782 };
1783
1784 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1785         .halt_reg = 0x29004,
1786         .halt_check = BRANCH_HALT,
1787         .clkr = {
1788                 .enable_reg = 0x29004,
1789                 .enable_mask = BIT(0),
1790                 .hw.init = &(struct clk_init_data){
1791                         .name = "gcc_blsp2_uart2_apps_clk",
1792                         .parent_names = (const char *[]){
1793                                 "blsp2_uart2_apps_clk_src",
1794                         },
1795                         .num_parents = 1,
1796                         .ops = &clk_branch2_ops,
1797                 },
1798         },
1799 };
1800
1801 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1802         .halt_reg = 0x2b004,
1803         .halt_check = BRANCH_HALT,
1804         .clkr = {
1805                 .enable_reg = 0x2b004,
1806                 .enable_mask = BIT(0),
1807                 .hw.init = &(struct clk_init_data){
1808                         .name = "gcc_blsp2_uart3_apps_clk",
1809                         .parent_names = (const char *[]){
1810                                 "blsp2_uart3_apps_clk_src",
1811                         },
1812                         .num_parents = 1,
1813                         .ops = &clk_branch2_ops,
1814                 },
1815         },
1816 };
1817
1818 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1819         .halt_reg = 0x5018,
1820         .halt_check = BRANCH_HALT,
1821         .clkr = {
1822                 .enable_reg = 0x5018,
1823                 .enable_mask = BIT(0),
1824                 .hw.init = &(struct clk_init_data){
1825                         .name = "gcc_cfg_noc_usb3_axi_clk",
1826                         .parent_names = (const char *[]){
1827                                 "usb30_master_clk_src",
1828                         },
1829                         .num_parents = 1,
1830                         .ops = &clk_branch2_ops,
1831                 },
1832         },
1833 };
1834
1835 static struct clk_branch gcc_gp1_clk = {
1836         .halt_reg = 0x64000,
1837         .halt_check = BRANCH_HALT,
1838         .clkr = {
1839                 .enable_reg = 0x64000,
1840                 .enable_mask = BIT(0),
1841                 .hw.init = &(struct clk_init_data){
1842                         .name = "gcc_gp1_clk",
1843                         .parent_names = (const char *[]){
1844                                 "gp1_clk_src",
1845                         },
1846                         .num_parents = 1,
1847                         .ops = &clk_branch2_ops,
1848                 },
1849         },
1850 };
1851
1852 static struct clk_branch gcc_gp2_clk = {
1853         .halt_reg = 0x65000,
1854         .halt_check = BRANCH_HALT,
1855         .clkr = {
1856                 .enable_reg = 0x65000,
1857                 .enable_mask = BIT(0),
1858                 .hw.init = &(struct clk_init_data){
1859                         .name = "gcc_gp2_clk",
1860                         .parent_names = (const char *[]){
1861                                 "gp2_clk_src",
1862                         },
1863                         .num_parents = 1,
1864                         .ops = &clk_branch2_ops,
1865                 },
1866         },
1867 };
1868
1869 static struct clk_branch gcc_gp3_clk = {
1870         .halt_reg = 0x66000,
1871         .halt_check = BRANCH_HALT,
1872         .clkr = {
1873                 .enable_reg = 0x66000,
1874                 .enable_mask = BIT(0),
1875                 .hw.init = &(struct clk_init_data){
1876                         .name = "gcc_gp3_clk",
1877                         .parent_names = (const char *[]){
1878                                 "gp3_clk_src",
1879                         },
1880                         .num_parents = 1,
1881                         .ops = &clk_branch2_ops,
1882                 },
1883         },
1884 };
1885
1886 static struct clk_branch gcc_gpu_bimc_gfx_clk = {
1887         .halt_reg = 0x71010,
1888         .halt_check = BRANCH_HALT,
1889         .clkr = {
1890                 .enable_reg = 0x71010,
1891                 .enable_mask = BIT(0),
1892                 .hw.init = &(struct clk_init_data){
1893                         .name = "gcc_gpu_bimc_gfx_clk",
1894                         .ops = &clk_branch2_ops,
1895                 },
1896         },
1897 };
1898
1899 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
1900         .halt_reg = 0x7100c,
1901         .halt_check = BRANCH_HALT,
1902         .clkr = {
1903                 .enable_reg = 0x7100c,
1904                 .enable_mask = BIT(0),
1905                 .hw.init = &(struct clk_init_data){
1906                         .name = "gcc_gpu_bimc_gfx_src_clk",
1907                         .ops = &clk_branch2_ops,
1908                 },
1909         },
1910 };
1911
1912 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1913         .halt_reg = 0x71004,
1914         .halt_check = BRANCH_HALT,
1915         .clkr = {
1916                 .enable_reg = 0x71004,
1917                 .enable_mask = BIT(0),
1918                 .hw.init = &(struct clk_init_data){
1919                         .name = "gcc_gpu_cfg_ahb_clk",
1920                         .ops = &clk_branch2_ops,
1921                 },
1922         },
1923 };
1924
1925 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1926         .halt_reg = 0x71018,
1927         .halt_check = BRANCH_HALT,
1928         .clkr = {
1929                 .enable_reg = 0x71018,
1930                 .enable_mask = BIT(0),
1931                 .hw.init = &(struct clk_init_data){
1932                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1933                         .ops = &clk_branch2_ops,
1934                 },
1935         },
1936 };
1937
1938 static struct clk_branch gcc_hmss_ahb_clk = {
1939         .halt_reg = 0x48000,
1940         .halt_check = BRANCH_HALT_VOTED,
1941         .clkr = {
1942                 .enable_reg = 0x52004,
1943                 .enable_mask = BIT(21),
1944                 .hw.init = &(struct clk_init_data){
1945                         .name = "gcc_hmss_ahb_clk",
1946                         .parent_names = (const char *[]){
1947                                 "hmss_ahb_clk_src",
1948                         },
1949                         .num_parents = 1,
1950                         .ops = &clk_branch2_ops,
1951                 },
1952         },
1953 };
1954
1955 static struct clk_branch gcc_hmss_at_clk = {
1956         .halt_reg = 0x48010,
1957         .halt_check = BRANCH_HALT,
1958         .clkr = {
1959                 .enable_reg = 0x48010,
1960                 .enable_mask = BIT(0),
1961                 .hw.init = &(struct clk_init_data){
1962                         .name = "gcc_hmss_at_clk",
1963                         .ops = &clk_branch2_ops,
1964                 },
1965         },
1966 };
1967
1968 static struct clk_branch gcc_hmss_dvm_bus_clk = {
1969         .halt_reg = 0x4808c,
1970         .halt_check = BRANCH_HALT,
1971         .clkr = {
1972                 .enable_reg = 0x4808c,
1973                 .enable_mask = BIT(0),
1974                 .hw.init = &(struct clk_init_data){
1975                         .name = "gcc_hmss_dvm_bus_clk",
1976                         .ops = &clk_branch2_ops,
1977                 },
1978         },
1979 };
1980
1981 static struct clk_branch gcc_hmss_rbcpr_clk = {
1982         .halt_reg = 0x48008,
1983         .halt_check = BRANCH_HALT,
1984         .clkr = {
1985                 .enable_reg = 0x48008,
1986                 .enable_mask = BIT(0),
1987                 .hw.init = &(struct clk_init_data){
1988                         .name = "gcc_hmss_rbcpr_clk",
1989                         .parent_names = (const char *[]){
1990                                 "hmss_rbcpr_clk_src",
1991                         },
1992                         .num_parents = 1,
1993                         .ops = &clk_branch2_ops,
1994                 },
1995         },
1996 };
1997
1998 static struct clk_branch gcc_hmss_trig_clk = {
1999         .halt_reg = 0x4800c,
2000         .halt_check = BRANCH_HALT,
2001         .clkr = {
2002                 .enable_reg = 0x4800c,
2003                 .enable_mask = BIT(0),
2004                 .hw.init = &(struct clk_init_data){
2005                         .name = "gcc_hmss_trig_clk",
2006                         .ops = &clk_branch2_ops,
2007                 },
2008         },
2009 };
2010
2011 static struct clk_branch gcc_lpass_at_clk = {
2012         .halt_reg = 0x47020,
2013         .halt_check = BRANCH_HALT,
2014         .clkr = {
2015                 .enable_reg = 0x47020,
2016                 .enable_mask = BIT(0),
2017                 .hw.init = &(struct clk_init_data){
2018                         .name = "gcc_lpass_at_clk",
2019                         .ops = &clk_branch2_ops,
2020                 },
2021         },
2022 };
2023
2024 static struct clk_branch gcc_lpass_trig_clk = {
2025         .halt_reg = 0x4701c,
2026         .halt_check = BRANCH_HALT,
2027         .clkr = {
2028                 .enable_reg = 0x4701c,
2029                 .enable_mask = BIT(0),
2030                 .hw.init = &(struct clk_init_data){
2031                         .name = "gcc_lpass_trig_clk",
2032                         .ops = &clk_branch2_ops,
2033                 },
2034         },
2035 };
2036
2037 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
2038         .halt_reg = 0x9004,
2039         .halt_check = BRANCH_HALT,
2040         .clkr = {
2041                 .enable_reg = 0x9004,
2042                 .enable_mask = BIT(0),
2043                 .hw.init = &(struct clk_init_data){
2044                         .name = "gcc_mmss_noc_cfg_ahb_clk",
2045                         .ops = &clk_branch2_ops,
2046                 },
2047         },
2048 };
2049
2050 static struct clk_branch gcc_mmss_qm_ahb_clk = {
2051         .halt_reg = 0x9030,
2052         .halt_check = BRANCH_HALT,
2053         .clkr = {
2054                 .enable_reg = 0x9030,
2055                 .enable_mask = BIT(0),
2056                 .hw.init = &(struct clk_init_data){
2057                         .name = "gcc_mmss_qm_ahb_clk",
2058                         .ops = &clk_branch2_ops,
2059                 },
2060         },
2061 };
2062
2063 static struct clk_branch gcc_mmss_qm_core_clk = {
2064         .halt_reg = 0x900c,
2065         .halt_check = BRANCH_HALT,
2066         .clkr = {
2067                 .enable_reg = 0x900c,
2068                 .enable_mask = BIT(0),
2069                 .hw.init = &(struct clk_init_data){
2070                         .name = "gcc_mmss_qm_core_clk",
2071                         .ops = &clk_branch2_ops,
2072                 },
2073         },
2074 };
2075
2076 static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
2077         .halt_reg = 0x9000,
2078         .halt_check = BRANCH_HALT,
2079         .clkr = {
2080                 .enable_reg = 0x9000,
2081                 .enable_mask = BIT(0),
2082                 .hw.init = &(struct clk_init_data){
2083                         .name = "gcc_mmss_sys_noc_axi_clk",
2084                         .ops = &clk_branch2_ops,
2085                 },
2086         },
2087 };
2088
2089 static struct clk_branch gcc_mss_at_clk = {
2090         .halt_reg = 0x8a00c,
2091         .halt_check = BRANCH_HALT,
2092         .clkr = {
2093                 .enable_reg = 0x8a00c,
2094                 .enable_mask = BIT(0),
2095                 .hw.init = &(struct clk_init_data){
2096                         .name = "gcc_mss_at_clk",
2097                         .ops = &clk_branch2_ops,
2098                 },
2099         },
2100 };
2101
2102 static struct clk_branch gcc_pcie_0_aux_clk = {
2103         .halt_reg = 0x6b014,
2104         .halt_check = BRANCH_HALT,
2105         .clkr = {
2106                 .enable_reg = 0x6b014,
2107                 .enable_mask = BIT(0),
2108                 .hw.init = &(struct clk_init_data){
2109                         .name = "gcc_pcie_0_aux_clk",
2110                         .parent_names = (const char *[]){
2111                                 "pcie_aux_clk_src",
2112                         },
2113                         .num_parents = 1,
2114                         .ops = &clk_branch2_ops,
2115                 },
2116         },
2117 };
2118
2119 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2120         .halt_reg = 0x6b010,
2121         .halt_check = BRANCH_HALT,
2122         .clkr = {
2123                 .enable_reg = 0x6b010,
2124                 .enable_mask = BIT(0),
2125                 .hw.init = &(struct clk_init_data){
2126                         .name = "gcc_pcie_0_cfg_ahb_clk",
2127                         .ops = &clk_branch2_ops,
2128                 },
2129         },
2130 };
2131
2132 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2133         .halt_reg = 0x6b00c,
2134         .halt_check = BRANCH_HALT,
2135         .clkr = {
2136                 .enable_reg = 0x6b00c,
2137                 .enable_mask = BIT(0),
2138                 .hw.init = &(struct clk_init_data){
2139                         .name = "gcc_pcie_0_mstr_axi_clk",
2140                         .ops = &clk_branch2_ops,
2141                 },
2142         },
2143 };
2144
2145 static struct clk_branch gcc_pcie_0_pipe_clk = {
2146         .halt_reg = 0x6b018,
2147         .halt_check = BRANCH_HALT_SKIP,
2148         .clkr = {
2149                 .enable_reg = 0x6b018,
2150                 .enable_mask = BIT(0),
2151                 .hw.init = &(struct clk_init_data){
2152                         .name = "gcc_pcie_0_pipe_clk",
2153                         .ops = &clk_branch2_ops,
2154                 },
2155         },
2156 };
2157
2158 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2159         .halt_reg = 0x6b008,
2160         .halt_check = BRANCH_HALT,
2161         .clkr = {
2162                 .enable_reg = 0x6b008,
2163                 .enable_mask = BIT(0),
2164                 .hw.init = &(struct clk_init_data){
2165                         .name = "gcc_pcie_0_slv_axi_clk",
2166                         .ops = &clk_branch2_ops,
2167                 },
2168         },
2169 };
2170
2171 static struct clk_branch gcc_pcie_phy_aux_clk = {
2172         .halt_reg = 0x6f004,
2173         .halt_check = BRANCH_HALT,
2174         .clkr = {
2175                 .enable_reg = 0x6f004,
2176                 .enable_mask = BIT(0),
2177                 .hw.init = &(struct clk_init_data){
2178                         .name = "gcc_pcie_phy_aux_clk",
2179                         .parent_names = (const char *[]){
2180                                 "pcie_aux_clk_src",
2181                         },
2182                         .num_parents = 1,
2183                         .ops = &clk_branch2_ops,
2184                 },
2185         },
2186 };
2187
2188 static struct clk_branch gcc_pdm2_clk = {
2189         .halt_reg = 0x3300c,
2190         .halt_check = BRANCH_HALT,
2191         .clkr = {
2192                 .enable_reg = 0x3300c,
2193                 .enable_mask = BIT(0),
2194                 .hw.init = &(struct clk_init_data){
2195                         .name = "gcc_pdm2_clk",
2196                         .parent_names = (const char *[]){
2197                                 "pdm2_clk_src",
2198                         },
2199                         .num_parents = 1,
2200                         .ops = &clk_branch2_ops,
2201                 },
2202         },
2203 };
2204
2205 static struct clk_branch gcc_pdm_ahb_clk = {
2206         .halt_reg = 0x33004,
2207         .halt_check = BRANCH_HALT,
2208         .clkr = {
2209                 .enable_reg = 0x33004,
2210                 .enable_mask = BIT(0),
2211                 .hw.init = &(struct clk_init_data){
2212                         .name = "gcc_pdm_ahb_clk",
2213                         .ops = &clk_branch2_ops,
2214                 },
2215         },
2216 };
2217
2218 static struct clk_branch gcc_pdm_xo4_clk = {
2219         .halt_reg = 0x33008,
2220         .halt_check = BRANCH_HALT,
2221         .clkr = {
2222                 .enable_reg = 0x33008,
2223                 .enable_mask = BIT(0),
2224                 .hw.init = &(struct clk_init_data){
2225                         .name = "gcc_pdm_xo4_clk",
2226                         .ops = &clk_branch2_ops,
2227                 },
2228         },
2229 };
2230
2231 static struct clk_branch gcc_prng_ahb_clk = {
2232         .halt_reg = 0x34004,
2233         .halt_check = BRANCH_HALT_VOTED,
2234         .clkr = {
2235                 .enable_reg = 0x52004,
2236                 .enable_mask = BIT(13),
2237                 .hw.init = &(struct clk_init_data){
2238                         .name = "gcc_prng_ahb_clk",
2239                         .ops = &clk_branch2_ops,
2240                 },
2241         },
2242 };
2243
2244 static struct clk_branch gcc_sdcc2_ahb_clk = {
2245         .halt_reg = 0x14008,
2246         .halt_check = BRANCH_HALT,
2247         .clkr = {
2248                 .enable_reg = 0x14008,
2249                 .enable_mask = BIT(0),
2250                 .hw.init = &(struct clk_init_data){
2251                         .name = "gcc_sdcc2_ahb_clk",
2252                         .ops = &clk_branch2_ops,
2253                 },
2254         },
2255 };
2256
2257 static struct clk_branch gcc_sdcc2_apps_clk = {
2258         .halt_reg = 0x14004,
2259         .halt_check = BRANCH_HALT,
2260         .clkr = {
2261                 .enable_reg = 0x14004,
2262                 .enable_mask = BIT(0),
2263                 .hw.init = &(struct clk_init_data){
2264                         .name = "gcc_sdcc2_apps_clk",
2265                         .parent_names = (const char *[]){
2266                                 "sdcc2_apps_clk_src",
2267                         },
2268                         .num_parents = 1,
2269                         .ops = &clk_branch2_ops,
2270                 },
2271         },
2272 };
2273
2274 static struct clk_branch gcc_sdcc4_ahb_clk = {
2275         .halt_reg = 0x16008,
2276         .halt_check = BRANCH_HALT,
2277         .clkr = {
2278                 .enable_reg = 0x16008,
2279                 .enable_mask = BIT(0),
2280                 .hw.init = &(struct clk_init_data){
2281                         .name = "gcc_sdcc4_ahb_clk",
2282                         .ops = &clk_branch2_ops,
2283                 },
2284         },
2285 };
2286
2287 static struct clk_branch gcc_sdcc4_apps_clk = {
2288         .halt_reg = 0x16004,
2289         .halt_check = BRANCH_HALT,
2290         .clkr = {
2291                 .enable_reg = 0x16004,
2292                 .enable_mask = BIT(0),
2293                 .hw.init = &(struct clk_init_data){
2294                         .name = "gcc_sdcc4_apps_clk",
2295                         .parent_names = (const char *[]){
2296                                 "sdcc4_apps_clk_src",
2297                         },
2298                         .num_parents = 1,
2299                         .ops = &clk_branch2_ops,
2300                 },
2301         },
2302 };
2303
2304 static struct clk_branch gcc_tsif_ahb_clk = {
2305         .halt_reg = 0x36004,
2306         .halt_check = BRANCH_HALT,
2307         .clkr = {
2308                 .enable_reg = 0x36004,
2309                 .enable_mask = BIT(0),
2310                 .hw.init = &(struct clk_init_data){
2311                         .name = "gcc_tsif_ahb_clk",
2312                         .ops = &clk_branch2_ops,
2313                 },
2314         },
2315 };
2316
2317 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2318         .halt_reg = 0x3600c,
2319         .halt_check = BRANCH_HALT,
2320         .clkr = {
2321                 .enable_reg = 0x3600c,
2322                 .enable_mask = BIT(0),
2323                 .hw.init = &(struct clk_init_data){
2324                         .name = "gcc_tsif_inactivity_timers_clk",
2325                         .ops = &clk_branch2_ops,
2326                 },
2327         },
2328 };
2329
2330 static struct clk_branch gcc_tsif_ref_clk = {
2331         .halt_reg = 0x36008,
2332         .halt_check = BRANCH_HALT,
2333         .clkr = {
2334                 .enable_reg = 0x36008,
2335                 .enable_mask = BIT(0),
2336                 .hw.init = &(struct clk_init_data){
2337                         .name = "gcc_tsif_ref_clk",
2338                         .parent_names = (const char *[]){
2339                                 "tsif_ref_clk_src",
2340                         },
2341                         .num_parents = 1,
2342                         .ops = &clk_branch2_ops,
2343                 },
2344         },
2345 };
2346
2347 static struct clk_branch gcc_ufs_ahb_clk = {
2348         .halt_reg = 0x7500c,
2349         .halt_check = BRANCH_HALT,
2350         .clkr = {
2351                 .enable_reg = 0x7500c,
2352                 .enable_mask = BIT(0),
2353                 .hw.init = &(struct clk_init_data){
2354                         .name = "gcc_ufs_ahb_clk",
2355                         .ops = &clk_branch2_ops,
2356                 },
2357         },
2358 };
2359
2360 static struct clk_branch gcc_ufs_axi_clk = {
2361         .halt_reg = 0x75008,
2362         .halt_check = BRANCH_HALT,
2363         .clkr = {
2364                 .enable_reg = 0x75008,
2365                 .enable_mask = BIT(0),
2366                 .hw.init = &(struct clk_init_data){
2367                         .name = "gcc_ufs_axi_clk",
2368                         .parent_names = (const char *[]){
2369                                 "ufs_axi_clk_src",
2370                         },
2371                         .num_parents = 1,
2372                         .ops = &clk_branch2_ops,
2373                 },
2374         },
2375 };
2376
2377 static struct clk_branch gcc_ufs_ice_core_clk = {
2378         .halt_reg = 0x7600c,
2379         .halt_check = BRANCH_HALT,
2380         .clkr = {
2381                 .enable_reg = 0x7600c,
2382                 .enable_mask = BIT(0),
2383                 .hw.init = &(struct clk_init_data){
2384                         .name = "gcc_ufs_ice_core_clk",
2385                         .ops = &clk_branch2_ops,
2386                 },
2387         },
2388 };
2389
2390 static struct clk_branch gcc_ufs_phy_aux_clk = {
2391         .halt_reg = 0x76040,
2392         .halt_check = BRANCH_HALT,
2393         .clkr = {
2394                 .enable_reg = 0x76040,
2395                 .enable_mask = BIT(0),
2396                 .hw.init = &(struct clk_init_data){
2397                         .name = "gcc_ufs_phy_aux_clk",
2398                         .ops = &clk_branch2_ops,
2399                 },
2400         },
2401 };
2402
2403 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2404         .halt_reg = 0x75014,
2405         .halt_check = BRANCH_HALT_SKIP,
2406         .clkr = {
2407                 .enable_reg = 0x75014,
2408                 .enable_mask = BIT(0),
2409                 .hw.init = &(struct clk_init_data){
2410                         .name = "gcc_ufs_rx_symbol_0_clk",
2411                         .ops = &clk_branch2_ops,
2412                 },
2413         },
2414 };
2415
2416 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2417         .halt_reg = 0x7605c,
2418         .halt_check = BRANCH_HALT_SKIP,
2419         .clkr = {
2420                 .enable_reg = 0x7605c,
2421                 .enable_mask = BIT(0),
2422                 .hw.init = &(struct clk_init_data){
2423                         .name = "gcc_ufs_rx_symbol_1_clk",
2424                         .ops = &clk_branch2_ops,
2425                 },
2426         },
2427 };
2428
2429 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2430         .halt_reg = 0x75010,
2431         .halt_check = BRANCH_HALT_SKIP,
2432         .clkr = {
2433                 .enable_reg = 0x75010,
2434                 .enable_mask = BIT(0),
2435                 .hw.init = &(struct clk_init_data){
2436                         .name = "gcc_ufs_tx_symbol_0_clk",
2437                         .ops = &clk_branch2_ops,
2438                 },
2439         },
2440 };
2441
2442 static struct clk_branch gcc_ufs_unipro_core_clk = {
2443         .halt_reg = 0x76008,
2444         .halt_check = BRANCH_HALT,
2445         .clkr = {
2446                 .enable_reg = 0x76008,
2447                 .enable_mask = BIT(0),
2448                 .hw.init = &(struct clk_init_data){
2449                         .name = "gcc_ufs_unipro_core_clk",
2450                         .ops = &clk_branch2_ops,
2451                 },
2452         },
2453 };
2454
2455 static struct clk_branch gcc_usb30_master_clk = {
2456         .halt_reg = 0xf008,
2457         .halt_check = BRANCH_HALT,
2458         .clkr = {
2459                 .enable_reg = 0xf008,
2460                 .enable_mask = BIT(0),
2461                 .hw.init = &(struct clk_init_data){
2462                         .name = "gcc_usb30_master_clk",
2463                         .parent_names = (const char *[]){
2464                                 "usb30_master_clk_src",
2465                         },
2466                         .num_parents = 1,
2467                         .ops = &clk_branch2_ops,
2468                 },
2469         },
2470 };
2471
2472 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2473         .halt_reg = 0xf010,
2474         .halt_check = BRANCH_HALT,
2475         .clkr = {
2476                 .enable_reg = 0xf010,
2477                 .enable_mask = BIT(0),
2478                 .hw.init = &(struct clk_init_data){
2479                         .name = "gcc_usb30_mock_utmi_clk",
2480                         .parent_names = (const char *[]){
2481                                 "usb30_mock_utmi_clk_src",
2482                         },
2483                         .num_parents = 1,
2484                         .ops = &clk_branch2_ops,
2485                 },
2486         },
2487 };
2488
2489 static struct clk_branch gcc_usb30_sleep_clk = {
2490         .halt_reg = 0xf00c,
2491         .halt_check = BRANCH_HALT,
2492         .clkr = {
2493                 .enable_reg = 0xf00c,
2494                 .enable_mask = BIT(0),
2495                 .hw.init = &(struct clk_init_data){
2496                         .name = "gcc_usb30_sleep_clk",
2497                         .ops = &clk_branch2_ops,
2498                 },
2499         },
2500 };
2501
2502 static struct clk_branch gcc_usb3_phy_aux_clk = {
2503         .halt_reg = 0x50000,
2504         .halt_check = BRANCH_HALT,
2505         .clkr = {
2506                 .enable_reg = 0x50000,
2507                 .enable_mask = BIT(0),
2508                 .hw.init = &(struct clk_init_data){
2509                         .name = "gcc_usb3_phy_aux_clk",
2510                         .parent_names = (const char *[]){
2511                                 "usb3_phy_aux_clk_src",
2512                         },
2513                         .num_parents = 1,
2514                         .ops = &clk_branch2_ops,
2515                 },
2516         },
2517 };
2518
2519 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2520         .halt_reg = 0x50004,
2521         .halt_check = BRANCH_HALT,
2522         .clkr = {
2523                 .enable_reg = 0x50004,
2524                 .enable_mask = BIT(0),
2525                 .hw.init = &(struct clk_init_data){
2526                         .name = "gcc_usb3_phy_pipe_clk",
2527                         .ops = &clk_branch2_ops,
2528                 },
2529         },
2530 };
2531
2532 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2533         .halt_reg = 0x6a004,
2534         .halt_check = BRANCH_HALT,
2535         .clkr = {
2536                 .enable_reg = 0x6a004,
2537                 .enable_mask = BIT(0),
2538                 .hw.init = &(struct clk_init_data){
2539                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2540                         .ops = &clk_branch2_ops,
2541                 },
2542         },
2543 };
2544
2545 static struct gdsc pcie_0_gdsc = {
2546         .gdscr = 0x6b004,
2547         .gds_hw_ctrl = 0x0,
2548         .pd = {
2549                 .name = "pcie_0_gdsc",
2550         },
2551         .pwrsts = PWRSTS_OFF_ON,
2552         .flags = VOTABLE,
2553 };
2554
2555 static struct gdsc ufs_gdsc = {
2556         .gdscr = 0x75004,
2557         .gds_hw_ctrl = 0x0,
2558         .pd = {
2559                 .name = "ufs_gdsc",
2560         },
2561         .pwrsts = PWRSTS_OFF_ON,
2562         .flags = VOTABLE,
2563 };
2564
2565 static struct gdsc usb_30_gdsc = {
2566         .gdscr = 0xf004,
2567         .gds_hw_ctrl = 0x0,
2568         .pd = {
2569                 .name = "usb_30_gdsc",
2570         },
2571         .pwrsts = PWRSTS_OFF_ON,
2572         .flags = VOTABLE,
2573 };
2574
2575 static struct clk_regmap *gcc_msm8998_clocks[] = {
2576         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2577         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2578         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2579         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2580         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2581         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2582         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2583         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2584         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2585         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2586         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2587         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2588         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2589         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2590         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2591         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2592         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2593         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2594         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2595         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2596         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2597         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2598         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2599         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2600         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2601         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2602         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2603         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2604         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2605         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2606         [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
2607         [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
2608         [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
2609         [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
2610         [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
2611         [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2612         [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2613         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2614         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2615         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2616         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2617         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2618         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2619         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2620         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2621         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2622         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2623         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2624         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2625         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2626         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2627         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2628         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2629         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2630         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2631         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2632         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2633         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2634         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2635         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2636         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2637         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2638         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2639         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2640         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2641         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2642         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2643         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
2644         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2645         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2646         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2647         [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2648         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2649         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2650         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2651         [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2652         [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
2653         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2654         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2655         [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
2656         [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
2657         [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
2658         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2659         [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
2660         [GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr,
2661         [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr,
2662         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2663         [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
2664         [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
2665         [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2666         [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
2667         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2668         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2669         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2670         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2671         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2672         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
2673         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2674         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2675         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2676         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2677         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2678         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2679         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2680         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2681         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2682         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2683         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2684         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2685         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2686         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2687         [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2688         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2689         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2690         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2691         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2692         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2693         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2694         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2695         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2696         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2697         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2698         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2699         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2700         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2701         [GPLL0] = &gpll0.clkr,
2702         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2703         [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2704         [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2705         [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
2706         [GPLL1] = &gpll1.clkr,
2707         [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
2708         [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2709         [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
2710         [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
2711         [GPLL2] = &gpll2.clkr,
2712         [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
2713         [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2714         [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
2715         [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
2716         [GPLL3] = &gpll3.clkr,
2717         [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
2718         [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2719         [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
2720         [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
2721         [GPLL4] = &gpll4.clkr,
2722         [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
2723         [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2724         [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
2725         [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
2726         [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
2727         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2728         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
2729         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2730         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2731         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2732         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2733         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2734         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2735         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2736         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2737 };
2738
2739 static struct gdsc *gcc_msm8998_gdscs[] = {
2740         [PCIE_0_GDSC] = &pcie_0_gdsc,
2741         [UFS_GDSC] = &ufs_gdsc,
2742         [USB_30_GDSC] = &usb_30_gdsc,
2743 };
2744
2745 static const struct qcom_reset_map gcc_msm8998_resets[] = {
2746         [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
2747         [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
2748         [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
2749         [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
2750         [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
2751         [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
2752         [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
2753         [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
2754         [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
2755         [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
2756         [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
2757         [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
2758         [GCC_PCIE_0_BCR] = { 0x6b000 },
2759         [GCC_PDM_BCR] = { 0x33000 },
2760         [GCC_SDCC2_BCR] = { 0x14000 },
2761         [GCC_SDCC4_BCR] = { 0x16000 },
2762         [GCC_TSIF_BCR] = { 0x36000 },
2763         [GCC_UFS_BCR] = { 0x75000 },
2764         [GCC_USB_30_BCR] = { 0xf000 },
2765 };
2766
2767 static const struct regmap_config gcc_msm8998_regmap_config = {
2768         .reg_bits       = 32,
2769         .reg_stride     = 4,
2770         .val_bits       = 32,
2771         .max_register   = 0x8f000,
2772         .fast_io        = true,
2773 };
2774
2775 static const struct qcom_cc_desc gcc_msm8998_desc = {
2776         .config = &gcc_msm8998_regmap_config,
2777         .clks = gcc_msm8998_clocks,
2778         .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
2779         .resets = gcc_msm8998_resets,
2780         .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
2781         .gdscs = gcc_msm8998_gdscs,
2782         .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
2783 };
2784
2785 static int gcc_msm8998_probe(struct platform_device *pdev)
2786 {
2787         struct regmap *regmap;
2788         int ret;
2789
2790         regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
2791         if (IS_ERR(regmap))
2792                 return PTR_ERR(regmap);
2793
2794         /*
2795          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
2796          * turned off by hardware during certain apps low power modes.
2797          */
2798         ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
2799         if (ret)
2800                 return ret;
2801
2802         return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
2803 }
2804
2805 static const struct of_device_id gcc_msm8998_match_table[] = {
2806         { .compatible = "qcom,gcc-msm8998" },
2807         { }
2808 };
2809 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
2810
2811 static struct platform_driver gcc_msm8998_driver = {
2812         .probe          = gcc_msm8998_probe,
2813         .driver         = {
2814                 .name   = "gcc-msm8998",
2815                 .of_match_table = gcc_msm8998_match_table,
2816         },
2817 };
2818
2819 static int __init gcc_msm8998_init(void)
2820 {
2821         return platform_driver_register(&gcc_msm8998_driver);
2822 }
2823 core_initcall(gcc_msm8998_init);
2824
2825 static void __exit gcc_msm8998_exit(void)
2826 {
2827         platform_driver_unregister(&gcc_msm8998_driver);
2828 }
2829 module_exit(gcc_msm8998_exit);
2830
2831 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
2832 MODULE_LICENSE("GPL v2");
2833 MODULE_ALIAS("platform:gcc-msm8998");