drivers/clk/qcom/mmcc-msm8974.c

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
  26 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34 #include "gdsc.h"
  35
  36 enum {
  37         P_XO,
  38         P_MMPLL0,
  39         P_EDPLINK,
  40         P_MMPLL1,
  41         P_HDMIPLL,
  42         P_GPLL0,
  43         P_EDPVCO,
  44         P_GPLL1,
  45         P_DSI0PLL,
  46         P_DSI0PLL_BYTE,
  47         P_MMPLL2,
  48         P_MMPLL3,
  49         P_DSI1PLL,
  50         P_DSI1PLL_BYTE,
  51 };
  52
  53 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
  54         { P_XO, 0 },
  55         { P_MMPLL0, 1 },
  56         { P_MMPLL1, 2 },
  57         { P_GPLL0, 5 }
  58 };
  59
  60 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
  61         "xo",
  62         "mmpll0_vote",
  63         "mmpll1_vote",
  64         "mmss_gpll0_vote",
  65 };
  66
  67 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
  68         { P_XO, 0 },
  69         { P_MMPLL0, 1 },
  70         { P_HDMIPLL, 4 },
  71         { P_GPLL0, 5 },
  72         { P_DSI0PLL, 2 },
  73         { P_DSI1PLL, 3 }
  74 };
  75
  76 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
  77         "xo",
  78         "mmpll0_vote",
  79         "hdmipll",
  80         "mmss_gpll0_vote",
  81         "dsi0pll",
  82         "dsi1pll",
  83 };
  84
  85 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
  86         { P_XO, 0 },
  87         { P_MMPLL0, 1 },
  88         { P_MMPLL1, 2 },
  89         { P_GPLL0, 5 },
  90         { P_MMPLL2, 3 }
  91 };
  92
  93 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
  94         "xo",
  95         "mmpll0_vote",
  96         "mmpll1_vote",
  97         "mmss_gpll0_vote",
  98         "mmpll2",
  99 };
 100
 101 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
 102         { P_XO, 0 },
 103         { P_MMPLL0, 1 },
 104         { P_MMPLL1, 2 },
 105         { P_GPLL0, 5 },
 106         { P_MMPLL3, 3 }
 107 };
 108
 109 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
 110         "xo",
 111         "mmpll0_vote",
 112         "mmpll1_vote",
 113         "mmss_gpll0_vote",
 114         "mmpll3",
 115 };
 116
 117 static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
 118         { P_XO, 0 },
 119         { P_MMPLL0, 1 },
 120         { P_MMPLL1, 2 },
 121         { P_GPLL0, 5 },
 122         { P_GPLL1, 4 }
 123 };
 124
 125 static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
 126         "xo",
 127         "mmpll0_vote",
 128         "mmpll1_vote",
 129         "mmss_gpll0_vote",
 130         "gpll1_vote",
 131 };
 132
 133 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
 134         { P_XO, 0 },
 135         { P_EDPLINK, 4 },
 136         { P_HDMIPLL, 3 },
 137         { P_EDPVCO, 5 },
 138         { P_DSI0PLL, 1 },
 139         { P_DSI1PLL, 2 }
 140 };
 141
 142 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
 143         "xo",
 144         "edp_link_clk",
 145         "hdmipll",
 146         "edp_vco_div",
 147         "dsi0pll",
 148         "dsi1pll",
 149 };
 150
 151 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
 152         { P_XO, 0 },
 153         { P_EDPLINK, 4 },
 154         { P_HDMIPLL, 3 },
 155         { P_GPLL0, 5 },
 156         { P_DSI0PLL, 1 },
 157         { P_DSI1PLL, 2 }
 158 };
 159
 160 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
 161         "xo",
 162         "edp_link_clk",
 163         "hdmipll",
 164         "gpll0_vote",
 165         "dsi0pll",
 166         "dsi1pll",
 167 };
 168
 169 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
 170         { P_XO, 0 },
 171         { P_EDPLINK, 4 },
 172         { P_HDMIPLL, 3 },
 173         { P_GPLL0, 5 },
 174         { P_DSI0PLL_BYTE, 1 },
 175         { P_DSI1PLL_BYTE, 2 }
 176 };
 177
 178 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
 179         "xo",
 180         "edp_link_clk",
 181         "hdmipll",
 182         "gpll0_vote",
 183         "dsi0pllbyte",
 184         "dsi1pllbyte",
 185 };
 186
 187 static struct clk_pll mmpll0 = {
 188         .l_reg = 0x0004,
 189         .m_reg = 0x0008,
 190         .n_reg = 0x000c,
 191         .config_reg = 0x0014,
 192         .mode_reg = 0x0000,
 193         .status_reg = 0x001c,
 194         .status_bit = 17,
 195         .clkr.hw.init = &(struct clk_init_data){
 196                 .name = "mmpll0",
 197                 .parent_names = (const char *[]){ "xo" },
 198                 .num_parents = 1,
 199                 .ops = &clk_pll_ops,
 200         },
 201 };
 202
 203 static struct clk_regmap mmpll0_vote = {
 204         .enable_reg = 0x0100,
 205         .enable_mask = BIT(0),
 206         .hw.init = &(struct clk_init_data){
 207                 .name = "mmpll0_vote",
 208                 .parent_names = (const char *[]){ "mmpll0" },
 209                 .num_parents = 1,
 210                 .ops = &clk_pll_vote_ops,
 211         },
 212 };
 213
 214 static struct clk_pll mmpll1 = {
 215         .l_reg = 0x0044,
 216         .m_reg = 0x0048,
 217         .n_reg = 0x004c,
 218         .config_reg = 0x0050,
 219         .mode_reg = 0x0040,
 220         .status_reg = 0x005c,
 221         .status_bit = 17,
 222         .clkr.hw.init = &(struct clk_init_data){
 223                 .name = "mmpll1",
 224                 .parent_names = (const char *[]){ "xo" },
 225                 .num_parents = 1,
 226                 .ops = &clk_pll_ops,
 227         },
 228 };
 229
 230 static struct clk_regmap mmpll1_vote = {
 231         .enable_reg = 0x0100,
 232         .enable_mask = BIT(1),
 233         .hw.init = &(struct clk_init_data){
 234                 .name = "mmpll1_vote",
 235                 .parent_names = (const char *[]){ "mmpll1" },
 236                 .num_parents = 1,
 237                 .ops = &clk_pll_vote_ops,
 238         },
 239 };
 240
 241 static struct clk_pll mmpll2 = {
 242         .l_reg = 0x4104,
 243         .m_reg = 0x4108,
 244         .n_reg = 0x410c,
 245         .config_reg = 0x4110,
 246         .mode_reg = 0x4100,
 247         .status_reg = 0x411c,
 248         .clkr.hw.init = &(struct clk_init_data){
 249                 .name = "mmpll2",
 250                 .parent_names = (const char *[]){ "xo" },
 251                 .num_parents = 1,
 252                 .ops = &clk_pll_ops,
 253         },
 254 };
 255
 256 static struct clk_pll mmpll3 = {
 257         .l_reg = 0x0084,
 258         .m_reg = 0x0088,
 259         .n_reg = 0x008c,
 260         .config_reg = 0x0090,
 261         .mode_reg = 0x0080,
 262         .status_reg = 0x009c,
 263         .status_bit = 17,
 264         .clkr.hw.init = &(struct clk_init_data){
 265                 .name = "mmpll3",
 266                 .parent_names = (const char *[]){ "xo" },
 267                 .num_parents = 1,
 268                 .ops = &clk_pll_ops,
 269         },
 270 };
 271
 272 static struct clk_rcg2 mmss_ahb_clk_src = {
 273         .cmd_rcgr = 0x5000,
 274         .hid_width = 5,
 275         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 276         .clkr.hw.init = &(struct clk_init_data){
 277                 .name = "mmss_ahb_clk_src",
 278                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 279                 .num_parents = 4,
 280                 .ops = &clk_rcg2_ops,
 281         },
 282 };
 283
 284 static struct freq_tbl ftbl_mmss_axi_clk[] = {
 285         F( 19200000, P_XO, 1, 0, 0),
 286         F( 37500000, P_GPLL0, 16, 0, 0),
 287         F( 50000000, P_GPLL0, 12, 0, 0),
 288         F( 75000000, P_GPLL0, 8, 0, 0),
 289         F(100000000, P_GPLL0, 6, 0, 0),
 290         F(150000000, P_GPLL0, 4, 0, 0),
 291         F(291750000, P_MMPLL1, 4, 0, 0),
 292         F(400000000, P_MMPLL0, 2, 0, 0),
 293         F(466800000, P_MMPLL1, 2.5, 0, 0),
 294 };
 295
 296 static struct clk_rcg2 mmss_axi_clk_src = {
 297         .cmd_rcgr = 0x5040,
 298         .hid_width = 5,
 299         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 300         .freq_tbl = ftbl_mmss_axi_clk,
 301         .clkr.hw.init = &(struct clk_init_data){
 302                 .name = "mmss_axi_clk_src",
 303                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 304                 .num_parents = 4,
 305                 .ops = &clk_rcg2_ops,
 306         },
 307 };
 308
 309 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
 310         F( 19200000, P_XO, 1, 0, 0),
 311         F( 37500000, P_GPLL0, 16, 0, 0),
 312         F( 50000000, P_GPLL0, 12, 0, 0),
 313         F( 75000000, P_GPLL0, 8, 0, 0),
 314         F(100000000, P_GPLL0, 6, 0, 0),
 315         F(150000000, P_GPLL0, 4, 0, 0),
 316         F(291750000, P_MMPLL1, 4, 0, 0),
 317         F(400000000, P_MMPLL0, 2, 0, 0),
 318 };
 319
 320 static struct clk_rcg2 ocmemnoc_clk_src = {
 321         .cmd_rcgr = 0x5090,
 322         .hid_width = 5,
 323         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 324         .freq_tbl = ftbl_ocmemnoc_clk,
 325         .clkr.hw.init = &(struct clk_init_data){
 326                 .name = "ocmemnoc_clk_src",
 327                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 328                 .num_parents = 4,
 329                 .ops = &clk_rcg2_ops,
 330         },
 331 };
 332
 333 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
 334         F(100000000, P_GPLL0, 6, 0, 0),
 335         F(200000000, P_MMPLL0, 4, 0, 0),
 336         { }
 337 };
 338
 339 static struct clk_rcg2 csi0_clk_src = {
 340         .cmd_rcgr = 0x3090,
 341         .hid_width = 5,
 342         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 343         .freq_tbl = ftbl_camss_csi0_3_clk,
 344         .clkr.hw.init = &(struct clk_init_data){
 345                 .name = "csi0_clk_src",
 346                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 347                 .num_parents = 4,
 348                 .ops = &clk_rcg2_ops,
 349         },
 350 };
 351
 352 static struct clk_rcg2 csi1_clk_src = {
 353         .cmd_rcgr = 0x3100,
 354         .hid_width = 5,
 355         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 356         .freq_tbl = ftbl_camss_csi0_3_clk,
 357         .clkr.hw.init = &(struct clk_init_data){
 358                 .name = "csi1_clk_src",
 359                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 360                 .num_parents = 4,
 361                 .ops = &clk_rcg2_ops,
 362         },
 363 };
 364
 365 static struct clk_rcg2 csi2_clk_src = {
 366         .cmd_rcgr = 0x3160,
 367         .hid_width = 5,
 368         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 369         .freq_tbl = ftbl_camss_csi0_3_clk,
 370         .clkr.hw.init = &(struct clk_init_data){
 371                 .name = "csi2_clk_src",
 372                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 373                 .num_parents = 4,
 374                 .ops = &clk_rcg2_ops,
 375         },
 376 };
 377
 378 static struct clk_rcg2 csi3_clk_src = {
 379         .cmd_rcgr = 0x31c0,
 380         .hid_width = 5,
 381         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 382         .freq_tbl = ftbl_camss_csi0_3_clk,
 383         .clkr.hw.init = &(struct clk_init_data){
 384                 .name = "csi3_clk_src",
 385                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 386                 .num_parents = 4,
 387                 .ops = &clk_rcg2_ops,
 388         },
 389 };
 390
 391 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
 392         F(37500000, P_GPLL0, 16, 0, 0),
 393         F(50000000, P_GPLL0, 12, 0, 0),
 394         F(60000000, P_GPLL0, 10, 0, 0),
 395         F(80000000, P_GPLL0, 7.5, 0, 0),
 396         F(100000000, P_GPLL0, 6, 0, 0),
 397         F(109090000, P_GPLL0, 5.5, 0, 0),
 398         F(133330000, P_GPLL0, 4.5, 0, 0),
 399         F(200000000, P_GPLL0, 3, 0, 0),
 400         F(228570000, P_MMPLL0, 3.5, 0, 0),
 401         F(266670000, P_MMPLL0, 3, 0, 0),
 402         F(320000000, P_MMPLL0, 2.5, 0, 0),
 403         F(400000000, P_MMPLL0, 2, 0, 0),
 404         F(465000000, P_MMPLL3, 2, 0, 0),
 405         { }
 406 };
 407
 408 static struct clk_rcg2 vfe0_clk_src = {
 409         .cmd_rcgr = 0x3600,
 410         .hid_width = 5,
 411         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 412         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 413         .clkr.hw.init = &(struct clk_init_data){
 414                 .name = "vfe0_clk_src",
 415                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 416                 .num_parents = 4,
 417                 .ops = &clk_rcg2_ops,
 418         },
 419 };
 420
 421 static struct clk_rcg2 vfe1_clk_src = {
 422         .cmd_rcgr = 0x3620,
 423         .hid_width = 5,
 424         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 425         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 426         .clkr.hw.init = &(struct clk_init_data){
 427                 .name = "vfe1_clk_src",
 428                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 429                 .num_parents = 4,
 430                 .ops = &clk_rcg2_ops,
 431         },
 432 };
 433
 434 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
 435         F(37500000, P_GPLL0, 16, 0, 0),
 436         F(60000000, P_GPLL0, 10, 0, 0),
 437         F(75000000, P_GPLL0, 8, 0, 0),
 438         F(85710000, P_GPLL0, 7, 0, 0),
 439         F(100000000, P_GPLL0, 6, 0, 0),
 440         F(133330000, P_MMPLL0, 6, 0, 0),
 441         F(160000000, P_MMPLL0, 5, 0, 0),
 442         F(200000000, P_MMPLL0, 4, 0, 0),
 443         F(228570000, P_MMPLL0, 3.5, 0, 0),
 444         F(240000000, P_GPLL0, 2.5, 0, 0),
 445         F(266670000, P_MMPLL0, 3, 0, 0),
 446         F(320000000, P_MMPLL0, 2.5, 0, 0),
 447         { }
 448 };
 449
 450 static struct clk_rcg2 mdp_clk_src = {
 451         .cmd_rcgr = 0x2040,
 452         .hid_width = 5,
 453         .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
 454         .freq_tbl = ftbl_mdss_mdp_clk,
 455         .clkr.hw.init = &(struct clk_init_data){
 456                 .name = "mdp_clk_src",
 457                 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
 458                 .num_parents = 6,
 459                 .ops = &clk_rcg2_ops,
 460         },
 461 };
 462
 463 static struct clk_rcg2 gfx3d_clk_src = {
 464         .cmd_rcgr = 0x4000,
 465         .hid_width = 5,
 466         .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
 467         .clkr.hw.init = &(struct clk_init_data){
 468                 .name = "gfx3d_clk_src",
 469                 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
 470                 .num_parents = 5,
 471                 .ops = &clk_rcg2_ops,
 472         },
 473 };
 474
 475 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
 476         F(75000000, P_GPLL0, 8, 0, 0),
 477         F(133330000, P_GPLL0, 4.5, 0, 0),
 478         F(200000000, P_GPLL0, 3, 0, 0),
 479         F(228570000, P_MMPLL0, 3.5, 0, 0),
 480         F(266670000, P_MMPLL0, 3, 0, 0),
 481         F(320000000, P_MMPLL0, 2.5, 0, 0),
 482         { }
 483 };
 484
 485 static struct clk_rcg2 jpeg0_clk_src = {
 486         .cmd_rcgr = 0x3500,
 487         .hid_width = 5,
 488         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 489         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 490         .clkr.hw.init = &(struct clk_init_data){
 491                 .name = "jpeg0_clk_src",
 492                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 493                 .num_parents = 4,
 494                 .ops = &clk_rcg2_ops,
 495         },
 496 };
 497
 498 static struct clk_rcg2 jpeg1_clk_src = {
 499         .cmd_rcgr = 0x3520,
 500         .hid_width = 5,
 501         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 502         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 503         .clkr.hw.init = &(struct clk_init_data){
 504                 .name = "jpeg1_clk_src",
 505                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 506                 .num_parents = 4,
 507                 .ops = &clk_rcg2_ops,
 508         },
 509 };
 510
 511 static struct clk_rcg2 jpeg2_clk_src = {
 512         .cmd_rcgr = 0x3540,
 513         .hid_width = 5,
 514         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 515         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 516         .clkr.hw.init = &(struct clk_init_data){
 517                 .name = "jpeg2_clk_src",
 518                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 519                 .num_parents = 4,
 520                 .ops = &clk_rcg2_ops,
 521         },
 522 };
 523
 524 static struct clk_rcg2 pclk0_clk_src = {
 525         .cmd_rcgr = 0x2000,
 526         .mnd_width = 8,
 527         .hid_width = 5,
 528         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 529         .clkr.hw.init = &(struct clk_init_data){
 530                 .name = "pclk0_clk_src",
 531                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 532                 .num_parents = 6,
 533                 .ops = &clk_pixel_ops,
 534                 .flags = CLK_SET_RATE_PARENT,
 535         },
 536 };
 537
 538 static struct clk_rcg2 pclk1_clk_src = {
 539         .cmd_rcgr = 0x2020,
 540         .mnd_width = 8,
 541         .hid_width = 5,
 542         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 543         .clkr.hw.init = &(struct clk_init_data){
 544                 .name = "pclk1_clk_src",
 545                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 546                 .num_parents = 6,
 547                 .ops = &clk_pixel_ops,
 548                 .flags = CLK_SET_RATE_PARENT,
 549         },
 550 };
 551
 552 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
 553         F(50000000, P_GPLL0, 12, 0, 0),
 554         F(100000000, P_GPLL0, 6, 0, 0),
 555         F(133330000, P_MMPLL0, 6, 0, 0),
 556         F(200000000, P_MMPLL0, 4, 0, 0),
 557         F(266670000, P_MMPLL0, 3, 0, 0),
 558         F(465000000, P_MMPLL3, 2, 0, 0),
 559         { }
 560 };
 561
 562 static struct clk_rcg2 vcodec0_clk_src = {
 563         .cmd_rcgr = 0x1000,
 564         .mnd_width = 8,
 565         .hid_width = 5,
 566         .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
 567         .freq_tbl = ftbl_venus0_vcodec0_clk,
 568         .clkr.hw.init = &(struct clk_init_data){
 569                 .name = "vcodec0_clk_src",
 570                 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
 571                 .num_parents = 5,
 572                 .ops = &clk_rcg2_ops,
 573         },
 574 };
 575
 576 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
 577         F(19200000, P_XO, 1, 0, 0),
 578         { }
 579 };
 580
 581 static struct clk_rcg2 cci_clk_src = {
 582         .cmd_rcgr = 0x3300,
 583         .hid_width = 5,
 584         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 585         .freq_tbl = ftbl_camss_cci_cci_clk,
 586         .clkr.hw.init = &(struct clk_init_data){
 587                 .name = "cci_clk_src",
 588                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 589                 .num_parents = 4,
 590                 .ops = &clk_rcg2_ops,
 591         },
 592 };
 593
 594 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
 595         F(10000, P_XO, 16, 1, 120),
 596         F(24000, P_XO, 16, 1, 50),
 597         F(6000000, P_GPLL0, 10, 1, 10),
 598         F(12000000, P_GPLL0, 10, 1, 5),
 599         F(13000000, P_GPLL0, 4, 13, 150),
 600         F(24000000, P_GPLL0, 5, 1, 5),
 601         { }
 602 };
 603
 604 static struct clk_rcg2 camss_gp0_clk_src = {
 605         .cmd_rcgr = 0x3420,
 606         .mnd_width = 8,
 607         .hid_width = 5,
 608         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 609         .freq_tbl = ftbl_camss_gp0_1_clk,
 610         .clkr.hw.init = &(struct clk_init_data){
 611                 .name = "camss_gp0_clk_src",
 612                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 613                 .num_parents = 5,
 614                 .ops = &clk_rcg2_ops,
 615         },
 616 };
 617
 618 static struct clk_rcg2 camss_gp1_clk_src = {
 619         .cmd_rcgr = 0x3450,
 620         .mnd_width = 8,
 621         .hid_width = 5,
 622         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 623         .freq_tbl = ftbl_camss_gp0_1_clk,
 624         .clkr.hw.init = &(struct clk_init_data){
 625                 .name = "camss_gp1_clk_src",
 626                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 627                 .num_parents = 5,
 628                 .ops = &clk_rcg2_ops,
 629         },
 630 };
 631
 632 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
 633         F(4800000, P_XO, 4, 0, 0),
 634         F(6000000, P_GPLL0, 10, 1, 10),
 635         F(8000000, P_GPLL0, 15, 1, 5),
 636         F(9600000, P_XO, 2, 0, 0),
 637         F(16000000, P_GPLL0, 12.5, 1, 3),
 638         F(19200000, P_XO, 1, 0, 0),
 639         F(24000000, P_GPLL0, 5, 1, 5),
 640         F(32000000, P_MMPLL0, 5, 1, 5),
 641         F(48000000, P_GPLL0, 12.5, 0, 0),
 642         F(64000000, P_MMPLL0, 12.5, 0, 0),
 643         F(66670000, P_GPLL0, 9, 0, 0),
 644         { }
 645 };
 646
 647 static struct clk_rcg2 mclk0_clk_src = {
 648         .cmd_rcgr = 0x3360,
 649         .hid_width = 5,
 650         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 651         .freq_tbl = ftbl_camss_mclk0_3_clk,
 652         .clkr.hw.init = &(struct clk_init_data){
 653                 .name = "mclk0_clk_src",
 654                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 655                 .num_parents = 4,
 656                 .ops = &clk_rcg2_ops,
 657         },
 658 };
 659
 660 static struct clk_rcg2 mclk1_clk_src = {
 661         .cmd_rcgr = 0x3390,
 662         .hid_width = 5,
 663         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 664         .freq_tbl = ftbl_camss_mclk0_3_clk,
 665         .clkr.hw.init = &(struct clk_init_data){
 666                 .name = "mclk1_clk_src",
 667                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 668                 .num_parents = 4,
 669                 .ops = &clk_rcg2_ops,
 670         },
 671 };
 672
 673 static struct clk_rcg2 mclk2_clk_src = {
 674         .cmd_rcgr = 0x33c0,
 675         .hid_width = 5,
 676         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 677         .freq_tbl = ftbl_camss_mclk0_3_clk,
 678         .clkr.hw.init = &(struct clk_init_data){
 679                 .name = "mclk2_clk_src",
 680                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 681                 .num_parents = 4,
 682                 .ops = &clk_rcg2_ops,
 683         },
 684 };
 685
 686 static struct clk_rcg2 mclk3_clk_src = {
 687         .cmd_rcgr = 0x33f0,
 688         .hid_width = 5,
 689         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 690         .freq_tbl = ftbl_camss_mclk0_3_clk,
 691         .clkr.hw.init = &(struct clk_init_data){
 692                 .name = "mclk3_clk_src",
 693                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 694                 .num_parents = 4,
 695                 .ops = &clk_rcg2_ops,
 696         },
 697 };
 698
 699 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
 700         F(100000000, P_GPLL0, 6, 0, 0),
 701         F(200000000, P_MMPLL0, 4, 0, 0),
 702         { }
 703 };
 704
 705 static struct clk_rcg2 csi0phytimer_clk_src = {
 706         .cmd_rcgr = 0x3000,
 707         .hid_width = 5,
 708         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 709         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 710         .clkr.hw.init = &(struct clk_init_data){
 711                 .name = "csi0phytimer_clk_src",
 712                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 713                 .num_parents = 4,
 714                 .ops = &clk_rcg2_ops,
 715         },
 716 };
 717
 718 static struct clk_rcg2 csi1phytimer_clk_src = {
 719         .cmd_rcgr = 0x3030,
 720         .hid_width = 5,
 721         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 722         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 723         .clkr.hw.init = &(struct clk_init_data){
 724                 .name = "csi1phytimer_clk_src",
 725                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 726                 .num_parents = 4,
 727                 .ops = &clk_rcg2_ops,
 728         },
 729 };
 730
 731 static struct clk_rcg2 csi2phytimer_clk_src = {
 732         .cmd_rcgr = 0x3060,
 733         .hid_width = 5,
 734         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 735         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 736         .clkr.hw.init = &(struct clk_init_data){
 737                 .name = "csi2phytimer_clk_src",
 738                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 739                 .num_parents = 4,
 740                 .ops = &clk_rcg2_ops,
 741         },
 742 };
 743
 744 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
 745         F(133330000, P_GPLL0, 4.5, 0, 0),
 746         F(266670000, P_MMPLL0, 3, 0, 0),
 747         F(320000000, P_MMPLL0, 2.5, 0, 0),
 748         F(400000000, P_MMPLL0, 2, 0, 0),
 749         F(465000000, P_MMPLL3, 2, 0, 0),
 750         { }
 751 };
 752
 753 static struct clk_rcg2 cpp_clk_src = {
 754         .cmd_rcgr = 0x3640,
 755         .hid_width = 5,
 756         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 757         .freq_tbl = ftbl_camss_vfe_cpp_clk,
 758         .clkr.hw.init = &(struct clk_init_data){
 759                 .name = "cpp_clk_src",
 760                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 761                 .num_parents = 4,
 762                 .ops = &clk_rcg2_ops,
 763         },
 764 };
 765
 766 static struct freq_tbl byte_freq_tbl[] = {
 767         { .src = P_DSI0PLL_BYTE },
 768         { }
 769 };
 770
 771 static struct clk_rcg2 byte0_clk_src = {
 772         .cmd_rcgr = 0x2120,
 773         .hid_width = 5,
 774         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 775         .freq_tbl = byte_freq_tbl,
 776         .clkr.hw.init = &(struct clk_init_data){
 777                 .name = "byte0_clk_src",
 778                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 779                 .num_parents = 6,
 780                 .ops = &clk_byte2_ops,
 781                 .flags = CLK_SET_RATE_PARENT,
 782         },
 783 };
 784
 785 static struct clk_rcg2 byte1_clk_src = {
 786         .cmd_rcgr = 0x2140,
 787         .hid_width = 5,
 788         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 789         .freq_tbl = byte_freq_tbl,
 790         .clkr.hw.init = &(struct clk_init_data){
 791                 .name = "byte1_clk_src",
 792                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 793                 .num_parents = 6,
 794                 .ops = &clk_byte2_ops,
 795                 .flags = CLK_SET_RATE_PARENT,
 796         },
 797 };
 798
 799 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
 800         F(19200000, P_XO, 1, 0, 0),
 801         { }
 802 };
 803
 804 static struct clk_rcg2 edpaux_clk_src = {
 805         .cmd_rcgr = 0x20e0,
 806         .hid_width = 5,
 807         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 808         .freq_tbl = ftbl_mdss_edpaux_clk,
 809         .clkr.hw.init = &(struct clk_init_data){
 810                 .name = "edpaux_clk_src",
 811                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 812                 .num_parents = 4,
 813                 .ops = &clk_rcg2_ops,
 814         },
 815 };
 816
 817 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
 818         F(135000000, P_EDPLINK, 2, 0, 0),
 819         F(270000000, P_EDPLINK, 11, 0, 0),
 820         { }
 821 };
 822
 823 static struct clk_rcg2 edplink_clk_src = {
 824         .cmd_rcgr = 0x20c0,
 825         .hid_width = 5,
 826         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 827         .freq_tbl = ftbl_mdss_edplink_clk,
 828         .clkr.hw.init = &(struct clk_init_data){
 829                 .name = "edplink_clk_src",
 830                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 831                 .num_parents = 6,
 832                 .ops = &clk_rcg2_ops,
 833                 .flags = CLK_SET_RATE_PARENT,
 834         },
 835 };
 836
 837 static struct freq_tbl edp_pixel_freq_tbl[] = {
 838         { .src = P_EDPVCO },
 839         { }
 840 };
 841
 842 static struct clk_rcg2 edppixel_clk_src = {
 843         .cmd_rcgr = 0x20a0,
 844         .mnd_width = 8,
 845         .hid_width = 5,
 846         .parent_map = mmcc_xo_dsi_hdmi_edp_map,
 847         .freq_tbl = edp_pixel_freq_tbl,
 848         .clkr.hw.init = &(struct clk_init_data){
 849                 .name = "edppixel_clk_src",
 850                 .parent_names = mmcc_xo_dsi_hdmi_edp,
 851                 .num_parents = 6,
 852                 .ops = &clk_edp_pixel_ops,
 853         },
 854 };
 855
 856 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 857         F(19200000, P_XO, 1, 0, 0),
 858         { }
 859 };
 860
 861 static struct clk_rcg2 esc0_clk_src = {
 862         .cmd_rcgr = 0x2160,
 863         .hid_width = 5,
 864         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 865         .freq_tbl = ftbl_mdss_esc0_1_clk,
 866         .clkr.hw.init = &(struct clk_init_data){
 867                 .name = "esc0_clk_src",
 868                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 869                 .num_parents = 6,
 870                 .ops = &clk_rcg2_ops,
 871         },
 872 };
 873
 874 static struct clk_rcg2 esc1_clk_src = {
 875         .cmd_rcgr = 0x2180,
 876         .hid_width = 5,
 877         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 878         .freq_tbl = ftbl_mdss_esc0_1_clk,
 879         .clkr.hw.init = &(struct clk_init_data){
 880                 .name = "esc1_clk_src",
 881                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 882                 .num_parents = 6,
 883                 .ops = &clk_rcg2_ops,
 884         },
 885 };
 886
 887 static struct freq_tbl extpclk_freq_tbl[] = {
 888         { .src = P_HDMIPLL },
 889         { }
 890 };
 891
 892 static struct clk_rcg2 extpclk_clk_src = {
 893         .cmd_rcgr = 0x2060,
 894         .hid_width = 5,
 895         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 896         .freq_tbl = extpclk_freq_tbl,
 897         .clkr.hw.init = &(struct clk_init_data){
 898                 .name = "extpclk_clk_src",
 899                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 900                 .num_parents = 6,
 901                 .ops = &clk_byte_ops,
 902                 .flags = CLK_SET_RATE_PARENT,
 903         },
 904 };
 905
 906 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 907         F(19200000, P_XO, 1, 0, 0),
 908         { }
 909 };
 910
 911 static struct clk_rcg2 hdmi_clk_src = {
 912         .cmd_rcgr = 0x2100,
 913         .hid_width = 5,
 914         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 915         .freq_tbl = ftbl_mdss_hdmi_clk,
 916         .clkr.hw.init = &(struct clk_init_data){
 917                 .name = "hdmi_clk_src",
 918                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 919                 .num_parents = 4,
 920                 .ops = &clk_rcg2_ops,
 921         },
 922 };
 923
 924 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
 925         F(19200000, P_XO, 1, 0, 0),
 926         { }
 927 };
 928
 929 static struct clk_rcg2 vsync_clk_src = {
 930         .cmd_rcgr = 0x2080,
 931         .hid_width = 5,
 932         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 933         .freq_tbl = ftbl_mdss_vsync_clk,
 934         .clkr.hw.init = &(struct clk_init_data){
 935                 .name = "vsync_clk_src",
 936                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 937                 .num_parents = 4,
 938                 .ops = &clk_rcg2_ops,
 939         },
 940 };
 941
 942 static struct clk_branch camss_cci_cci_ahb_clk = {
 943         .halt_reg = 0x3348,
 944         .clkr = {
 945                 .enable_reg = 0x3348,
 946                 .enable_mask = BIT(0),
 947                 .hw.init = &(struct clk_init_data){
 948                         .name = "camss_cci_cci_ahb_clk",
 949                         .parent_names = (const char *[]){
 950                                 "mmss_ahb_clk_src",
 951                         },
 952                         .num_parents = 1,
 953                         .ops = &clk_branch2_ops,
 954                 },
 955         },
 956 };
 957
 958 static struct clk_branch camss_cci_cci_clk = {
 959         .halt_reg = 0x3344,
 960         .clkr = {
 961                 .enable_reg = 0x3344,
 962                 .enable_mask = BIT(0),
 963                 .hw.init = &(struct clk_init_data){
 964                         .name = "camss_cci_cci_clk",
 965                         .parent_names = (const char *[]){
 966                                 "cci_clk_src",
 967                         },
 968                         .num_parents = 1,
 969                         .flags = CLK_SET_RATE_PARENT,
 970                         .ops = &clk_branch2_ops,
 971                 },
 972         },
 973 };
 974
 975 static struct clk_branch camss_csi0_ahb_clk = {
 976         .halt_reg = 0x30bc,
 977         .clkr = {
 978                 .enable_reg = 0x30bc,
 979                 .enable_mask = BIT(0),
 980                 .hw.init = &(struct clk_init_data){
 981                         .name = "camss_csi0_ahb_clk",
 982                         .parent_names = (const char *[]){
 983                                 "mmss_ahb_clk_src",
 984                         },
 985                         .num_parents = 1,
 986                         .ops = &clk_branch2_ops,
 987                 },
 988         },
 989 };
 990
 991 static struct clk_branch camss_csi0_clk = {
 992         .halt_reg = 0x30b4,
 993         .clkr = {
 994                 .enable_reg = 0x30b4,
 995                 .enable_mask = BIT(0),
 996                 .hw.init = &(struct clk_init_data){
 997                         .name = "camss_csi0_clk",
 998                         .parent_names = (const char *[]){
 999                                 "csi0_clk_src",
1000                         },
1001                         .num_parents = 1,
1002                         .flags = CLK_SET_RATE_PARENT,
1003                         .ops = &clk_branch2_ops,
1004                 },
1005         },
1006 };
1007
1008 static struct clk_branch camss_csi0phy_clk = {
1009         .halt_reg = 0x30c4,
1010         .clkr = {
1011                 .enable_reg = 0x30c4,
1012                 .enable_mask = BIT(0),
1013                 .hw.init = &(struct clk_init_data){
1014                         .name = "camss_csi0phy_clk",
1015                         .parent_names = (const char *[]){
1016                                 "csi0_clk_src",
1017                         },
1018                         .num_parents = 1,
1019                         .flags = CLK_SET_RATE_PARENT,
1020                         .ops = &clk_branch2_ops,
1021                 },
1022         },
1023 };
1024
1025 static struct clk_branch camss_csi0pix_clk = {
1026         .halt_reg = 0x30e4,
1027         .clkr = {
1028                 .enable_reg = 0x30e4,
1029                 .enable_mask = BIT(0),
1030                 .hw.init = &(struct clk_init_data){
1031                         .name = "camss_csi0pix_clk",
1032                         .parent_names = (const char *[]){
1033                                 "csi0_clk_src",
1034                         },
1035                         .num_parents = 1,
1036                         .flags = CLK_SET_RATE_PARENT,
1037                         .ops = &clk_branch2_ops,
1038                 },
1039         },
1040 };
1041
1042 static struct clk_branch camss_csi0rdi_clk = {
1043         .halt_reg = 0x30d4,
1044         .clkr = {
1045                 .enable_reg = 0x30d4,
1046                 .enable_mask = BIT(0),
1047                 .hw.init = &(struct clk_init_data){
1048                         .name = "camss_csi0rdi_clk",
1049                         .parent_names = (const char *[]){
1050                                 "csi0_clk_src",
1051                         },
1052                         .num_parents = 1,
1053                         .flags = CLK_SET_RATE_PARENT,
1054                         .ops = &clk_branch2_ops,
1055                 },
1056         },
1057 };
1058
1059 static struct clk_branch camss_csi1_ahb_clk = {
1060         .halt_reg = 0x3128,
1061         .clkr = {
1062                 .enable_reg = 0x3128,
1063                 .enable_mask = BIT(0),
1064                 .hw.init = &(struct clk_init_data){
1065                         .name = "camss_csi1_ahb_clk",
1066                         .parent_names = (const char *[]){
1067                                 "mmss_ahb_clk_src",
1068                         },
1069                         .num_parents = 1,
1070                         .ops = &clk_branch2_ops,
1071                 },
1072         },
1073 };
1074
1075 static struct clk_branch camss_csi1_clk = {
1076         .halt_reg = 0x3124,
1077         .clkr = {
1078                 .enable_reg = 0x3124,
1079                 .enable_mask = BIT(0),
1080                 .hw.init = &(struct clk_init_data){
1081                         .name = "camss_csi1_clk",
1082                         .parent_names = (const char *[]){
1083                                 "csi1_clk_src",
1084                         },
1085                         .num_parents = 1,
1086                         .flags = CLK_SET_RATE_PARENT,
1087                         .ops = &clk_branch2_ops,
1088                 },
1089         },
1090 };
1091
1092 static struct clk_branch camss_csi1phy_clk = {
1093         .halt_reg = 0x3134,
1094         .clkr = {
1095                 .enable_reg = 0x3134,
1096                 .enable_mask = BIT(0),
1097                 .hw.init = &(struct clk_init_data){
1098                         .name = "camss_csi1phy_clk",
1099                         .parent_names = (const char *[]){
1100                                 "csi1_clk_src",
1101                         },
1102                         .num_parents = 1,
1103                         .flags = CLK_SET_RATE_PARENT,
1104                         .ops = &clk_branch2_ops,
1105                 },
1106         },
1107 };
1108
1109 static struct clk_branch camss_csi1pix_clk = {
1110         .halt_reg = 0x3154,
1111         .clkr = {
1112                 .enable_reg = 0x3154,
1113                 .enable_mask = BIT(0),
1114                 .hw.init = &(struct clk_init_data){
1115                         .name = "camss_csi1pix_clk",
1116                         .parent_names = (const char *[]){
1117                                 "csi1_clk_src",
1118                         },
1119                         .num_parents = 1,
1120                         .flags = CLK_SET_RATE_PARENT,
1121                         .ops = &clk_branch2_ops,
1122                 },
1123         },
1124 };
1125
1126 static struct clk_branch camss_csi1rdi_clk = {
1127         .halt_reg = 0x3144,
1128         .clkr = {
1129                 .enable_reg = 0x3144,
1130                 .enable_mask = BIT(0),
1131                 .hw.init = &(struct clk_init_data){
1132                         .name = "camss_csi1rdi_clk",
1133                         .parent_names = (const char *[]){
1134                                 "csi1_clk_src",
1135                         },
1136                         .num_parents = 1,
1137                         .flags = CLK_SET_RATE_PARENT,
1138                         .ops = &clk_branch2_ops,
1139                 },
1140         },
1141 };
1142
1143 static struct clk_branch camss_csi2_ahb_clk = {
1144         .halt_reg = 0x3188,
1145         .clkr = {
1146                 .enable_reg = 0x3188,
1147                 .enable_mask = BIT(0),
1148                 .hw.init = &(struct clk_init_data){
1149                         .name = "camss_csi2_ahb_clk",
1150                         .parent_names = (const char *[]){
1151                                 "mmss_ahb_clk_src",
1152                         },
1153                         .num_parents = 1,
1154                         .ops = &clk_branch2_ops,
1155                 },
1156         },
1157 };
1158
1159 static struct clk_branch camss_csi2_clk = {
1160         .halt_reg = 0x3184,
1161         .clkr = {
1162                 .enable_reg = 0x3184,
1163                 .enable_mask = BIT(0),
1164                 .hw.init = &(struct clk_init_data){
1165                         .name = "camss_csi2_clk",
1166                         .parent_names = (const char *[]){
1167                                 "csi2_clk_src",
1168                         },
1169                         .num_parents = 1,
1170                         .flags = CLK_SET_RATE_PARENT,
1171                         .ops = &clk_branch2_ops,
1172                 },
1173         },
1174 };
1175
1176 static struct clk_branch camss_csi2phy_clk = {
1177         .halt_reg = 0x3194,
1178         .clkr = {
1179                 .enable_reg = 0x3194,
1180                 .enable_mask = BIT(0),
1181                 .hw.init = &(struct clk_init_data){
1182                         .name = "camss_csi2phy_clk",
1183                         .parent_names = (const char *[]){
1184                                 "csi2_clk_src",
1185                         },
1186                         .num_parents = 1,
1187                         .flags = CLK_SET_RATE_PARENT,
1188                         .ops = &clk_branch2_ops,
1189                 },
1190         },
1191 };
1192
1193 static struct clk_branch camss_csi2pix_clk = {
1194         .halt_reg = 0x31b4,
1195         .clkr = {
1196                 .enable_reg = 0x31b4,
1197                 .enable_mask = BIT(0),
1198                 .hw.init = &(struct clk_init_data){
1199                         .name = "camss_csi2pix_clk",
1200                         .parent_names = (const char *[]){
1201                                 "csi2_clk_src",
1202                         },
1203                         .num_parents = 1,
1204                         .flags = CLK_SET_RATE_PARENT,
1205                         .ops = &clk_branch2_ops,
1206                 },
1207         },
1208 };
1209
1210 static struct clk_branch camss_csi2rdi_clk = {
1211         .halt_reg = 0x31a4,
1212         .clkr = {
1213                 .enable_reg = 0x31a4,
1214                 .enable_mask = BIT(0),
1215                 .hw.init = &(struct clk_init_data){
1216                         .name = "camss_csi2rdi_clk",
1217                         .parent_names = (const char *[]){
1218                                 "csi2_clk_src",
1219                         },
1220                         .num_parents = 1,
1221                         .flags = CLK_SET_RATE_PARENT,
1222                         .ops = &clk_branch2_ops,
1223                 },
1224         },
1225 };
1226
1227 static struct clk_branch camss_csi3_ahb_clk = {
1228         .halt_reg = 0x31e8,
1229         .clkr = {
1230                 .enable_reg = 0x31e8,
1231                 .enable_mask = BIT(0),
1232                 .hw.init = &(struct clk_init_data){
1233                         .name = "camss_csi3_ahb_clk",
1234                         .parent_names = (const char *[]){
1235                                 "mmss_ahb_clk_src",
1236                         },
1237                         .num_parents = 1,
1238                         .ops = &clk_branch2_ops,
1239                 },
1240         },
1241 };
1242
1243 static struct clk_branch camss_csi3_clk = {
1244         .halt_reg = 0x31e4,
1245         .clkr = {
1246                 .enable_reg = 0x31e4,
1247                 .enable_mask = BIT(0),
1248                 .hw.init = &(struct clk_init_data){
1249                         .name = "camss_csi3_clk",
1250                         .parent_names = (const char *[]){
1251                                 "csi3_clk_src",
1252                         },
1253                         .num_parents = 1,
1254                         .flags = CLK_SET_RATE_PARENT,
1255                         .ops = &clk_branch2_ops,
1256                 },
1257         },
1258 };
1259
1260 static struct clk_branch camss_csi3phy_clk = {
1261         .halt_reg = 0x31f4,
1262         .clkr = {
1263                 .enable_reg = 0x31f4,
1264                 .enable_mask = BIT(0),
1265                 .hw.init = &(struct clk_init_data){
1266                         .name = "camss_csi3phy_clk",
1267                         .parent_names = (const char *[]){
1268                                 "csi3_clk_src",
1269                         },
1270                         .num_parents = 1,
1271                         .flags = CLK_SET_RATE_PARENT,
1272                         .ops = &clk_branch2_ops,
1273                 },
1274         },
1275 };
1276
1277 static struct clk_branch camss_csi3pix_clk = {
1278         .halt_reg = 0x3214,
1279         .clkr = {
1280                 .enable_reg = 0x3214,
1281                 .enable_mask = BIT(0),
1282                 .hw.init = &(struct clk_init_data){
1283                         .name = "camss_csi3pix_clk",
1284                         .parent_names = (const char *[]){
1285                                 "csi3_clk_src",
1286                         },
1287                         .num_parents = 1,
1288                         .flags = CLK_SET_RATE_PARENT,
1289                         .ops = &clk_branch2_ops,
1290                 },
1291         },
1292 };
1293
1294 static struct clk_branch camss_csi3rdi_clk = {
1295         .halt_reg = 0x3204,
1296         .clkr = {
1297                 .enable_reg = 0x3204,
1298                 .enable_mask = BIT(0),
1299                 .hw.init = &(struct clk_init_data){
1300                         .name = "camss_csi3rdi_clk",
1301                         .parent_names = (const char *[]){
1302                                 "csi3_clk_src",
1303                         },
1304                         .num_parents = 1,
1305                         .flags = CLK_SET_RATE_PARENT,
1306                         .ops = &clk_branch2_ops,
1307                 },
1308         },
1309 };
1310
1311 static struct clk_branch camss_csi_vfe0_clk = {
1312         .halt_reg = 0x3704,
1313         .clkr = {
1314                 .enable_reg = 0x3704,
1315                 .enable_mask = BIT(0),
1316                 .hw.init = &(struct clk_init_data){
1317                         .name = "camss_csi_vfe0_clk",
1318                         .parent_names = (const char *[]){
1319                                 "vfe0_clk_src",
1320                         },
1321                         .num_parents = 1,
1322                         .flags = CLK_SET_RATE_PARENT,
1323                         .ops = &clk_branch2_ops,
1324                 },
1325         },
1326 };
1327
1328 static struct clk_branch camss_csi_vfe1_clk = {
1329         .halt_reg = 0x3714,
1330         .clkr = {
1331                 .enable_reg = 0x3714,
1332                 .enable_mask = BIT(0),
1333                 .hw.init = &(struct clk_init_data){
1334                         .name = "camss_csi_vfe1_clk",
1335                         .parent_names = (const char *[]){
1336                                 "vfe1_clk_src",
1337                         },
1338                         .num_parents = 1,
1339                         .flags = CLK_SET_RATE_PARENT,
1340                         .ops = &clk_branch2_ops,
1341                 },
1342         },
1343 };
1344
1345 static struct clk_branch camss_gp0_clk = {
1346         .halt_reg = 0x3444,
1347         .clkr = {
1348                 .enable_reg = 0x3444,
1349                 .enable_mask = BIT(0),
1350                 .hw.init = &(struct clk_init_data){
1351                         .name = "camss_gp0_clk",
1352                         .parent_names = (const char *[]){
1353                                 "camss_gp0_clk_src",
1354                         },
1355                         .num_parents = 1,
1356                         .flags = CLK_SET_RATE_PARENT,
1357                         .ops = &clk_branch2_ops,
1358                 },
1359         },
1360 };
1361
1362 static struct clk_branch camss_gp1_clk = {
1363         .halt_reg = 0x3474,
1364         .clkr = {
1365                 .enable_reg = 0x3474,
1366                 .enable_mask = BIT(0),
1367                 .hw.init = &(struct clk_init_data){
1368                         .name = "camss_gp1_clk",
1369                         .parent_names = (const char *[]){
1370                                 "camss_gp1_clk_src",
1371                         },
1372                         .num_parents = 1,
1373                         .flags = CLK_SET_RATE_PARENT,
1374                         .ops = &clk_branch2_ops,
1375                 },
1376         },
1377 };
1378
1379 static struct clk_branch camss_ispif_ahb_clk = {
1380         .halt_reg = 0x3224,
1381         .clkr = {
1382                 .enable_reg = 0x3224,
1383                 .enable_mask = BIT(0),
1384                 .hw.init = &(struct clk_init_data){
1385                         .name = "camss_ispif_ahb_clk",
1386                         .parent_names = (const char *[]){
1387                                 "mmss_ahb_clk_src",
1388                         },
1389                         .num_parents = 1,
1390                         .ops = &clk_branch2_ops,
1391                 },
1392         },
1393 };
1394
1395 static struct clk_branch camss_jpeg_jpeg0_clk = {
1396         .halt_reg = 0x35a8,
1397         .clkr = {
1398                 .enable_reg = 0x35a8,
1399                 .enable_mask = BIT(0),
1400                 .hw.init = &(struct clk_init_data){
1401                         .name = "camss_jpeg_jpeg0_clk",
1402                         .parent_names = (const char *[]){
1403                                 "jpeg0_clk_src",
1404                         },
1405                         .num_parents = 1,
1406                         .flags = CLK_SET_RATE_PARENT,
1407                         .ops = &clk_branch2_ops,
1408                 },
1409         },
1410 };
1411
1412 static struct clk_branch camss_jpeg_jpeg1_clk = {
1413         .halt_reg = 0x35ac,
1414         .clkr = {
1415                 .enable_reg = 0x35ac,
1416                 .enable_mask = BIT(0),
1417                 .hw.init = &(struct clk_init_data){
1418                         .name = "camss_jpeg_jpeg1_clk",
1419                         .parent_names = (const char *[]){
1420                                 "jpeg1_clk_src",
1421                         },
1422                         .num_parents = 1,
1423                         .flags = CLK_SET_RATE_PARENT,
1424                         .ops = &clk_branch2_ops,
1425                 },
1426         },
1427 };
1428
1429 static struct clk_branch camss_jpeg_jpeg2_clk = {
1430         .halt_reg = 0x35b0,
1431         .clkr = {
1432                 .enable_reg = 0x35b0,
1433                 .enable_mask = BIT(0),
1434                 .hw.init = &(struct clk_init_data){
1435                         .name = "camss_jpeg_jpeg2_clk",
1436                         .parent_names = (const char *[]){
1437                                 "jpeg2_clk_src",
1438                         },
1439                         .num_parents = 1,
1440                         .flags = CLK_SET_RATE_PARENT,
1441                         .ops = &clk_branch2_ops,
1442                 },
1443         },
1444 };
1445
1446 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1447         .halt_reg = 0x35b4,
1448         .clkr = {
1449                 .enable_reg = 0x35b4,
1450                 .enable_mask = BIT(0),
1451                 .hw.init = &(struct clk_init_data){
1452                         .name = "camss_jpeg_jpeg_ahb_clk",
1453                         .parent_names = (const char *[]){
1454                                 "mmss_ahb_clk_src",
1455                         },
1456                         .num_parents = 1,
1457                         .ops = &clk_branch2_ops,
1458                 },
1459         },
1460 };
1461
1462 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1463         .halt_reg = 0x35b8,
1464         .clkr = {
1465                 .enable_reg = 0x35b8,
1466                 .enable_mask = BIT(0),
1467                 .hw.init = &(struct clk_init_data){
1468                         .name = "camss_jpeg_jpeg_axi_clk",
1469                         .parent_names = (const char *[]){
1470                                 "mmss_axi_clk_src",
1471                         },
1472                         .num_parents = 1,
1473                         .ops = &clk_branch2_ops,
1474                 },
1475         },
1476 };
1477
1478 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1479         .halt_reg = 0x35bc,
1480         .clkr = {
1481                 .enable_reg = 0x35bc,
1482                 .enable_mask = BIT(0),
1483                 .hw.init = &(struct clk_init_data){
1484                         .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1485                         .parent_names = (const char *[]){
1486                                 "ocmemnoc_clk_src",
1487                         },
1488                         .num_parents = 1,
1489                         .flags = CLK_SET_RATE_PARENT,
1490                         .ops = &clk_branch2_ops,
1491                 },
1492         },
1493 };
1494
1495 static struct clk_branch camss_mclk0_clk = {
1496         .halt_reg = 0x3384,
1497         .clkr = {
1498                 .enable_reg = 0x3384,
1499                 .enable_mask = BIT(0),
1500                 .hw.init = &(struct clk_init_data){
1501                         .name = "camss_mclk0_clk",
1502                         .parent_names = (const char *[]){
1503                                 "mclk0_clk_src",
1504                         },
1505                         .num_parents = 1,
1506                         .flags = CLK_SET_RATE_PARENT,
1507                         .ops = &clk_branch2_ops,
1508                 },
1509         },
1510 };
1511
1512 static struct clk_branch camss_mclk1_clk = {
1513         .halt_reg = 0x33b4,
1514         .clkr = {
1515                 .enable_reg = 0x33b4,
1516                 .enable_mask = BIT(0),
1517                 .hw.init = &(struct clk_init_data){
1518                         .name = "camss_mclk1_clk",
1519                         .parent_names = (const char *[]){
1520                                 "mclk1_clk_src",
1521                         },
1522                         .num_parents = 1,
1523                         .flags = CLK_SET_RATE_PARENT,
1524                         .ops = &clk_branch2_ops,
1525                 },
1526         },
1527 };
1528
1529 static struct clk_branch camss_mclk2_clk = {
1530         .halt_reg = 0x33e4,
1531         .clkr = {
1532                 .enable_reg = 0x33e4,
1533                 .enable_mask = BIT(0),
1534                 .hw.init = &(struct clk_init_data){
1535                         .name = "camss_mclk2_clk",
1536                         .parent_names = (const char *[]){
1537                                 "mclk2_clk_src",
1538                         },
1539                         .num_parents = 1,
1540                         .flags = CLK_SET_RATE_PARENT,
1541                         .ops = &clk_branch2_ops,
1542                 },
1543         },
1544 };
1545
1546 static struct clk_branch camss_mclk3_clk = {
1547         .halt_reg = 0x3414,
1548         .clkr = {
1549                 .enable_reg = 0x3414,
1550                 .enable_mask = BIT(0),
1551                 .hw.init = &(struct clk_init_data){
1552                         .name = "camss_mclk3_clk",
1553                         .parent_names = (const char *[]){
1554                                 "mclk3_clk_src",
1555                         },
1556                         .num_parents = 1,
1557                         .flags = CLK_SET_RATE_PARENT,
1558                         .ops = &clk_branch2_ops,
1559                 },
1560         },
1561 };
1562
1563 static struct clk_branch camss_micro_ahb_clk = {
1564         .halt_reg = 0x3494,
1565         .clkr = {
1566                 .enable_reg = 0x3494,
1567                 .enable_mask = BIT(0),
1568                 .hw.init = &(struct clk_init_data){
1569                         .name = "camss_micro_ahb_clk",
1570                         .parent_names = (const char *[]){
1571                                 "mmss_ahb_clk_src",
1572                         },
1573                         .num_parents = 1,
1574                         .ops = &clk_branch2_ops,
1575                 },
1576         },
1577 };
1578
1579 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1580         .halt_reg = 0x3024,
1581         .clkr = {
1582                 .enable_reg = 0x3024,
1583                 .enable_mask = BIT(0),
1584                 .hw.init = &(struct clk_init_data){
1585                         .name = "camss_phy0_csi0phytimer_clk",
1586                         .parent_names = (const char *[]){
1587                                 "csi0phytimer_clk_src",
1588                         },
1589                         .num_parents = 1,
1590                         .flags = CLK_SET_RATE_PARENT,
1591                         .ops = &clk_branch2_ops,
1592                 },
1593         },
1594 };
1595
1596 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1597         .halt_reg = 0x3054,
1598         .clkr = {
1599                 .enable_reg = 0x3054,
1600                 .enable_mask = BIT(0),
1601                 .hw.init = &(struct clk_init_data){
1602                         .name = "camss_phy1_csi1phytimer_clk",
1603                         .parent_names = (const char *[]){
1604                                 "csi1phytimer_clk_src",
1605                         },
1606                         .num_parents = 1,
1607                         .flags = CLK_SET_RATE_PARENT,
1608                         .ops = &clk_branch2_ops,
1609                 },
1610         },
1611 };
1612
1613 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1614         .halt_reg = 0x3084,
1615         .clkr = {
1616                 .enable_reg = 0x3084,
1617                 .enable_mask = BIT(0),
1618                 .hw.init = &(struct clk_init_data){
1619                         .name = "camss_phy2_csi2phytimer_clk",
1620                         .parent_names = (const char *[]){
1621                                 "csi2phytimer_clk_src",
1622                         },
1623                         .num_parents = 1,
1624                         .flags = CLK_SET_RATE_PARENT,
1625                         .ops = &clk_branch2_ops,
1626                 },
1627         },
1628 };
1629
1630 static struct clk_branch camss_top_ahb_clk = {
1631         .halt_reg = 0x3484,
1632         .clkr = {
1633                 .enable_reg = 0x3484,
1634                 .enable_mask = BIT(0),
1635                 .hw.init = &(struct clk_init_data){
1636                         .name = "camss_top_ahb_clk",
1637                         .parent_names = (const char *[]){
1638                                 "mmss_ahb_clk_src",
1639                         },
1640                         .num_parents = 1,
1641                         .ops = &clk_branch2_ops,
1642                 },
1643         },
1644 };
1645
1646 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1647         .halt_reg = 0x36b4,
1648         .clkr = {
1649                 .enable_reg = 0x36b4,
1650                 .enable_mask = BIT(0),
1651                 .hw.init = &(struct clk_init_data){
1652                         .name = "camss_vfe_cpp_ahb_clk",
1653                         .parent_names = (const char *[]){
1654                                 "mmss_ahb_clk_src",
1655                         },
1656                         .num_parents = 1,
1657                         .ops = &clk_branch2_ops,
1658                 },
1659         },
1660 };
1661
1662 static struct clk_branch camss_vfe_cpp_clk = {
1663         .halt_reg = 0x36b0,
1664         .clkr = {
1665                 .enable_reg = 0x36b0,
1666                 .enable_mask = BIT(0),
1667                 .hw.init = &(struct clk_init_data){
1668                         .name = "camss_vfe_cpp_clk",
1669                         .parent_names = (const char *[]){
1670                                 "cpp_clk_src",
1671                         },
1672                         .num_parents = 1,
1673                         .flags = CLK_SET_RATE_PARENT,
1674                         .ops = &clk_branch2_ops,
1675                 },
1676         },
1677 };
1678
1679 static struct clk_branch camss_vfe_vfe0_clk = {
1680         .halt_reg = 0x36a8,
1681         .clkr = {
1682                 .enable_reg = 0x36a8,
1683                 .enable_mask = BIT(0),
1684                 .hw.init = &(struct clk_init_data){
1685                         .name = "camss_vfe_vfe0_clk",
1686                         .parent_names = (const char *[]){
1687                                 "vfe0_clk_src",
1688                         },
1689                         .num_parents = 1,
1690                         .flags = CLK_SET_RATE_PARENT,
1691                         .ops = &clk_branch2_ops,
1692                 },
1693         },
1694 };
1695
1696 static struct clk_branch camss_vfe_vfe1_clk = {
1697         .halt_reg = 0x36ac,
1698         .clkr = {
1699                 .enable_reg = 0x36ac,
1700                 .enable_mask = BIT(0),
1701                 .hw.init = &(struct clk_init_data){
1702                         .name = "camss_vfe_vfe1_clk",
1703                         .parent_names = (const char *[]){
1704                                 "vfe1_clk_src",
1705                         },
1706                         .num_parents = 1,
1707                         .flags = CLK_SET_RATE_PARENT,
1708                         .ops = &clk_branch2_ops,
1709                 },
1710         },
1711 };
1712
1713 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1714         .halt_reg = 0x36b8,
1715         .clkr = {
1716                 .enable_reg = 0x36b8,
1717                 .enable_mask = BIT(0),
1718                 .hw.init = &(struct clk_init_data){
1719                         .name = "camss_vfe_vfe_ahb_clk",
1720                         .parent_names = (const char *[]){
1721                                 "mmss_ahb_clk_src",
1722                         },
1723                         .num_parents = 1,
1724                         .ops = &clk_branch2_ops,
1725                 },
1726         },
1727 };
1728
1729 static struct clk_branch camss_vfe_vfe_axi_clk = {
1730         .halt_reg = 0x36bc,
1731         .clkr = {
1732                 .enable_reg = 0x36bc,
1733                 .enable_mask = BIT(0),
1734                 .hw.init = &(struct clk_init_data){
1735                         .name = "camss_vfe_vfe_axi_clk",
1736                         .parent_names = (const char *[]){
1737                                 "mmss_axi_clk_src",
1738                         },
1739                         .num_parents = 1,
1740                         .ops = &clk_branch2_ops,
1741                 },
1742         },
1743 };
1744
1745 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1746         .halt_reg = 0x36c0,
1747         .clkr = {
1748                 .enable_reg = 0x36c0,
1749                 .enable_mask = BIT(0),
1750                 .hw.init = &(struct clk_init_data){
1751                         .name = "camss_vfe_vfe_ocmemnoc_clk",
1752                         .parent_names = (const char *[]){
1753                                 "ocmemnoc_clk_src",
1754                         },
1755                         .num_parents = 1,
1756                         .flags = CLK_SET_RATE_PARENT,
1757                         .ops = &clk_branch2_ops,
1758                 },
1759         },
1760 };
1761
1762 static struct clk_branch mdss_ahb_clk = {
1763         .halt_reg = 0x2308,
1764         .clkr = {
1765                 .enable_reg = 0x2308,
1766                 .enable_mask = BIT(0),
1767                 .hw.init = &(struct clk_init_data){
1768                         .name = "mdss_ahb_clk",
1769                         .parent_names = (const char *[]){
1770                                 "mmss_ahb_clk_src",
1771                         },
1772                         .num_parents = 1,
1773                         .ops = &clk_branch2_ops,
1774                 },
1775         },
1776 };
1777
1778 static struct clk_branch mdss_axi_clk = {
1779         .halt_reg = 0x2310,
1780         .clkr = {
1781                 .enable_reg = 0x2310,
1782                 .enable_mask = BIT(0),
1783                 .hw.init = &(struct clk_init_data){
1784                         .name = "mdss_axi_clk",
1785                         .parent_names = (const char *[]){
1786                                 "mmss_axi_clk_src",
1787                         },
1788                         .num_parents = 1,
1789                         .flags = CLK_SET_RATE_PARENT,
1790                         .ops = &clk_branch2_ops,
1791                 },
1792         },
1793 };
1794
1795 static struct clk_branch mdss_byte0_clk = {
1796         .halt_reg = 0x233c,
1797         .clkr = {
1798                 .enable_reg = 0x233c,
1799                 .enable_mask = BIT(0),
1800                 .hw.init = &(struct clk_init_data){
1801                         .name = "mdss_byte0_clk",
1802                         .parent_names = (const char *[]){
1803                                 "byte0_clk_src",
1804                         },
1805                         .num_parents = 1,
1806                         .flags = CLK_SET_RATE_PARENT,
1807                         .ops = &clk_branch2_ops,
1808                 },
1809         },
1810 };
1811
1812 static struct clk_branch mdss_byte1_clk = {
1813         .halt_reg = 0x2340,
1814         .clkr = {
1815                 .enable_reg = 0x2340,
1816                 .enable_mask = BIT(0),
1817                 .hw.init = &(struct clk_init_data){
1818                         .name = "mdss_byte1_clk",
1819                         .parent_names = (const char *[]){
1820                                 "byte1_clk_src",
1821                         },
1822                         .num_parents = 1,
1823                         .flags = CLK_SET_RATE_PARENT,
1824                         .ops = &clk_branch2_ops,
1825                 },
1826         },
1827 };
1828
1829 static struct clk_branch mdss_edpaux_clk = {
1830         .halt_reg = 0x2334,
1831         .clkr = {
1832                 .enable_reg = 0x2334,
1833                 .enable_mask = BIT(0),
1834                 .hw.init = &(struct clk_init_data){
1835                         .name = "mdss_edpaux_clk",
1836                         .parent_names = (const char *[]){
1837                                 "edpaux_clk_src",
1838                         },
1839                         .num_parents = 1,
1840                         .flags = CLK_SET_RATE_PARENT,
1841                         .ops = &clk_branch2_ops,
1842                 },
1843         },
1844 };
1845
1846 static struct clk_branch mdss_edplink_clk = {
1847         .halt_reg = 0x2330,
1848         .clkr = {
1849                 .enable_reg = 0x2330,
1850                 .enable_mask = BIT(0),
1851                 .hw.init = &(struct clk_init_data){
1852                         .name = "mdss_edplink_clk",
1853                         .parent_names = (const char *[]){
1854                                 "edplink_clk_src",
1855                         },
1856                         .num_parents = 1,
1857                         .flags = CLK_SET_RATE_PARENT,
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch mdss_edppixel_clk = {
1864         .halt_reg = 0x232c,
1865         .clkr = {
1866                 .enable_reg = 0x232c,
1867                 .enable_mask = BIT(0),
1868                 .hw.init = &(struct clk_init_data){
1869                         .name = "mdss_edppixel_clk",
1870                         .parent_names = (const char *[]){
1871                                 "edppixel_clk_src",
1872                         },
1873                         .num_parents = 1,
1874                         .flags = CLK_SET_RATE_PARENT,
1875                         .ops = &clk_branch2_ops,
1876                 },
1877         },
1878 };
1879
1880 static struct clk_branch mdss_esc0_clk = {
1881         .halt_reg = 0x2344,
1882         .clkr = {
1883                 .enable_reg = 0x2344,
1884                 .enable_mask = BIT(0),
1885                 .hw.init = &(struct clk_init_data){
1886                         .name = "mdss_esc0_clk",
1887                         .parent_names = (const char *[]){
1888                                 "esc0_clk_src",
1889                         },
1890                         .num_parents = 1,
1891                         .flags = CLK_SET_RATE_PARENT,
1892                         .ops = &clk_branch2_ops,
1893                 },
1894         },
1895 };
1896
1897 static struct clk_branch mdss_esc1_clk = {
1898         .halt_reg = 0x2348,
1899         .clkr = {
1900                 .enable_reg = 0x2348,
1901                 .enable_mask = BIT(0),
1902                 .hw.init = &(struct clk_init_data){
1903                         .name = "mdss_esc1_clk",
1904                         .parent_names = (const char *[]){
1905                                 "esc1_clk_src",
1906                         },
1907                         .num_parents = 1,
1908                         .flags = CLK_SET_RATE_PARENT,
1909                         .ops = &clk_branch2_ops,
1910                 },
1911         },
1912 };
1913
1914 static struct clk_branch mdss_extpclk_clk = {
1915         .halt_reg = 0x2324,
1916         .clkr = {
1917                 .enable_reg = 0x2324,
1918                 .enable_mask = BIT(0),
1919                 .hw.init = &(struct clk_init_data){
1920                         .name = "mdss_extpclk_clk",
1921                         .parent_names = (const char *[]){
1922                                 "extpclk_clk_src",
1923                         },
1924                         .num_parents = 1,
1925                         .flags = CLK_SET_RATE_PARENT,
1926                         .ops = &clk_branch2_ops,
1927                 },
1928         },
1929 };
1930
1931 static struct clk_branch mdss_hdmi_ahb_clk = {
1932         .halt_reg = 0x230c,
1933         .clkr = {
1934                 .enable_reg = 0x230c,
1935                 .enable_mask = BIT(0),
1936                 .hw.init = &(struct clk_init_data){
1937                         .name = "mdss_hdmi_ahb_clk",
1938                         .parent_names = (const char *[]){
1939                                 "mmss_ahb_clk_src",
1940                         },
1941                         .num_parents = 1,
1942                         .ops = &clk_branch2_ops,
1943                 },
1944         },
1945 };
1946
1947 static struct clk_branch mdss_hdmi_clk = {
1948         .halt_reg = 0x2338,
1949         .clkr = {
1950                 .enable_reg = 0x2338,
1951                 .enable_mask = BIT(0),
1952                 .hw.init = &(struct clk_init_data){
1953                         .name = "mdss_hdmi_clk",
1954                         .parent_names = (const char *[]){
1955                                 "hdmi_clk_src",
1956                         },
1957                         .num_parents = 1,
1958                         .flags = CLK_SET_RATE_PARENT,
1959                         .ops = &clk_branch2_ops,
1960                 },
1961         },
1962 };
1963
1964 static struct clk_branch mdss_mdp_clk = {
1965         .halt_reg = 0x231c,
1966         .clkr = {
1967                 .enable_reg = 0x231c,
1968                 .enable_mask = BIT(0),
1969                 .hw.init = &(struct clk_init_data){
1970                         .name = "mdss_mdp_clk",
1971                         .parent_names = (const char *[]){
1972                                 "mdp_clk_src",
1973                         },
1974                         .num_parents = 1,
1975                         .flags = CLK_SET_RATE_PARENT,
1976                         .ops = &clk_branch2_ops,
1977                 },
1978         },
1979 };
1980
1981 static struct clk_branch mdss_mdp_lut_clk = {
1982         .halt_reg = 0x2320,
1983         .clkr = {
1984                 .enable_reg = 0x2320,
1985                 .enable_mask = BIT(0),
1986                 .hw.init = &(struct clk_init_data){
1987                         .name = "mdss_mdp_lut_clk",
1988                         .parent_names = (const char *[]){
1989                                 "mdp_clk_src",
1990                         },
1991                         .num_parents = 1,
1992                         .flags = CLK_SET_RATE_PARENT,
1993                         .ops = &clk_branch2_ops,
1994                 },
1995         },
1996 };
1997
1998 static struct clk_branch mdss_pclk0_clk = {
1999         .halt_reg = 0x2314,
2000         .clkr = {
2001                 .enable_reg = 0x2314,
2002                 .enable_mask = BIT(0),
2003                 .hw.init = &(struct clk_init_data){
2004                         .name = "mdss_pclk0_clk",
2005                         .parent_names = (const char *[]){
2006                                 "pclk0_clk_src",
2007                         },
2008                         .num_parents = 1,
2009                         .flags = CLK_SET_RATE_PARENT,
2010                         .ops = &clk_branch2_ops,
2011                 },
2012         },
2013 };
2014
2015 static struct clk_branch mdss_pclk1_clk = {
2016         .halt_reg = 0x2318,
2017         .clkr = {
2018                 .enable_reg = 0x2318,
2019                 .enable_mask = BIT(0),
2020                 .hw.init = &(struct clk_init_data){
2021                         .name = "mdss_pclk1_clk",
2022                         .parent_names = (const char *[]){
2023                                 "pclk1_clk_src",
2024                         },
2025                         .num_parents = 1,
2026                         .flags = CLK_SET_RATE_PARENT,
2027                         .ops = &clk_branch2_ops,
2028                 },
2029         },
2030 };
2031
2032 static struct clk_branch mdss_vsync_clk = {
2033         .halt_reg = 0x2328,
2034         .clkr = {
2035                 .enable_reg = 0x2328,
2036                 .enable_mask = BIT(0),
2037                 .hw.init = &(struct clk_init_data){
2038                         .name = "mdss_vsync_clk",
2039                         .parent_names = (const char *[]){
2040                                 "vsync_clk_src",
2041                         },
2042                         .num_parents = 1,
2043                         .flags = CLK_SET_RATE_PARENT,
2044                         .ops = &clk_branch2_ops,
2045                 },
2046         },
2047 };
2048
2049 static struct clk_branch mmss_misc_ahb_clk = {
2050         .halt_reg = 0x502c,
2051         .clkr = {
2052                 .enable_reg = 0x502c,
2053                 .enable_mask = BIT(0),
2054                 .hw.init = &(struct clk_init_data){
2055                         .name = "mmss_misc_ahb_clk",
2056                         .parent_names = (const char *[]){
2057                                 "mmss_ahb_clk_src",
2058                         },
2059                         .num_parents = 1,
2060                         .ops = &clk_branch2_ops,
2061                 },
2062         },
2063 };
2064
2065 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2066         .halt_reg = 0x5024,
2067         .clkr = {
2068                 .enable_reg = 0x5024,
2069                 .enable_mask = BIT(0),
2070                 .hw.init = &(struct clk_init_data){
2071                         .name = "mmss_mmssnoc_ahb_clk",
2072                         .parent_names = (const char *[]){
2073                                 "mmss_ahb_clk_src",
2074                         },
2075                         .num_parents = 1,
2076                         .ops = &clk_branch2_ops,
2077                         .flags = CLK_IGNORE_UNUSED,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2083         .halt_reg = 0x5028,
2084         .clkr = {
2085                 .enable_reg = 0x5028,
2086                 .enable_mask = BIT(0),
2087                 .hw.init = &(struct clk_init_data){
2088                         .name = "mmss_mmssnoc_bto_ahb_clk",
2089                         .parent_names = (const char *[]){
2090                                 "mmss_ahb_clk_src",
2091                         },
2092                         .num_parents = 1,
2093                         .ops = &clk_branch2_ops,
2094                         .flags = CLK_IGNORE_UNUSED,
2095                 },
2096         },
2097 };
2098
2099 static struct clk_branch mmss_mmssnoc_axi_clk = {
2100         .halt_reg = 0x506c,
2101         .clkr = {
2102                 .enable_reg = 0x506c,
2103                 .enable_mask = BIT(0),
2104                 .hw.init = &(struct clk_init_data){
2105                         .name = "mmss_mmssnoc_axi_clk",
2106                         .parent_names = (const char *[]){
2107                                 "mmss_axi_clk_src",
2108                         },
2109                         .num_parents = 1,
2110                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2111                         .ops = &clk_branch2_ops,
2112                 },
2113         },
2114 };
2115
2116 static struct clk_branch mmss_s0_axi_clk = {
2117         .halt_reg = 0x5064,
2118         .clkr = {
2119                 .enable_reg = 0x5064,
2120                 .enable_mask = BIT(0),
2121                 .hw.init = &(struct clk_init_data){
2122                         .name = "mmss_s0_axi_clk",
2123                         .parent_names = (const char *[]){
2124                                 "mmss_axi_clk_src",
2125                         },
2126                         .num_parents = 1,
2127                         .ops = &clk_branch2_ops,
2128                         .flags = CLK_IGNORE_UNUSED,
2129                 },
2130         },
2131 };
2132
2133 static struct clk_branch ocmemcx_ahb_clk = {
2134         .halt_reg = 0x405c,
2135         .clkr = {
2136                 .enable_reg = 0x405c,
2137                 .enable_mask = BIT(0),
2138                 .hw.init = &(struct clk_init_data){
2139                         .name = "ocmemcx_ahb_clk",
2140                         .parent_names = (const char *[]){
2141                                 "mmss_ahb_clk_src",
2142                         },
2143                         .num_parents = 1,
2144                         .ops = &clk_branch2_ops,
2145                 },
2146         },
2147 };
2148
2149 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2150         .halt_reg = 0x4058,
2151         .clkr = {
2152                 .enable_reg = 0x4058,
2153                 .enable_mask = BIT(0),
2154                 .hw.init = &(struct clk_init_data){
2155                         .name = "ocmemcx_ocmemnoc_clk",
2156                         .parent_names = (const char *[]){
2157                                 "ocmemnoc_clk_src",
2158                         },
2159                         .num_parents = 1,
2160                         .flags = CLK_SET_RATE_PARENT,
2161                         .ops = &clk_branch2_ops,
2162                 },
2163         },
2164 };
2165
2166 static struct clk_branch oxili_ocmemgx_clk = {
2167         .halt_reg = 0x402c,
2168         .clkr = {
2169                 .enable_reg = 0x402c,
2170                 .enable_mask = BIT(0),
2171                 .hw.init = &(struct clk_init_data){
2172                         .name = "oxili_ocmemgx_clk",
2173                         .parent_names = (const char *[]){
2174                                 "gfx3d_clk_src",
2175                         },
2176                         .num_parents = 1,
2177                         .flags = CLK_SET_RATE_PARENT,
2178                         .ops = &clk_branch2_ops,
2179                 },
2180         },
2181 };
2182
2183 static struct clk_branch ocmemnoc_clk = {
2184         .halt_reg = 0x50b4,
2185         .clkr = {
2186                 .enable_reg = 0x50b4,
2187                 .enable_mask = BIT(0),
2188                 .hw.init = &(struct clk_init_data){
2189                         .name = "ocmemnoc_clk",
2190                         .parent_names = (const char *[]){
2191                                 "ocmemnoc_clk_src",
2192                         },
2193                         .num_parents = 1,
2194                         .flags = CLK_SET_RATE_PARENT,
2195                         .ops = &clk_branch2_ops,
2196                 },
2197         },
2198 };
2199
2200 static struct clk_branch oxili_gfx3d_clk = {
2201         .halt_reg = 0x4028,
2202         .clkr = {
2203                 .enable_reg = 0x4028,
2204                 .enable_mask = BIT(0),
2205                 .hw.init = &(struct clk_init_data){
2206                         .name = "oxili_gfx3d_clk",
2207                         .parent_names = (const char *[]){
2208                                 "gfx3d_clk_src",
2209                         },
2210                         .num_parents = 1,
2211                         .flags = CLK_SET_RATE_PARENT,
2212                         .ops = &clk_branch2_ops,
2213                 },
2214         },
2215 };
2216
2217 static struct clk_branch oxilicx_ahb_clk = {
2218         .halt_reg = 0x403c,
2219         .clkr = {
2220                 .enable_reg = 0x403c,
2221                 .enable_mask = BIT(0),
2222                 .hw.init = &(struct clk_init_data){
2223                         .name = "oxilicx_ahb_clk",
2224                         .parent_names = (const char *[]){
2225                                 "mmss_ahb_clk_src",
2226                         },
2227                         .num_parents = 1,
2228                         .ops = &clk_branch2_ops,
2229                 },
2230         },
2231 };
2232
2233 static struct clk_branch oxilicx_axi_clk = {
2234         .halt_reg = 0x4038,
2235         .clkr = {
2236                 .enable_reg = 0x4038,
2237                 .enable_mask = BIT(0),
2238                 .hw.init = &(struct clk_init_data){
2239                         .name = "oxilicx_axi_clk",
2240                         .parent_names = (const char *[]){
2241                                 "mmss_axi_clk_src",
2242                         },
2243                         .num_parents = 1,
2244                         .ops = &clk_branch2_ops,
2245                 },
2246         },
2247 };
2248
2249 static struct clk_branch venus0_ahb_clk = {
2250         .halt_reg = 0x1030,
2251         .clkr = {
2252                 .enable_reg = 0x1030,
2253                 .enable_mask = BIT(0),
2254                 .hw.init = &(struct clk_init_data){
2255                         .name = "venus0_ahb_clk",
2256                         .parent_names = (const char *[]){
2257                                 "mmss_ahb_clk_src",
2258                         },
2259                         .num_parents = 1,
2260                         .ops = &clk_branch2_ops,
2261                 },
2262         },
2263 };
2264
2265 static struct clk_branch venus0_axi_clk = {
2266         .halt_reg = 0x1034,
2267         .clkr = {
2268                 .enable_reg = 0x1034,
2269                 .enable_mask = BIT(0),
2270                 .hw.init = &(struct clk_init_data){
2271                         .name = "venus0_axi_clk",
2272                         .parent_names = (const char *[]){
2273                                 "mmss_axi_clk_src",
2274                         },
2275                         .num_parents = 1,
2276                         .ops = &clk_branch2_ops,
2277                 },
2278         },
2279 };
2280
2281 static struct clk_branch venus0_ocmemnoc_clk = {
2282         .halt_reg = 0x1038,
2283         .clkr = {
2284                 .enable_reg = 0x1038,
2285                 .enable_mask = BIT(0),
2286                 .hw.init = &(struct clk_init_data){
2287                         .name = "venus0_ocmemnoc_clk",
2288                         .parent_names = (const char *[]){
2289                                 "ocmemnoc_clk_src",
2290                         },
2291                         .num_parents = 1,
2292                         .flags = CLK_SET_RATE_PARENT,
2293                         .ops = &clk_branch2_ops,
2294                 },
2295         },
2296 };
2297
2298 static struct clk_branch venus0_vcodec0_clk = {
2299         .halt_reg = 0x1028,
2300         .clkr = {
2301                 .enable_reg = 0x1028,
2302                 .enable_mask = BIT(0),
2303                 .hw.init = &(struct clk_init_data){
2304                         .name = "venus0_vcodec0_clk",
2305                         .parent_names = (const char *[]){
2306                                 "vcodec0_clk_src",
2307                         },
2308                         .num_parents = 1,
2309                         .flags = CLK_SET_RATE_PARENT,
2310                         .ops = &clk_branch2_ops,
2311                 },
2312         },
2313 };
2314
2315 static const struct pll_config mmpll1_config = {
2316         .l = 60,
2317         .m = 25,
2318         .n = 32,
2319         .vco_val = 0x0,
2320         .vco_mask = 0x3 << 20,
2321         .pre_div_val = 0x0,
2322         .pre_div_mask = 0x7 << 12,
2323         .post_div_val = 0x0,
2324         .post_div_mask = 0x3 << 8,
2325         .mn_ena_mask = BIT(24),
2326         .main_output_mask = BIT(0),
2327 };
2328
2329 static struct pll_config mmpll3_config = {
2330         .l = 48,
2331         .m = 7,
2332         .n = 16,
2333         .vco_val = 0x0,
2334         .vco_mask = 0x3 << 20,
2335         .pre_div_val = 0x0,
2336         .pre_div_mask = 0x7 << 12,
2337         .post_div_val = 0x0,
2338         .post_div_mask = 0x3 << 8,
2339         .mn_ena_mask = BIT(24),
2340         .main_output_mask = BIT(0),
2341         .aux_output_mask = BIT(1),
2342 };
2343
2344 static struct gdsc venus0_gdsc = {
2345         .gdscr = 0x1024,
2346         .cxcs = (unsigned int []){ 0x1028 },
2347         .cxc_count = 1,
2348         .resets = (unsigned int []){ VENUS0_RESET },
2349         .reset_count = 1,
2350         .pd = {
2351                 .name = "venus0",
2352         },
2353         .pwrsts = PWRSTS_ON,
2354 };
2355
2356 static struct gdsc mdss_gdsc = {
2357         .gdscr = 0x2304,
2358         .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2359         .cxc_count = 2,
2360         .pd = {
2361                 .name = "mdss",
2362         },
2363         .pwrsts = PWRSTS_RET_ON,
2364 };
2365
2366 static struct gdsc camss_jpeg_gdsc = {
2367         .gdscr = 0x35a4,
2368         .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2369         .cxc_count = 3,
2370         .pd = {
2371                 .name = "camss_jpeg",
2372         },
2373         .pwrsts = PWRSTS_OFF_ON,
2374 };
2375
2376 static struct gdsc camss_vfe_gdsc = {
2377         .gdscr = 0x36a4,
2378         .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2379         .cxc_count = 5,
2380         .pd = {
2381                 .name = "camss_vfe",
2382         },
2383         .pwrsts = PWRSTS_OFF_ON,
2384 };
2385
2386 static struct gdsc oxili_gdsc = {
2387         .gdscr = 0x4024,
2388         .cxcs = (unsigned int []){ 0x4028 },
2389         .cxc_count = 1,
2390         .pd = {
2391                 .name = "oxili",
2392         },
2393         .pwrsts = PWRSTS_OFF_ON,
2394 };
2395
2396 static struct gdsc oxilicx_gdsc = {
2397         .gdscr = 0x4034,
2398         .pd = {
2399                 .name = "oxilicx",
2400         },
2401         .parent = &oxili_gdsc.pd,
2402         .pwrsts = PWRSTS_OFF_ON,
2403 };
2404
2405 static struct clk_regmap *mmcc_msm8974_clocks[] = {
2406         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2407         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2408         [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2409         [MMPLL0] = &mmpll0.clkr,
2410         [MMPLL0_VOTE] = &mmpll0_vote,
2411         [MMPLL1] = &mmpll1.clkr,
2412         [MMPLL1_VOTE] = &mmpll1_vote,
2413         [MMPLL2] = &mmpll2.clkr,
2414         [MMPLL3] = &mmpll3.clkr,
2415         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2416         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2417         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2418         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2419         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2420         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2421         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2422         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2423         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2424         [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2425         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2426         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2427         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2428         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2429         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2430         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2431         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2432         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2433         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2434         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2435         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2436         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2437         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2438         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2439         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2440         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2441         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2442         [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2443         [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2444         [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2445         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2446         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2447         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2448         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2449         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2450         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2451         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2452         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2453         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2454         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2455         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2456         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2457         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2458         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2459         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2460         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2461         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2462         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2463         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2464         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2465         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2466         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2467         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2468         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2469         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2470         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2471         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2472         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2473         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2474         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2475         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2476         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2477         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2478         [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2479         [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2480         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2481         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2482         [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2483         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2484         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2485         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2486         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2487         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2488         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2489         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2490         [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2491         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2492         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2493         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2494         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2495         [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2496         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2497         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2498         [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2499         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2500         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2501         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2502         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2503         [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2504         [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2505         [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2506         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2507         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2508         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2509         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2510         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2511         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2512         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2513         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2514         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2515         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2516         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2517         [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2518         [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2519         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2520         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2521         [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2522         [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2523         [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2524         [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2525         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2526         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2527         [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2528         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2529         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2530         [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2531         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2532 };
2533
2534 static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2535         [SPDM_RESET] = { 0x0200 },
2536         [SPDM_RM_RESET] = { 0x0300 },
2537         [VENUS0_RESET] = { 0x1020 },
2538         [MDSS_RESET] = { 0x2300 },
2539         [CAMSS_PHY0_RESET] = { 0x3020 },
2540         [CAMSS_PHY1_RESET] = { 0x3050 },
2541         [CAMSS_PHY2_RESET] = { 0x3080 },
2542         [CAMSS_CSI0_RESET] = { 0x30b0 },
2543         [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2544         [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2545         [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2546         [CAMSS_CSI1_RESET] = { 0x3120 },
2547         [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2548         [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2549         [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2550         [CAMSS_CSI2_RESET] = { 0x3180 },
2551         [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2552         [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2553         [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2554         [CAMSS_CSI3_RESET] = { 0x31e0 },
2555         [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2556         [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2557         [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2558         [CAMSS_ISPIF_RESET] = { 0x3220 },
2559         [CAMSS_CCI_RESET] = { 0x3340 },
2560         [CAMSS_MCLK0_RESET] = { 0x3380 },
2561         [CAMSS_MCLK1_RESET] = { 0x33b0 },
2562         [CAMSS_MCLK2_RESET] = { 0x33e0 },
2563         [CAMSS_MCLK3_RESET] = { 0x3410 },
2564         [CAMSS_GP0_RESET] = { 0x3440 },
2565         [CAMSS_GP1_RESET] = { 0x3470 },
2566         [CAMSS_TOP_RESET] = { 0x3480 },
2567         [CAMSS_MICRO_RESET] = { 0x3490 },
2568         [CAMSS_JPEG_RESET] = { 0x35a0 },
2569         [CAMSS_VFE_RESET] = { 0x36a0 },
2570         [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2571         [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2572         [OXILI_RESET] = { 0x4020 },
2573         [OXILICX_RESET] = { 0x4030 },
2574         [OCMEMCX_RESET] = { 0x4050 },
2575         [MMSS_RBCRP_RESET] = { 0x4080 },
2576         [MMSSNOCAHB_RESET] = { 0x5020 },
2577         [MMSSNOCAXI_RESET] = { 0x5060 },
2578         [OCMEMNOC_RESET] = { 0x50b0 },
2579 };
2580
2581 static struct gdsc *mmcc_msm8974_gdscs[] = {
2582         [VENUS0_GDSC] = &venus0_gdsc,
2583         [MDSS_GDSC] = &mdss_gdsc,
2584         [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2585         [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2586         [OXILI_GDSC] = &oxili_gdsc,
2587         [OXILICX_GDSC] = &oxilicx_gdsc,
2588 };
2589
2590 static const struct regmap_config mmcc_msm8974_regmap_config = {
2591         .reg_bits       = 32,
2592         .reg_stride     = 4,
2593         .val_bits       = 32,
2594         .max_register   = 0x5104,
2595         .fast_io        = true,
2596 };
2597
2598 static const struct qcom_cc_desc mmcc_msm8974_desc = {
2599         .config = &mmcc_msm8974_regmap_config,
2600         .clks = mmcc_msm8974_clocks,
2601         .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2602         .resets = mmcc_msm8974_resets,
2603         .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2604         .gdscs = mmcc_msm8974_gdscs,
2605         .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
2606 };
2607
2608 static const struct of_device_id mmcc_msm8974_match_table[] = {
2609         { .compatible = "qcom,mmcc-msm8974" },
2610         { }
2611 };
2612 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2613
2614 static int mmcc_msm8974_probe(struct platform_device *pdev)
2615 {
2616         struct regmap *regmap;
2617
2618         regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
2619         if (IS_ERR(regmap))
2620                 return PTR_ERR(regmap);
2621
2622         clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2623         clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2624
2625         return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
2626 }
2627
2628 static struct platform_driver mmcc_msm8974_driver = {
2629         .probe          = mmcc_msm8974_probe,
2630         .driver         = {
2631                 .name   = "mmcc-msm8974",
2632                 .of_match_table = mmcc_msm8974_match_table,
2633         },
2634 };
2635 module_platform_driver(mmcc_msm8974_driver);
2636
2637 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2638 MODULE_LICENSE("GPL v2");
2639 MODULE_ALIAS("platform:mmcc-msm8974");