drivers/clk/renesas/r8a7790-cpg-mssr.c

   1 /*
   2  * r8a7790 Clock Pulse Generator / Module Standby and Software Reset
   3  *
   4  * Copyright (C) 2017 Glider bvba
   5  *
   6  * Based on clk-rcar-gen2.c
   7  *
   8  * Copyright (C) 2013 Ideas On Board SPRL
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; version 2 of the License.
  13  */
  14
  15 #include <linux/device.h>
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/soc/renesas/rcar-rst.h>
  19
  20 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
  21
  22 #include "renesas-cpg-mssr.h"
  23 #include "rcar-gen2-cpg.h"
  24
  25 enum clk_ids {
  26         /* Core Clock Outputs exported to DT */
  27         LAST_DT_CORE_CLK = R8A7790_CLK_OSC,
  28
  29         /* External Input Clocks */
  30         CLK_EXTAL,
  31         CLK_USB_EXTAL,
  32
  33         /* Internal Core Clocks */
  34         CLK_MAIN,
  35         CLK_PLL0,
  36         CLK_PLL1,
  37         CLK_PLL3,
  38         CLK_PLL1_DIV2,
  39
  40         /* Module Clocks */
  41         MOD_CLK_BASE
  42 };
  43
  44 static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
  45         /* External Clock Inputs */
  46         DEF_INPUT("extal",     CLK_EXTAL),
  47         DEF_INPUT("usb_extal", CLK_USB_EXTAL),
  48
  49         /* Internal Core Clocks */
  50         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
  51         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
  52         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
  53         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
  54
  55         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
  56
  57         /* Core Clock Outputs */
  58         DEF_BASE("z",    R8A7790_CLK_Z,    CLK_TYPE_GEN2_Z,    CLK_PLL0),
  59         DEF_BASE("lb",   R8A7790_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
  60         DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
  61         DEF_BASE("sdh",  R8A7790_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
  62         DEF_BASE("sd0",  R8A7790_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
  63         DEF_BASE("sd1",  R8A7790_CLK_SD1,  CLK_TYPE_GEN2_SD1,  CLK_PLL1),
  64         DEF_BASE("qspi", R8A7790_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
  65         DEF_BASE("rcan", R8A7790_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
  66
  67         DEF_FIXED("z2",     R8A7790_CLK_Z2,    CLK_PLL1,          2, 1),
  68         DEF_FIXED("zg",     R8A7790_CLK_ZG,    CLK_PLL1,          3, 1),
  69         DEF_FIXED("zx",     R8A7790_CLK_ZX,    CLK_PLL1,          3, 1),
  70         DEF_FIXED("zs",     R8A7790_CLK_ZS,    CLK_PLL1,          6, 1),
  71         DEF_FIXED("hp",     R8A7790_CLK_HP,    CLK_PLL1,         12, 1),
  72         DEF_FIXED("i",      R8A7790_CLK_I,     CLK_PLL1,          2, 1),
  73         DEF_FIXED("b",      R8A7790_CLK_B,     CLK_PLL1,         12, 1),
  74         DEF_FIXED("p",      R8A7790_CLK_P,     CLK_PLL1,         24, 1),
  75         DEF_FIXED("cl",     R8A7790_CLK_CL,    CLK_PLL1,         48, 1),
  76         DEF_FIXED("m2",     R8A7790_CLK_M2,    CLK_PLL1,          8, 1),
  77         DEF_FIXED("imp",    R8A7790_CLK_IMP,   CLK_PLL1,          4, 1),
  78         DEF_FIXED("zb3",    R8A7790_CLK_ZB3,   CLK_PLL3,          4, 1),
  79         DEF_FIXED("zb3d2",  R8A7790_CLK_ZB3D2, CLK_PLL3,          8, 1),
  80         DEF_FIXED("ddr",    R8A7790_CLK_DDR,   CLK_PLL3,          8, 1),
  81         DEF_FIXED("mp",     R8A7790_CLK_MP,    CLK_PLL1_DIV2,    15, 1),
  82         DEF_FIXED("cp",     R8A7790_CLK_CP,    CLK_EXTAL,         2, 1),
  83         DEF_FIXED("r",      R8A7790_CLK_R,     CLK_PLL1,      49152, 1),
  84         DEF_FIXED("osc",    R8A7790_CLK_OSC,   CLK_PLL1,      12288, 1),
  85
  86         DEF_DIV6P1("sd2",   R8A7790_CLK_SD2,   CLK_PLL1_DIV2, 0x078),
  87         DEF_DIV6P1("sd3",   R8A7790_CLK_SD3,   CLK_PLL1_DIV2, 0x26c),
  88         DEF_DIV6P1("mmc0",  R8A7790_CLK_MMC0,  CLK_PLL1_DIV2, 0x240),
  89         DEF_DIV6P1("mmc1",  R8A7790_CLK_MMC1,  CLK_PLL1_DIV2, 0x244),
  90         DEF_DIV6P1("ssp",   R8A7790_CLK_SSP,   CLK_PLL1_DIV2, 0x248),
  91         DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
  92 };
  93
  94 static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
  95         DEF_MOD("msiof0",                  0,   R8A7790_CLK_MP),
  96         DEF_MOD("vcp1",                  100,   R8A7790_CLK_ZS),
  97         DEF_MOD("vcp0",                  101,   R8A7790_CLK_ZS),
  98         DEF_MOD("vpc1",                  102,   R8A7790_CLK_ZS),
  99         DEF_MOD("vpc0",                  103,   R8A7790_CLK_ZS),
 100         DEF_MOD("jpu",                   106,   R8A7790_CLK_M2),
 101         DEF_MOD("ssp1",                  109,   R8A7790_CLK_ZS),
 102         DEF_MOD("tmu1",                  111,   R8A7790_CLK_P),
 103         DEF_MOD("3dg",                   112,   R8A7790_CLK_ZG),
 104         DEF_MOD("2d-dmac",               115,   R8A7790_CLK_ZS),
 105         DEF_MOD("fdp1-2",                117,   R8A7790_CLK_ZS),
 106         DEF_MOD("fdp1-1",                118,   R8A7790_CLK_ZS),
 107         DEF_MOD("fdp1-0",                119,   R8A7790_CLK_ZS),
 108         DEF_MOD("tmu3",                  121,   R8A7790_CLK_P),
 109         DEF_MOD("tmu2",                  122,   R8A7790_CLK_P),
 110         DEF_MOD("cmt0",                  124,   R8A7790_CLK_R),
 111         DEF_MOD("tmu0",                  125,   R8A7790_CLK_CP),
 112         DEF_MOD("vsp1du1",               127,   R8A7790_CLK_ZS),
 113         DEF_MOD("vsp1du0",               128,   R8A7790_CLK_ZS),
 114         DEF_MOD("vsp1-rt",               130,   R8A7790_CLK_ZS),
 115         DEF_MOD("vsp1-sy",               131,   R8A7790_CLK_ZS),
 116         DEF_MOD("scifa2",                202,   R8A7790_CLK_MP),
 117         DEF_MOD("scifa1",                203,   R8A7790_CLK_MP),
 118         DEF_MOD("scifa0",                204,   R8A7790_CLK_MP),
 119         DEF_MOD("msiof2",                205,   R8A7790_CLK_MP),
 120         DEF_MOD("scifb0",                206,   R8A7790_CLK_MP),
 121         DEF_MOD("scifb1",                207,   R8A7790_CLK_MP),
 122         DEF_MOD("msiof1",                208,   R8A7790_CLK_MP),
 123         DEF_MOD("msiof3",                215,   R8A7790_CLK_MP),
 124         DEF_MOD("scifb2",                216,   R8A7790_CLK_MP),
 125         DEF_MOD("sys-dmac1",             218,   R8A7790_CLK_ZS),
 126         DEF_MOD("sys-dmac0",             219,   R8A7790_CLK_ZS),
 127         DEF_MOD("iic2",                  300,   R8A7790_CLK_HP),
 128         DEF_MOD("tpu0",                  304,   R8A7790_CLK_CP),
 129         DEF_MOD("mmcif1",                305,   R8A7790_CLK_MMC1),
 130         DEF_MOD("scif2",                 310,   R8A7790_CLK_P),
 131         DEF_MOD("sdhi3",                 311,   R8A7790_CLK_SD3),
 132         DEF_MOD("sdhi2",                 312,   R8A7790_CLK_SD2),
 133         DEF_MOD("sdhi1",                 313,   R8A7790_CLK_SD1),
 134         DEF_MOD("sdhi0",                 314,   R8A7790_CLK_SD0),
 135         DEF_MOD("mmcif0",                315,   R8A7790_CLK_MMC0),
 136         DEF_MOD("iic0",                  318,   R8A7790_CLK_HP),
 137         DEF_MOD("pciec",                 319,   R8A7790_CLK_MP),
 138         DEF_MOD("iic1",                  323,   R8A7790_CLK_HP),
 139         DEF_MOD("usb3.0",                328,   R8A7790_CLK_MP),
 140         DEF_MOD("cmt1",                  329,   R8A7790_CLK_R),
 141         DEF_MOD("usbhs-dmac0",           330,   R8A7790_CLK_HP),
 142         DEF_MOD("usbhs-dmac1",           331,   R8A7790_CLK_HP),
 143         DEF_MOD("irqc",                  407,   R8A7790_CLK_CP),
 144         DEF_MOD("intc-sys",              408,   R8A7790_CLK_ZS),
 145         DEF_MOD("audio-dmac1",           501,   R8A7790_CLK_HP),
 146         DEF_MOD("audio-dmac0",           502,   R8A7790_CLK_HP),
 147         DEF_MOD("adsp_mod",              506,   R8A7790_CLK_ADSP),
 148         DEF_MOD("thermal",               522,   CLK_EXTAL),
 149         DEF_MOD("pwm",                   523,   R8A7790_CLK_P),
 150         DEF_MOD("usb-ehci",              703,   R8A7790_CLK_MP),
 151         DEF_MOD("usbhs",                 704,   R8A7790_CLK_HP),
 152         DEF_MOD("hscif1",                716,   R8A7790_CLK_ZS),
 153         DEF_MOD("hscif0",                717,   R8A7790_CLK_ZS),
 154         DEF_MOD("scif1",                 720,   R8A7790_CLK_P),
 155         DEF_MOD("scif0",                 721,   R8A7790_CLK_P),
 156         DEF_MOD("du2",                   722,   R8A7790_CLK_ZX),
 157         DEF_MOD("du1",                   723,   R8A7790_CLK_ZX),
 158         DEF_MOD("du0",                   724,   R8A7790_CLK_ZX),
 159         DEF_MOD("lvds1",                 725,   R8A7790_CLK_ZX),
 160         DEF_MOD("lvds0",                 726,   R8A7790_CLK_ZX),
 161         DEF_MOD("mlb",                   802,   R8A7790_CLK_HP),
 162         DEF_MOD("vin3",                  808,   R8A7790_CLK_ZG),
 163         DEF_MOD("vin2",                  809,   R8A7790_CLK_ZG),
 164         DEF_MOD("vin1",                  810,   R8A7790_CLK_ZG),
 165         DEF_MOD("vin0",                  811,   R8A7790_CLK_ZG),
 166         DEF_MOD("etheravb",              812,   R8A7790_CLK_HP),
 167         DEF_MOD("ether",                 813,   R8A7790_CLK_P),
 168         DEF_MOD("sata1",                 814,   R8A7790_CLK_ZS),
 169         DEF_MOD("sata0",                 815,   R8A7790_CLK_ZS),
 170         DEF_MOD("gyro-adc",              901,   R8A7790_CLK_P),
 171         DEF_MOD("gpio5",                 907,   R8A7790_CLK_CP),
 172         DEF_MOD("gpio4",                 908,   R8A7790_CLK_CP),
 173         DEF_MOD("gpio3",                 909,   R8A7790_CLK_CP),
 174         DEF_MOD("gpio2",                 910,   R8A7790_CLK_CP),
 175         DEF_MOD("gpio1",                 911,   R8A7790_CLK_CP),
 176         DEF_MOD("gpio0",                 912,   R8A7790_CLK_CP),
 177         DEF_MOD("can1",                  915,   R8A7790_CLK_P),
 178         DEF_MOD("can0",                  916,   R8A7790_CLK_P),
 179         DEF_MOD("qspi_mod",              917,   R8A7790_CLK_QSPI),
 180         DEF_MOD("iicdvfs",               926,   R8A7790_CLK_CP),
 181         DEF_MOD("i2c3",                  928,   R8A7790_CLK_HP),
 182         DEF_MOD("i2c2",                  929,   R8A7790_CLK_HP),
 183         DEF_MOD("i2c1",                  930,   R8A7790_CLK_HP),
 184         DEF_MOD("i2c0",                  931,   R8A7790_CLK_HP),
 185         DEF_MOD("ssi-all",              1005,   R8A7790_CLK_P),
 186         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 187         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 188         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 189         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 190         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 191         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 192         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 193         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 194         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 195         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 196         DEF_MOD("scu-all",              1017,   R8A7790_CLK_P),
 197         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 198         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 199         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 200         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 201         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 202         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 203         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 204         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 205         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 206         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 207         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 208         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 209         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 210         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 211 };
 212
 213 static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
 214         MOD_CLK_ID(408),        /* INTC-SYS (GIC) */
 215 };
 216
 217 /*
 218  * CPG Clock Data
 219  */
 220
 221 /*
 222  *   MD         EXTAL           PLL0    PLL1    PLL3
 223  * 14 13 19     (MHz)           *1      *1
 224  *---------------------------------------------------
 225  * 0  0  0      15              x172/2  x208/2  x106
 226  * 0  0  1      15              x172/2  x208/2  x88
 227  * 0  1  0      20              x130/2  x156/2  x80
 228  * 0  1  1      20              x130/2  x156/2  x66
 229  * 1  0  0      26 / 2          x200/2  x240/2  x122
 230  * 1  0  1      26 / 2          x200/2  x240/2  x102
 231  * 1  1  0      30 / 2          x172/2  x208/2  x106
 232  * 1  1  1      30 / 2          x172/2  x208/2  x88
 233  *
 234  * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
 235  */
 236 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 12) | \
 237                                          (((md) & BIT(13)) >> 12) | \
 238                                          (((md) & BIT(19)) >> 19))
 239 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
 240         { 1, 208, 106 }, { 1, 208,  88 }, { 1, 156,  80 }, { 1, 156,  66 },
 241         { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208,  88 },
 242 };
 243
 244 static int __init r8a7790_cpg_mssr_init(struct device *dev)
 245 {
 246         const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
 247         u32 cpg_mode;
 248         int error;
 249
 250         error = rcar_rst_read_mode_pins(&cpg_mode);
 251         if (error)
 252                 return error;
 253
 254         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 255
 256         return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
 257 }
 258
 259 const struct cpg_mssr_info r8a7790_cpg_mssr_info __initconst = {
 260         /* Core Clocks */
 261         .core_clks = r8a7790_core_clks,
 262         .num_core_clks = ARRAY_SIZE(r8a7790_core_clks),
 263         .last_dt_core_clk = LAST_DT_CORE_CLK,
 264         .num_total_core_clks = MOD_CLK_BASE,
 265
 266         /* Module Clocks */
 267         .mod_clks = r8a7790_mod_clks,
 268         .num_mod_clks = ARRAY_SIZE(r8a7790_mod_clks),
 269         .num_hw_mod_clks = 12 * 32,
 270
 271         /* Critical Module Clocks */
 272         .crit_mod_clks = r8a7790_crit_mod_clks,
 273         .num_crit_mod_clks = ARRAY_SIZE(r8a7790_crit_mod_clks),
 274
 275         /* Callbacks */
 276         .init = r8a7790_cpg_mssr_init,
 277         .cpg_clk_register = rcar_gen2_cpg_clk_register,
 278 };