2 * R-Car Gen3 Clock Pulse Generator
4 * Copyright (C) 2015-2016 Glider bvba
6 * Based on clk-rcar-gen3.c
8 * Copyright (C) 2015 Renesas Electronics Corp.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
15 #include <linux/bug.h>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/device.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/sys_soc.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
28 #define CPG_PLL0CR 0x00d8
29 #define CPG_PLL2CR 0x002c
30 #define CPG_PLL4CR 0x01f4
36 #define CPG_SD_STP_HCK BIT(9)
37 #define CPG_SD_STP_CK BIT(8)
39 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
40 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
42 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
44 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
45 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
59 const struct sd_div_table *div_table;
63 unsigned int cur_div_idx;
68 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
69 *-------------------------------------------------------------------
81 static const struct sd_div_table cpg_sd_div_table[] = {
82 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
83 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
84 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
85 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
86 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
87 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
88 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
89 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
90 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
91 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
92 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
95 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
97 static int cpg_sd_clock_enable(struct clk_hw *hw)
99 struct sd_clock *clock = to_sd_clock(hw);
100 u32 val = readl(clock->reg);
102 val &= ~(CPG_SD_STP_MASK);
103 val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
105 writel(val, clock->reg);
110 static void cpg_sd_clock_disable(struct clk_hw *hw)
112 struct sd_clock *clock = to_sd_clock(hw);
114 writel(readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
117 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
119 struct sd_clock *clock = to_sd_clock(hw);
121 return !(readl(clock->reg) & CPG_SD_STP_MASK);
124 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
125 unsigned long parent_rate)
127 struct sd_clock *clock = to_sd_clock(hw);
129 return DIV_ROUND_CLOSEST(parent_rate,
130 clock->div_table[clock->cur_div_idx].div);
133 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
135 unsigned long parent_rate)
142 div = DIV_ROUND_CLOSEST(parent_rate, rate);
144 return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
147 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
148 unsigned long *parent_rate)
150 struct sd_clock *clock = to_sd_clock(hw);
151 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
153 return DIV_ROUND_CLOSEST(*parent_rate, div);
156 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
157 unsigned long parent_rate)
159 struct sd_clock *clock = to_sd_clock(hw);
160 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
164 for (i = 0; i < clock->div_num; i++)
165 if (div == clock->div_table[i].div)
168 if (i >= clock->div_num)
171 clock->cur_div_idx = i;
173 val = readl(clock->reg);
174 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
175 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
176 writel(val, clock->reg);
181 static const struct clk_ops cpg_sd_clock_ops = {
182 .enable = cpg_sd_clock_enable,
183 .disable = cpg_sd_clock_disable,
184 .is_enabled = cpg_sd_clock_is_enabled,
185 .recalc_rate = cpg_sd_clock_recalc_rate,
186 .round_rate = cpg_sd_clock_round_rate,
187 .set_rate = cpg_sd_clock_set_rate,
190 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
192 const char *parent_name)
194 struct clk_init_data init;
195 struct sd_clock *clock;
200 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
202 return ERR_PTR(-ENOMEM);
204 init.name = core->name;
205 init.ops = &cpg_sd_clock_ops;
206 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
207 init.parent_names = &parent_name;
208 init.num_parents = 1;
210 clock->reg = base + core->offset;
211 clock->hw.init = &init;
212 clock->div_table = cpg_sd_div_table;
213 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
215 sd_fc = readl(clock->reg) & CPG_SD_FC_MASK;
216 for (i = 0; i < clock->div_num; i++)
217 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
220 if (WARN_ON(i >= clock->div_num)) {
222 return ERR_PTR(-EINVAL);
225 clock->cur_div_idx = i;
227 clock->div_max = clock->div_table[0].div;
228 clock->div_min = clock->div_max;
229 for (i = 1; i < clock->div_num; i++) {
230 clock->div_max = max(clock->div_max, clock->div_table[i].div);
231 clock->div_min = min(clock->div_min, clock->div_table[i].div);
234 clk = clk_register(NULL, &clock->hw);
242 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
243 static unsigned int cpg_clk_extalr __initdata;
244 static u32 cpg_mode __initdata;
245 static u32 cpg_quirks __initdata;
247 #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
248 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
250 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
252 .soc_id = "r8a7795", .revision = "ES1.0",
253 .data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
256 .soc_id = "r8a7795", .revision = "ES1.*",
257 .data = (void *)RCKCR_CKSEL,
260 .soc_id = "r8a7796", .revision = "ES1.0",
261 .data = (void *)RCKCR_CKSEL,
266 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
267 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
268 struct clk **clks, void __iomem *base)
270 const struct clk *parent;
271 unsigned int mult = 1;
272 unsigned int div = 1;
275 parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */
277 return ERR_CAST(parent);
279 switch (core->type) {
280 case CLK_TYPE_GEN3_MAIN:
281 div = cpg_pll_config->extal_div;
284 case CLK_TYPE_GEN3_PLL0:
286 * PLL0 is a configurable multiplier clock. Register it as a
287 * fixed factor clock for now as there's no generic multiplier
288 * clock implementation and we currently have no need to change
289 * the multiplier value.
291 value = readl(base + CPG_PLL0CR);
292 mult = (((value >> 24) & 0x7f) + 1) * 2;
293 if (cpg_quirks & PLL_ERRATA)
297 case CLK_TYPE_GEN3_PLL1:
298 mult = cpg_pll_config->pll1_mult;
299 div = cpg_pll_config->pll1_div;
302 case CLK_TYPE_GEN3_PLL2:
304 * PLL2 is a configurable multiplier clock. Register it as a
305 * fixed factor clock for now as there's no generic multiplier
306 * clock implementation and we currently have no need to change
307 * the multiplier value.
309 value = readl(base + CPG_PLL2CR);
310 mult = (((value >> 24) & 0x7f) + 1) * 2;
311 if (cpg_quirks & PLL_ERRATA)
315 case CLK_TYPE_GEN3_PLL3:
316 mult = cpg_pll_config->pll3_mult;
317 div = cpg_pll_config->pll3_div;
320 case CLK_TYPE_GEN3_PLL4:
322 * PLL4 is a configurable multiplier clock. Register it as a
323 * fixed factor clock for now as there's no generic multiplier
324 * clock implementation and we currently have no need to change
325 * the multiplier value.
327 value = readl(base + CPG_PLL4CR);
328 mult = (((value >> 24) & 0x7f) + 1) * 2;
329 if (cpg_quirks & PLL_ERRATA)
333 case CLK_TYPE_GEN3_SD:
334 return cpg_sd_clk_register(core, base, __clk_get_name(parent));
336 case CLK_TYPE_GEN3_R:
337 if (cpg_quirks & RCKCR_CKSEL) {
340 * Only if EXTALR is populated, we switch to it.
342 value = readl(base + CPG_RCKCR) & 0x3f;
344 if (clk_get_rate(clks[cpg_clk_extalr])) {
345 parent = clks[cpg_clk_extalr];
349 writel(value, base + CPG_RCKCR);
353 /* Select parent clock of RCLK by MD28 */
354 if (cpg_mode & BIT(28))
355 parent = clks[cpg_clk_extalr];
358 case CLK_TYPE_GEN3_PE:
360 * Peripheral clock with a fixed divider, selectable between
361 * clean and spread spectrum parents using MD12
363 if (cpg_mode & BIT(12)) {
365 div = core->div & 0xffff;
368 parent = clks[core->parent >> 16];
370 return ERR_CAST(parent);
371 div = core->div >> 16;
377 return ERR_PTR(-EINVAL);
380 return clk_register_fixed_factor(NULL, core->name,
381 __clk_get_name(parent), 0, mult, div);
384 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
385 unsigned int clk_extalr, u32 mode)
387 const struct soc_device_attribute *attr;
389 cpg_pll_config = config;
390 cpg_clk_extalr = clk_extalr;
392 attr = soc_device_match(cpg_quirks_match);
394 cpg_quirks = (uintptr_t)attr->data;
395 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);