drivers/clk/tegra/clk-emc.c

   1 /*
   2  * drivers/clk/tegra/clk-emc.c
   3  *
   4  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Author:
   7  *      Mikko Perttunen <mperttunen@nvidia.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/clk-provider.h>
  20 #include <linux/clk.h>
  21 #include <linux/clkdev.h>
  22 #include <linux/delay.h>
  23 #include <linux/module.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/sort.h>
  28 #include <linux/string.h>
  29
  30 #include <soc/tegra/fuse.h>
  31 #include <soc/tegra/emc.h>
  32
  33 #include "clk.h"
  34
  35 #define CLK_SOURCE_EMC 0x19c
  36
  37 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
  38 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
  39 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
  40                                               CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
  41
  42 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
  43 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
  44 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
  45                                           CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
  46
  47 static const char * const emc_parent_clk_names[] = {
  48         "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
  49         "pll_c2", "pll_c3", "pll_c_ud"
  50 };
  51
  52 /*
  53  * List of clock sources for various parents the EMC clock can have.
  54  * When we change the timing to a timing with a parent that has the same
  55  * clock source as the current parent, we must first change to a backup
  56  * timing that has a different clock source.
  57  */
  58
  59 #define EMC_SRC_PLL_M 0
  60 #define EMC_SRC_PLL_C 1
  61 #define EMC_SRC_PLL_P 2
  62 #define EMC_SRC_CLK_M 3
  63 #define EMC_SRC_PLL_C2 4
  64 #define EMC_SRC_PLL_C3 5
  65
  66 static const char emc_parent_clk_sources[] = {
  67         EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
  68         EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
  69 };
  70
  71 struct emc_timing {
  72         unsigned long rate, parent_rate;
  73         u8 parent_index;
  74         struct clk *parent;
  75         u32 ram_code;
  76 };
  77
  78 struct tegra_clk_emc {
  79         struct clk_hw hw;
  80         void __iomem *clk_regs;
  81         struct clk *prev_parent;
  82         bool changing_timing;
  83
  84         struct device_node *emc_node;
  85         struct tegra_emc *emc;
  86
  87         int num_timings;
  88         struct emc_timing *timings;
  89         spinlock_t *lock;
  90 };
  91
  92 /* Common clock framework callback implementations */
  93
  94 static unsigned long emc_recalc_rate(struct clk_hw *hw,
  95                                      unsigned long parent_rate)
  96 {
  97         struct tegra_clk_emc *tegra;
  98         u32 val, div;
  99
 100         tegra = container_of(hw, struct tegra_clk_emc, hw);
 101
 102         /*
 103          * CCF wrongly assumes that the parent won't change during set_rate,
 104          * so get the parent rate explicitly.
 105          */
 106         parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 107
 108         val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
 109         div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
 110
 111         return parent_rate / (div + 2) * 2;
 112 }
 113
 114 /*
 115  * Rounds up unless no higher rate exists, in which case down. This way is
 116  * safer since things have EMC rate floors. Also don't touch parent_rate
 117  * since we don't want the CCF to play with our parent clocks.
 118  */
 119 static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
 120 {
 121         struct tegra_clk_emc *tegra;
 122         u8 ram_code = tegra_read_ram_code();
 123         struct emc_timing *timing = NULL;
 124         int i;
 125
 126         tegra = container_of(hw, struct tegra_clk_emc, hw);
 127
 128         for (i = 0; i < tegra->num_timings; i++) {
 129                 if (tegra->timings[i].ram_code != ram_code)
 130                         continue;
 131
 132                 timing = tegra->timings + i;
 133
 134                 if (timing->rate > req->max_rate) {
 135                         i = max(i, 1);
 136                         req->rate = tegra->timings[i - 1].rate;
 137                         return 0;
 138                 }
 139
 140                 if (timing->rate < req->min_rate)
 141                         continue;
 142
 143                 if (timing->rate >= req->rate) {
 144                         req->rate = timing->rate;
 145                         return 0;
 146                 }
 147         }
 148
 149         if (timing) {
 150                 req->rate = timing->rate;
 151                 return 0;
 152         }
 153
 154         req->rate = clk_hw_get_rate(hw);
 155         return 0;
 156 }
 157
 158 static u8 emc_get_parent(struct clk_hw *hw)
 159 {
 160         struct tegra_clk_emc *tegra;
 161         u32 val;
 162
 163         tegra = container_of(hw, struct tegra_clk_emc, hw);
 164
 165         val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
 166
 167         return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
 168                 & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
 169 }
 170
 171 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
 172 {
 173         struct platform_device *pdev;
 174
 175         if (tegra->emc)
 176                 return tegra->emc;
 177
 178         if (!tegra->emc_node)
 179                 return NULL;
 180
 181         pdev = of_find_device_by_node(tegra->emc_node);
 182         if (!pdev) {
 183                 pr_err("%s: could not get external memory controller\n",
 184                        __func__);
 185                 return NULL;
 186         }
 187
 188         of_node_put(tegra->emc_node);
 189         tegra->emc_node = NULL;
 190
 191         tegra->emc = platform_get_drvdata(pdev);
 192         if (!tegra->emc) {
 193                 put_device(&pdev->dev);
 194                 pr_err("%s: cannot find EMC driver\n", __func__);
 195                 return NULL;
 196         }
 197
 198         return tegra->emc;
 199 }
 200
 201 static int emc_set_timing(struct tegra_clk_emc *tegra,
 202                           struct emc_timing *timing)
 203 {
 204         int err;
 205         u8 div;
 206         u32 car_value;
 207         unsigned long flags = 0;
 208         struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
 209
 210         if (!emc)
 211                 return -ENOENT;
 212
 213         pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
 214                  timing->parent_rate, __clk_get_name(timing->parent));
 215
 216         if (emc_get_parent(&tegra->hw) == timing->parent_index &&
 217             clk_get_rate(timing->parent) != timing->parent_rate) {
 218                 BUG();
 219                 return -EINVAL;
 220         }
 221
 222         tegra->changing_timing = true;
 223
 224         err = clk_set_rate(timing->parent, timing->parent_rate);
 225         if (err) {
 226                 pr_err("cannot change parent %s rate to %ld: %d\n",
 227                        __clk_get_name(timing->parent), timing->parent_rate,
 228                        err);
 229
 230                 return err;
 231         }
 232
 233         err = clk_prepare_enable(timing->parent);
 234         if (err) {
 235                 pr_err("cannot enable parent clock: %d\n", err);
 236                 return err;
 237         }
 238
 239         div = timing->parent_rate / (timing->rate / 2) - 2;
 240
 241         err = tegra_emc_prepare_timing_change(emc, timing->rate);
 242         if (err)
 243                 return err;
 244
 245         spin_lock_irqsave(tegra->lock, flags);
 246
 247         car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
 248
 249         car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
 250         car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
 251
 252         car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
 253         car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
 254
 255         writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
 256
 257         spin_unlock_irqrestore(tegra->lock, flags);
 258
 259         tegra_emc_complete_timing_change(emc, timing->rate);
 260
 261         clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
 262         clk_disable_unprepare(tegra->prev_parent);
 263
 264         tegra->prev_parent = timing->parent;
 265         tegra->changing_timing = false;
 266
 267         return 0;
 268 }
 269
 270 /*
 271  * Get backup timing to use as an intermediate step when a change between
 272  * two timings with the same clock source has been requested. First try to
 273  * find a timing with a higher clock rate to avoid a rate below any set rate
 274  * floors. If that is not possible, find a lower rate.
 275  */
 276 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
 277                                             int timing_index)
 278 {
 279         int i;
 280         u32 ram_code = tegra_read_ram_code();
 281         struct emc_timing *timing;
 282
 283         for (i = timing_index+1; i < tegra->num_timings; i++) {
 284                 timing = tegra->timings + i;
 285                 if (timing->ram_code != ram_code)
 286                         continue;
 287
 288                 if (emc_parent_clk_sources[timing->parent_index] !=
 289                     emc_parent_clk_sources[
 290                       tegra->timings[timing_index].parent_index])
 291                         return timing;
 292         }
 293
 294         for (i = timing_index-1; i >= 0; --i) {
 295                 timing = tegra->timings + i;
 296                 if (timing->ram_code != ram_code)
 297                         continue;
 298
 299                 if (emc_parent_clk_sources[timing->parent_index] !=
 300                     emc_parent_clk_sources[
 301                       tegra->timings[timing_index].parent_index])
 302                         return timing;
 303         }
 304
 305         return NULL;
 306 }
 307
 308 static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
 309                         unsigned long parent_rate)
 310 {
 311         struct tegra_clk_emc *tegra;
 312         struct emc_timing *timing = NULL;
 313         int i, err;
 314         u32 ram_code = tegra_read_ram_code();
 315
 316         tegra = container_of(hw, struct tegra_clk_emc, hw);
 317
 318         if (clk_hw_get_rate(hw) == rate)
 319                 return 0;
 320
 321         /*
 322          * When emc_set_timing changes the parent rate, CCF will propagate
 323          * that downward to us, so ignore any set_rate calls while a rate
 324          * change is already going on.
 325          */
 326         if (tegra->changing_timing)
 327                 return 0;
 328
 329         for (i = 0; i < tegra->num_timings; i++) {
 330                 if (tegra->timings[i].rate == rate &&
 331                     tegra->timings[i].ram_code == ram_code) {
 332                         timing = tegra->timings + i;
 333                         break;
 334                 }
 335         }
 336
 337         if (!timing) {
 338                 pr_err("cannot switch to rate %ld without emc table\n", rate);
 339                 return -EINVAL;
 340         }
 341
 342         if (emc_parent_clk_sources[emc_get_parent(hw)] ==
 343             emc_parent_clk_sources[timing->parent_index] &&
 344             clk_get_rate(timing->parent) != timing->parent_rate) {
 345                 /*
 346                  * Parent clock source not changed but parent rate has changed,
 347                  * need to temporarily switch to another parent
 348                  */
 349
 350                 struct emc_timing *backup_timing;
 351
 352                 backup_timing = get_backup_timing(tegra, i);
 353                 if (!backup_timing) {
 354                         pr_err("cannot find backup timing\n");
 355                         return -EINVAL;
 356                 }
 357
 358                 pr_debug("using %ld as backup rate when going to %ld\n",
 359                          backup_timing->rate, rate);
 360
 361                 err = emc_set_timing(tegra, backup_timing);
 362                 if (err) {
 363                         pr_err("cannot set backup timing: %d\n", err);
 364                         return err;
 365                 }
 366         }
 367
 368         return emc_set_timing(tegra, timing);
 369 }
 370
 371 /* Initialization and deinitialization */
 372
 373 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
 374                                    struct emc_timing *timing,
 375                                    struct device_node *node)
 376 {
 377         int err, i;
 378         u32 tmp;
 379
 380         err = of_property_read_u32(node, "clock-frequency", &tmp);
 381         if (err) {
 382                 pr_err("timing %pOF: failed to read rate\n", node);
 383                 return err;
 384         }
 385
 386         timing->rate = tmp;
 387
 388         err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
 389         if (err) {
 390                 pr_err("timing %pOF: failed to read parent rate\n", node);
 391                 return err;
 392         }
 393
 394         timing->parent_rate = tmp;
 395
 396         timing->parent = of_clk_get_by_name(node, "emc-parent");
 397         if (IS_ERR(timing->parent)) {
 398                 pr_err("timing %pOF: failed to get parent clock\n", node);
 399                 return PTR_ERR(timing->parent);
 400         }
 401
 402         timing->parent_index = 0xff;
 403         for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
 404                 if (!strcmp(emc_parent_clk_names[i],
 405                             __clk_get_name(timing->parent))) {
 406                         timing->parent_index = i;
 407                         break;
 408                 }
 409         }
 410         if (timing->parent_index == 0xff) {
 411                 pr_err("timing %pOF: %s is not a valid parent\n",
 412                        node, __clk_get_name(timing->parent));
 413                 clk_put(timing->parent);
 414                 return -EINVAL;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int cmp_timings(const void *_a, const void *_b)
 421 {
 422         const struct emc_timing *a = _a;
 423         const struct emc_timing *b = _b;
 424
 425         if (a->rate < b->rate)
 426                 return -1;
 427         else if (a->rate == b->rate)
 428                 return 0;
 429         else
 430                 return 1;
 431 }
 432
 433 static int load_timings_from_dt(struct tegra_clk_emc *tegra,
 434                                 struct device_node *node,
 435                                 u32 ram_code)
 436 {
 437         struct device_node *child;
 438         int child_count = of_get_child_count(node);
 439         int i = 0, err;
 440
 441         tegra->timings = kcalloc(child_count, sizeof(struct emc_timing),
 442                                  GFP_KERNEL);
 443         if (!tegra->timings)
 444                 return -ENOMEM;
 445
 446         tegra->num_timings = child_count;
 447
 448         for_each_child_of_node(node, child) {
 449                 struct emc_timing *timing = tegra->timings + (i++);
 450
 451                 err = load_one_timing_from_dt(tegra, timing, child);
 452                 if (err) {
 453                         of_node_put(child);
 454                         return err;
 455                 }
 456
 457                 timing->ram_code = ram_code;
 458         }
 459
 460         sort(tegra->timings, tegra->num_timings, sizeof(struct emc_timing),
 461              cmp_timings, NULL);
 462
 463         return 0;
 464 }
 465
 466 static const struct clk_ops tegra_clk_emc_ops = {
 467         .recalc_rate = emc_recalc_rate,
 468         .determine_rate = emc_determine_rate,
 469         .set_rate = emc_set_rate,
 470         .get_parent = emc_get_parent,
 471 };
 472
 473 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
 474                                    spinlock_t *lock)
 475 {
 476         struct tegra_clk_emc *tegra;
 477         struct clk_init_data init;
 478         struct device_node *node;
 479         u32 node_ram_code;
 480         struct clk *clk;
 481         int err;
 482
 483         tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
 484         if (!tegra)
 485                 return ERR_PTR(-ENOMEM);
 486
 487         tegra->clk_regs = base;
 488         tegra->lock = lock;
 489
 490         tegra->num_timings = 0;
 491
 492         for_each_child_of_node(np, node) {
 493                 err = of_property_read_u32(node, "nvidia,ram-code",
 494                                            &node_ram_code);
 495                 if (err)
 496                         continue;
 497
 498                 /*
 499                  * Store timings for all ram codes as we cannot read the
 500                  * fuses until the apbmisc driver is loaded.
 501                  */
 502                 err = load_timings_from_dt(tegra, node, node_ram_code);
 503                 of_node_put(node);
 504                 if (err)
 505                         return ERR_PTR(err);
 506                 break;
 507         }
 508
 509         if (tegra->num_timings == 0)
 510                 pr_warn("%s: no memory timings registered\n", __func__);
 511
 512         tegra->emc_node = of_parse_phandle(np,
 513                         "nvidia,external-memory-controller", 0);
 514         if (!tegra->emc_node)
 515                 pr_warn("%s: couldn't find node for EMC driver\n", __func__);
 516
 517         init.name = "emc";
 518         init.ops = &tegra_clk_emc_ops;
 519         init.flags = CLK_IS_CRITICAL;
 520         init.parent_names = emc_parent_clk_names;
 521         init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
 522
 523         tegra->hw.init = &init;
 524
 525         clk = clk_register(NULL, &tegra->hw);
 526         if (IS_ERR(clk))
 527                 return clk;
 528
 529         tegra->prev_parent = clk_hw_get_parent_by_index(
 530                 &tegra->hw, emc_get_parent(&tegra->hw))->clk;
 531         tegra->changing_timing = false;
 532
 533         /* Allow debugging tools to see the EMC clock */
 534         clk_register_clkdev(clk, "emc", "tegra-clk-debug");
 535
 536         clk_prepare_enable(clk);
 537
 538         return clk;
 539 };