drivers/clk/tegra/clk-pll.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/clk-provider.h>
  23
  24 #include "clk.h"
  25
  26 #define PLL_BASE_BYPASS BIT(31)
  27 #define PLL_BASE_ENABLE BIT(30)
  28 #define PLL_BASE_REF_ENABLE BIT(29)
  29 #define PLL_BASE_OVERRIDE BIT(28)
  30
  31 #define PLL_BASE_DIVP_SHIFT 20
  32 #define PLL_BASE_DIVP_WIDTH 3
  33 #define PLL_BASE_DIVN_SHIFT 8
  34 #define PLL_BASE_DIVN_WIDTH 10
  35 #define PLL_BASE_DIVM_SHIFT 0
  36 #define PLL_BASE_DIVM_WIDTH 5
  37 #define PLLU_POST_DIVP_MASK 0x1
  38
  39 #define PLL_MISC_DCCON_SHIFT 20
  40 #define PLL_MISC_CPCON_SHIFT 8
  41 #define PLL_MISC_CPCON_WIDTH 4
  42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  43 #define PLL_MISC_LFCON_SHIFT 4
  44 #define PLL_MISC_LFCON_WIDTH 4
  45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  46 #define PLL_MISC_VCOCON_SHIFT 0
  47 #define PLL_MISC_VCOCON_WIDTH 4
  48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  49
  50 #define OUT_OF_TABLE_CPCON 8
  51
  52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  55
  56 #define PLL_POST_LOCK_DELAY 50
  57
  58 #define PLLDU_LFCON_SET_DIVN 600
  59
  60 #define PLLE_BASE_DIVCML_SHIFT 24
  61 #define PLLE_BASE_DIVCML_MASK 0xf
  62 #define PLLE_BASE_DIVP_SHIFT 16
  63 #define PLLE_BASE_DIVP_WIDTH 6
  64 #define PLLE_BASE_DIVN_SHIFT 8
  65 #define PLLE_BASE_DIVN_WIDTH 8
  66 #define PLLE_BASE_DIVM_SHIFT 0
  67 #define PLLE_BASE_DIVM_WIDTH 8
  68 #define PLLE_BASE_ENABLE BIT(31)
  69
  70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  73 #define PLLE_MISC_READY BIT(15)
  74 #define PLLE_MISC_SETUP_EX_SHIFT 2
  75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  77                               PLLE_MISC_SETUP_EX_MASK)
  78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  79
  80 #define PLLE_SS_CTRL 0x68
  81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  84 #define PLLE_SS_CNTL_CENTER BIT(14)
  85 #define PLLE_SS_CNTL_INVERT BIT(15)
  86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  87                                 PLLE_SS_CNTL_SSC_BYP)
  88 #define PLLE_SS_MAX_MASK 0x1ff
  89 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
  90 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
  91 #define PLLE_SS_INC_MASK (0xff << 16)
  92 #define PLLE_SS_INC_VAL (0x1 << 16)
  93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  94 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
  95 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
  96 #define PLLE_SS_COEFFICIENTS_MASK \
  97         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  98 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
  99         (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
 100          PLLE_SS_INCINTRV_VAL_TEGRA114)
 101 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
 102         (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
 103          PLLE_SS_INCINTRV_VAL_TEGRA210)
 104
 105 #define PLLE_AUX_PLLP_SEL       BIT(2)
 106 #define PLLE_AUX_USE_LOCKDET    BIT(3)
 107 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
 108 #define PLLE_AUX_SS_SWCTL       BIT(6)
 109 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
 110 #define PLLE_AUX_SEQ_START_STATE BIT(25)
 111 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 112 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
 113
 114 #define XUSBIO_PLL_CFG0         0x51c
 115 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL      BIT(0)
 116 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL        BIT(2)
 117 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET      BIT(6)
 118 #define XUSBIO_PLL_CFG0_SEQ_ENABLE              BIT(24)
 119 #define XUSBIO_PLL_CFG0_SEQ_START_STATE         BIT(25)
 120
 121 #define SATA_PLL_CFG0           0x490
 122 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
 123 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
 124 #define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
 125 #define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 126
 127 #define PLLE_MISC_PLLE_PTS      BIT(8)
 128 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 129 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 130 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 131 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 132 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 133 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 134
 135 #define PLLCX_MISC_STROBE       BIT(31)
 136 #define PLLCX_MISC_RESET        BIT(30)
 137 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 138 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 139 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 140 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 141 #define PLLCX_MISC_ALPHA_SHIFT 18
 142 #define PLLCX_MISC_DIV_LOW_RANGE \
 143                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 144                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 145 #define PLLCX_MISC_DIV_HIGH_RANGE \
 146                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 147                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 148 #define PLLCX_MISC_COEF_LOW_RANGE \
 149                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 150 #define PLLCX_MISC_KA_SHIFT 2
 151 #define PLLCX_MISC_KB_SHIFT 9
 152 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 153                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 154                             PLLCX_MISC_DIV_LOW_RANGE | \
 155                             PLLCX_MISC_RESET)
 156 #define PLLCX_MISC1_DEFAULT 0x000d2308
 157 #define PLLCX_MISC2_DEFAULT 0x30211200
 158 #define PLLCX_MISC3_DEFAULT 0x200
 159
 160 #define PMC_SATA_PWRGT 0x1ac
 161 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 162 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 163
 164 #define PLLSS_MISC_KCP          0
 165 #define PLLSS_MISC_KVCO         0
 166 #define PLLSS_MISC_SETUP        0
 167 #define PLLSS_EN_SDM            0
 168 #define PLLSS_EN_SSC            0
 169 #define PLLSS_EN_DITHER2        0
 170 #define PLLSS_EN_DITHER         1
 171 #define PLLSS_SDM_RESET         0
 172 #define PLLSS_CLAMP             0
 173 #define PLLSS_SDM_SSC_MAX       0
 174 #define PLLSS_SDM_SSC_MIN       0
 175 #define PLLSS_SDM_SSC_STEP      0
 176 #define PLLSS_SDM_DIN           0
 177 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 178                             (PLLSS_MISC_KVCO << 24) | \
 179                             PLLSS_MISC_SETUP)
 180 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 181                            (PLLSS_EN_SSC << 30) | \
 182                            (PLLSS_EN_DITHER2 << 29) | \
 183                            (PLLSS_EN_DITHER << 28) | \
 184                            (PLLSS_SDM_RESET) << 27 | \
 185                            (PLLSS_CLAMP << 22))
 186 #define PLLSS_CTRL1_DEFAULT \
 187                         ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 188 #define PLLSS_CTRL2_DEFAULT \
 189                         ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 190 #define PLLSS_LOCK_OVERRIDE     BIT(24)
 191 #define PLLSS_REF_SRC_SEL_SHIFT 25
 192 #define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 193
 194 #define UTMIP_PLL_CFG1 0x484
 195 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 196 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
 197 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 198 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 199 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
 200 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 201 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
 202
 203 #define UTMIP_PLL_CFG2 0x488
 204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
 205 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 206 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
 208 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 209 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
 210 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 211 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
 212 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
 213 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
 214 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
 215
 216 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
 217 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
 218 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
 219 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 220 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
 221 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
 222 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 223 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 224 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
 225
 226 #define PLLU_HW_PWRDN_CFG0 0x530
 227 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
 228 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 229 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 230 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
 231 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 232 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
 233
 234 #define XUSB_PLL_CFG0 0x534
 235 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
 236 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
 237
 238 #define PLLU_BASE_CLKENABLE_USB BIT(21)
 239 #define PLLU_BASE_OVERRIDE BIT(24)
 240
 241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 244 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
 246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
 247
 248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 251 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
 253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
 254
 255 #define mask(w) ((1 << (w)) - 1)
 256 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 257 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 258 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 259                       mask(p->params->div_nmp->divp_width))
 260 #define sdm_din_mask(p) p->params->sdm_din_mask
 261 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
 262
 263 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 264 #define divn_shift(p) (p)->params->div_nmp->divn_shift
 265 #define divp_shift(p) (p)->params->div_nmp->divp_shift
 266
 267 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 268 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 269 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 270
 271 #define divm_max(p) (divm_mask(p))
 272 #define divn_max(p) (divn_mask(p))
 273 #define divp_max(p) (1 << (divp_mask(p)))
 274
 275 #define sdin_din_to_data(din)   ((u16)((din) ? : 0xFFFFU))
 276 #define sdin_data_to_din(dat)   (((dat) == 0xFFFFU) ? 0 : (s16)dat)
 277
 278 static struct div_nmp default_nmp = {
 279         .divn_shift = PLL_BASE_DIVN_SHIFT,
 280         .divn_width = PLL_BASE_DIVN_WIDTH,
 281         .divm_shift = PLL_BASE_DIVM_SHIFT,
 282         .divm_width = PLL_BASE_DIVM_WIDTH,
 283         .divp_shift = PLL_BASE_DIVP_SHIFT,
 284         .divp_width = PLL_BASE_DIVP_WIDTH,
 285 };
 286
 287 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 288 {
 289         u32 val;
 290
 291         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 292                 return;
 293
 294         if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 295                 return;
 296
 297         val = pll_readl_misc(pll);
 298         val |= BIT(pll->params->lock_enable_bit_idx);
 299         pll_writel_misc(val, pll);
 300 }
 301
 302 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 303 {
 304         int i;
 305         u32 val, lock_mask;
 306         void __iomem *lock_addr;
 307
 308         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 309                 udelay(pll->params->lock_delay);
 310                 return 0;
 311         }
 312
 313         lock_addr = pll->clk_base;
 314         if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 315                 lock_addr += pll->params->misc_reg;
 316         else
 317                 lock_addr += pll->params->base_reg;
 318
 319         lock_mask = pll->params->lock_mask;
 320
 321         for (i = 0; i < pll->params->lock_delay; i++) {
 322                 val = readl_relaxed(lock_addr);
 323                 if ((val & lock_mask) == lock_mask) {
 324                         udelay(PLL_POST_LOCK_DELAY);
 325                         return 0;
 326                 }
 327                 udelay(2); /* timeout = 2 * lock time */
 328         }
 329
 330         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 331                clk_hw_get_name(&pll->hw));
 332
 333         return -1;
 334 }
 335
 336 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
 337 {
 338         return clk_pll_wait_for_lock(pll);
 339 }
 340
 341 static int clk_pll_is_enabled(struct clk_hw *hw)
 342 {
 343         struct tegra_clk_pll *pll = to_clk_pll(hw);
 344         u32 val;
 345
 346         if (pll->params->flags & TEGRA_PLLM) {
 347                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 348                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 349                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 350         }
 351
 352         val = pll_readl_base(pll);
 353
 354         return val & PLL_BASE_ENABLE ? 1 : 0;
 355 }
 356
 357 static void _clk_pll_enable(struct clk_hw *hw)
 358 {
 359         struct tegra_clk_pll *pll = to_clk_pll(hw);
 360         u32 val;
 361
 362         if (pll->params->iddq_reg) {
 363                 val = pll_readl(pll->params->iddq_reg, pll);
 364                 val &= ~BIT(pll->params->iddq_bit_idx);
 365                 pll_writel(val, pll->params->iddq_reg, pll);
 366                 udelay(5);
 367         }
 368
 369         if (pll->params->reset_reg) {
 370                 val = pll_readl(pll->params->reset_reg, pll);
 371                 val &= ~BIT(pll->params->reset_bit_idx);
 372                 pll_writel(val, pll->params->reset_reg, pll);
 373         }
 374
 375         clk_pll_enable_lock(pll);
 376
 377         val = pll_readl_base(pll);
 378         if (pll->params->flags & TEGRA_PLL_BYPASS)
 379                 val &= ~PLL_BASE_BYPASS;
 380         val |= PLL_BASE_ENABLE;
 381         pll_writel_base(val, pll);
 382
 383         if (pll->params->flags & TEGRA_PLLM) {
 384                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 385                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 386                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 387         }
 388 }
 389
 390 static void _clk_pll_disable(struct clk_hw *hw)
 391 {
 392         struct tegra_clk_pll *pll = to_clk_pll(hw);
 393         u32 val;
 394
 395         val = pll_readl_base(pll);
 396         if (pll->params->flags & TEGRA_PLL_BYPASS)
 397                 val &= ~PLL_BASE_BYPASS;
 398         val &= ~PLL_BASE_ENABLE;
 399         pll_writel_base(val, pll);
 400
 401         if (pll->params->flags & TEGRA_PLLM) {
 402                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 403                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 404                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 405         }
 406
 407         if (pll->params->reset_reg) {
 408                 val = pll_readl(pll->params->reset_reg, pll);
 409                 val |= BIT(pll->params->reset_bit_idx);
 410                 pll_writel(val, pll->params->reset_reg, pll);
 411         }
 412
 413         if (pll->params->iddq_reg) {
 414                 val = pll_readl(pll->params->iddq_reg, pll);
 415                 val |= BIT(pll->params->iddq_bit_idx);
 416                 pll_writel(val, pll->params->iddq_reg, pll);
 417                 udelay(2);
 418         }
 419 }
 420
 421 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
 422 {
 423         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 424                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 425
 426                 val |= pll->params->ssc_ctrl_en_mask;
 427                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 428         }
 429 }
 430
 431 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
 432 {
 433         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 434                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 435
 436                 val &= ~pll->params->ssc_ctrl_en_mask;
 437                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 438         }
 439 }
 440
 441 static int clk_pll_enable(struct clk_hw *hw)
 442 {
 443         struct tegra_clk_pll *pll = to_clk_pll(hw);
 444         unsigned long flags = 0;
 445         int ret;
 446
 447         if (pll->lock)
 448                 spin_lock_irqsave(pll->lock, flags);
 449
 450         _clk_pll_enable(hw);
 451
 452         ret = clk_pll_wait_for_lock(pll);
 453
 454         pll_clk_start_ss(pll);
 455
 456         if (pll->lock)
 457                 spin_unlock_irqrestore(pll->lock, flags);
 458
 459         return ret;
 460 }
 461
 462 static void clk_pll_disable(struct clk_hw *hw)
 463 {
 464         struct tegra_clk_pll *pll = to_clk_pll(hw);
 465         unsigned long flags = 0;
 466
 467         if (pll->lock)
 468                 spin_lock_irqsave(pll->lock, flags);
 469
 470         pll_clk_stop_ss(pll);
 471
 472         _clk_pll_disable(hw);
 473
 474         if (pll->lock)
 475                 spin_unlock_irqrestore(pll->lock, flags);
 476 }
 477
 478 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 479 {
 480         struct tegra_clk_pll *pll = to_clk_pll(hw);
 481         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 482
 483         if (p_tohw) {
 484                 while (p_tohw->pdiv) {
 485                         if (p_div <= p_tohw->pdiv)
 486                                 return p_tohw->hw_val;
 487                         p_tohw++;
 488                 }
 489                 return -EINVAL;
 490         }
 491         return -EINVAL;
 492 }
 493
 494 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
 495 {
 496         return _p_div_to_hw(&pll->hw, p_div);
 497 }
 498
 499 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 500 {
 501         struct tegra_clk_pll *pll = to_clk_pll(hw);
 502         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 503
 504         if (p_tohw) {
 505                 while (p_tohw->pdiv) {
 506                         if (p_div_hw == p_tohw->hw_val)
 507                                 return p_tohw->pdiv;
 508                         p_tohw++;
 509                 }
 510                 return -EINVAL;
 511         }
 512
 513         return 1 << p_div_hw;
 514 }
 515
 516 static int _get_table_rate(struct clk_hw *hw,
 517                            struct tegra_clk_pll_freq_table *cfg,
 518                            unsigned long rate, unsigned long parent_rate)
 519 {
 520         struct tegra_clk_pll *pll = to_clk_pll(hw);
 521         struct tegra_clk_pll_freq_table *sel;
 522         int p;
 523
 524         for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 525                 if (sel->input_rate == parent_rate &&
 526                     sel->output_rate == rate)
 527                         break;
 528
 529         if (sel->input_rate == 0)
 530                 return -EINVAL;
 531
 532         if (pll->params->pdiv_tohw) {
 533                 p = _p_div_to_hw(hw, sel->p);
 534                 if (p < 0)
 535                         return p;
 536         } else {
 537                 p = ilog2(sel->p);
 538         }
 539
 540         cfg->input_rate = sel->input_rate;
 541         cfg->output_rate = sel->output_rate;
 542         cfg->m = sel->m;
 543         cfg->n = sel->n;
 544         cfg->p = p;
 545         cfg->cpcon = sel->cpcon;
 546         cfg->sdm_data = sel->sdm_data;
 547
 548         return 0;
 549 }
 550
 551 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 552                       unsigned long rate, unsigned long parent_rate)
 553 {
 554         struct tegra_clk_pll *pll = to_clk_pll(hw);
 555         unsigned long cfreq;
 556         u32 p_div = 0;
 557         int ret;
 558
 559         switch (parent_rate) {
 560         case 12000000:
 561         case 26000000:
 562                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 563                 break;
 564         case 13000000:
 565                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 566                 break;
 567         case 16800000:
 568         case 19200000:
 569                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 570                 break;
 571         case 9600000:
 572         case 28800000:
 573                 /*
 574                  * PLL_P_OUT1 rate is not listed in PLLA table
 575                  */
 576                 cfreq = parent_rate / (parent_rate / 1000000);
 577                 break;
 578         default:
 579                 pr_err("%s Unexpected reference rate %lu\n",
 580                        __func__, parent_rate);
 581                 BUG();
 582         }
 583
 584         /* Raise VCO to guarantee 0.5% accuracy */
 585         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 586              cfg->output_rate <<= 1)
 587                 p_div++;
 588
 589         cfg->m = parent_rate / cfreq;
 590         cfg->n = cfg->output_rate / cfreq;
 591         cfg->cpcon = OUT_OF_TABLE_CPCON;
 592
 593         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
 594             (1 << p_div) > divp_max(pll)
 595             || cfg->output_rate > pll->params->vco_max) {
 596                 return -EINVAL;
 597         }
 598
 599         cfg->output_rate >>= p_div;
 600
 601         if (pll->params->pdiv_tohw) {
 602                 ret = _p_div_to_hw(hw, 1 << p_div);
 603                 if (ret < 0)
 604                         return ret;
 605                 else
 606                         cfg->p = ret;
 607         } else
 608                 cfg->p = p_div;
 609
 610         return 0;
 611 }
 612
 613 /*
 614  * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
 615  * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
 616  * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
 617  * to indicate that SDM is disabled.
 618  *
 619  * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
 620  */
 621 static void clk_pll_set_sdm_data(struct clk_hw *hw,
 622                                  struct tegra_clk_pll_freq_table *cfg)
 623 {
 624         struct tegra_clk_pll *pll = to_clk_pll(hw);
 625         u32 val;
 626         bool enabled;
 627
 628         if (!pll->params->sdm_din_reg)
 629                 return;
 630
 631         if (cfg->sdm_data) {
 632                 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
 633                 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
 634                 pll_writel_sdm_din(val, pll);
 635         }
 636
 637         val = pll_readl_sdm_ctrl(pll);
 638         enabled = (val & sdm_en_mask(pll));
 639
 640         if (cfg->sdm_data == 0 && enabled)
 641                 val &= ~pll->params->sdm_ctrl_en_mask;
 642
 643         if (cfg->sdm_data != 0 && !enabled)
 644                 val |= pll->params->sdm_ctrl_en_mask;
 645
 646         pll_writel_sdm_ctrl(val, pll);
 647 }
 648
 649 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 650                             struct tegra_clk_pll_freq_table *cfg)
 651 {
 652         u32 val;
 653         struct tegra_clk_pll_params *params = pll->params;
 654         struct div_nmp *div_nmp = params->div_nmp;
 655
 656         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 657                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 658                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 659                 val = pll_override_readl(params->pmc_divp_reg, pll);
 660                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 661                 val |= cfg->p << div_nmp->override_divp_shift;
 662                 pll_override_writel(val, params->pmc_divp_reg, pll);
 663
 664                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 665                 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
 666                         (divn_mask(pll) << div_nmp->override_divn_shift));
 667                 val |= (cfg->m << div_nmp->override_divm_shift) |
 668                         (cfg->n << div_nmp->override_divn_shift);
 669                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 670         } else {
 671                 val = pll_readl_base(pll);
 672
 673                 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 674                          divp_mask_shifted(pll));
 675
 676                 val |= (cfg->m << divm_shift(pll)) |
 677                        (cfg->n << divn_shift(pll)) |
 678                        (cfg->p << divp_shift(pll));
 679
 680                 pll_writel_base(val, pll);
 681
 682                 clk_pll_set_sdm_data(&pll->hw, cfg);
 683         }
 684 }
 685
 686 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 687                          struct tegra_clk_pll_freq_table *cfg)
 688 {
 689         u32 val;
 690         struct tegra_clk_pll_params *params = pll->params;
 691         struct div_nmp *div_nmp = params->div_nmp;
 692
 693         *cfg = (struct tegra_clk_pll_freq_table) { };
 694
 695         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 696                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 697                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 698                 val = pll_override_readl(params->pmc_divp_reg, pll);
 699                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 700
 701                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 702                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 703                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 704         }  else {
 705                 val = pll_readl_base(pll);
 706
 707                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 708                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 709                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 710
 711                 if (pll->params->sdm_din_reg) {
 712                         if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
 713                                 val = pll_readl_sdm_din(pll);
 714                                 val &= sdm_din_mask(pll);
 715                                 cfg->sdm_data = sdin_din_to_data(val);
 716                         }
 717                 }
 718         }
 719 }
 720
 721 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 722                               struct tegra_clk_pll_freq_table *cfg,
 723                               unsigned long rate)
 724 {
 725         u32 val;
 726
 727         val = pll_readl_misc(pll);
 728
 729         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 730         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 731
 732         if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 733                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 734                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 735                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 736         } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 737                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 738                 if (rate >= (pll->params->vco_max >> 1))
 739                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 740         }
 741
 742         pll_writel_misc(val, pll);
 743 }
 744
 745 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 746                         unsigned long rate)
 747 {
 748         struct tegra_clk_pll *pll = to_clk_pll(hw);
 749         struct tegra_clk_pll_freq_table old_cfg;
 750         int state, ret = 0;
 751
 752         state = clk_pll_is_enabled(hw);
 753
 754         _get_pll_mnp(pll, &old_cfg);
 755
 756         if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
 757                         (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
 758                 ret = pll->params->dyn_ramp(pll, cfg);
 759                 if (!ret)
 760                         return 0;
 761         }
 762
 763         if (state) {
 764                 pll_clk_stop_ss(pll);
 765                 _clk_pll_disable(hw);
 766         }
 767
 768         if (!pll->params->defaults_set && pll->params->set_defaults)
 769                 pll->params->set_defaults(pll);
 770
 771         _update_pll_mnp(pll, cfg);
 772
 773         if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 774                 _update_pll_cpcon(pll, cfg, rate);
 775
 776         if (state) {
 777                 _clk_pll_enable(hw);
 778                 ret = clk_pll_wait_for_lock(pll);
 779                 pll_clk_start_ss(pll);
 780         }
 781
 782         return ret;
 783 }
 784
 785 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 786                         unsigned long parent_rate)
 787 {
 788         struct tegra_clk_pll *pll = to_clk_pll(hw);
 789         struct tegra_clk_pll_freq_table cfg, old_cfg;
 790         unsigned long flags = 0;
 791         int ret = 0;
 792
 793         if (pll->params->flags & TEGRA_PLL_FIXED) {
 794                 if (rate != pll->params->fixed_rate) {
 795                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 796                                 __func__, clk_hw_get_name(hw),
 797                                 pll->params->fixed_rate, rate);
 798                         return -EINVAL;
 799                 }
 800                 return 0;
 801         }
 802
 803         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 804             pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
 805                 pr_err("%s: Failed to set %s rate %lu\n", __func__,
 806                        clk_hw_get_name(hw), rate);
 807                 WARN_ON(1);
 808                 return -EINVAL;
 809         }
 810         if (pll->lock)
 811                 spin_lock_irqsave(pll->lock, flags);
 812
 813         _get_pll_mnp(pll, &old_cfg);
 814         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
 815                 cfg.p = old_cfg.p;
 816
 817         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
 818                 old_cfg.sdm_data != cfg.sdm_data)
 819                 ret = _program_pll(hw, &cfg, rate);
 820
 821         if (pll->lock)
 822                 spin_unlock_irqrestore(pll->lock, flags);
 823
 824         return ret;
 825 }
 826
 827 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 828                         unsigned long *prate)
 829 {
 830         struct tegra_clk_pll *pll = to_clk_pll(hw);
 831         struct tegra_clk_pll_freq_table cfg;
 832
 833         if (pll->params->flags & TEGRA_PLL_FIXED) {
 834                 /* PLLM/MB are used for memory; we do not change rate */
 835                 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
 836                         return clk_hw_get_rate(hw);
 837                 return pll->params->fixed_rate;
 838         }
 839
 840         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 841             pll->params->calc_rate(hw, &cfg, rate, *prate))
 842                 return -EINVAL;
 843
 844         return cfg.output_rate;
 845 }
 846
 847 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 848                                          unsigned long parent_rate)
 849 {
 850         struct tegra_clk_pll *pll = to_clk_pll(hw);
 851         struct tegra_clk_pll_freq_table cfg;
 852         u32 val;
 853         u64 rate = parent_rate;
 854         int pdiv;
 855
 856         val = pll_readl_base(pll);
 857
 858         if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 859                 return parent_rate;
 860
 861         if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 862             !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 863                         !(val & PLL_BASE_OVERRIDE)) {
 864                 struct tegra_clk_pll_freq_table sel;
 865                 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 866                                         parent_rate)) {
 867                         pr_err("Clock %s has unknown fixed frequency\n",
 868                                clk_hw_get_name(hw));
 869                         BUG();
 870                 }
 871                 return pll->params->fixed_rate;
 872         }
 873
 874         _get_pll_mnp(pll, &cfg);
 875
 876         if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
 877                 pdiv = 1;
 878         } else {
 879                 pdiv = _hw_to_p_div(hw, cfg.p);
 880                 if (pdiv < 0) {
 881                         WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
 882                              clk_hw_get_name(hw), cfg.p);
 883                         pdiv = 1;
 884                 }
 885         }
 886
 887         if (pll->params->set_gain)
 888                 pll->params->set_gain(&cfg);
 889
 890         cfg.m *= pdiv;
 891
 892         rate *= cfg.n;
 893         do_div(rate, cfg.m);
 894
 895         return rate;
 896 }
 897
 898 static int clk_plle_training(struct tegra_clk_pll *pll)
 899 {
 900         u32 val;
 901         unsigned long timeout;
 902
 903         if (!pll->pmc)
 904                 return -ENOSYS;
 905
 906         /*
 907          * PLLE is already disabled, and setup cleared;
 908          * create falling edge on PLLE IDDQ input.
 909          */
 910         val = readl(pll->pmc + PMC_SATA_PWRGT);
 911         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 912         writel(val, pll->pmc + PMC_SATA_PWRGT);
 913
 914         val = readl(pll->pmc + PMC_SATA_PWRGT);
 915         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 916         writel(val, pll->pmc + PMC_SATA_PWRGT);
 917
 918         val = readl(pll->pmc + PMC_SATA_PWRGT);
 919         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 920         writel(val, pll->pmc + PMC_SATA_PWRGT);
 921
 922         val = pll_readl_misc(pll);
 923
 924         timeout = jiffies + msecs_to_jiffies(100);
 925         while (1) {
 926                 val = pll_readl_misc(pll);
 927                 if (val & PLLE_MISC_READY)
 928                         break;
 929                 if (time_after(jiffies, timeout)) {
 930                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 931                         return -EBUSY;
 932                 }
 933                 udelay(300);
 934         }
 935
 936         return 0;
 937 }
 938
 939 static int clk_plle_enable(struct clk_hw *hw)
 940 {
 941         struct tegra_clk_pll *pll = to_clk_pll(hw);
 942         unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 943         struct tegra_clk_pll_freq_table sel;
 944         u32 val;
 945         int err;
 946
 947         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 948                 return -EINVAL;
 949
 950         clk_pll_disable(hw);
 951
 952         val = pll_readl_misc(pll);
 953         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 954         pll_writel_misc(val, pll);
 955
 956         val = pll_readl_misc(pll);
 957         if (!(val & PLLE_MISC_READY)) {
 958                 err = clk_plle_training(pll);
 959                 if (err)
 960                         return err;
 961         }
 962
 963         if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 964                 /* configure dividers */
 965                 val = pll_readl_base(pll);
 966                 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 967                          divm_mask_shifted(pll));
 968                 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 969                 val |= sel.m << divm_shift(pll);
 970                 val |= sel.n << divn_shift(pll);
 971                 val |= sel.p << divp_shift(pll);
 972                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 973                 pll_writel_base(val, pll);
 974         }
 975
 976         val = pll_readl_misc(pll);
 977         val |= PLLE_MISC_SETUP_VALUE;
 978         val |= PLLE_MISC_LOCK_ENABLE;
 979         pll_writel_misc(val, pll);
 980
 981         val = readl(pll->clk_base + PLLE_SS_CTRL);
 982         val &= ~PLLE_SS_COEFFICIENTS_MASK;
 983         val |= PLLE_SS_DISABLE;
 984         writel(val, pll->clk_base + PLLE_SS_CTRL);
 985
 986         val = pll_readl_base(pll);
 987         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 988         pll_writel_base(val, pll);
 989
 990         clk_pll_wait_for_lock(pll);
 991
 992         return 0;
 993 }
 994
 995 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 996                                          unsigned long parent_rate)
 997 {
 998         struct tegra_clk_pll *pll = to_clk_pll(hw);
 999         u32 val = pll_readl_base(pll);
1000         u32 divn = 0, divm = 0, divp = 0;
1001         u64 rate = parent_rate;
1002
1003         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1004         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1005         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1006         divm *= divp;
1007
1008         rate *= divn;
1009         do_div(rate, divm);
1010         return rate;
1011 }
1012
1013 const struct clk_ops tegra_clk_pll_ops = {
1014         .is_enabled = clk_pll_is_enabled,
1015         .enable = clk_pll_enable,
1016         .disable = clk_pll_disable,
1017         .recalc_rate = clk_pll_recalc_rate,
1018         .round_rate = clk_pll_round_rate,
1019         .set_rate = clk_pll_set_rate,
1020 };
1021
1022 const struct clk_ops tegra_clk_plle_ops = {
1023         .recalc_rate = clk_plle_recalc_rate,
1024         .is_enabled = clk_pll_is_enabled,
1025         .disable = clk_pll_disable,
1026         .enable = clk_plle_enable,
1027 };
1028
1029 /*
1030  * Structure defining the fields for USB UTMI clocks Parameters.
1031  */
1032 struct utmi_clk_param {
1033         /* Oscillator Frequency in Hz */
1034         u32 osc_frequency;
1035         /* UTMIP PLL Enable Delay Count  */
1036         u8 enable_delay_count;
1037         /* UTMIP PLL Stable count */
1038         u8 stable_count;
1039         /*  UTMIP PLL Active delay count */
1040         u8 active_delay_count;
1041         /* UTMIP PLL Xtal frequency count */
1042         u8 xtal_freq_count;
1043 };
1044
1045 static const struct utmi_clk_param utmi_parameters[] = {
1046         {
1047                 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1048                 .stable_count = 0x33, .active_delay_count = 0x05,
1049                 .xtal_freq_count = 0x7f
1050         }, {
1051                 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1052                 .stable_count = 0x4b, .active_delay_count = 0x06,
1053                 .xtal_freq_count = 0xbb
1054         }, {
1055                 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1056                 .stable_count = 0x2f, .active_delay_count = 0x04,
1057                 .xtal_freq_count = 0x76
1058         }, {
1059                 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1060                 .stable_count = 0x66, .active_delay_count = 0x09,
1061                 .xtal_freq_count = 0xfe
1062         }, {
1063                 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1064                 .stable_count = 0x41, .active_delay_count = 0x0a,
1065                 .xtal_freq_count = 0xa4
1066         }, {
1067                 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1068                 .stable_count = 0x0, .active_delay_count = 0x6,
1069                 .xtal_freq_count = 0x80
1070         },
1071 };
1072
1073 static int clk_pllu_enable(struct clk_hw *hw)
1074 {
1075         struct tegra_clk_pll *pll = to_clk_pll(hw);
1076         struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1077         struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1078         const struct utmi_clk_param *params = NULL;
1079         unsigned long flags = 0, input_rate;
1080         unsigned int i;
1081         int ret = 0;
1082         u32 value;
1083
1084         if (!osc) {
1085                 pr_err("%s: failed to get OSC clock\n", __func__);
1086                 return -EINVAL;
1087         }
1088
1089         input_rate = clk_hw_get_rate(osc);
1090
1091         if (pll->lock)
1092                 spin_lock_irqsave(pll->lock, flags);
1093
1094         if (!clk_pll_is_enabled(hw))
1095                 _clk_pll_enable(hw);
1096
1097         ret = clk_pll_wait_for_lock(pll);
1098         if (ret < 0)
1099                 goto out;
1100
1101         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1102                 if (input_rate == utmi_parameters[i].osc_frequency) {
1103                         params = &utmi_parameters[i];
1104                         break;
1105                 }
1106         }
1107
1108         if (!params) {
1109                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1110                        input_rate);
1111                 ret = -EINVAL;
1112                 goto out;
1113         }
1114
1115         value = pll_readl_base(pll);
1116         value &= ~PLLU_BASE_OVERRIDE;
1117         pll_writel_base(value, pll);
1118
1119         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1120         /* Program UTMIP PLL stable and active counts */
1121         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1122         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1123         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1124         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1125         /* Remove power downs from UTMIP PLL control bits */
1126         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1127         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1128         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1129         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1130
1131         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1132         /* Program UTMIP PLL delay and oscillator frequency counts */
1133         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1134         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1135         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1136         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1137         /* Remove power downs from UTMIP PLL control bits */
1138         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1139         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1140         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1141         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1142
1143 out:
1144         if (pll->lock)
1145                 spin_unlock_irqrestore(pll->lock, flags);
1146
1147         return ret;
1148 }
1149
1150 static const struct clk_ops tegra_clk_pllu_ops = {
1151         .is_enabled = clk_pll_is_enabled,
1152         .enable = clk_pllu_enable,
1153         .disable = clk_pll_disable,
1154         .recalc_rate = clk_pll_recalc_rate,
1155         .round_rate = clk_pll_round_rate,
1156         .set_rate = clk_pll_set_rate,
1157 };
1158
1159 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1160                            unsigned long parent_rate)
1161 {
1162         u16 mdiv = parent_rate / pll_params->cf_min;
1163
1164         if (pll_params->flags & TEGRA_MDIV_NEW)
1165                 return (!pll_params->mdiv_default ? mdiv :
1166                         min(mdiv, pll_params->mdiv_default));
1167
1168         if (pll_params->mdiv_default)
1169                 return pll_params->mdiv_default;
1170
1171         if (parent_rate > pll_params->cf_max)
1172                 return 2;
1173         else
1174                 return 1;
1175 }
1176
1177 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1178                                 struct tegra_clk_pll_freq_table *cfg,
1179                                 unsigned long rate, unsigned long parent_rate)
1180 {
1181         struct tegra_clk_pll *pll = to_clk_pll(hw);
1182         unsigned int p;
1183         int p_div;
1184
1185         if (!rate)
1186                 return -EINVAL;
1187
1188         p = DIV_ROUND_UP(pll->params->vco_min, rate);
1189         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1190         cfg->output_rate = rate * p;
1191         cfg->n = cfg->output_rate * cfg->m / parent_rate;
1192         cfg->input_rate = parent_rate;
1193
1194         p_div = _p_div_to_hw(hw, p);
1195         if (p_div < 0)
1196                 return p_div;
1197
1198         cfg->p = p_div;
1199
1200         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1201                 return -EINVAL;
1202
1203         return 0;
1204 }
1205
1206 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1207         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1208         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1209         defined(CONFIG_ARCH_TEGRA_210_SOC)
1210
1211 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1212 {
1213         struct tegra_clk_pll *pll = to_clk_pll(hw);
1214
1215         return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1216 }
1217
1218 static unsigned long _clip_vco_min(unsigned long vco_min,
1219                                    unsigned long parent_rate)
1220 {
1221         return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1222 }
1223
1224 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1225                                void __iomem *clk_base,
1226                                unsigned long parent_rate)
1227 {
1228         u32 val;
1229         u32 step_a, step_b;
1230
1231         switch (parent_rate) {
1232         case 12000000:
1233         case 13000000:
1234         case 26000000:
1235                 step_a = 0x2B;
1236                 step_b = 0x0B;
1237                 break;
1238         case 16800000:
1239                 step_a = 0x1A;
1240                 step_b = 0x09;
1241                 break;
1242         case 19200000:
1243                 step_a = 0x12;
1244                 step_b = 0x08;
1245                 break;
1246         default:
1247                 pr_err("%s: Unexpected reference rate %lu\n",
1248                         __func__, parent_rate);
1249                 WARN_ON(1);
1250                 return -EINVAL;
1251         }
1252
1253         val = step_a << pll_params->stepa_shift;
1254         val |= step_b << pll_params->stepb_shift;
1255         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1256
1257         return 0;
1258 }
1259
1260 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1261                               struct tegra_clk_pll_freq_table *cfg,
1262                               unsigned long rate, unsigned long parent_rate)
1263 {
1264         struct tegra_clk_pll *pll = to_clk_pll(hw);
1265         int err = 0;
1266
1267         err = _get_table_rate(hw, cfg, rate, parent_rate);
1268         if (err < 0)
1269                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1270         else {
1271                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1272                         WARN_ON(1);
1273                         err = -EINVAL;
1274                         goto out;
1275                 }
1276         }
1277
1278         if (cfg->p >  pll->params->max_p)
1279                 err = -EINVAL;
1280
1281 out:
1282         return err;
1283 }
1284
1285 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1286                                 unsigned long parent_rate)
1287 {
1288         struct tegra_clk_pll *pll = to_clk_pll(hw);
1289         struct tegra_clk_pll_freq_table cfg, old_cfg;
1290         unsigned long flags = 0;
1291         int ret;
1292
1293         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1294         if (ret < 0)
1295                 return ret;
1296
1297         if (pll->lock)
1298                 spin_lock_irqsave(pll->lock, flags);
1299
1300         _get_pll_mnp(pll, &old_cfg);
1301         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1302                 cfg.p = old_cfg.p;
1303
1304         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1305                 ret = _program_pll(hw, &cfg, rate);
1306
1307         if (pll->lock)
1308                 spin_unlock_irqrestore(pll->lock, flags);
1309
1310         return ret;
1311 }
1312
1313 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1314                                 unsigned long *prate)
1315 {
1316         struct tegra_clk_pll *pll = to_clk_pll(hw);
1317         struct tegra_clk_pll_freq_table cfg;
1318         int ret, p_div;
1319         u64 output_rate = *prate;
1320
1321         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1322         if (ret < 0)
1323                 return ret;
1324
1325         p_div = _hw_to_p_div(hw, cfg.p);
1326         if (p_div < 0)
1327                 return p_div;
1328
1329         if (pll->params->set_gain)
1330                 pll->params->set_gain(&cfg);
1331
1332         output_rate *= cfg.n;
1333         do_div(output_rate, cfg.m * p_div);
1334
1335         return output_rate;
1336 }
1337
1338 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1339 {
1340         u32 val;
1341
1342         val = pll_readl_misc(pll);
1343         val |= PLLCX_MISC_STROBE;
1344         pll_writel_misc(val, pll);
1345         udelay(2);
1346
1347         val &= ~PLLCX_MISC_STROBE;
1348         pll_writel_misc(val, pll);
1349 }
1350
1351 static int clk_pllc_enable(struct clk_hw *hw)
1352 {
1353         struct tegra_clk_pll *pll = to_clk_pll(hw);
1354         u32 val;
1355         int ret;
1356         unsigned long flags = 0;
1357
1358         if (pll->lock)
1359                 spin_lock_irqsave(pll->lock, flags);
1360
1361         _clk_pll_enable(hw);
1362         udelay(2);
1363
1364         val = pll_readl_misc(pll);
1365         val &= ~PLLCX_MISC_RESET;
1366         pll_writel_misc(val, pll);
1367         udelay(2);
1368
1369         _pllcx_strobe(pll);
1370
1371         ret = clk_pll_wait_for_lock(pll);
1372
1373         if (pll->lock)
1374                 spin_unlock_irqrestore(pll->lock, flags);
1375
1376         return ret;
1377 }
1378
1379 static void _clk_pllc_disable(struct clk_hw *hw)
1380 {
1381         struct tegra_clk_pll *pll = to_clk_pll(hw);
1382         u32 val;
1383
1384         _clk_pll_disable(hw);
1385
1386         val = pll_readl_misc(pll);
1387         val |= PLLCX_MISC_RESET;
1388         pll_writel_misc(val, pll);
1389         udelay(2);
1390 }
1391
1392 static void clk_pllc_disable(struct clk_hw *hw)
1393 {
1394         struct tegra_clk_pll *pll = to_clk_pll(hw);
1395         unsigned long flags = 0;
1396
1397         if (pll->lock)
1398                 spin_lock_irqsave(pll->lock, flags);
1399
1400         _clk_pllc_disable(hw);
1401
1402         if (pll->lock)
1403                 spin_unlock_irqrestore(pll->lock, flags);
1404 }
1405
1406 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1407                                         unsigned long input_rate, u32 n)
1408 {
1409         u32 val, n_threshold;
1410
1411         switch (input_rate) {
1412         case 12000000:
1413                 n_threshold = 70;
1414                 break;
1415         case 13000000:
1416         case 26000000:
1417                 n_threshold = 71;
1418                 break;
1419         case 16800000:
1420                 n_threshold = 55;
1421                 break;
1422         case 19200000:
1423                 n_threshold = 48;
1424                 break;
1425         default:
1426                 pr_err("%s: Unexpected reference rate %lu\n",
1427                         __func__, input_rate);
1428                 return -EINVAL;
1429         }
1430
1431         val = pll_readl_misc(pll);
1432         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1433         val |= n <= n_threshold ?
1434                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1435         pll_writel_misc(val, pll);
1436
1437         return 0;
1438 }
1439
1440 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1441                                 unsigned long parent_rate)
1442 {
1443         struct tegra_clk_pll_freq_table cfg, old_cfg;
1444         struct tegra_clk_pll *pll = to_clk_pll(hw);
1445         unsigned long flags = 0;
1446         int state, ret = 0;
1447
1448         if (pll->lock)
1449                 spin_lock_irqsave(pll->lock, flags);
1450
1451         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1452         if (ret < 0)
1453                 goto out;
1454
1455         _get_pll_mnp(pll, &old_cfg);
1456
1457         if (cfg.m != old_cfg.m) {
1458                 WARN_ON(1);
1459                 goto out;
1460         }
1461
1462         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1463                 goto out;
1464
1465         state = clk_pll_is_enabled(hw);
1466         if (state)
1467                 _clk_pllc_disable(hw);
1468
1469         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1470         if (ret < 0)
1471                 goto out;
1472
1473         _update_pll_mnp(pll, &cfg);
1474
1475         if (state)
1476                 ret = clk_pllc_enable(hw);
1477
1478 out:
1479         if (pll->lock)
1480                 spin_unlock_irqrestore(pll->lock, flags);
1481
1482         return ret;
1483 }
1484
1485 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1486                              struct tegra_clk_pll_freq_table *cfg,
1487                              unsigned long rate, unsigned long parent_rate)
1488 {
1489         u16 m, n;
1490         u64 output_rate = parent_rate;
1491
1492         m = _pll_fixed_mdiv(pll->params, parent_rate);
1493         n = rate * m / parent_rate;
1494
1495         output_rate *= n;
1496         do_div(output_rate, m);
1497
1498         if (cfg) {
1499                 cfg->m = m;
1500                 cfg->n = n;
1501         }
1502
1503         return output_rate;
1504 }
1505
1506 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1507                                 unsigned long parent_rate)
1508 {
1509         struct tegra_clk_pll_freq_table cfg, old_cfg;
1510         struct tegra_clk_pll *pll = to_clk_pll(hw);
1511         unsigned long flags = 0;
1512         int state, ret = 0;
1513
1514         if (pll->lock)
1515                 spin_lock_irqsave(pll->lock, flags);
1516
1517         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1518         _get_pll_mnp(pll, &old_cfg);
1519         cfg.p = old_cfg.p;
1520
1521         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1522                 state = clk_pll_is_enabled(hw);
1523                 if (state)
1524                         _clk_pll_disable(hw);
1525
1526                 _update_pll_mnp(pll, &cfg);
1527
1528                 if (state) {
1529                         _clk_pll_enable(hw);
1530                         ret = clk_pll_wait_for_lock(pll);
1531                 }
1532         }
1533
1534         if (pll->lock)
1535                 spin_unlock_irqrestore(pll->lock, flags);
1536
1537         return ret;
1538 }
1539
1540 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1541                                          unsigned long parent_rate)
1542 {
1543         struct tegra_clk_pll_freq_table cfg;
1544         struct tegra_clk_pll *pll = to_clk_pll(hw);
1545         u64 rate = parent_rate;
1546
1547         _get_pll_mnp(pll, &cfg);
1548
1549         rate *= cfg.n;
1550         do_div(rate, cfg.m);
1551
1552         return rate;
1553 }
1554
1555 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1556                                  unsigned long *prate)
1557 {
1558         struct tegra_clk_pll *pll = to_clk_pll(hw);
1559
1560         return _pllre_calc_rate(pll, NULL, rate, *prate);
1561 }
1562
1563 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1564 {
1565         struct tegra_clk_pll *pll = to_clk_pll(hw);
1566         struct tegra_clk_pll_freq_table sel;
1567         u32 val;
1568         int ret;
1569         unsigned long flags = 0;
1570         unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1571
1572         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1573                 return -EINVAL;
1574
1575         if (pll->lock)
1576                 spin_lock_irqsave(pll->lock, flags);
1577
1578         val = pll_readl_base(pll);
1579         val &= ~BIT(29); /* Disable lock override */
1580         pll_writel_base(val, pll);
1581
1582         val = pll_readl(pll->params->aux_reg, pll);
1583         val |= PLLE_AUX_ENABLE_SWCTL;
1584         val &= ~PLLE_AUX_SEQ_ENABLE;
1585         pll_writel(val, pll->params->aux_reg, pll);
1586         udelay(1);
1587
1588         val = pll_readl_misc(pll);
1589         val |= PLLE_MISC_LOCK_ENABLE;
1590         val |= PLLE_MISC_IDDQ_SW_CTRL;
1591         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1592         val |= PLLE_MISC_PLLE_PTS;
1593         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1594         pll_writel_misc(val, pll);
1595         udelay(5);
1596
1597         val = pll_readl(PLLE_SS_CTRL, pll);
1598         val |= PLLE_SS_DISABLE;
1599         pll_writel(val, PLLE_SS_CTRL, pll);
1600
1601         val = pll_readl_base(pll);
1602         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1603                  divm_mask_shifted(pll));
1604         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1605         val |= sel.m << divm_shift(pll);
1606         val |= sel.n << divn_shift(pll);
1607         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1608         pll_writel_base(val, pll);
1609         udelay(1);
1610
1611         _clk_pll_enable(hw);
1612         ret = clk_pll_wait_for_lock(pll);
1613
1614         if (ret < 0)
1615                 goto out;
1616
1617         val = pll_readl(PLLE_SS_CTRL, pll);
1618         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1619         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1620         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1621         pll_writel(val, PLLE_SS_CTRL, pll);
1622         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1623         pll_writel(val, PLLE_SS_CTRL, pll);
1624         udelay(1);
1625         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1626         pll_writel(val, PLLE_SS_CTRL, pll);
1627         udelay(1);
1628
1629         /* Enable hw control of xusb brick pll */
1630         val = pll_readl_misc(pll);
1631         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1632         pll_writel_misc(val, pll);
1633
1634         val = pll_readl(pll->params->aux_reg, pll);
1635         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1636         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1637         pll_writel(val, pll->params->aux_reg, pll);
1638         udelay(1);
1639         val |= PLLE_AUX_SEQ_ENABLE;
1640         pll_writel(val, pll->params->aux_reg, pll);
1641
1642         val = pll_readl(XUSBIO_PLL_CFG0, pll);
1643         val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1644                 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1645         val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1646                  XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1647         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1648         udelay(1);
1649         val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1650         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1651
1652         /* Enable hw control of SATA pll */
1653         val = pll_readl(SATA_PLL_CFG0, pll);
1654         val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1655         val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1656         val |= SATA_PLL_CFG0_SEQ_START_STATE;
1657         pll_writel(val, SATA_PLL_CFG0, pll);
1658
1659         udelay(1);
1660
1661         val = pll_readl(SATA_PLL_CFG0, pll);
1662         val |= SATA_PLL_CFG0_SEQ_ENABLE;
1663         pll_writel(val, SATA_PLL_CFG0, pll);
1664
1665 out:
1666         if (pll->lock)
1667                 spin_unlock_irqrestore(pll->lock, flags);
1668
1669         return ret;
1670 }
1671
1672 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1673 {
1674         struct tegra_clk_pll *pll = to_clk_pll(hw);
1675         unsigned long flags = 0;
1676         u32 val;
1677
1678         if (pll->lock)
1679                 spin_lock_irqsave(pll->lock, flags);
1680
1681         _clk_pll_disable(hw);
1682
1683         val = pll_readl_misc(pll);
1684         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1685         pll_writel_misc(val, pll);
1686         udelay(1);
1687
1688         if (pll->lock)
1689                 spin_unlock_irqrestore(pll->lock, flags);
1690 }
1691
1692 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1693 {
1694         struct tegra_clk_pll *pll = to_clk_pll(hw);
1695         const struct utmi_clk_param *params = NULL;
1696         struct clk *osc = __clk_lookup("osc");
1697         unsigned long flags = 0, input_rate;
1698         unsigned int i;
1699         int ret = 0;
1700         u32 value;
1701
1702         if (!osc) {
1703                 pr_err("%s: failed to get OSC clock\n", __func__);
1704                 return -EINVAL;
1705         }
1706
1707         input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1708
1709         if (pll->lock)
1710                 spin_lock_irqsave(pll->lock, flags);
1711
1712         if (!clk_pll_is_enabled(hw))
1713                 _clk_pll_enable(hw);
1714
1715         ret = clk_pll_wait_for_lock(pll);
1716         if (ret < 0)
1717                 goto out;
1718
1719         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1720                 if (input_rate == utmi_parameters[i].osc_frequency) {
1721                         params = &utmi_parameters[i];
1722                         break;
1723                 }
1724         }
1725
1726         if (!params) {
1727                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1728                        input_rate);
1729                 ret = -EINVAL;
1730                 goto out;
1731         }
1732
1733         value = pll_readl_base(pll);
1734         value &= ~PLLU_BASE_OVERRIDE;
1735         pll_writel_base(value, pll);
1736
1737         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1738         /* Program UTMIP PLL stable and active counts */
1739         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1740         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1741         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1742         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1743         /* Remove power downs from UTMIP PLL control bits */
1744         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1745         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1746         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1747         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1748
1749         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1750         /* Program UTMIP PLL delay and oscillator frequency counts */
1751         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1752         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1753         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1754         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1755         /* Remove power downs from UTMIP PLL control bits */
1756         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1757         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1758         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1759         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1760         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1761
1762         /* Setup HW control of UTMIPLL */
1763         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1764         value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1765         value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1766         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1767         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1768
1769         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1770         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1771         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1772         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1773
1774         udelay(1);
1775
1776         /*
1777          * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1778          * to USB2
1779          */
1780         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1781         value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1782         value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1783         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1784
1785         udelay(1);
1786
1787         /* Enable HW control of UTMIPLL */
1788         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1789         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1790         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1791
1792 out:
1793         if (pll->lock)
1794                 spin_unlock_irqrestore(pll->lock, flags);
1795
1796         return ret;
1797 }
1798 #endif
1799
1800 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1801                 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1802                 spinlock_t *lock)
1803 {
1804         struct tegra_clk_pll *pll;
1805
1806         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1807         if (!pll)
1808                 return ERR_PTR(-ENOMEM);
1809
1810         pll->clk_base = clk_base;
1811         pll->pmc = pmc;
1812
1813         pll->params = pll_params;
1814         pll->lock = lock;
1815
1816         if (!pll_params->div_nmp)
1817                 pll_params->div_nmp = &default_nmp;
1818
1819         return pll;
1820 }
1821
1822 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1823                 const char *name, const char *parent_name, unsigned long flags,
1824                 const struct clk_ops *ops)
1825 {
1826         struct clk_init_data init;
1827
1828         init.name = name;
1829         init.ops = ops;
1830         init.flags = flags;
1831         init.parent_names = (parent_name ? &parent_name : NULL);
1832         init.num_parents = (parent_name ? 1 : 0);
1833
1834         /* Default to _calc_rate if unspecified */
1835         if (!pll->params->calc_rate) {
1836                 if (pll->params->flags & TEGRA_PLLM)
1837                         pll->params->calc_rate = _calc_dynamic_ramp_rate;
1838                 else
1839                         pll->params->calc_rate = _calc_rate;
1840         }
1841
1842         if (pll->params->set_defaults)
1843                 pll->params->set_defaults(pll);
1844
1845         /* Data in .init is copied by clk_register(), so stack variable OK */
1846         pll->hw.init = &init;
1847
1848         return clk_register(NULL, &pll->hw);
1849 }
1850
1851 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1852                 void __iomem *clk_base, void __iomem *pmc,
1853                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1854                 spinlock_t *lock)
1855 {
1856         struct tegra_clk_pll *pll;
1857         struct clk *clk;
1858
1859         pll_params->flags |= TEGRA_PLL_BYPASS;
1860
1861         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1862         if (IS_ERR(pll))
1863                 return ERR_CAST(pll);
1864
1865         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1866                                       &tegra_clk_pll_ops);
1867         if (IS_ERR(clk))
1868                 kfree(pll);
1869
1870         return clk;
1871 }
1872
1873 static struct div_nmp pll_e_nmp = {
1874         .divn_shift = PLLE_BASE_DIVN_SHIFT,
1875         .divn_width = PLLE_BASE_DIVN_WIDTH,
1876         .divm_shift = PLLE_BASE_DIVM_SHIFT,
1877         .divm_width = PLLE_BASE_DIVM_WIDTH,
1878         .divp_shift = PLLE_BASE_DIVP_SHIFT,
1879         .divp_width = PLLE_BASE_DIVP_WIDTH,
1880 };
1881
1882 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1883                 void __iomem *clk_base, void __iomem *pmc,
1884                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1885                 spinlock_t *lock)
1886 {
1887         struct tegra_clk_pll *pll;
1888         struct clk *clk;
1889
1890         pll_params->flags |= TEGRA_PLL_BYPASS;
1891
1892         if (!pll_params->div_nmp)
1893                 pll_params->div_nmp = &pll_e_nmp;
1894
1895         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1896         if (IS_ERR(pll))
1897                 return ERR_CAST(pll);
1898
1899         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1900                                       &tegra_clk_plle_ops);
1901         if (IS_ERR(clk))
1902                 kfree(pll);
1903
1904         return clk;
1905 }
1906
1907 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1908                 void __iomem *clk_base, unsigned long flags,
1909                 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1910 {
1911         struct tegra_clk_pll *pll;
1912         struct clk *clk;
1913
1914         pll_params->flags |= TEGRA_PLLU;
1915
1916         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1917         if (IS_ERR(pll))
1918                 return ERR_CAST(pll);
1919
1920         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1921                                       &tegra_clk_pllu_ops);
1922         if (IS_ERR(clk))
1923                 kfree(pll);
1924
1925         return clk;
1926 }
1927
1928 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1929         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1930         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1931         defined(CONFIG_ARCH_TEGRA_210_SOC)
1932 static const struct clk_ops tegra_clk_pllxc_ops = {
1933         .is_enabled = clk_pll_is_enabled,
1934         .enable = clk_pll_enable,
1935         .disable = clk_pll_disable,
1936         .recalc_rate = clk_pll_recalc_rate,
1937         .round_rate = clk_pll_ramp_round_rate,
1938         .set_rate = clk_pllxc_set_rate,
1939 };
1940
1941 static const struct clk_ops tegra_clk_pllc_ops = {
1942         .is_enabled = clk_pll_is_enabled,
1943         .enable = clk_pllc_enable,
1944         .disable = clk_pllc_disable,
1945         .recalc_rate = clk_pll_recalc_rate,
1946         .round_rate = clk_pll_ramp_round_rate,
1947         .set_rate = clk_pllc_set_rate,
1948 };
1949
1950 static const struct clk_ops tegra_clk_pllre_ops = {
1951         .is_enabled = clk_pll_is_enabled,
1952         .enable = clk_pll_enable,
1953         .disable = clk_pll_disable,
1954         .recalc_rate = clk_pllre_recalc_rate,
1955         .round_rate = clk_pllre_round_rate,
1956         .set_rate = clk_pllre_set_rate,
1957 };
1958
1959 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1960         .is_enabled =  clk_pll_is_enabled,
1961         .enable = clk_plle_tegra114_enable,
1962         .disable = clk_plle_tegra114_disable,
1963         .recalc_rate = clk_pll_recalc_rate,
1964 };
1965
1966 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
1967         .is_enabled =  clk_pll_is_enabled,
1968         .enable = clk_pllu_tegra114_enable,
1969         .disable = clk_pll_disable,
1970         .recalc_rate = clk_pll_recalc_rate,
1971 };
1972
1973 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1974                           void __iomem *clk_base, void __iomem *pmc,
1975                           unsigned long flags,
1976                           struct tegra_clk_pll_params *pll_params,
1977                           spinlock_t *lock)
1978 {
1979         struct tegra_clk_pll *pll;
1980         struct clk *clk, *parent;
1981         unsigned long parent_rate;
1982         u32 val, val_iddq;
1983
1984         parent = __clk_lookup(parent_name);
1985         if (!parent) {
1986                 WARN(1, "parent clk %s of %s must be registered first\n",
1987                         parent_name, name);
1988                 return ERR_PTR(-EINVAL);
1989         }
1990
1991         if (!pll_params->pdiv_tohw)
1992                 return ERR_PTR(-EINVAL);
1993
1994         parent_rate = clk_get_rate(parent);
1995
1996         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1997
1998         if (pll_params->adjust_vco)
1999                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2000                                                              parent_rate);
2001
2002         /*
2003          * If the pll has a set_defaults callback, it will take care of
2004          * configuring dynamic ramping and setting IDDQ in that path.
2005          */
2006         if (!pll_params->set_defaults) {
2007                 int err;
2008
2009                 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2010                 if (err)
2011                         return ERR_PTR(err);
2012
2013                 val = readl_relaxed(clk_base + pll_params->base_reg);
2014                 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2015
2016                 if (val & PLL_BASE_ENABLE)
2017                         WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2018                 else {
2019                         val_iddq |= BIT(pll_params->iddq_bit_idx);
2020                         writel_relaxed(val_iddq,
2021                                        clk_base + pll_params->iddq_reg);
2022                 }
2023         }
2024
2025         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2026         if (IS_ERR(pll))
2027                 return ERR_CAST(pll);
2028
2029         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2030                                       &tegra_clk_pllxc_ops);
2031         if (IS_ERR(clk))
2032                 kfree(pll);
2033
2034         return clk;
2035 }
2036
2037 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2038                           void __iomem *clk_base, void __iomem *pmc,
2039                           unsigned long flags,
2040                           struct tegra_clk_pll_params *pll_params,
2041                           spinlock_t *lock, unsigned long parent_rate)
2042 {
2043         u32 val;
2044         struct tegra_clk_pll *pll;
2045         struct clk *clk;
2046
2047         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2048
2049         if (pll_params->adjust_vco)
2050                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2051                                                              parent_rate);
2052
2053         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2054         if (IS_ERR(pll))
2055                 return ERR_CAST(pll);
2056
2057         /* program minimum rate by default */
2058
2059         val = pll_readl_base(pll);
2060         if (val & PLL_BASE_ENABLE)
2061                 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2062                                 BIT(pll_params->iddq_bit_idx));
2063         else {
2064                 int m;
2065
2066                 m = _pll_fixed_mdiv(pll_params, parent_rate);
2067                 val = m << divm_shift(pll);
2068                 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2069                 pll_writel_base(val, pll);
2070         }
2071
2072         /* disable lock override */
2073
2074         val = pll_readl_misc(pll);
2075         val &= ~BIT(29);
2076         pll_writel_misc(val, pll);
2077
2078         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2079                                       &tegra_clk_pllre_ops);
2080         if (IS_ERR(clk))
2081                 kfree(pll);
2082
2083         return clk;
2084 }
2085
2086 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2087                           void __iomem *clk_base, void __iomem *pmc,
2088                           unsigned long flags,
2089                           struct tegra_clk_pll_params *pll_params,
2090                           spinlock_t *lock)
2091 {
2092         struct tegra_clk_pll *pll;
2093         struct clk *clk, *parent;
2094         unsigned long parent_rate;
2095
2096         if (!pll_params->pdiv_tohw)
2097                 return ERR_PTR(-EINVAL);
2098
2099         parent = __clk_lookup(parent_name);
2100         if (!parent) {
2101                 WARN(1, "parent clk %s of %s must be registered first\n",
2102                         parent_name, name);
2103                 return ERR_PTR(-EINVAL);
2104         }
2105
2106         parent_rate = clk_get_rate(parent);
2107
2108         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2109
2110         if (pll_params->adjust_vco)
2111                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2112                                                              parent_rate);
2113
2114         pll_params->flags |= TEGRA_PLL_BYPASS;
2115         pll_params->flags |= TEGRA_PLLM;
2116         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2117         if (IS_ERR(pll))
2118                 return ERR_CAST(pll);
2119
2120         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2121                                       &tegra_clk_pll_ops);
2122         if (IS_ERR(clk))
2123                 kfree(pll);
2124
2125         return clk;
2126 }
2127
2128 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2129                           void __iomem *clk_base, void __iomem *pmc,
2130                           unsigned long flags,
2131                           struct tegra_clk_pll_params *pll_params,
2132                           spinlock_t *lock)
2133 {
2134         struct clk *parent, *clk;
2135         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2136         struct tegra_clk_pll *pll;
2137         struct tegra_clk_pll_freq_table cfg;
2138         unsigned long parent_rate;
2139
2140         if (!p_tohw)
2141                 return ERR_PTR(-EINVAL);
2142
2143         parent = __clk_lookup(parent_name);
2144         if (!parent) {
2145                 WARN(1, "parent clk %s of %s must be registered first\n",
2146                         parent_name, name);
2147                 return ERR_PTR(-EINVAL);
2148         }
2149
2150         parent_rate = clk_get_rate(parent);
2151
2152         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2153
2154         pll_params->flags |= TEGRA_PLL_BYPASS;
2155         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2156         if (IS_ERR(pll))
2157                 return ERR_CAST(pll);
2158
2159         /*
2160          * Most of PLLC register fields are shadowed, and can not be read
2161          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2162          * Initialize PLL to default state: disabled, reset; shadow registers
2163          * loaded with default parameters; dividers are preset for half of
2164          * minimum VCO rate (the latter assured that shadowed divider settings
2165          * are within supported range).
2166          */
2167
2168         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2169         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2170
2171         while (p_tohw->pdiv) {
2172                 if (p_tohw->pdiv == 2) {
2173                         cfg.p = p_tohw->hw_val;
2174                         break;
2175                 }
2176                 p_tohw++;
2177         }
2178
2179         if (!p_tohw->pdiv) {
2180                 WARN_ON(1);
2181                 return ERR_PTR(-EINVAL);
2182         }
2183
2184         pll_writel_base(0, pll);
2185         _update_pll_mnp(pll, &cfg);
2186
2187         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2188         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2189         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2190         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2191
2192         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2193
2194         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2195                                       &tegra_clk_pllc_ops);
2196         if (IS_ERR(clk))
2197                 kfree(pll);
2198
2199         return clk;
2200 }
2201
2202 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2203                                 const char *parent_name,
2204                                 void __iomem *clk_base, unsigned long flags,
2205                                 struct tegra_clk_pll_params *pll_params,
2206                                 spinlock_t *lock)
2207 {
2208         struct tegra_clk_pll *pll;
2209         struct clk *clk;
2210         u32 val, val_aux;
2211
2212         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2213         if (IS_ERR(pll))
2214                 return ERR_CAST(pll);
2215
2216         /* ensure parent is set to pll_re_vco */
2217
2218         val = pll_readl_base(pll);
2219         val_aux = pll_readl(pll_params->aux_reg, pll);
2220
2221         if (val & PLL_BASE_ENABLE) {
2222                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2223                         (val_aux & PLLE_AUX_PLLP_SEL))
2224                         WARN(1, "pll_e enabled with unsupported parent %s\n",
2225                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2226                                         "pll_re_vco");
2227         } else {
2228                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2229                 pll_writel(val_aux, pll_params->aux_reg, pll);
2230         }
2231
2232         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2233                                       &tegra_clk_plle_tegra114_ops);
2234         if (IS_ERR(clk))
2235                 kfree(pll);
2236
2237         return clk;
2238 }
2239
2240 struct clk *
2241 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2242                                  void __iomem *clk_base, unsigned long flags,
2243                                  struct tegra_clk_pll_params *pll_params,
2244                                  spinlock_t *lock)
2245 {
2246         struct tegra_clk_pll *pll;
2247         struct clk *clk;
2248
2249         pll_params->flags |= TEGRA_PLLU;
2250
2251         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2252         if (IS_ERR(pll))
2253                 return ERR_CAST(pll);
2254
2255         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2256                                       &tegra_clk_pllu_tegra114_ops);
2257         if (IS_ERR(clk))
2258                 kfree(pll);
2259
2260         return clk;
2261 }
2262 #endif
2263
2264 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2265 static const struct clk_ops tegra_clk_pllss_ops = {
2266         .is_enabled = clk_pll_is_enabled,
2267         .enable = clk_pll_enable,
2268         .disable = clk_pll_disable,
2269         .recalc_rate = clk_pll_recalc_rate,
2270         .round_rate = clk_pll_ramp_round_rate,
2271         .set_rate = clk_pllxc_set_rate,
2272 };
2273
2274 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2275                                 void __iomem *clk_base, unsigned long flags,
2276                                 struct tegra_clk_pll_params *pll_params,
2277                                 spinlock_t *lock)
2278 {
2279         struct tegra_clk_pll *pll;
2280         struct clk *clk, *parent;
2281         struct tegra_clk_pll_freq_table cfg;
2282         unsigned long parent_rate;
2283         u32 val, val_iddq;
2284         int i;
2285
2286         if (!pll_params->div_nmp)
2287                 return ERR_PTR(-EINVAL);
2288
2289         parent = __clk_lookup(parent_name);
2290         if (!parent) {
2291                 WARN(1, "parent clk %s of %s must be registered first\n",
2292                         parent_name, name);
2293                 return ERR_PTR(-EINVAL);
2294         }
2295
2296         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2297         if (IS_ERR(pll))
2298                 return ERR_CAST(pll);
2299
2300         val = pll_readl_base(pll);
2301         val &= ~PLLSS_REF_SRC_SEL_MASK;
2302         pll_writel_base(val, pll);
2303
2304         parent_rate = clk_get_rate(parent);
2305
2306         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2307
2308         /* initialize PLL to minimum rate */
2309
2310         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2311         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2312
2313         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2314                 ;
2315         if (!i) {
2316                 kfree(pll);
2317                 return ERR_PTR(-EINVAL);
2318         }
2319
2320         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2321
2322         _update_pll_mnp(pll, &cfg);
2323
2324         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2325         pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2326         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2327         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2328
2329         val = pll_readl_base(pll);
2330         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2331         if (val & PLL_BASE_ENABLE) {
2332                 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2333                         WARN(1, "%s is on but IDDQ set\n", name);
2334                         kfree(pll);
2335                         return ERR_PTR(-EINVAL);
2336                 }
2337         } else {
2338                 val_iddq |= BIT(pll_params->iddq_bit_idx);
2339                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2340         }
2341
2342         val &= ~PLLSS_LOCK_OVERRIDE;
2343         pll_writel_base(val, pll);
2344
2345         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2346                                         &tegra_clk_pllss_ops);
2347
2348         if (IS_ERR(clk))
2349                 kfree(pll);
2350
2351         return clk;
2352 }
2353 #endif
2354
2355 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2356 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2357                           const char *parent_name, void __iomem *clk_base,
2358                           void __iomem *pmc, unsigned long flags,
2359                           struct tegra_clk_pll_params *pll_params,
2360                           spinlock_t *lock, unsigned long parent_rate)
2361 {
2362         struct tegra_clk_pll *pll;
2363         struct clk *clk;
2364
2365         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2366
2367         if (pll_params->adjust_vco)
2368                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2369                                                              parent_rate);
2370
2371         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2372         if (IS_ERR(pll))
2373                 return ERR_CAST(pll);
2374
2375         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2376                                       &tegra_clk_pll_ops);
2377         if (IS_ERR(clk))
2378                 kfree(pll);
2379
2380         return clk;
2381 }
2382
2383 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2384 {
2385         struct tegra_clk_pll *pll = to_clk_pll(hw);
2386         struct tegra_clk_pll_freq_table sel;
2387         u32 val;
2388         int ret = 0;
2389         unsigned long flags = 0;
2390         unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2391
2392         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2393                 return -EINVAL;
2394
2395         if (pll->lock)
2396                 spin_lock_irqsave(pll->lock, flags);
2397
2398         val = pll_readl(pll->params->aux_reg, pll);
2399         if (val & PLLE_AUX_SEQ_ENABLE)
2400                 goto out;
2401
2402         val = pll_readl_base(pll);
2403         val &= ~BIT(30); /* Disable lock override */
2404         pll_writel_base(val, pll);
2405
2406         val = pll_readl_misc(pll);
2407         val |= PLLE_MISC_LOCK_ENABLE;
2408         val |= PLLE_MISC_IDDQ_SW_CTRL;
2409         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2410         val |= PLLE_MISC_PLLE_PTS;
2411         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2412         pll_writel_misc(val, pll);
2413         udelay(5);
2414
2415         val = pll_readl(PLLE_SS_CTRL, pll);
2416         val |= PLLE_SS_DISABLE;
2417         pll_writel(val, PLLE_SS_CTRL, pll);
2418
2419         val = pll_readl_base(pll);
2420         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2421                  divm_mask_shifted(pll));
2422         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2423         val |= sel.m << divm_shift(pll);
2424         val |= sel.n << divn_shift(pll);
2425         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2426         pll_writel_base(val, pll);
2427         udelay(1);
2428
2429         val = pll_readl_base(pll);
2430         val |= PLLE_BASE_ENABLE;
2431         pll_writel_base(val, pll);
2432
2433         ret = clk_pll_wait_for_lock(pll);
2434
2435         if (ret < 0)
2436                 goto out;
2437
2438         val = pll_readl(PLLE_SS_CTRL, pll);
2439         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2440         val &= ~PLLE_SS_COEFFICIENTS_MASK;
2441         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2442         pll_writel(val, PLLE_SS_CTRL, pll);
2443         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2444         pll_writel(val, PLLE_SS_CTRL, pll);
2445         udelay(1);
2446         val &= ~PLLE_SS_CNTL_INTERP_RESET;
2447         pll_writel(val, PLLE_SS_CTRL, pll);
2448         udelay(1);
2449
2450         val = pll_readl_misc(pll);
2451         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2452         pll_writel_misc(val, pll);
2453
2454         val = pll_readl(pll->params->aux_reg, pll);
2455         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2456         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2457         pll_writel(val, pll->params->aux_reg, pll);
2458         udelay(1);
2459         val |= PLLE_AUX_SEQ_ENABLE;
2460         pll_writel(val, pll->params->aux_reg, pll);
2461
2462 out:
2463         if (pll->lock)
2464                 spin_unlock_irqrestore(pll->lock, flags);
2465
2466         return ret;
2467 }
2468
2469 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2470 {
2471         struct tegra_clk_pll *pll = to_clk_pll(hw);
2472         unsigned long flags = 0;
2473         u32 val;
2474
2475         if (pll->lock)
2476                 spin_lock_irqsave(pll->lock, flags);
2477
2478         /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2479         val = pll_readl(pll->params->aux_reg, pll);
2480         if (val & PLLE_AUX_SEQ_ENABLE)
2481                 goto out;
2482
2483         val = pll_readl_base(pll);
2484         val &= ~PLLE_BASE_ENABLE;
2485         pll_writel_base(val, pll);
2486
2487         val = pll_readl(pll->params->aux_reg, pll);
2488         val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2489         pll_writel(val, pll->params->aux_reg, pll);
2490
2491         val = pll_readl_misc(pll);
2492         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2493         pll_writel_misc(val, pll);
2494         udelay(1);
2495
2496 out:
2497         if (pll->lock)
2498                 spin_unlock_irqrestore(pll->lock, flags);
2499 }
2500
2501 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2502 {
2503         struct tegra_clk_pll *pll = to_clk_pll(hw);
2504         u32 val;
2505
2506         val = pll_readl_base(pll);
2507
2508         return val & PLLE_BASE_ENABLE ? 1 : 0;
2509 }
2510
2511 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2512         .is_enabled =  clk_plle_tegra210_is_enabled,
2513         .enable = clk_plle_tegra210_enable,
2514         .disable = clk_plle_tegra210_disable,
2515         .recalc_rate = clk_pll_recalc_rate,
2516 };
2517
2518 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2519                                 const char *parent_name,
2520                                 void __iomem *clk_base, unsigned long flags,
2521                                 struct tegra_clk_pll_params *pll_params,
2522                                 spinlock_t *lock)
2523 {
2524         struct tegra_clk_pll *pll;
2525         struct clk *clk;
2526         u32 val, val_aux;
2527
2528         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2529         if (IS_ERR(pll))
2530                 return ERR_CAST(pll);
2531
2532         /* ensure parent is set to pll_re_vco */
2533
2534         val = pll_readl_base(pll);
2535         val_aux = pll_readl(pll_params->aux_reg, pll);
2536
2537         if (val & PLLE_BASE_ENABLE) {
2538                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2539                         (val_aux & PLLE_AUX_PLLP_SEL))
2540                         WARN(1, "pll_e enabled with unsupported parent %s\n",
2541                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2542                                         "pll_re_vco");
2543         } else {
2544                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2545                 pll_writel(val_aux, pll_params->aux_reg, pll);
2546         }
2547
2548         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2549                                       &tegra_clk_plle_tegra210_ops);
2550         if (IS_ERR(clk))
2551                 kfree(pll);
2552
2553         return clk;
2554 }
2555
2556 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2557                         const char *parent_name, void __iomem *clk_base,
2558                         void __iomem *pmc, unsigned long flags,
2559                         struct tegra_clk_pll_params *pll_params,
2560                         spinlock_t *lock)
2561 {
2562         struct clk *parent, *clk;
2563         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2564         struct tegra_clk_pll *pll;
2565         unsigned long parent_rate;
2566
2567         if (!p_tohw)
2568                 return ERR_PTR(-EINVAL);
2569
2570         parent = __clk_lookup(parent_name);
2571         if (!parent) {
2572                 WARN(1, "parent clk %s of %s must be registered first\n",
2573                         name, parent_name);
2574                 return ERR_PTR(-EINVAL);
2575         }
2576
2577         parent_rate = clk_get_rate(parent);
2578
2579         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2580
2581         if (pll_params->adjust_vco)
2582                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2583                                                              parent_rate);
2584
2585         pll_params->flags |= TEGRA_PLL_BYPASS;
2586         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2587         if (IS_ERR(pll))
2588                 return ERR_CAST(pll);
2589
2590         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2591                                       &tegra_clk_pll_ops);
2592         if (IS_ERR(clk))
2593                 kfree(pll);
2594
2595         return clk;
2596 }
2597
2598 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2599                                 const char *parent_name, void __iomem *clk_base,
2600                                 unsigned long flags,
2601                                 struct tegra_clk_pll_params *pll_params,
2602                                 spinlock_t *lock)
2603 {
2604         struct tegra_clk_pll *pll;
2605         struct clk *clk, *parent;
2606         unsigned long parent_rate;
2607         u32 val;
2608
2609         if (!pll_params->div_nmp)
2610                 return ERR_PTR(-EINVAL);
2611
2612         parent = __clk_lookup(parent_name);
2613         if (!parent) {
2614                 WARN(1, "parent clk %s of %s must be registered first\n",
2615                         name, parent_name);
2616                 return ERR_PTR(-EINVAL);
2617         }
2618
2619         val = readl_relaxed(clk_base + pll_params->base_reg);
2620         if (val & PLLSS_REF_SRC_SEL_MASK) {
2621                 WARN(1, "not supported reference clock for %s\n", name);
2622                 return ERR_PTR(-EINVAL);
2623         }
2624
2625         parent_rate = clk_get_rate(parent);
2626
2627         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2628
2629         if (pll_params->adjust_vco)
2630                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2631                                                              parent_rate);
2632
2633         pll_params->flags |= TEGRA_PLL_BYPASS;
2634         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2635         if (IS_ERR(pll))
2636                 return ERR_CAST(pll);
2637
2638         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2639                                         &tegra_clk_pll_ops);
2640
2641         if (IS_ERR(clk))
2642                 kfree(pll);
2643
2644         return clk;
2645 }
2646
2647 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2648                           void __iomem *clk_base, void __iomem *pmc,
2649                           unsigned long flags,
2650                           struct tegra_clk_pll_params *pll_params,
2651                           spinlock_t *lock)
2652 {
2653         struct tegra_clk_pll *pll;
2654         struct clk *clk, *parent;
2655         unsigned long parent_rate;
2656
2657         if (!pll_params->pdiv_tohw)
2658                 return ERR_PTR(-EINVAL);
2659
2660         parent = __clk_lookup(parent_name);
2661         if (!parent) {
2662                 WARN(1, "parent clk %s of %s must be registered first\n",
2663                         parent_name, name);
2664                 return ERR_PTR(-EINVAL);
2665         }
2666
2667         parent_rate = clk_get_rate(parent);
2668
2669         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2670
2671         if (pll_params->adjust_vco)
2672                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2673                                                              parent_rate);
2674
2675         pll_params->flags |= TEGRA_PLL_BYPASS;
2676         pll_params->flags |= TEGRA_PLLMB;
2677         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2678         if (IS_ERR(pll))
2679                 return ERR_CAST(pll);
2680
2681         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2682                                       &tegra_clk_pll_ops);
2683         if (IS_ERR(clk))
2684                 kfree(pll);
2685
2686         return clk;
2687 }
2688
2689 #endif