drivers/clk/ti/clk-54xx.c

   1 /*
   2  * OMAP5 Clock init
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo (t-kristo@ti.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/list.h>
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/io.h>
  18 #include <linux/clk/ti.h>
  19 #include <dt-bindings/clock/omap5.h>
  20
  21 #include "clock.h"
  22
  23 #define OMAP5_DPLL_ABE_DEFFREQ                          98304000
  24
  25 /*
  26  * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
  27  * states it must be at 960MHz
  28  */
  29 #define OMAP5_DPLL_USB_DEFFREQ                          960000000
  30
  31 static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
  32         { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
  33         { 0 },
  34 };
  35
  36 static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
  37         { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" },
  38         { 0 },
  39 };
  40
  41 static const char * const omap5_dmic_gfclk_parents[] __initconst = {
  42         "abe_cm:clk:0018:26",
  43         "pad_clks_ck",
  44         "slimbus_clk",
  45         NULL,
  46 };
  47
  48 static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
  49         "abe_24m_fclk",
  50         "dss_syc_gfclk_div",
  51         "func_24m_clk",
  52         NULL,
  53 };
  54
  55 static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
  56         { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
  57         { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
  58         { 0 },
  59 };
  60
  61 static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
  62         "abe_cm:clk:0028:26",
  63         "pad_clks_ck",
  64         "slimbus_clk",
  65         NULL,
  66 };
  67
  68 static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
  69         { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
  70         { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
  71         { 0 },
  72 };
  73
  74 static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
  75         "abe_cm:clk:0030:26",
  76         "pad_clks_ck",
  77         "slimbus_clk",
  78         NULL,
  79 };
  80
  81 static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
  82         { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
  83         { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
  84         { 0 },
  85 };
  86
  87 static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
  88         "abe_cm:clk:0038:26",
  89         "pad_clks_ck",
  90         "slimbus_clk",
  91         NULL,
  92 };
  93
  94 static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
  95         { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
  96         { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
  97         { 0 },
  98 };
  99
 100 static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
 101         "dss_syc_gfclk_div",
 102         "sys_32k_ck",
 103         NULL,
 104 };
 105
 106 static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
 107         { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
 108         { 0 },
 109 };
 110
 111 static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
 112         { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
 113         { 0 },
 114 };
 115
 116 static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
 117         { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
 118         { 0 },
 119 };
 120
 121 static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
 122         { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
 123         { 0 },
 124 };
 125
 126 static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
 127         { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
 128         { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
 129         { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
 130         { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
 131         { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
 132         { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
 133         { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
 134         { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
 135         { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
 136         { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
 137         { 0 },
 138 };
 139
 140 static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
 141         { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 142         { 0 },
 143 };
 144
 145 static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
 146         { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
 147         { 0 },
 148 };
 149
 150 static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
 151         { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
 152         { 0 },
 153 };
 154
 155 static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
 156         { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 157         { 0 },
 158 };
 159
 160 static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
 161         { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 162         { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
 163         { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
 164         { 0 },
 165 };
 166
 167 static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
 168         { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
 169         { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
 170         { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
 171         { 0 },
 172 };
 173
 174 static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
 175         { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 176         { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 177         { 0 },
 178 };
 179
 180 static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
 181         "sys_clkin",
 182         "sys_32k_ck",
 183         NULL,
 184 };
 185
 186 static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
 187         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 188         { 0 },
 189 };
 190
 191 static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
 192         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 193         { 0 },
 194 };
 195
 196 static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
 197         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 198         { 0 },
 199 };
 200
 201 static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
 202         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 203         { 0 },
 204 };
 205
 206 static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
 207         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 208         { 0 },
 209 };
 210
 211 static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
 212         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 213         { 0 },
 214 };
 215
 216 static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
 217         "sys_32k_ck",
 218         NULL,
 219 };
 220
 221 static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
 222         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 223         { 0 },
 224 };
 225
 226 static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
 227         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 228         { 0 },
 229 };
 230
 231 static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
 232         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 233         { 0 },
 234 };
 235
 236 static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
 237         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 238         { 0 },
 239 };
 240
 241 static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
 242         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 243         { 0 },
 244 };
 245
 246 static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
 247         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 248         { 0 },
 249 };
 250
 251 static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
 252         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 253         { 0 },
 254 };
 255
 256 static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
 257         { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
 258         { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
 259         { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
 260         { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
 261         { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
 262         { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
 263         { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 264         { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 265         { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 266         { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 267         { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 268         { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 269         { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 270         { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 271         { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 272         { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
 273         { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 274         { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 275         { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 276         { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 277         { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 278         { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 279         { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 280         { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 281         { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 282         { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 283         { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 284         { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 285         { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 286         { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 287         { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 288         { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 289         { 0 },
 290 };
 291
 292 static const char * const omap5_dss_dss_clk_parents[] __initconst = {
 293         "dpll_per_h12x2_ck",
 294         NULL,
 295 };
 296
 297 static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
 298         "func_48m_fclk",
 299         NULL,
 300 };
 301
 302 static const char * const omap5_dss_sys_clk_parents[] __initconst = {
 303         "dss_syc_gfclk_div",
 304         NULL,
 305 };
 306
 307 static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
 308         { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
 309         { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
 310         { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
 311         { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 312         { 0 },
 313 };
 314
 315 static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
 316         { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
 317         { 0 },
 318 };
 319
 320 static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
 321         "func_128m_clk",
 322         "dpll_per_m2x2_ck",
 323         NULL,
 324 };
 325
 326 static const char * const omap5_mmc1_fclk_parents[] __initconst = {
 327         "l3init_cm:clk:0008:24",
 328         NULL,
 329 };
 330
 331 static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
 332         .max_div = 2,
 333 };
 334
 335 static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
 336         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 337         { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
 338         { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
 339         { 0 },
 340 };
 341
 342 static const char * const omap5_mmc2_fclk_parents[] __initconst = {
 343         "l3init_cm:clk:0010:24",
 344         NULL,
 345 };
 346
 347 static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
 348         .max_div = 2,
 349 };
 350
 351 static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
 352         { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
 353         { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
 354         { 0 },
 355 };
 356
 357 static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
 358         "l3init_60m_fclk",
 359         NULL,
 360 };
 361
 362 static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
 363         "dpll_usb_m2_ck",
 364         NULL,
 365 };
 366
 367 static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
 368         "l3init_cm:clk:0038:24",
 369         NULL,
 370 };
 371
 372 static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
 373         "l3init_cm:clk:0038:25",
 374         NULL,
 375 };
 376
 377 static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
 378         "l3init_60m_fclk",
 379         "xclk60mhsp1_ck",
 380         NULL,
 381 };
 382
 383 static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
 384         "l3init_60m_fclk",
 385         "xclk60mhsp2_ck",
 386         NULL,
 387 };
 388
 389 static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
 390         { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 391         { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
 392         { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
 393         { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
 394         { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 395         { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 396         { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 397         { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
 398         { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
 399         { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
 400         { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
 401         { 0 },
 402 };
 403
 404 static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
 405         { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 406         { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 407         { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 408         { 0 },
 409 };
 410
 411 static const char * const omap5_sata_ref_clk_parents[] __initconst = {
 412         "sys_clkin",
 413         NULL,
 414 };
 415
 416 static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
 417         { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
 418         { 0 },
 419 };
 420
 421 static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
 422         "dpll_usb_clkdcoldo",
 423         NULL,
 424 };
 425
 426 static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
 427         { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
 428         { 0 },
 429 };
 430
 431 static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
 432         { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
 433         { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
 434         { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
 435         { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 436         { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
 437         { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
 438         { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
 439         { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 440         { 0 },
 441 };
 442
 443 static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
 444         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 445         { 0 },
 446 };
 447
 448 static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
 449         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 450         { 0 },
 451 };
 452
 453 static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
 454         { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 455         { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 456         { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
 457         { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
 458         { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 459         { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 460         { 0 },
 461 };
 462
 463 const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
 464         { 0x4a004320, omap5_mpu_clkctrl_regs },
 465         { 0x4a004420, omap5_dsp_clkctrl_regs },
 466         { 0x4a004520, omap5_abe_clkctrl_regs },
 467         { 0x4a008720, omap5_l3main1_clkctrl_regs },
 468         { 0x4a008820, omap5_l3main2_clkctrl_regs },
 469         { 0x4a008920, omap5_ipu_clkctrl_regs },
 470         { 0x4a008a20, omap5_dma_clkctrl_regs },
 471         { 0x4a008b20, omap5_emif_clkctrl_regs },
 472         { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
 473         { 0x4a008e20, omap5_l3instr_clkctrl_regs },
 474         { 0x4a009020, omap5_l4per_clkctrl_regs },
 475         { 0x4a009420, omap5_dss_clkctrl_regs },
 476         { 0x4a009620, omap5_l3init_clkctrl_regs },
 477         { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
 478         { 0 },
 479 };
 480
 481 static struct ti_dt_clk omap54xx_clks[] = {
 482         DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
 483         DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
 484         DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
 485         DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
 486         DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
 487         DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
 488         DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
 489         DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
 490         DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
 491         DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
 492         DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
 493         DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
 494         DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
 495         DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
 496         DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
 497         DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
 498         DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
 499         DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
 500         DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
 501         DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
 502         DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
 503         DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
 504         DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
 505         DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
 506         DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
 507         DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
 508         DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
 509         DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
 510         DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
 511         DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
 512         DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
 513         DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
 514         DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
 515         DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
 516         DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
 517         DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
 518         DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
 519         DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
 520         DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
 521         DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
 522         DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
 523         DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
 524         DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
 525         DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
 526         DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
 527         DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
 528         DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
 529         DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
 530         DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
 531         DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
 532         DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
 533         DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
 534         DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
 535         DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
 536         { .node_name = NULL },
 537 };
 538
 539 int __init omap5xxx_dt_clk_init(void)
 540 {
 541         int rc;
 542         struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
 543
 544         ti_dt_clocks_register(omap54xx_clks);
 545
 546         omap2_clk_disable_autoidle_all();
 547
 548         ti_clk_add_aliases();
 549
 550         abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
 551         sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
 552         rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
 553         abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
 554         if (!rc)
 555                 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
 556         if (rc)
 557                 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 558
 559         abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
 560         if (!rc)
 561                 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
 562         if (rc)
 563                 pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
 564
 565         usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
 566         rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
 567         if (rc)
 568                 pr_err("%s: failed to configure USB DPLL!\n", __func__);
 569
 570         usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
 571         rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
 572         if (rc)
 573                 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 574
 575         return 0;
 576 }