drivers/clk/ti/clkctrl.c

   1 /*
   2  * OMAP clkctrl clock support
   3  *
   4  * Copyright (C) 2017 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo <t-kristo@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/slab.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/clk/ti.h>
  23 #include <linux/delay.h>
  24 #include "clock.h"
  25
  26 #define NO_IDLEST                       0x1
  27
  28 #define OMAP4_MODULEMODE_MASK           0x3
  29
  30 #define MODULEMODE_HWCTRL               0x1
  31 #define MODULEMODE_SWCTRL               0x2
  32
  33 #define OMAP4_IDLEST_MASK               (0x3 << 16)
  34 #define OMAP4_IDLEST_SHIFT              16
  35
  36 #define CLKCTRL_IDLEST_FUNCTIONAL       0x0
  37 #define CLKCTRL_IDLEST_INTERFACE_IDLE   0x2
  38 #define CLKCTRL_IDLEST_DISABLED         0x3
  39
  40 /* These timeouts are in us */
  41 #define OMAP4_MAX_MODULE_READY_TIME     2000
  42 #define OMAP4_MAX_MODULE_DISABLE_TIME   5000
  43
  44 static bool _early_timeout = true;
  45
  46 struct omap_clkctrl_provider {
  47         void __iomem *base;
  48         struct list_head clocks;
  49 };
  50
  51 struct omap_clkctrl_clk {
  52         struct clk_hw *clk;
  53         u16 reg_offset;
  54         int bit_offset;
  55         struct list_head node;
  56 };
  57
  58 union omap4_timeout {
  59         u32 cycles;
  60         ktime_t start;
  61 };
  62
  63 static const struct omap_clkctrl_data default_clkctrl_data[] __initconst = {
  64         { 0 },
  65 };
  66
  67 static u32 _omap4_idlest(u32 val)
  68 {
  69         val &= OMAP4_IDLEST_MASK;
  70         val >>= OMAP4_IDLEST_SHIFT;
  71
  72         return val;
  73 }
  74
  75 static bool _omap4_is_idle(u32 val)
  76 {
  77         val = _omap4_idlest(val);
  78
  79         return val == CLKCTRL_IDLEST_DISABLED;
  80 }
  81
  82 static bool _omap4_is_ready(u32 val)
  83 {
  84         val = _omap4_idlest(val);
  85
  86         return val == CLKCTRL_IDLEST_FUNCTIONAL ||
  87                val == CLKCTRL_IDLEST_INTERFACE_IDLE;
  88 }
  89
  90 static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
  91 {
  92         if (unlikely(_early_timeout)) {
  93                 if (time->cycles++ < timeout) {
  94                         udelay(1);
  95                         return false;
  96                 }
  97         } else {
  98                 if (!ktime_to_ns(time->start)) {
  99                         time->start = ktime_get();
 100                         return false;
 101                 }
 102
 103                 if (ktime_us_delta(ktime_get(), time->start) < timeout) {
 104                         cpu_relax();
 105                         return false;
 106                 }
 107         }
 108
 109         return true;
 110 }
 111
 112 static int __init _omap4_disable_early_timeout(void)
 113 {
 114         _early_timeout = false;
 115
 116         return 0;
 117 }
 118 arch_initcall(_omap4_disable_early_timeout);
 119
 120 static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
 121 {
 122         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 123         u32 val;
 124         int ret;
 125         union omap4_timeout timeout = { 0 };
 126
 127         if (clk->clkdm) {
 128                 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
 129                 if (ret) {
 130                         WARN(1,
 131                              "%s: could not enable %s's clockdomain %s: %d\n",
 132                              __func__, clk_hw_get_name(hw),
 133                              clk->clkdm_name, ret);
 134                         return ret;
 135                 }
 136         }
 137
 138         if (!clk->enable_bit)
 139                 return 0;
 140
 141         val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
 142
 143         val &= ~OMAP4_MODULEMODE_MASK;
 144         val |= clk->enable_bit;
 145
 146         ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
 147
 148         if (clk->flags & NO_IDLEST)
 149                 return 0;
 150
 151         /* Wait until module is enabled */
 152         while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
 153                 if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
 154                         pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
 155                         return -EBUSY;
 156                 }
 157         }
 158
 159         return 0;
 160 }
 161
 162 static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
 163 {
 164         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 165         u32 val;
 166         union omap4_timeout timeout = { 0 };
 167
 168         if (!clk->enable_bit)
 169                 goto exit;
 170
 171         val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
 172
 173         val &= ~OMAP4_MODULEMODE_MASK;
 174
 175         ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
 176
 177         if (clk->flags & NO_IDLEST)
 178                 goto exit;
 179
 180         /* Wait until module is disabled */
 181         while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
 182                 if (_omap4_is_timeout(&timeout,
 183                                       OMAP4_MAX_MODULE_DISABLE_TIME)) {
 184                         pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
 185                         break;
 186                 }
 187         }
 188
 189 exit:
 190         if (clk->clkdm)
 191                 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
 192 }
 193
 194 static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
 195 {
 196         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 197         u32 val;
 198
 199         val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
 200
 201         if (val & clk->enable_bit)
 202                 return 1;
 203
 204         return 0;
 205 }
 206
 207 static const struct clk_ops omap4_clkctrl_clk_ops = {
 208         .enable         = _omap4_clkctrl_clk_enable,
 209         .disable        = _omap4_clkctrl_clk_disable,
 210         .is_enabled     = _omap4_clkctrl_clk_is_enabled,
 211 };
 212
 213 static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
 214                                               void *data)
 215 {
 216         struct omap_clkctrl_provider *provider = data;
 217         struct omap_clkctrl_clk *entry;
 218         bool found = false;
 219
 220         if (clkspec->args_count != 2)
 221                 return ERR_PTR(-EINVAL);
 222
 223         pr_debug("%s: looking for %x:%x\n", __func__,
 224                  clkspec->args[0], clkspec->args[1]);
 225
 226         list_for_each_entry(entry, &provider->clocks, node) {
 227                 if (entry->reg_offset == clkspec->args[0] &&
 228                     entry->bit_offset == clkspec->args[1]) {
 229                         found = true;
 230                         break;
 231                 }
 232         }
 233
 234         if (!found)
 235                 return ERR_PTR(-EINVAL);
 236
 237         return entry->clk;
 238 }
 239
 240 static int __init
 241 _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
 242                          struct device_node *node, struct clk_hw *clk_hw,
 243                          u16 offset, u8 bit, const char * const *parents,
 244                          int num_parents, const struct clk_ops *ops)
 245 {
 246         struct clk_init_data init = { NULL };
 247         struct clk *clk;
 248         struct omap_clkctrl_clk *clkctrl_clk;
 249         int ret = 0;
 250
 251         init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d", node->parent->name,
 252                               node->name, offset, bit);
 253         clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
 254         if (!init.name || !clkctrl_clk) {
 255                 ret = -ENOMEM;
 256                 goto cleanup;
 257         }
 258
 259         clk_hw->init = &init;
 260         init.parent_names = parents;
 261         init.num_parents = num_parents;
 262         init.ops = ops;
 263         init.flags = CLK_IS_BASIC;
 264
 265         clk = ti_clk_register(NULL, clk_hw, init.name);
 266         if (IS_ERR_OR_NULL(clk)) {
 267                 ret = -EINVAL;
 268                 goto cleanup;
 269         }
 270
 271         clkctrl_clk->reg_offset = offset;
 272         clkctrl_clk->bit_offset = bit;
 273         clkctrl_clk->clk = clk_hw;
 274
 275         list_add(&clkctrl_clk->node, &provider->clocks);
 276
 277         return 0;
 278
 279 cleanup:
 280         kfree(init.name);
 281         kfree(clkctrl_clk);
 282         return ret;
 283 }
 284
 285 static void __init
 286 _ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
 287                        struct device_node *node, u16 offset,
 288                        const struct omap_clkctrl_bit_data *data,
 289                        void __iomem *reg)
 290 {
 291         struct clk_hw_omap *clk_hw;
 292
 293         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
 294         if (!clk_hw)
 295                 return;
 296
 297         clk_hw->enable_bit = data->bit;
 298         clk_hw->enable_reg.ptr = reg;
 299
 300         if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
 301                                      data->bit, data->parents, 1,
 302                                      &omap_gate_clk_ops))
 303                 kfree(clk_hw);
 304 }
 305
 306 static void __init
 307 _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
 308                       struct device_node *node, u16 offset,
 309                       const struct omap_clkctrl_bit_data *data,
 310                       void __iomem *reg)
 311 {
 312         struct clk_omap_mux *mux;
 313         int num_parents = 0;
 314         const char * const *pname;
 315
 316         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 317         if (!mux)
 318                 return;
 319
 320         pname = data->parents;
 321         while (*pname) {
 322                 num_parents++;
 323                 pname++;
 324         }
 325
 326         mux->mask = num_parents;
 327         mux->mask = (1 << fls(mux->mask)) - 1;
 328
 329         mux->shift = data->bit;
 330         mux->reg.ptr = reg;
 331
 332         if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
 333                                      data->bit, data->parents, num_parents,
 334                                      &ti_clk_mux_ops))
 335                 kfree(mux);
 336 }
 337
 338 static void __init
 339 _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
 340                       struct device_node *node, u16 offset,
 341                       const struct omap_clkctrl_bit_data *data,
 342                       void __iomem *reg)
 343 {
 344         struct clk_omap_divider *div;
 345         const struct omap_clkctrl_div_data *div_data = data->data;
 346
 347         div = kzalloc(sizeof(*div), GFP_KERNEL);
 348         if (!div)
 349                 return;
 350
 351         div->reg.ptr = reg;
 352         div->shift = data->bit;
 353
 354         if (ti_clk_parse_divider_data((int *)div_data->dividers,
 355                                       div_data->max_div, 0, 0,
 356                                       &div->width, &div->table)) {
 357                 pr_err("%s: Data parsing for %s:%04x:%d failed\n", __func__,
 358                        node->name, offset, data->bit);
 359                 kfree(div);
 360                 return;
 361         }
 362
 363         if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
 364                                      data->bit, data->parents, 1,
 365                                      &ti_clk_divider_ops))
 366                 kfree(div);
 367 }
 368
 369 static void __init
 370 _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
 371                           struct device_node *node,
 372                           const struct omap_clkctrl_reg_data *data,
 373                           void __iomem *reg)
 374 {
 375         const struct omap_clkctrl_bit_data *bits = data->bit_data;
 376
 377         if (!bits)
 378                 return;
 379
 380         while (bits->bit) {
 381                 switch (bits->type) {
 382                 case TI_CLK_GATE:
 383                         _ti_clkctrl_setup_gate(provider, node, data->offset,
 384                                                bits, reg);
 385                         break;
 386
 387                 case TI_CLK_DIVIDER:
 388                         _ti_clkctrl_setup_div(provider, node, data->offset,
 389                                               bits, reg);
 390                         break;
 391
 392                 case TI_CLK_MUX:
 393                         _ti_clkctrl_setup_mux(provider, node, data->offset,
 394                                               bits, reg);
 395                         break;
 396
 397                 default:
 398                         pr_err("%s: bad subclk type: %d\n", __func__,
 399                                bits->type);
 400                         return;
 401                 }
 402                 bits++;
 403         }
 404 }
 405
 406 static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
 407 {
 408         struct omap_clkctrl_provider *provider;
 409         const struct omap_clkctrl_data *data = default_clkctrl_data;
 410         const struct omap_clkctrl_reg_data *reg_data;
 411         struct clk_init_data init = { NULL };
 412         struct clk_hw_omap *hw;
 413         struct clk *clk;
 414         struct omap_clkctrl_clk *clkctrl_clk;
 415         const __be32 *addrp;
 416         u32 addr;
 417
 418         addrp = of_get_address(node, 0, NULL, NULL);
 419         addr = (u32)of_translate_address(node, addrp);
 420
 421 #ifdef CONFIG_ARCH_OMAP4
 422         if (of_machine_is_compatible("ti,omap4"))
 423                 data = omap4_clkctrl_data;
 424 #endif
 425
 426         while (data->addr) {
 427                 if (addr == data->addr)
 428                         break;
 429
 430                 data++;
 431         }
 432
 433         if (!data->addr) {
 434                 pr_err("%s not found from clkctrl data.\n", node->name);
 435                 return;
 436         }
 437
 438         provider = kzalloc(sizeof(*provider), GFP_KERNEL);
 439         if (!provider)
 440                 return;
 441
 442         provider->base = of_iomap(node, 0);
 443
 444         INIT_LIST_HEAD(&provider->clocks);
 445
 446         /* Generate clocks */
 447         reg_data = data->regs;
 448
 449         while (reg_data->parent) {
 450                 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
 451                 if (!hw)
 452                         return;
 453
 454                 hw->enable_reg.ptr = provider->base + reg_data->offset;
 455
 456                 _ti_clkctrl_setup_subclks(provider, node, reg_data,
 457                                           hw->enable_reg.ptr);
 458
 459                 if (reg_data->flags & CLKF_SW_SUP)
 460                         hw->enable_bit = MODULEMODE_SWCTRL;
 461                 if (reg_data->flags & CLKF_HW_SUP)
 462                         hw->enable_bit = MODULEMODE_HWCTRL;
 463                 if (reg_data->flags & CLKF_NO_IDLEST)
 464                         hw->flags |= NO_IDLEST;
 465
 466                 init.parent_names = &reg_data->parent;
 467                 init.num_parents = 1;
 468                 init.flags = 0;
 469                 init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
 470                                       node->parent->name, node->name,
 471                                       reg_data->offset, 0);
 472                 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
 473                 if (!init.name || !clkctrl_clk)
 474                         goto cleanup;
 475
 476                 init.ops = &omap4_clkctrl_clk_ops;
 477                 hw->hw.init = &init;
 478
 479                 clk = ti_clk_register(NULL, &hw->hw, init.name);
 480                 if (IS_ERR_OR_NULL(clk))
 481                         goto cleanup;
 482
 483                 clkctrl_clk->reg_offset = reg_data->offset;
 484                 clkctrl_clk->clk = &hw->hw;
 485
 486                 list_add(&clkctrl_clk->node, &provider->clocks);
 487
 488                 reg_data++;
 489         }
 490
 491         of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
 492         return;
 493
 494 cleanup:
 495         kfree(hw);
 496         kfree(init.name);
 497         kfree(clkctrl_clk);
 498 }
 499 CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
 500                _ti_omap4_clkctrl_setup);