4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
31 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
32 int num_parents = clk_hw_get_num_parents(hw);
36 * FIXME need a mux-specific flag to determine if val is bitwise or
37 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
38 * from 0x1 to 0x7 (index starts at one)
39 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
40 * val = 0x4 really means "bit 2, index starts at bit 0"
42 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
48 for (i = 0; i < num_parents; i++)
49 if (mux->table[i] == val)
54 if (val && (mux->flags & CLK_MUX_INDEX_BIT))
57 if (val && (mux->flags & CLK_MUX_INDEX_ONE))
60 if (val >= num_parents)
66 static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
68 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
72 index = mux->table[index];
74 if (mux->flags & CLK_MUX_INDEX_BIT)
75 index = (1 << ffs(index));
77 if (mux->flags & CLK_MUX_INDEX_ONE)
81 if (mux->flags & CLK_MUX_HIWORD_MASK) {
82 val = mux->mask << (mux->shift + 16);
84 val = ti_clk_ll_ops->clk_readl(&mux->reg);
85 val &= ~(mux->mask << mux->shift);
87 val |= index << mux->shift;
88 ti_clk_ll_ops->clk_writel(val, &mux->reg);
93 const struct clk_ops ti_clk_mux_ops = {
94 .get_parent = ti_clk_mux_get_parent,
95 .set_parent = ti_clk_mux_set_parent,
96 .determine_rate = __clk_mux_determine_rate,
99 static struct clk *_register_mux(struct device *dev, const char *name,
100 const char * const *parent_names,
101 u8 num_parents, unsigned long flags,
102 struct clk_omap_reg *reg, u8 shift, u32 mask,
103 u8 clk_mux_flags, u32 *table)
105 struct clk_omap_mux *mux;
107 struct clk_init_data init;
109 /* allocate the mux */
110 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
112 pr_err("%s: could not allocate mux clk\n", __func__);
113 return ERR_PTR(-ENOMEM);
117 init.ops = &ti_clk_mux_ops;
118 init.flags = flags | CLK_IS_BASIC;
119 init.parent_names = parent_names;
120 init.num_parents = num_parents;
122 /* struct clk_mux assignments */
123 memcpy(&mux->reg, reg, sizeof(*reg));
126 mux->flags = clk_mux_flags;
128 mux->hw.init = &init;
130 clk = ti_clk_register(dev, &mux->hw, name);
138 struct clk *ti_clk_register_mux(struct ti_clk *setup)
140 struct ti_clk_mux *mux;
143 struct clk_omap_reg reg;
147 flags = CLK_SET_RATE_NO_REPARENT;
149 mask = mux->num_parents;
150 if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
153 mask = (1 << fls(mask)) - 1;
154 reg.index = mux->module;
155 reg.offset = mux->reg;
158 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
159 mux_flags |= CLK_MUX_INDEX_ONE;
161 if (mux->flags & CLKF_SET_RATE_PARENT)
162 flags |= CLK_SET_RATE_PARENT;
164 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
165 flags, ®, mux->bit_shift, mask,
170 * of_mux_clk_setup - Setup function for simple mux rate clock
171 * @node: DT node for the clock
173 * Sets up a basic clock multiplexer.
175 static void of_mux_clk_setup(struct device_node *node)
178 struct clk_omap_reg reg;
179 unsigned int num_parents;
180 const char **parent_names;
181 u8 clk_mux_flags = 0;
184 u32 flags = CLK_SET_RATE_NO_REPARENT;
186 num_parents = of_clk_get_parent_count(node);
187 if (num_parents < 2) {
188 pr_err("mux-clock %s must have parents\n", node->name);
191 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
195 of_clk_parent_fill(node, parent_names, num_parents);
197 if (ti_clk_get_reg_addr(node, 0, ®))
200 of_property_read_u32(node, "ti,bit-shift", &shift);
202 if (of_property_read_bool(node, "ti,index-starts-at-one"))
203 clk_mux_flags |= CLK_MUX_INDEX_ONE;
205 if (of_property_read_bool(node, "ti,set-rate-parent"))
206 flags |= CLK_SET_RATE_PARENT;
208 /* Generate bit-mask based on parent info */
210 if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
213 mask = (1 << fls(mask)) - 1;
215 clk = _register_mux(NULL, node->name, parent_names, num_parents,
216 flags, ®, shift, mask, clk_mux_flags, NULL);
219 of_clk_add_provider(node, of_clk_src_simple_get, clk);
224 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
226 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
228 struct clk_omap_mux *mux;
234 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
236 return ERR_PTR(-ENOMEM);
238 mux->shift = setup->bit_shift;
240 mux->reg.index = setup->module;
241 mux->reg.offset = setup->reg;
243 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
244 mux->flags |= CLK_MUX_INDEX_ONE;
246 num_parents = setup->num_parents;
248 mux->mask = num_parents - 1;
249 mux->mask = (1 << fls(mux->mask)) - 1;
254 static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
256 struct clk_omap_mux *mux;
257 unsigned int num_parents;
260 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
264 if (ti_clk_get_reg_addr(node, 0, &mux->reg))
267 if (!of_property_read_u32(node, "ti,bit-shift", &val))
270 if (of_property_read_bool(node, "ti,index-starts-at-one"))
271 mux->flags |= CLK_MUX_INDEX_ONE;
273 num_parents = of_clk_get_parent_count(node);
275 if (num_parents < 2) {
276 pr_err("%s must have parents\n", node->name);
280 mux->mask = num_parents - 1;
281 mux->mask = (1 << fls(mux->mask)) - 1;
283 if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
289 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
290 of_ti_composite_mux_clk_setup);