drivers/cpufreq/imx6q-cpufreq.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/cpu.h>
  11 #include <linux/cpufreq.h>
  12 #include <linux/err.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/regulator/consumer.h>
  18
  19 #define PU_SOC_VOLTAGE_NORMAL   1250000
  20 #define PU_SOC_VOLTAGE_HIGH     1275000
  21 #define FREQ_1P2_GHZ            1200000000
  22
  23 static struct regulator *arm_reg;
  24 static struct regulator *pu_reg;
  25 static struct regulator *soc_reg;
  26
  27 static struct clk *arm_clk;
  28 static struct clk *pll1_sys_clk;
  29 static struct clk *pll1_sw_clk;
  30 static struct clk *step_clk;
  31 static struct clk *pll2_pfd2_396m_clk;
  32
  33 /* clk used by i.MX6UL */
  34 static struct clk *pll2_bus_clk;
  35 static struct clk *secondary_sel_clk;
  36
  37 static struct device *cpu_dev;
  38 static bool free_opp;
  39 static struct cpufreq_frequency_table *freq_table;
  40 static unsigned int transition_latency;
  41
  42 static u32 *imx6_soc_volt;
  43 static u32 soc_opp_count;
  44
  45 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
  46 {
  47         struct dev_pm_opp *opp;
  48         unsigned long freq_hz, volt, volt_old;
  49         unsigned int old_freq, new_freq;
  50         bool pll1_sys_temp_enabled = false;
  51         int ret;
  52
  53         new_freq = freq_table[index].frequency;
  54         freq_hz = new_freq * 1000;
  55         old_freq = clk_get_rate(arm_clk) / 1000;
  56
  57         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
  58         if (IS_ERR(opp)) {
  59                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  60                 return PTR_ERR(opp);
  61         }
  62
  63         volt = dev_pm_opp_get_voltage(opp);
  64         dev_pm_opp_put(opp);
  65
  66         volt_old = regulator_get_voltage(arm_reg);
  67
  68         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  69                 old_freq / 1000, volt_old / 1000,
  70                 new_freq / 1000, volt / 1000);
  71
  72         /* scaling up?  scale voltage before frequency */
  73         if (new_freq > old_freq) {
  74                 if (!IS_ERR(pu_reg)) {
  75                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
  76                         if (ret) {
  77                                 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
  78                                 return ret;
  79                         }
  80                 }
  81                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
  82                 if (ret) {
  83                         dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
  84                         return ret;
  85                 }
  86                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  87                 if (ret) {
  88                         dev_err(cpu_dev,
  89                                 "failed to scale vddarm up: %d\n", ret);
  90                         return ret;
  91                 }
  92         }
  93
  94         /*
  95          * The setpoints are selected per PLL/PDF frequencies, so we need to
  96          * reprogram PLL for frequency scaling.  The procedure of reprogramming
  97          * PLL1 is as below.
  98          * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
  99          * flow is slightly different from other i.MX6 OSC.
 100          * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
 101          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
 102          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 103          *  - Disable pll2_pfd2_396m_clk
 104          */
 105         if (of_machine_is_compatible("fsl,imx6ul") ||
 106             of_machine_is_compatible("fsl,imx6ull")) {
 107                 /*
 108                  * When changing pll1_sw_clk's parent to pll1_sys_clk,
 109                  * CPU may run at higher than 528MHz, this will lead to
 110                  * the system unstable if the voltage is lower than the
 111                  * voltage of 528MHz, so lower the CPU frequency to one
 112                  * half before changing CPU frequency.
 113                  */
 114                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
 115                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
 116                 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
 117                         clk_set_parent(secondary_sel_clk, pll2_bus_clk);
 118                 else
 119                         clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
 120                 clk_set_parent(step_clk, secondary_sel_clk);
 121                 clk_set_parent(pll1_sw_clk, step_clk);
 122         } else {
 123                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 124                 clk_set_parent(pll1_sw_clk, step_clk);
 125                 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
 126                         clk_set_rate(pll1_sys_clk, new_freq * 1000);
 127                         clk_set_parent(pll1_sw_clk, pll1_sys_clk);
 128                 } else {
 129                         /* pll1_sys needs to be enabled for divider rate change to work. */
 130                         pll1_sys_temp_enabled = true;
 131                         clk_prepare_enable(pll1_sys_clk);
 132                 }
 133         }
 134
 135         /* Ensure the arm clock divider is what we expect */
 136         ret = clk_set_rate(arm_clk, new_freq * 1000);
 137         if (ret) {
 138                 int ret1;
 139
 140                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
 141                 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
 142                 if (ret1)
 143                         dev_warn(cpu_dev,
 144                                  "failed to restore vddarm voltage: %d\n", ret1);
 145                 return ret;
 146         }
 147
 148         /* PLL1 is only needed until after ARM-PODF is set. */
 149         if (pll1_sys_temp_enabled)
 150                 clk_disable_unprepare(pll1_sys_clk);
 151
 152         /* scaling down?  scale voltage after frequency */
 153         if (new_freq < old_freq) {
 154                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 155                 if (ret) {
 156                         dev_warn(cpu_dev,
 157                                  "failed to scale vddarm down: %d\n", ret);
 158                         ret = 0;
 159                 }
 160                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
 161                 if (ret) {
 162                         dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
 163                         ret = 0;
 164                 }
 165                 if (!IS_ERR(pu_reg)) {
 166                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
 167                         if (ret) {
 168                                 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
 169                                 ret = 0;
 170                         }
 171                 }
 172         }
 173
 174         return 0;
 175 }
 176
 177 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
 178 {
 179         int ret;
 180
 181         policy->clk = arm_clk;
 182         ret = cpufreq_generic_init(policy, freq_table, transition_latency);
 183         policy->suspend_freq = policy->max;
 184
 185         return ret;
 186 }
 187
 188 static struct cpufreq_driver imx6q_cpufreq_driver = {
 189         .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 190         .verify = cpufreq_generic_frequency_table_verify,
 191         .target_index = imx6q_set_target,
 192         .get = cpufreq_generic_get,
 193         .init = imx6q_cpufreq_init,
 194         .name = "imx6q-cpufreq",
 195         .attr = cpufreq_generic_attr,
 196         .suspend = cpufreq_generic_suspend,
 197 };
 198
 199 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 200 {
 201         struct device_node *np;
 202         struct dev_pm_opp *opp;
 203         unsigned long min_volt, max_volt;
 204         int num, ret;
 205         const struct property *prop;
 206         const __be32 *val;
 207         u32 nr, i, j;
 208
 209         cpu_dev = get_cpu_device(0);
 210         if (!cpu_dev) {
 211                 pr_err("failed to get cpu0 device\n");
 212                 return -ENODEV;
 213         }
 214
 215         np = of_node_get(cpu_dev->of_node);
 216         if (!np) {
 217                 dev_err(cpu_dev, "failed to find cpu0 node\n");
 218                 return -ENOENT;
 219         }
 220
 221         arm_clk = clk_get(cpu_dev, "arm");
 222         pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
 223         pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
 224         step_clk = clk_get(cpu_dev, "step");
 225         pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
 226         if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
 227             IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
 228                 dev_err(cpu_dev, "failed to get clocks\n");
 229                 ret = -ENOENT;
 230                 goto put_clk;
 231         }
 232
 233         if (of_machine_is_compatible("fsl,imx6ul") ||
 234             of_machine_is_compatible("fsl,imx6ull")) {
 235                 pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
 236                 secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
 237                 if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
 238                         dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
 239                         ret = -ENOENT;
 240                         goto put_clk;
 241                 }
 242         }
 243
 244         arm_reg = regulator_get(cpu_dev, "arm");
 245         pu_reg = regulator_get_optional(cpu_dev, "pu");
 246         soc_reg = regulator_get(cpu_dev, "soc");
 247         if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
 248                         PTR_ERR(soc_reg) == -EPROBE_DEFER ||
 249                         PTR_ERR(pu_reg) == -EPROBE_DEFER) {
 250                 ret = -EPROBE_DEFER;
 251                 dev_dbg(cpu_dev, "regulators not ready, defer\n");
 252                 goto put_reg;
 253         }
 254         if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
 255                 dev_err(cpu_dev, "failed to get regulators\n");
 256                 ret = -ENOENT;
 257                 goto put_reg;
 258         }
 259
 260         /*
 261          * We expect an OPP table supplied by platform.
 262          * Just, incase the platform did not supply the OPP
 263          * table, it will try to get it.
 264          */
 265         num = dev_pm_opp_get_opp_count(cpu_dev);
 266         if (num < 0) {
 267                 ret = dev_pm_opp_of_add_table(cpu_dev);
 268                 if (ret < 0) {
 269                         dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
 270                         goto put_reg;
 271                 }
 272
 273                 /* Because we have added the OPPs here, we must free them */
 274                 free_opp = true;
 275
 276                 num = dev_pm_opp_get_opp_count(cpu_dev);
 277                 if (num < 0) {
 278                         ret = num;
 279                         dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
 280                         goto out_free_opp;
 281                 }
 282         }
 283
 284         ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
 285         if (ret) {
 286                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
 287                 goto out_free_opp;
 288         }
 289
 290         /* Make imx6_soc_volt array's size same as arm opp number */
 291         imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
 292         if (imx6_soc_volt == NULL) {
 293                 ret = -ENOMEM;
 294                 goto free_freq_table;
 295         }
 296
 297         prop = of_find_property(np, "fsl,soc-operating-points", NULL);
 298         if (!prop || !prop->value)
 299                 goto soc_opp_out;
 300
 301         /*
 302          * Each OPP is a set of tuples consisting of frequency and
 303          * voltage like <freq-kHz vol-uV>.
 304          */
 305         nr = prop->length / sizeof(u32);
 306         if (nr % 2 || (nr / 2) < num)
 307                 goto soc_opp_out;
 308
 309         for (j = 0; j < num; j++) {
 310                 val = prop->value;
 311                 for (i = 0; i < nr / 2; i++) {
 312                         unsigned long freq = be32_to_cpup(val++);
 313                         unsigned long volt = be32_to_cpup(val++);
 314                         if (freq_table[j].frequency == freq) {
 315                                 imx6_soc_volt[soc_opp_count++] = volt;
 316                                 break;
 317                         }
 318                 }
 319         }
 320
 321 soc_opp_out:
 322         /* use fixed soc opp volt if no valid soc opp info found in dtb */
 323         if (soc_opp_count != num) {
 324                 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
 325                 for (j = 0; j < num; j++)
 326                         imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
 327                 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
 328                         imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
 329         }
 330
 331         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 332                 transition_latency = CPUFREQ_ETERNAL;
 333
 334         /*
 335          * Calculate the ramp time for max voltage change in the
 336          * VDDSOC and VDDPU regulators.
 337          */
 338         ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 339         if (ret > 0)
 340                 transition_latency += ret * 1000;
 341         if (!IS_ERR(pu_reg)) {
 342                 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 343                 if (ret > 0)
 344                         transition_latency += ret * 1000;
 345         }
 346
 347         /*
 348          * OPP is maintained in order of increasing frequency, and
 349          * freq_table initialised from OPP is therefore sorted in the
 350          * same order.
 351          */
 352         opp = dev_pm_opp_find_freq_exact(cpu_dev,
 353                                   freq_table[0].frequency * 1000, true);
 354         min_volt = dev_pm_opp_get_voltage(opp);
 355         dev_pm_opp_put(opp);
 356         opp = dev_pm_opp_find_freq_exact(cpu_dev,
 357                                   freq_table[--num].frequency * 1000, true);
 358         max_volt = dev_pm_opp_get_voltage(opp);
 359         dev_pm_opp_put(opp);
 360
 361         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
 362         if (ret > 0)
 363                 transition_latency += ret * 1000;
 364
 365         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
 366         if (ret) {
 367                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
 368                 goto free_freq_table;
 369         }
 370
 371         of_node_put(np);
 372         return 0;
 373
 374 free_freq_table:
 375         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 376 out_free_opp:
 377         if (free_opp)
 378                 dev_pm_opp_of_remove_table(cpu_dev);
 379 put_reg:
 380         if (!IS_ERR(arm_reg))
 381                 regulator_put(arm_reg);
 382         if (!IS_ERR(pu_reg))
 383                 regulator_put(pu_reg);
 384         if (!IS_ERR(soc_reg))
 385                 regulator_put(soc_reg);
 386 put_clk:
 387         if (!IS_ERR(arm_clk))
 388                 clk_put(arm_clk);
 389         if (!IS_ERR(pll1_sys_clk))
 390                 clk_put(pll1_sys_clk);
 391         if (!IS_ERR(pll1_sw_clk))
 392                 clk_put(pll1_sw_clk);
 393         if (!IS_ERR(step_clk))
 394                 clk_put(step_clk);
 395         if (!IS_ERR(pll2_pfd2_396m_clk))
 396                 clk_put(pll2_pfd2_396m_clk);
 397         if (!IS_ERR(pll2_bus_clk))
 398                 clk_put(pll2_bus_clk);
 399         if (!IS_ERR(secondary_sel_clk))
 400                 clk_put(secondary_sel_clk);
 401         of_node_put(np);
 402         return ret;
 403 }
 404
 405 static int imx6q_cpufreq_remove(struct platform_device *pdev)
 406 {
 407         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
 408         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 409         if (free_opp)
 410                 dev_pm_opp_of_remove_table(cpu_dev);
 411         regulator_put(arm_reg);
 412         if (!IS_ERR(pu_reg))
 413                 regulator_put(pu_reg);
 414         regulator_put(soc_reg);
 415         clk_put(arm_clk);
 416         clk_put(pll1_sys_clk);
 417         clk_put(pll1_sw_clk);
 418         clk_put(step_clk);
 419         clk_put(pll2_pfd2_396m_clk);
 420         clk_put(pll2_bus_clk);
 421         clk_put(secondary_sel_clk);
 422
 423         return 0;
 424 }
 425
 426 static struct platform_driver imx6q_cpufreq_platdrv = {
 427         .driver = {
 428                 .name   = "imx6q-cpufreq",
 429         },
 430         .probe          = imx6q_cpufreq_probe,
 431         .remove         = imx6q_cpufreq_remove,
 432 };
 433 module_platform_driver(imx6q_cpufreq_platdrv);
 434
 435 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 436 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
 437 MODULE_LICENSE("GPL");