drivers/cpufreq/imx6q-cpufreq.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/cpu.h>
  11 #include <linux/cpufreq.h>
  12 #include <linux/cpu_cooling.h>
  13 #include <linux/err.h>
  14 #include <linux/module.h>
  15 #include <linux/nvmem-consumer.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/pm_opp.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regulator/consumer.h>
  21
  22 #define PU_SOC_VOLTAGE_NORMAL   1250000
  23 #define PU_SOC_VOLTAGE_HIGH     1275000
  24 #define FREQ_1P2_GHZ            1200000000
  25
  26 static struct regulator *arm_reg;
  27 static struct regulator *pu_reg;
  28 static struct regulator *soc_reg;
  29
  30 enum IMX6_CPUFREQ_CLKS {
  31         ARM,
  32         PLL1_SYS,
  33         STEP,
  34         PLL1_SW,
  35         PLL2_PFD2_396M,
  36         /* MX6UL requires two more clks */
  37         PLL2_BUS,
  38         SECONDARY_SEL,
  39 };
  40 #define IMX6Q_CPUFREQ_CLK_NUM           5
  41 #define IMX6UL_CPUFREQ_CLK_NUM          7
  42
  43 static int num_clks;
  44 static struct clk_bulk_data clks[] = {
  45         { .id = "arm" },
  46         { .id = "pll1_sys" },
  47         { .id = "step" },
  48         { .id = "pll1_sw" },
  49         { .id = "pll2_pfd2_396m" },
  50         { .id = "pll2_bus" },
  51         { .id = "secondary_sel" },
  52 };
  53
  54 static struct device *cpu_dev;
  55 static struct thermal_cooling_device *cdev;
  56 static bool free_opp;
  57 static struct cpufreq_frequency_table *freq_table;
  58 static unsigned int max_freq;
  59 static unsigned int transition_latency;
  60
  61 static u32 *imx6_soc_volt;
  62 static u32 soc_opp_count;
  63
  64 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
  65 {
  66         struct dev_pm_opp *opp;
  67         unsigned long freq_hz, volt, volt_old;
  68         unsigned int old_freq, new_freq;
  69         bool pll1_sys_temp_enabled = false;
  70         int ret;
  71
  72         new_freq = freq_table[index].frequency;
  73         freq_hz = new_freq * 1000;
  74         old_freq = clk_get_rate(clks[ARM].clk) / 1000;
  75
  76         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
  77         if (IS_ERR(opp)) {
  78                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  79                 return PTR_ERR(opp);
  80         }
  81
  82         volt = dev_pm_opp_get_voltage(opp);
  83         dev_pm_opp_put(opp);
  84
  85         volt_old = regulator_get_voltage(arm_reg);
  86
  87         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  88                 old_freq / 1000, volt_old / 1000,
  89                 new_freq / 1000, volt / 1000);
  90
  91         /* scaling up?  scale voltage before frequency */
  92         if (new_freq > old_freq) {
  93                 if (!IS_ERR(pu_reg)) {
  94                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
  95                         if (ret) {
  96                                 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
  97                                 return ret;
  98                         }
  99                 }
 100                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
 101                 if (ret) {
 102                         dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
 103                         return ret;
 104                 }
 105                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 106                 if (ret) {
 107                         dev_err(cpu_dev,
 108                                 "failed to scale vddarm up: %d\n", ret);
 109                         return ret;
 110                 }
 111         }
 112
 113         /*
 114          * The setpoints are selected per PLL/PDF frequencies, so we need to
 115          * reprogram PLL for frequency scaling.  The procedure of reprogramming
 116          * PLL1 is as below.
 117          * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
 118          * flow is slightly different from other i.MX6 OSC.
 119          * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
 120          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
 121          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 122          *  - Disable pll2_pfd2_396m_clk
 123          */
 124         if (of_machine_is_compatible("fsl,imx6ul") ||
 125             of_machine_is_compatible("fsl,imx6ull")) {
 126                 /*
 127                  * When changing pll1_sw_clk's parent to pll1_sys_clk,
 128                  * CPU may run at higher than 528MHz, this will lead to
 129                  * the system unstable if the voltage is lower than the
 130                  * voltage of 528MHz, so lower the CPU frequency to one
 131                  * half before changing CPU frequency.
 132                  */
 133                 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
 134                 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
 135                 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
 136                         clk_set_parent(clks[SECONDARY_SEL].clk,
 137                                        clks[PLL2_BUS].clk);
 138                 else
 139                         clk_set_parent(clks[SECONDARY_SEL].clk,
 140                                        clks[PLL2_PFD2_396M].clk);
 141                 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
 142                 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
 143                 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
 144                         clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
 145                         clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
 146                 }
 147         } else {
 148                 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
 149                 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
 150                 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
 151                         clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
 152                         clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
 153                 } else {
 154                         /* pll1_sys needs to be enabled for divider rate change to work. */
 155                         pll1_sys_temp_enabled = true;
 156                         clk_prepare_enable(clks[PLL1_SYS].clk);
 157                 }
 158         }
 159
 160         /* Ensure the arm clock divider is what we expect */
 161         ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
 162         if (ret) {
 163                 int ret1;
 164
 165                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
 166                 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
 167                 if (ret1)
 168                         dev_warn(cpu_dev,
 169                                  "failed to restore vddarm voltage: %d\n", ret1);
 170                 return ret;
 171         }
 172
 173         /* PLL1 is only needed until after ARM-PODF is set. */
 174         if (pll1_sys_temp_enabled)
 175                 clk_disable_unprepare(clks[PLL1_SYS].clk);
 176
 177         /* scaling down?  scale voltage after frequency */
 178         if (new_freq < old_freq) {
 179                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 180                 if (ret) {
 181                         dev_warn(cpu_dev,
 182                                  "failed to scale vddarm down: %d\n", ret);
 183                         ret = 0;
 184                 }
 185                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
 186                 if (ret) {
 187                         dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
 188                         ret = 0;
 189                 }
 190                 if (!IS_ERR(pu_reg)) {
 191                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
 192                         if (ret) {
 193                                 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
 194                                 ret = 0;
 195                         }
 196                 }
 197         }
 198
 199         return 0;
 200 }
 201
 202 static void imx6q_cpufreq_ready(struct cpufreq_policy *policy)
 203 {
 204         cdev = of_cpufreq_cooling_register(policy);
 205
 206         if (!cdev)
 207                 dev_err(cpu_dev,
 208                         "running cpufreq without cooling device: %ld\n",
 209                         PTR_ERR(cdev));
 210 }
 211
 212 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
 213 {
 214         int ret;
 215
 216         policy->clk = clks[ARM].clk;
 217         ret = cpufreq_generic_init(policy, freq_table, transition_latency);
 218         policy->suspend_freq = max_freq;
 219
 220         return ret;
 221 }
 222
 223 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
 224 {
 225         cpufreq_cooling_unregister(cdev);
 226
 227         return 0;
 228 }
 229
 230 static struct cpufreq_driver imx6q_cpufreq_driver = {
 231         .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 232         .verify = cpufreq_generic_frequency_table_verify,
 233         .target_index = imx6q_set_target,
 234         .get = cpufreq_generic_get,
 235         .init = imx6q_cpufreq_init,
 236         .exit = imx6q_cpufreq_exit,
 237         .name = "imx6q-cpufreq",
 238         .ready = imx6q_cpufreq_ready,
 239         .attr = cpufreq_generic_attr,
 240         .suspend = cpufreq_generic_suspend,
 241 };
 242
 243 #define OCOTP_CFG3                      0x440
 244 #define OCOTP_CFG3_SPEED_SHIFT          16
 245 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
 246 #define OCOTP_CFG3_SPEED_996MHZ         0x2
 247 #define OCOTP_CFG3_SPEED_852MHZ         0x1
 248
 249 static void imx6q_opp_check_speed_grading(struct device *dev)
 250 {
 251         struct device_node *np;
 252         void __iomem *base;
 253         u32 val;
 254
 255         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 256         if (!np)
 257                 return;
 258
 259         base = of_iomap(np, 0);
 260         if (!base) {
 261                 dev_err(dev, "failed to map ocotp\n");
 262                 goto put_node;
 263         }
 264
 265         /*
 266          * SPEED_GRADING[1:0] defines the max speed of ARM:
 267          * 2b'11: 1200000000Hz;
 268          * 2b'10: 996000000Hz;
 269          * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
 270          * 2b'00: 792000000Hz;
 271          * We need to set the max speed of ARM according to fuse map.
 272          */
 273         val = readl_relaxed(base + OCOTP_CFG3);
 274         val >>= OCOTP_CFG3_SPEED_SHIFT;
 275         val &= 0x3;
 276
 277         if (val < OCOTP_CFG3_SPEED_996MHZ)
 278                 if (dev_pm_opp_disable(dev, 996000000))
 279                         dev_warn(dev, "failed to disable 996MHz OPP\n");
 280
 281         if (of_machine_is_compatible("fsl,imx6q") ||
 282             of_machine_is_compatible("fsl,imx6qp")) {
 283                 if (val != OCOTP_CFG3_SPEED_852MHZ)
 284                         if (dev_pm_opp_disable(dev, 852000000))
 285                                 dev_warn(dev, "failed to disable 852MHz OPP\n");
 286                 if (val != OCOTP_CFG3_SPEED_1P2GHZ)
 287                         if (dev_pm_opp_disable(dev, 1200000000))
 288                                 dev_warn(dev, "failed to disable 1.2GHz OPP\n");
 289         }
 290         iounmap(base);
 291 put_node:
 292         of_node_put(np);
 293 }
 294
 295 #define OCOTP_CFG3_6UL_SPEED_696MHZ     0x2
 296 #define OCOTP_CFG3_6ULL_SPEED_792MHZ    0x2
 297 #define OCOTP_CFG3_6ULL_SPEED_900MHZ    0x3
 298
 299 static int imx6ul_opp_check_speed_grading(struct device *dev)
 300 {
 301         u32 val;
 302         int ret = 0;
 303
 304         if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
 305                 ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
 306                 if (ret)
 307                         return ret;
 308         } else {
 309                 struct device_node *np;
 310                 void __iomem *base;
 311
 312                 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
 313                 if (!np)
 314                         np = of_find_compatible_node(NULL, NULL,
 315                                                      "fsl,imx6ull-ocotp");
 316                 if (!np)
 317                         return -ENOENT;
 318
 319                 base = of_iomap(np, 0);
 320                 of_node_put(np);
 321                 if (!base) {
 322                         dev_err(dev, "failed to map ocotp\n");
 323                         return -EFAULT;
 324                 }
 325
 326                 val = readl_relaxed(base + OCOTP_CFG3);
 327                 iounmap(base);
 328         }
 329
 330         /*
 331          * Speed GRADING[1:0] defines the max speed of ARM:
 332          * 2b'00: Reserved;
 333          * 2b'01: 528000000Hz;
 334          * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
 335          * 2b'11: 900000000Hz on i.MX6ULL only;
 336          * We need to set the max speed of ARM according to fuse map.
 337          */
 338         val >>= OCOTP_CFG3_SPEED_SHIFT;
 339         val &= 0x3;
 340
 341         if (of_machine_is_compatible("fsl,imx6ul")) {
 342                 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
 343                         if (dev_pm_opp_disable(dev, 696000000))
 344                                 dev_warn(dev, "failed to disable 696MHz OPP\n");
 345         }
 346
 347         if (of_machine_is_compatible("fsl,imx6ull")) {
 348                 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
 349                         if (dev_pm_opp_disable(dev, 792000000))
 350                                 dev_warn(dev, "failed to disable 792MHz OPP\n");
 351
 352                 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
 353                         if (dev_pm_opp_disable(dev, 900000000))
 354                                 dev_warn(dev, "failed to disable 900MHz OPP\n");
 355         }
 356
 357         return ret;
 358 }
 359
 360 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 361 {
 362         struct device_node *np;
 363         struct dev_pm_opp *opp;
 364         unsigned long min_volt, max_volt;
 365         int num, ret;
 366         const struct property *prop;
 367         const __be32 *val;
 368         u32 nr, i, j;
 369
 370         cpu_dev = get_cpu_device(0);
 371         if (!cpu_dev) {
 372                 pr_err("failed to get cpu0 device\n");
 373                 return -ENODEV;
 374         }
 375
 376         np = of_node_get(cpu_dev->of_node);
 377         if (!np) {
 378                 dev_err(cpu_dev, "failed to find cpu0 node\n");
 379                 return -ENOENT;
 380         }
 381
 382         if (of_machine_is_compatible("fsl,imx6ul") ||
 383             of_machine_is_compatible("fsl,imx6ull"))
 384                 num_clks = IMX6UL_CPUFREQ_CLK_NUM;
 385         else
 386                 num_clks = IMX6Q_CPUFREQ_CLK_NUM;
 387
 388         ret = clk_bulk_get(cpu_dev, num_clks, clks);
 389         if (ret)
 390                 goto put_node;
 391
 392         arm_reg = regulator_get(cpu_dev, "arm");
 393         pu_reg = regulator_get_optional(cpu_dev, "pu");
 394         soc_reg = regulator_get(cpu_dev, "soc");
 395         if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
 396                         PTR_ERR(soc_reg) == -EPROBE_DEFER ||
 397                         PTR_ERR(pu_reg) == -EPROBE_DEFER) {
 398                 ret = -EPROBE_DEFER;
 399                 dev_dbg(cpu_dev, "regulators not ready, defer\n");
 400                 goto put_reg;
 401         }
 402         if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
 403                 dev_err(cpu_dev, "failed to get regulators\n");
 404                 ret = -ENOENT;
 405                 goto put_reg;
 406         }
 407
 408         ret = dev_pm_opp_of_add_table(cpu_dev);
 409         if (ret < 0) {
 410                 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
 411                 goto put_reg;
 412         }
 413
 414         if (of_machine_is_compatible("fsl,imx6ul") ||
 415             of_machine_is_compatible("fsl,imx6ull")) {
 416                 ret = imx6ul_opp_check_speed_grading(cpu_dev);
 417                 if (ret == -EPROBE_DEFER)
 418                         return ret;
 419                 if (ret) {
 420                         dev_err(cpu_dev, "failed to read ocotp: %d\n",
 421                                 ret);
 422                         return ret;
 423                 }
 424         } else {
 425                 imx6q_opp_check_speed_grading(cpu_dev);
 426         }
 427
 428         /* Because we have added the OPPs here, we must free them */
 429         free_opp = true;
 430         num = dev_pm_opp_get_opp_count(cpu_dev);
 431         if (num < 0) {
 432                 ret = num;
 433                 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
 434                 goto out_free_opp;
 435         }
 436
 437         ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
 438         if (ret) {
 439                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
 440                 goto out_free_opp;
 441         }
 442
 443         /* Make imx6_soc_volt array's size same as arm opp number */
 444         imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
 445                                      GFP_KERNEL);
 446         if (imx6_soc_volt == NULL) {
 447                 ret = -ENOMEM;
 448                 goto free_freq_table;
 449         }
 450
 451         prop = of_find_property(np, "fsl,soc-operating-points", NULL);
 452         if (!prop || !prop->value)
 453                 goto soc_opp_out;
 454
 455         /*
 456          * Each OPP is a set of tuples consisting of frequency and
 457          * voltage like <freq-kHz vol-uV>.
 458          */
 459         nr = prop->length / sizeof(u32);
 460         if (nr % 2 || (nr / 2) < num)
 461                 goto soc_opp_out;
 462
 463         for (j = 0; j < num; j++) {
 464                 val = prop->value;
 465                 for (i = 0; i < nr / 2; i++) {
 466                         unsigned long freq = be32_to_cpup(val++);
 467                         unsigned long volt = be32_to_cpup(val++);
 468                         if (freq_table[j].frequency == freq) {
 469                                 imx6_soc_volt[soc_opp_count++] = volt;
 470                                 break;
 471                         }
 472                 }
 473         }
 474
 475 soc_opp_out:
 476         /* use fixed soc opp volt if no valid soc opp info found in dtb */
 477         if (soc_opp_count != num) {
 478                 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
 479                 for (j = 0; j < num; j++)
 480                         imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
 481                 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
 482                         imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
 483         }
 484
 485         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 486                 transition_latency = CPUFREQ_ETERNAL;
 487
 488         /*
 489          * Calculate the ramp time for max voltage change in the
 490          * VDDSOC and VDDPU regulators.
 491          */
 492         ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 493         if (ret > 0)
 494                 transition_latency += ret * 1000;
 495         if (!IS_ERR(pu_reg)) {
 496                 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 497                 if (ret > 0)
 498                         transition_latency += ret * 1000;
 499         }
 500
 501         /*
 502          * OPP is maintained in order of increasing frequency, and
 503          * freq_table initialised from OPP is therefore sorted in the
 504          * same order.
 505          */
 506         max_freq = freq_table[--num].frequency;
 507         opp = dev_pm_opp_find_freq_exact(cpu_dev,
 508                                   freq_table[0].frequency * 1000, true);
 509         min_volt = dev_pm_opp_get_voltage(opp);
 510         dev_pm_opp_put(opp);
 511         opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
 512         max_volt = dev_pm_opp_get_voltage(opp);
 513         dev_pm_opp_put(opp);
 514
 515         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
 516         if (ret > 0)
 517                 transition_latency += ret * 1000;
 518
 519         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
 520         if (ret) {
 521                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
 522                 goto free_freq_table;
 523         }
 524
 525         of_node_put(np);
 526         return 0;
 527
 528 free_freq_table:
 529         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 530 out_free_opp:
 531         if (free_opp)
 532                 dev_pm_opp_of_remove_table(cpu_dev);
 533 put_reg:
 534         if (!IS_ERR(arm_reg))
 535                 regulator_put(arm_reg);
 536         if (!IS_ERR(pu_reg))
 537                 regulator_put(pu_reg);
 538         if (!IS_ERR(soc_reg))
 539                 regulator_put(soc_reg);
 540
 541         clk_bulk_put(num_clks, clks);
 542 put_node:
 543         of_node_put(np);
 544
 545         return ret;
 546 }
 547
 548 static int imx6q_cpufreq_remove(struct platform_device *pdev)
 549 {
 550         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
 551         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 552         if (free_opp)
 553                 dev_pm_opp_of_remove_table(cpu_dev);
 554         regulator_put(arm_reg);
 555         if (!IS_ERR(pu_reg))
 556                 regulator_put(pu_reg);
 557         regulator_put(soc_reg);
 558
 559         clk_bulk_put(num_clks, clks);
 560
 561         return 0;
 562 }
 563
 564 static struct platform_driver imx6q_cpufreq_platdrv = {
 565         .driver = {
 566                 .name   = "imx6q-cpufreq",
 567         },
 568         .probe          = imx6q_cpufreq_probe,
 569         .remove         = imx6q_cpufreq_remove,
 570 };
 571 module_platform_driver(imx6q_cpufreq_platdrv);
 572
 573 MODULE_ALIAS("platform:imx6q-cpufreq");
 574 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 575 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
 576 MODULE_LICENSE("GPL");