drivers/crypto/amcc/crypto4xx_core.c

   1 /**
   2  * AMCC SoC PPC4xx Crypto Driver
   3  *
   4  * Copyright (c) 2008 Applied Micro Circuits Corporation.
   5  * All rights reserved. James Hsiao <jhsiao@amcc.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * This file implements AMCC crypto offload Linux device driver for use with
  18  * Linux CryptoAPI.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/spinlock_types.h>
  24 #include <linux/random.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/crypto.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/init.h>
  30 #include <linux/module.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/slab.h>
  35 #include <asm/dcr.h>
  36 #include <asm/dcr-regs.h>
  37 #include <asm/cacheflush.h>
  38 #include <crypto/aes.h>
  39 #include <crypto/sha.h>
  40 #include "crypto4xx_reg_def.h"
  41 #include "crypto4xx_core.h"
  42 #include "crypto4xx_sa.h"
  43
  44 #define PPC4XX_SEC_VERSION_STR                  "0.5"
  45
  46 /**
  47  * PPC4xx Crypto Engine Initialization Routine
  48  */
  49 static void crypto4xx_hw_init(struct crypto4xx_device *dev)
  50 {
  51         union ce_ring_size ring_size;
  52         union ce_ring_contol ring_ctrl;
  53         union ce_part_ring_size part_ring_size;
  54         union ce_io_threshold io_threshold;
  55         u32 rand_num;
  56         union ce_pe_dma_cfg pe_dma_cfg;
  57         u32 device_ctrl;
  58
  59         writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
  60         /* setup pe dma, include reset sg, pdr and pe, then release reset */
  61         pe_dma_cfg.w = 0;
  62         pe_dma_cfg.bf.bo_sgpd_en = 1;
  63         pe_dma_cfg.bf.bo_data_en = 0;
  64         pe_dma_cfg.bf.bo_sa_en = 1;
  65         pe_dma_cfg.bf.bo_pd_en = 1;
  66         pe_dma_cfg.bf.dynamic_sa_en = 1;
  67         pe_dma_cfg.bf.reset_sg = 1;
  68         pe_dma_cfg.bf.reset_pdr = 1;
  69         pe_dma_cfg.bf.reset_pe = 1;
  70         writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
  71         /* un reset pe,sg and pdr */
  72         pe_dma_cfg.bf.pe_mode = 0;
  73         pe_dma_cfg.bf.reset_sg = 0;
  74         pe_dma_cfg.bf.reset_pdr = 0;
  75         pe_dma_cfg.bf.reset_pe = 0;
  76         pe_dma_cfg.bf.bo_td_en = 0;
  77         writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
  78         writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE);
  79         writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE);
  80         writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL);
  81         get_random_bytes(&rand_num, sizeof(rand_num));
  82         writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L);
  83         get_random_bytes(&rand_num, sizeof(rand_num));
  84         writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H);
  85         ring_size.w = 0;
  86         ring_size.bf.ring_offset = PPC4XX_PD_SIZE;
  87         ring_size.bf.ring_size   = PPC4XX_NUM_PD;
  88         writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
  89         ring_ctrl.w = 0;
  90         writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
  91         device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
  92         device_ctrl |= PPC4XX_DC_3DES_EN;
  93         writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
  94         writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
  95         writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
  96         part_ring_size.w = 0;
  97         part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE;
  98         part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE;
  99         writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE);
 100         writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG);
 101         io_threshold.w = 0;
 102         io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD;
 103         io_threshold.bf.input_threshold  = PPC4XX_INPUT_THRESHOLD;
 104         writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD);
 105         writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR);
 106         writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR);
 107         writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR);
 108         writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR);
 109         writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR);
 110         writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR);
 111         writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR);
 112         /* un reset pe,sg and pdr */
 113         pe_dma_cfg.bf.pe_mode = 1;
 114         pe_dma_cfg.bf.reset_sg = 0;
 115         pe_dma_cfg.bf.reset_pdr = 0;
 116         pe_dma_cfg.bf.reset_pe = 0;
 117         pe_dma_cfg.bf.bo_td_en = 0;
 118         writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
 119         /*clear all pending interrupt*/
 120         writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR);
 121         writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
 122         writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
 123         writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
 124         writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
 125 }
 126
 127 int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size)
 128 {
 129         ctx->sa_in = dma_alloc_coherent(ctx->dev->core_dev->device, size * 4,
 130                                         &ctx->sa_in_dma_addr, GFP_ATOMIC);
 131         if (ctx->sa_in == NULL)
 132                 return -ENOMEM;
 133
 134         ctx->sa_out = dma_alloc_coherent(ctx->dev->core_dev->device, size * 4,
 135                                          &ctx->sa_out_dma_addr, GFP_ATOMIC);
 136         if (ctx->sa_out == NULL) {
 137                 dma_free_coherent(ctx->dev->core_dev->device,
 138                                   ctx->sa_len * 4,
 139                                   ctx->sa_in, ctx->sa_in_dma_addr);
 140                 return -ENOMEM;
 141         }
 142
 143         memset(ctx->sa_in, 0, size * 4);
 144         memset(ctx->sa_out, 0, size * 4);
 145         ctx->sa_len = size;
 146
 147         return 0;
 148 }
 149
 150 void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
 151 {
 152         if (ctx->sa_in != NULL)
 153                 dma_free_coherent(ctx->dev->core_dev->device, ctx->sa_len * 4,
 154                                   ctx->sa_in, ctx->sa_in_dma_addr);
 155         if (ctx->sa_out != NULL)
 156                 dma_free_coherent(ctx->dev->core_dev->device, ctx->sa_len * 4,
 157                                   ctx->sa_out, ctx->sa_out_dma_addr);
 158
 159         ctx->sa_in_dma_addr = 0;
 160         ctx->sa_out_dma_addr = 0;
 161         ctx->sa_len = 0;
 162 }
 163
 164 u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx)
 165 {
 166         ctx->state_record = dma_alloc_coherent(ctx->dev->core_dev->device,
 167                                 sizeof(struct sa_state_record),
 168                                 &ctx->state_record_dma_addr, GFP_ATOMIC);
 169         if (!ctx->state_record_dma_addr)
 170                 return -ENOMEM;
 171         memset(ctx->state_record, 0, sizeof(struct sa_state_record));
 172
 173         return 0;
 174 }
 175
 176 void crypto4xx_free_state_record(struct crypto4xx_ctx *ctx)
 177 {
 178         if (ctx->state_record != NULL)
 179                 dma_free_coherent(ctx->dev->core_dev->device,
 180                                   sizeof(struct sa_state_record),
 181                                   ctx->state_record,
 182                                   ctx->state_record_dma_addr);
 183         ctx->state_record_dma_addr = 0;
 184 }
 185
 186 /**
 187  * alloc memory for the gather ring
 188  * no need to alloc buf for the ring
 189  * gdr_tail, gdr_head and gdr_count are initialized by this function
 190  */
 191 static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev)
 192 {
 193         int i;
 194         struct pd_uinfo *pd_uinfo;
 195         dev->pdr = dma_alloc_coherent(dev->core_dev->device,
 196                                       sizeof(struct ce_pd) * PPC4XX_NUM_PD,
 197                                       &dev->pdr_pa, GFP_ATOMIC);
 198         if (!dev->pdr)
 199                 return -ENOMEM;
 200
 201         dev->pdr_uinfo = kzalloc(sizeof(struct pd_uinfo) * PPC4XX_NUM_PD,
 202                                 GFP_KERNEL);
 203         if (!dev->pdr_uinfo) {
 204                 dma_free_coherent(dev->core_dev->device,
 205                                   sizeof(struct ce_pd) * PPC4XX_NUM_PD,
 206                                   dev->pdr,
 207                                   dev->pdr_pa);
 208                 return -ENOMEM;
 209         }
 210         memset(dev->pdr, 0, sizeof(struct ce_pd) * PPC4XX_NUM_PD);
 211         dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device,
 212                                    256 * PPC4XX_NUM_PD,
 213                                    &dev->shadow_sa_pool_pa,
 214                                    GFP_ATOMIC);
 215         if (!dev->shadow_sa_pool)
 216                 return -ENOMEM;
 217
 218         dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device,
 219                          sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
 220                          &dev->shadow_sr_pool_pa, GFP_ATOMIC);
 221         if (!dev->shadow_sr_pool)
 222                 return -ENOMEM;
 223         for (i = 0; i < PPC4XX_NUM_PD; i++) {
 224                 pd_uinfo = (struct pd_uinfo *) (dev->pdr_uinfo +
 225                                                 sizeof(struct pd_uinfo) * i);
 226
 227                 /* alloc 256 bytes which is enough for any kind of dynamic sa */
 228                 pd_uinfo->sa_va = dev->shadow_sa_pool + 256 * i;
 229                 pd_uinfo->sa_pa = dev->shadow_sa_pool_pa + 256 * i;
 230
 231                 /* alloc state record */
 232                 pd_uinfo->sr_va = dev->shadow_sr_pool +
 233                     sizeof(struct sa_state_record) * i;
 234                 pd_uinfo->sr_pa = dev->shadow_sr_pool_pa +
 235                     sizeof(struct sa_state_record) * i;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev)
 242 {
 243         if (dev->pdr)
 244                 dma_free_coherent(dev->core_dev->device,
 245                                   sizeof(struct ce_pd) * PPC4XX_NUM_PD,
 246                                   dev->pdr, dev->pdr_pa);
 247
 248         if (dev->shadow_sa_pool)
 249                 dma_free_coherent(dev->core_dev->device, 256 * PPC4XX_NUM_PD,
 250                                   dev->shadow_sa_pool, dev->shadow_sa_pool_pa);
 251
 252         if (dev->shadow_sr_pool)
 253                 dma_free_coherent(dev->core_dev->device,
 254                         sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
 255                         dev->shadow_sr_pool, dev->shadow_sr_pool_pa);
 256
 257         kfree(dev->pdr_uinfo);
 258 }
 259
 260 static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev)
 261 {
 262         u32 retval;
 263         u32 tmp;
 264
 265         retval = dev->pdr_head;
 266         tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD;
 267
 268         if (tmp == dev->pdr_tail)
 269                 return ERING_WAS_FULL;
 270
 271         dev->pdr_head = tmp;
 272
 273         return retval;
 274 }
 275
 276 static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx)
 277 {
 278         struct pd_uinfo *pd_uinfo;
 279         unsigned long flags;
 280
 281         pd_uinfo = (struct pd_uinfo *)(dev->pdr_uinfo +
 282                                        sizeof(struct pd_uinfo) * idx);
 283         spin_lock_irqsave(&dev->core_dev->lock, flags);
 284         if (dev->pdr_tail != PPC4XX_LAST_PD)
 285                 dev->pdr_tail++;
 286         else
 287                 dev->pdr_tail = 0;
 288         pd_uinfo->state = PD_ENTRY_FREE;
 289         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 290
 291         return 0;
 292 }
 293
 294 static struct ce_pd *crypto4xx_get_pdp(struct crypto4xx_device *dev,
 295                                        dma_addr_t *pd_dma, u32 idx)
 296 {
 297         *pd_dma = dev->pdr_pa + sizeof(struct ce_pd) * idx;
 298
 299         return dev->pdr + sizeof(struct ce_pd) * idx;
 300 }
 301
 302 /**
 303  * alloc memory for the gather ring
 304  * no need to alloc buf for the ring
 305  * gdr_tail, gdr_head and gdr_count are initialized by this function
 306  */
 307 static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
 308 {
 309         dev->gdr = dma_alloc_coherent(dev->core_dev->device,
 310                                       sizeof(struct ce_gd) * PPC4XX_NUM_GD,
 311                                       &dev->gdr_pa, GFP_ATOMIC);
 312         if (!dev->gdr)
 313                 return -ENOMEM;
 314
 315         memset(dev->gdr, 0, sizeof(struct ce_gd) * PPC4XX_NUM_GD);
 316
 317         return 0;
 318 }
 319
 320 static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev)
 321 {
 322         dma_free_coherent(dev->core_dev->device,
 323                           sizeof(struct ce_gd) * PPC4XX_NUM_GD,
 324                           dev->gdr, dev->gdr_pa);
 325 }
 326
 327 /*
 328  * when this function is called.
 329  * preemption or interrupt must be disabled
 330  */
 331 u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n)
 332 {
 333         u32 retval;
 334         u32 tmp;
 335         if (n >= PPC4XX_NUM_GD)
 336                 return ERING_WAS_FULL;
 337
 338         retval = dev->gdr_head;
 339         tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD;
 340         if (dev->gdr_head > dev->gdr_tail) {
 341                 if (tmp < dev->gdr_head && tmp >= dev->gdr_tail)
 342                         return ERING_WAS_FULL;
 343         } else if (dev->gdr_head < dev->gdr_tail) {
 344                 if (tmp < dev->gdr_head || tmp >= dev->gdr_tail)
 345                         return ERING_WAS_FULL;
 346         }
 347         dev->gdr_head = tmp;
 348
 349         return retval;
 350 }
 351
 352 static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev)
 353 {
 354         unsigned long flags;
 355
 356         spin_lock_irqsave(&dev->core_dev->lock, flags);
 357         if (dev->gdr_tail == dev->gdr_head) {
 358                 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 359                 return 0;
 360         }
 361
 362         if (dev->gdr_tail != PPC4XX_LAST_GD)
 363                 dev->gdr_tail++;
 364         else
 365                 dev->gdr_tail = 0;
 366
 367         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 368
 369         return 0;
 370 }
 371
 372 static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev,
 373                                               dma_addr_t *gd_dma, u32 idx)
 374 {
 375         *gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx;
 376
 377         return (struct ce_gd *) (dev->gdr + sizeof(struct ce_gd) * idx);
 378 }
 379
 380 /**
 381  * alloc memory for the scatter ring
 382  * need to alloc buf for the ring
 383  * sdr_tail, sdr_head and sdr_count are initialized by this function
 384  */
 385 static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev)
 386 {
 387         int i;
 388         struct ce_sd *sd_array;
 389
 390         /* alloc memory for scatter descriptor ring */
 391         dev->sdr = dma_alloc_coherent(dev->core_dev->device,
 392                                       sizeof(struct ce_sd) * PPC4XX_NUM_SD,
 393                                       &dev->sdr_pa, GFP_ATOMIC);
 394         if (!dev->sdr)
 395                 return -ENOMEM;
 396
 397         dev->scatter_buffer_size = PPC4XX_SD_BUFFER_SIZE;
 398         dev->scatter_buffer_va =
 399                 dma_alloc_coherent(dev->core_dev->device,
 400                         dev->scatter_buffer_size * PPC4XX_NUM_SD,
 401                         &dev->scatter_buffer_pa, GFP_ATOMIC);
 402         if (!dev->scatter_buffer_va)
 403                 return -ENOMEM;
 404
 405         sd_array = dev->sdr;
 406
 407         for (i = 0; i < PPC4XX_NUM_SD; i++) {
 408                 sd_array[i].ptr = dev->scatter_buffer_pa +
 409                                   dev->scatter_buffer_size * i;
 410         }
 411
 412         return 0;
 413 }
 414
 415 static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev)
 416 {
 417         if (dev->sdr)
 418                 dma_free_coherent(dev->core_dev->device,
 419                                   sizeof(struct ce_sd) * PPC4XX_NUM_SD,
 420                                   dev->sdr, dev->sdr_pa);
 421
 422         if (dev->scatter_buffer_va)
 423                 dma_free_coherent(dev->core_dev->device,
 424                                   dev->scatter_buffer_size * PPC4XX_NUM_SD,
 425                                   dev->scatter_buffer_va,
 426                                   dev->scatter_buffer_pa);
 427 }
 428
 429 /*
 430  * when this function is called.
 431  * preemption or interrupt must be disabled
 432  */
 433 static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n)
 434 {
 435         u32 retval;
 436         u32 tmp;
 437
 438         if (n >= PPC4XX_NUM_SD)
 439                 return ERING_WAS_FULL;
 440
 441         retval = dev->sdr_head;
 442         tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD;
 443         if (dev->sdr_head > dev->gdr_tail) {
 444                 if (tmp < dev->sdr_head && tmp >= dev->sdr_tail)
 445                         return ERING_WAS_FULL;
 446         } else if (dev->sdr_head < dev->sdr_tail) {
 447                 if (tmp < dev->sdr_head || tmp >= dev->sdr_tail)
 448                         return ERING_WAS_FULL;
 449         } /* the head = tail, or empty case is already take cared */
 450         dev->sdr_head = tmp;
 451
 452         return retval;
 453 }
 454
 455 static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev)
 456 {
 457         unsigned long flags;
 458
 459         spin_lock_irqsave(&dev->core_dev->lock, flags);
 460         if (dev->sdr_tail == dev->sdr_head) {
 461                 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 462                 return 0;
 463         }
 464         if (dev->sdr_tail != PPC4XX_LAST_SD)
 465                 dev->sdr_tail++;
 466         else
 467                 dev->sdr_tail = 0;
 468         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 469
 470         return 0;
 471 }
 472
 473 static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev,
 474                                               dma_addr_t *sd_dma, u32 idx)
 475 {
 476         *sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx;
 477
 478         return  (struct ce_sd *)(dev->sdr + sizeof(struct ce_sd) * idx);
 479 }
 480
 481 static u32 crypto4xx_fill_one_page(struct crypto4xx_device *dev,
 482                                    dma_addr_t *addr, u32 *length,
 483                                    u32 *idx, u32 *offset, u32 *nbytes)
 484 {
 485         u32 len;
 486
 487         if (*length > dev->scatter_buffer_size) {
 488                 memcpy(phys_to_virt(*addr),
 489                         dev->scatter_buffer_va +
 490                         *idx * dev->scatter_buffer_size + *offset,
 491                         dev->scatter_buffer_size);
 492                 *offset = 0;
 493                 *length -= dev->scatter_buffer_size;
 494                 *nbytes -= dev->scatter_buffer_size;
 495                 if (*idx == PPC4XX_LAST_SD)
 496                         *idx = 0;
 497                 else
 498                         (*idx)++;
 499                 *addr = *addr +  dev->scatter_buffer_size;
 500                 return 1;
 501         } else if (*length < dev->scatter_buffer_size) {
 502                 memcpy(phys_to_virt(*addr),
 503                         dev->scatter_buffer_va +
 504                         *idx * dev->scatter_buffer_size + *offset, *length);
 505                 if ((*offset + *length) == dev->scatter_buffer_size) {
 506                         if (*idx == PPC4XX_LAST_SD)
 507                                 *idx = 0;
 508                         else
 509                                 (*idx)++;
 510                         *nbytes -= *length;
 511                         *offset = 0;
 512                 } else {
 513                         *nbytes -= *length;
 514                         *offset += *length;
 515                 }
 516
 517                 return 0;
 518         } else {
 519                 len = (*nbytes <= dev->scatter_buffer_size) ?
 520                                 (*nbytes) : dev->scatter_buffer_size;
 521                 memcpy(phys_to_virt(*addr),
 522                         dev->scatter_buffer_va +
 523                         *idx * dev->scatter_buffer_size + *offset,
 524                         len);
 525                 *offset = 0;
 526                 *nbytes -= len;
 527
 528                 if (*idx == PPC4XX_LAST_SD)
 529                         *idx = 0;
 530                 else
 531                         (*idx)++;
 532
 533                 return 0;
 534     }
 535 }
 536
 537 static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
 538                                       struct ce_pd *pd,
 539                                       struct pd_uinfo *pd_uinfo,
 540                                       u32 nbytes,
 541                                       struct scatterlist *dst)
 542 {
 543         dma_addr_t addr;
 544         u32 this_sd;
 545         u32 offset;
 546         u32 len;
 547         u32 i;
 548         u32 sg_len;
 549         struct scatterlist *sg;
 550
 551         this_sd = pd_uinfo->first_sd;
 552         offset = 0;
 553         i = 0;
 554
 555         while (nbytes) {
 556                 sg = &dst[i];
 557                 sg_len = sg->length;
 558                 addr = dma_map_page(dev->core_dev->device, sg_page(sg),
 559                                 sg->offset, sg->length, DMA_TO_DEVICE);
 560
 561                 if (offset == 0) {
 562                         len = (nbytes <= sg->length) ? nbytes : sg->length;
 563                         while (crypto4xx_fill_one_page(dev, &addr, &len,
 564                                 &this_sd, &offset, &nbytes))
 565                                 ;
 566                         if (!nbytes)
 567                                 return;
 568                         i++;
 569                 } else {
 570                         len = (nbytes <= (dev->scatter_buffer_size - offset)) ?
 571                                 nbytes : (dev->scatter_buffer_size - offset);
 572                         len = (sg->length < len) ? sg->length : len;
 573                         while (crypto4xx_fill_one_page(dev, &addr, &len,
 574                                                &this_sd, &offset, &nbytes))
 575                                 ;
 576                         if (!nbytes)
 577                                 return;
 578                         sg_len -= len;
 579                         if (sg_len) {
 580                                 addr += len;
 581                                 while (crypto4xx_fill_one_page(dev, &addr,
 582                                         &sg_len, &this_sd, &offset, &nbytes))
 583                                         ;
 584                         }
 585                         i++;
 586                 }
 587         }
 588 }
 589
 590 static u32 crypto4xx_copy_digest_to_dst(struct pd_uinfo *pd_uinfo,
 591                                         struct crypto4xx_ctx *ctx)
 592 {
 593         struct dynamic_sa_ctl *sa = (struct dynamic_sa_ctl *) ctx->sa_in;
 594         struct sa_state_record *state_record =
 595                                 (struct sa_state_record *) pd_uinfo->sr_va;
 596
 597         if (sa->sa_command_0.bf.hash_alg == SA_HASH_ALG_SHA1) {
 598                 memcpy((void *) pd_uinfo->dest_va, state_record->save_digest,
 599                        SA_HASH_ALG_SHA1_DIGEST_SIZE);
 600         }
 601
 602         return 0;
 603 }
 604
 605 static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev,
 606                                   struct pd_uinfo *pd_uinfo)
 607 {
 608         int i;
 609         if (pd_uinfo->num_gd) {
 610                 for (i = 0; i < pd_uinfo->num_gd; i++)
 611                         crypto4xx_put_gd_to_gdr(dev);
 612                 pd_uinfo->first_gd = 0xffffffff;
 613                 pd_uinfo->num_gd = 0;
 614         }
 615         if (pd_uinfo->num_sd) {
 616                 for (i = 0; i < pd_uinfo->num_sd; i++)
 617                         crypto4xx_put_sd_to_sdr(dev);
 618
 619                 pd_uinfo->first_sd = 0xffffffff;
 620                 pd_uinfo->num_sd = 0;
 621         }
 622 }
 623
 624 static u32 crypto4xx_ablkcipher_done(struct crypto4xx_device *dev,
 625                                      struct pd_uinfo *pd_uinfo,
 626                                      struct ce_pd *pd)
 627 {
 628         struct crypto4xx_ctx *ctx;
 629         struct ablkcipher_request *ablk_req;
 630         struct scatterlist *dst;
 631         dma_addr_t addr;
 632
 633         ablk_req = ablkcipher_request_cast(pd_uinfo->async_req);
 634         ctx  = crypto_tfm_ctx(ablk_req->base.tfm);
 635
 636         if (pd_uinfo->using_sd) {
 637                 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo, ablk_req->nbytes,
 638                                           ablk_req->dst);
 639         } else {
 640                 dst = pd_uinfo->dest_va;
 641                 addr = dma_map_page(dev->core_dev->device, sg_page(dst),
 642                                     dst->offset, dst->length, DMA_FROM_DEVICE);
 643         }
 644         crypto4xx_ret_sg_desc(dev, pd_uinfo);
 645         if (ablk_req->base.complete != NULL)
 646                 ablk_req->base.complete(&ablk_req->base, 0);
 647
 648         return 0;
 649 }
 650
 651 static u32 crypto4xx_ahash_done(struct crypto4xx_device *dev,
 652                                 struct pd_uinfo *pd_uinfo)
 653 {
 654         struct crypto4xx_ctx *ctx;
 655         struct ahash_request *ahash_req;
 656
 657         ahash_req = ahash_request_cast(pd_uinfo->async_req);
 658         ctx  = crypto_tfm_ctx(ahash_req->base.tfm);
 659
 660         crypto4xx_copy_digest_to_dst(pd_uinfo,
 661                                      crypto_tfm_ctx(ahash_req->base.tfm));
 662         crypto4xx_ret_sg_desc(dev, pd_uinfo);
 663         /* call user provided callback function x */
 664         if (ahash_req->base.complete != NULL)
 665                 ahash_req->base.complete(&ahash_req->base, 0);
 666
 667         return 0;
 668 }
 669
 670 static u32 crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
 671 {
 672         struct ce_pd *pd;
 673         struct pd_uinfo *pd_uinfo;
 674
 675         pd =  dev->pdr + sizeof(struct ce_pd)*idx;
 676         pd_uinfo = dev->pdr_uinfo + sizeof(struct pd_uinfo)*idx;
 677         if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) ==
 678                         CRYPTO_ALG_TYPE_ABLKCIPHER)
 679                 return crypto4xx_ablkcipher_done(dev, pd_uinfo, pd);
 680         else
 681                 return crypto4xx_ahash_done(dev, pd_uinfo);
 682 }
 683
 684 /**
 685  * Note: Only use this function to copy items that is word aligned.
 686  */
 687 void crypto4xx_memcpy_le(unsigned int *dst,
 688                          const unsigned char *buf,
 689                          int len)
 690 {
 691         u8 *tmp;
 692         for (; len >= 4; buf += 4, len -= 4)
 693                 *dst++ = cpu_to_le32(*(unsigned int *) buf);
 694
 695         tmp = (u8 *)dst;
 696         switch (len) {
 697         case 3:
 698                 *tmp++ = 0;
 699                 *tmp++ = *(buf+2);
 700                 *tmp++ = *(buf+1);
 701                 *tmp++ = *buf;
 702                 break;
 703         case 2:
 704                 *tmp++ = 0;
 705                 *tmp++ = 0;
 706                 *tmp++ = *(buf+1);
 707                 *tmp++ = *buf;
 708                 break;
 709         case 1:
 710                 *tmp++ = 0;
 711                 *tmp++ = 0;
 712                 *tmp++ = 0;
 713                 *tmp++ = *buf;
 714                 break;
 715         default:
 716                 break;
 717         }
 718 }
 719
 720 static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev)
 721 {
 722         crypto4xx_destroy_pdr(core_dev->dev);
 723         crypto4xx_destroy_gdr(core_dev->dev);
 724         crypto4xx_destroy_sdr(core_dev->dev);
 725         iounmap(core_dev->dev->ce_base);
 726         kfree(core_dev->dev);
 727         kfree(core_dev);
 728 }
 729
 730 void crypto4xx_return_pd(struct crypto4xx_device *dev,
 731                          u32 pd_entry, struct ce_pd *pd,
 732                          struct pd_uinfo *pd_uinfo)
 733 {
 734         /* irq should be already disabled */
 735         dev->pdr_head = pd_entry;
 736         pd->pd_ctl.w = 0;
 737         pd->pd_ctl_len.w = 0;
 738         pd_uinfo->state = PD_ENTRY_FREE;
 739 }
 740
 741 static u32 get_next_gd(u32 current)
 742 {
 743         if (current != PPC4XX_LAST_GD)
 744                 return current + 1;
 745         else
 746                 return 0;
 747 }
 748
 749 static u32 get_next_sd(u32 current)
 750 {
 751         if (current != PPC4XX_LAST_SD)
 752                 return current + 1;
 753         else
 754                 return 0;
 755 }
 756
 757 u32 crypto4xx_build_pd(struct crypto_async_request *req,
 758                        struct crypto4xx_ctx *ctx,
 759                        struct scatterlist *src,
 760                        struct scatterlist *dst,
 761                        unsigned int datalen,
 762                        void *iv, u32 iv_len)
 763 {
 764         struct crypto4xx_device *dev = ctx->dev;
 765         dma_addr_t addr, pd_dma, sd_dma, gd_dma;
 766         struct dynamic_sa_ctl *sa;
 767         struct scatterlist *sg;
 768         struct ce_gd *gd;
 769         struct ce_pd *pd;
 770         u32 num_gd, num_sd;
 771         u32 fst_gd = 0xffffffff;
 772         u32 fst_sd = 0xffffffff;
 773         u32 pd_entry;
 774         unsigned long flags;
 775         struct pd_uinfo *pd_uinfo = NULL;
 776         unsigned int nbytes = datalen, idx;
 777         unsigned int ivlen = 0;
 778         u32 gd_idx = 0;
 779
 780         /* figure how many gd is needed */
 781         num_gd = sg_nents_for_len(src, datalen);
 782         if (num_gd == 1)
 783                 num_gd = 0;
 784
 785         /* figure how many sd is needed */
 786         if (sg_is_last(dst) || ctx->is_hash) {
 787                 num_sd = 0;
 788         } else {
 789                 if (datalen > PPC4XX_SD_BUFFER_SIZE) {
 790                         num_sd = datalen / PPC4XX_SD_BUFFER_SIZE;
 791                         if (datalen % PPC4XX_SD_BUFFER_SIZE)
 792                                 num_sd++;
 793                 } else {
 794                         num_sd = 1;
 795                 }
 796         }
 797
 798         /*
 799          * The follow section of code needs to be protected
 800          * The gather ring and scatter ring needs to be consecutive
 801          * In case of run out of any kind of descriptor, the descriptor
 802          * already got must be return the original place.
 803          */
 804         spin_lock_irqsave(&dev->core_dev->lock, flags);
 805         if (num_gd) {
 806                 fst_gd = crypto4xx_get_n_gd(dev, num_gd);
 807                 if (fst_gd == ERING_WAS_FULL) {
 808                         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 809                         return -EAGAIN;
 810                 }
 811         }
 812         if (num_sd) {
 813                 fst_sd = crypto4xx_get_n_sd(dev, num_sd);
 814                 if (fst_sd == ERING_WAS_FULL) {
 815                         if (num_gd)
 816                                 dev->gdr_head = fst_gd;
 817                         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 818                         return -EAGAIN;
 819                 }
 820         }
 821         pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev);
 822         if (pd_entry == ERING_WAS_FULL) {
 823                 if (num_gd)
 824                         dev->gdr_head = fst_gd;
 825                 if (num_sd)
 826                         dev->sdr_head = fst_sd;
 827                 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 828                 return -EAGAIN;
 829         }
 830         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 831
 832         pd_uinfo = (struct pd_uinfo *)(dev->pdr_uinfo +
 833                                        sizeof(struct pd_uinfo) * pd_entry);
 834         pd = crypto4xx_get_pdp(dev, &pd_dma, pd_entry);
 835         pd_uinfo->async_req = req;
 836         pd_uinfo->num_gd = num_gd;
 837         pd_uinfo->num_sd = num_sd;
 838
 839         if (iv_len || ctx->is_hash) {
 840                 ivlen = iv_len;
 841                 pd->sa = pd_uinfo->sa_pa;
 842                 sa = (struct dynamic_sa_ctl *) pd_uinfo->sa_va;
 843                 if (ctx->direction == DIR_INBOUND)
 844                         memcpy(sa, ctx->sa_in, ctx->sa_len * 4);
 845                 else
 846                         memcpy(sa, ctx->sa_out, ctx->sa_len * 4);
 847
 848                 memcpy((void *) sa + ctx->offset_to_sr_ptr,
 849                         &pd_uinfo->sr_pa, 4);
 850
 851                 if (iv_len)
 852                         crypto4xx_memcpy_le(pd_uinfo->sr_va, iv, iv_len);
 853         } else {
 854                 if (ctx->direction == DIR_INBOUND) {
 855                         pd->sa = ctx->sa_in_dma_addr;
 856                         sa = (struct dynamic_sa_ctl *) ctx->sa_in;
 857                 } else {
 858                         pd->sa = ctx->sa_out_dma_addr;
 859                         sa = (struct dynamic_sa_ctl *) ctx->sa_out;
 860                 }
 861         }
 862         pd->sa_len = ctx->sa_len;
 863         if (num_gd) {
 864                 /* get first gd we are going to use */
 865                 gd_idx = fst_gd;
 866                 pd_uinfo->first_gd = fst_gd;
 867                 pd_uinfo->num_gd = num_gd;
 868                 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
 869                 pd->src = gd_dma;
 870                 /* enable gather */
 871                 sa->sa_command_0.bf.gather = 1;
 872                 idx = 0;
 873                 src = &src[0];
 874                 /* walk the sg, and setup gather array */
 875                 while (nbytes) {
 876                         sg = &src[idx];
 877                         addr = dma_map_page(dev->core_dev->device, sg_page(sg),
 878                                     sg->offset, sg->length, DMA_TO_DEVICE);
 879                         gd->ptr = addr;
 880                         gd->ctl_len.len = sg->length;
 881                         gd->ctl_len.done = 0;
 882                         gd->ctl_len.ready = 1;
 883                         if (sg->length >= nbytes)
 884                                 break;
 885                         nbytes -= sg->length;
 886                         gd_idx = get_next_gd(gd_idx);
 887                         gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
 888                         idx++;
 889                 }
 890         } else {
 891                 pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src),
 892                                 src->offset, src->length, DMA_TO_DEVICE);
 893                 /*
 894                  * Disable gather in sa command
 895                  */
 896                 sa->sa_command_0.bf.gather = 0;
 897                 /*
 898                  * Indicate gather array is not used
 899                  */
 900                 pd_uinfo->first_gd = 0xffffffff;
 901                 pd_uinfo->num_gd = 0;
 902         }
 903         if (ctx->is_hash || sg_is_last(dst)) {
 904                 /*
 905                  * we know application give us dst a whole piece of memory
 906                  * no need to use scatter ring.
 907                  * In case of is_hash, the icv is always at end of src data.
 908                  */
 909                 pd_uinfo->using_sd = 0;
 910                 pd_uinfo->first_sd = 0xffffffff;
 911                 pd_uinfo->num_sd = 0;
 912                 pd_uinfo->dest_va = dst;
 913                 sa->sa_command_0.bf.scatter = 0;
 914                 if (ctx->is_hash)
 915                         pd->dest = virt_to_phys((void *)dst);
 916                 else
 917                         pd->dest = (u32)dma_map_page(dev->core_dev->device,
 918                                         sg_page(dst), dst->offset,
 919                                         dst->length, DMA_TO_DEVICE);
 920         } else {
 921                 struct ce_sd *sd = NULL;
 922                 u32 sd_idx = fst_sd;
 923                 nbytes = datalen;
 924                 sa->sa_command_0.bf.scatter = 1;
 925                 pd_uinfo->using_sd = 1;
 926                 pd_uinfo->dest_va = dst;
 927                 pd_uinfo->first_sd = fst_sd;
 928                 pd_uinfo->num_sd = num_sd;
 929                 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
 930                 pd->dest = sd_dma;
 931                 /* setup scatter descriptor */
 932                 sd->ctl.done = 0;
 933                 sd->ctl.rdy = 1;
 934                 /* sd->ptr should be setup by sd_init routine*/
 935                 idx = 0;
 936                 if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
 937                         nbytes -= PPC4XX_SD_BUFFER_SIZE;
 938                 else
 939                         nbytes = 0;
 940                 while (nbytes) {
 941                         sd_idx = get_next_sd(sd_idx);
 942                         sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
 943                         /* setup scatter descriptor */
 944                         sd->ctl.done = 0;
 945                         sd->ctl.rdy = 1;
 946                         if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
 947                                 nbytes -= PPC4XX_SD_BUFFER_SIZE;
 948                         else
 949                                 /*
 950                                  * SD entry can hold PPC4XX_SD_BUFFER_SIZE,
 951                                  * which is more than nbytes, so done.
 952                                  */
 953                                 nbytes = 0;
 954                 }
 955         }
 956
 957         sa->sa_command_1.bf.hash_crypto_offset = 0;
 958         pd->pd_ctl.w = ctx->pd_ctl;
 959         pd->pd_ctl_len.w = 0x00400000 | (ctx->bypass << 24) | datalen;
 960         pd_uinfo->state = PD_ENTRY_INUSE;
 961         wmb();
 962         /* write any value to push engine to read a pd */
 963         writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
 964         return -EINPROGRESS;
 965 }
 966
 967 /**
 968  * Algorithm Registration Functions
 969  */
 970 static int crypto4xx_alg_init(struct crypto_tfm *tfm)
 971 {
 972         struct crypto_alg *alg = tfm->__crt_alg;
 973         struct crypto4xx_alg *amcc_alg = crypto_alg_to_crypto4xx_alg(alg);
 974         struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
 975
 976         ctx->dev = amcc_alg->dev;
 977         ctx->sa_in = NULL;
 978         ctx->sa_out = NULL;
 979         ctx->sa_in_dma_addr = 0;
 980         ctx->sa_out_dma_addr = 0;
 981         ctx->sa_len = 0;
 982
 983         switch (alg->cra_flags & CRYPTO_ALG_TYPE_MASK) {
 984         default:
 985                 tfm->crt_ablkcipher.reqsize = sizeof(struct crypto4xx_ctx);
 986                 break;
 987         case CRYPTO_ALG_TYPE_AHASH:
 988                 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 989                                          sizeof(struct crypto4xx_ctx));
 990                 break;
 991         }
 992
 993         return 0;
 994 }
 995
 996 static void crypto4xx_alg_exit(struct crypto_tfm *tfm)
 997 {
 998         struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
 999
1000         crypto4xx_free_sa(ctx);
1001         crypto4xx_free_state_record(ctx);
1002 }
1003
1004 int crypto4xx_register_alg(struct crypto4xx_device *sec_dev,
1005                            struct crypto4xx_alg_common *crypto_alg,
1006                            int array_size)
1007 {
1008         struct crypto4xx_alg *alg;
1009         int i;
1010         int rc = 0;
1011
1012         for (i = 0; i < array_size; i++) {
1013                 alg = kzalloc(sizeof(struct crypto4xx_alg), GFP_KERNEL);
1014                 if (!alg)
1015                         return -ENOMEM;
1016
1017                 alg->alg = crypto_alg[i];
1018                 alg->dev = sec_dev;
1019
1020                 switch (alg->alg.type) {
1021                 case CRYPTO_ALG_TYPE_AHASH:
1022                         rc = crypto_register_ahash(&alg->alg.u.hash);
1023                         break;
1024
1025                 default:
1026                         rc = crypto_register_alg(&alg->alg.u.cipher);
1027                         break;
1028                 }
1029
1030                 if (rc)
1031                         kfree(alg);
1032                 else
1033                         list_add_tail(&alg->entry, &sec_dev->alg_list);
1034         }
1035
1036         return 0;
1037 }
1038
1039 static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev)
1040 {
1041         struct crypto4xx_alg *alg, *tmp;
1042
1043         list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) {
1044                 list_del(&alg->entry);
1045                 switch (alg->alg.type) {
1046                 case CRYPTO_ALG_TYPE_AHASH:
1047                         crypto_unregister_ahash(&alg->alg.u.hash);
1048                         break;
1049
1050                 default:
1051                         crypto_unregister_alg(&alg->alg.u.cipher);
1052                 }
1053                 kfree(alg);
1054         }
1055 }
1056
1057 static void crypto4xx_bh_tasklet_cb(unsigned long data)
1058 {
1059         struct device *dev = (struct device *)data;
1060         struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1061         struct pd_uinfo *pd_uinfo;
1062         struct ce_pd *pd;
1063         u32 tail;
1064
1065         while (core_dev->dev->pdr_head != core_dev->dev->pdr_tail) {
1066                 tail = core_dev->dev->pdr_tail;
1067                 pd_uinfo = core_dev->dev->pdr_uinfo +
1068                         sizeof(struct pd_uinfo)*tail;
1069                 pd =  core_dev->dev->pdr + sizeof(struct ce_pd) * tail;
1070                 if ((pd_uinfo->state == PD_ENTRY_INUSE) &&
1071                                    pd->pd_ctl.bf.pe_done &&
1072                                    !pd->pd_ctl.bf.host_ready) {
1073                         pd->pd_ctl.bf.pe_done = 0;
1074                         crypto4xx_pd_done(core_dev->dev, tail);
1075                         crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
1076                         pd_uinfo->state = PD_ENTRY_FREE;
1077                 } else {
1078                         /* if tail not done, break */
1079                         break;
1080                 }
1081         }
1082 }
1083
1084 /**
1085  * Top Half of isr.
1086  */
1087 static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
1088 {
1089         struct device *dev = (struct device *)data;
1090         struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1091
1092         if (!core_dev->dev->ce_base)
1093                 return 0;
1094
1095         writel(PPC4XX_INTERRUPT_CLR,
1096                core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
1097         tasklet_schedule(&core_dev->tasklet);
1098
1099         return IRQ_HANDLED;
1100 }
1101
1102 /**
1103  * Supported Crypto Algorithms
1104  */
1105 struct crypto4xx_alg_common crypto4xx_alg[] = {
1106         /* Crypto AES modes */
1107         { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = {
1108                 .cra_name       = "cbc(aes)",
1109                 .cra_driver_name = "cbc-aes-ppc4xx",
1110                 .cra_priority   = CRYPTO4XX_CRYPTO_PRIORITY,
1111                 .cra_flags      = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1112                 .cra_blocksize  = AES_BLOCK_SIZE,
1113                 .cra_ctxsize    = sizeof(struct crypto4xx_ctx),
1114                 .cra_type       = &crypto_ablkcipher_type,
1115                 .cra_init       = crypto4xx_alg_init,
1116                 .cra_exit       = crypto4xx_alg_exit,
1117                 .cra_module     = THIS_MODULE,
1118                 .cra_u          = {
1119                         .ablkcipher = {
1120                                 .min_keysize    = AES_MIN_KEY_SIZE,
1121                                 .max_keysize    = AES_MAX_KEY_SIZE,
1122                                 .ivsize         = AES_IV_SIZE,
1123                                 .setkey         = crypto4xx_setkey_aes_cbc,
1124                                 .encrypt        = crypto4xx_encrypt,
1125                                 .decrypt        = crypto4xx_decrypt,
1126                         }
1127                 }
1128         }},
1129 };
1130
1131 /**
1132  * Module Initialization Routine
1133  */
1134 static int crypto4xx_probe(struct platform_device *ofdev)
1135 {
1136         int rc;
1137         struct resource res;
1138         struct device *dev = &ofdev->dev;
1139         struct crypto4xx_core_device *core_dev;
1140
1141         rc = of_address_to_resource(ofdev->dev.of_node, 0, &res);
1142         if (rc)
1143                 return -ENODEV;
1144
1145         if (of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto")) {
1146                 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1147                        mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET);
1148                 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1149                        mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET);
1150         } else if (of_find_compatible_node(NULL, NULL,
1151                         "amcc,ppc405ex-crypto")) {
1152                 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1153                        mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET);
1154                 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1155                        mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET);
1156         } else if (of_find_compatible_node(NULL, NULL,
1157                         "amcc,ppc460sx-crypto")) {
1158                 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1159                        mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET);
1160                 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1161                        mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET);
1162         } else {
1163                 printk(KERN_ERR "Crypto Function Not supported!\n");
1164                 return -EINVAL;
1165         }
1166
1167         core_dev = kzalloc(sizeof(struct crypto4xx_core_device), GFP_KERNEL);
1168         if (!core_dev)
1169                 return -ENOMEM;
1170
1171         dev_set_drvdata(dev, core_dev);
1172         core_dev->ofdev = ofdev;
1173         core_dev->dev = kzalloc(sizeof(struct crypto4xx_device), GFP_KERNEL);
1174         if (!core_dev->dev)
1175                 goto err_alloc_dev;
1176
1177         core_dev->dev->core_dev = core_dev;
1178         core_dev->device = dev;
1179         spin_lock_init(&core_dev->lock);
1180         INIT_LIST_HEAD(&core_dev->dev->alg_list);
1181         rc = crypto4xx_build_pdr(core_dev->dev);
1182         if (rc)
1183                 goto err_build_pdr;
1184
1185         rc = crypto4xx_build_gdr(core_dev->dev);
1186         if (rc)
1187                 goto err_build_pdr;
1188
1189         rc = crypto4xx_build_sdr(core_dev->dev);
1190         if (rc)
1191                 goto err_build_sdr;
1192
1193         /* Init tasklet for bottom half processing */
1194         tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb,
1195                      (unsigned long) dev);
1196
1197         /* Register for Crypto isr, Crypto Engine IRQ */
1198         core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1199         rc = request_irq(core_dev->irq, crypto4xx_ce_interrupt_handler, 0,
1200                          core_dev->dev->name, dev);
1201         if (rc)
1202                 goto err_request_irq;
1203
1204         core_dev->dev->ce_base = of_iomap(ofdev->dev.of_node, 0);
1205         if (!core_dev->dev->ce_base) {
1206                 dev_err(dev, "failed to of_iomap\n");
1207                 rc = -ENOMEM;
1208                 goto err_iomap;
1209         }
1210
1211         /* need to setup pdr, rdr, gdr and sdr before this */
1212         crypto4xx_hw_init(core_dev->dev);
1213
1214         /* Register security algorithms with Linux CryptoAPI */
1215         rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg,
1216                                ARRAY_SIZE(crypto4xx_alg));
1217         if (rc)
1218                 goto err_start_dev;
1219
1220         return 0;
1221
1222 err_start_dev:
1223         iounmap(core_dev->dev->ce_base);
1224 err_iomap:
1225         free_irq(core_dev->irq, dev);
1226 err_request_irq:
1227         irq_dispose_mapping(core_dev->irq);
1228         tasklet_kill(&core_dev->tasklet);
1229 err_build_sdr:
1230         crypto4xx_destroy_sdr(core_dev->dev);
1231         crypto4xx_destroy_gdr(core_dev->dev);
1232 err_build_pdr:
1233         crypto4xx_destroy_pdr(core_dev->dev);
1234         kfree(core_dev->dev);
1235 err_alloc_dev:
1236         kfree(core_dev);
1237
1238         return rc;
1239 }
1240
1241 static int crypto4xx_remove(struct platform_device *ofdev)
1242 {
1243         struct device *dev = &ofdev->dev;
1244         struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1245
1246         free_irq(core_dev->irq, dev);
1247         irq_dispose_mapping(core_dev->irq);
1248
1249         tasklet_kill(&core_dev->tasklet);
1250         /* Un-register with Linux CryptoAPI */
1251         crypto4xx_unregister_alg(core_dev->dev);
1252         /* Free all allocated memory */
1253         crypto4xx_stop_all(core_dev);
1254
1255         return 0;
1256 }
1257
1258 static const struct of_device_id crypto4xx_match[] = {
1259         { .compatible      = "amcc,ppc4xx-crypto",},
1260         { },
1261 };
1262 MODULE_DEVICE_TABLE(of, crypto4xx_match);
1263
1264 static struct platform_driver crypto4xx_driver = {
1265         .driver = {
1266                 .name = "crypto4xx",
1267                 .of_match_table = crypto4xx_match,
1268         },
1269         .probe          = crypto4xx_probe,
1270         .remove         = crypto4xx_remove,
1271 };
1272
1273 module_platform_driver(crypto4xx_driver);
1274
1275 MODULE_LICENSE("GPL");
1276 MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>");
1277 MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator");
1278