drivers/crypto/atmel-aes.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for ATMEL AES HW acceleration.
   5  *
   6  * Copyright (c) 2012 Eukréa Electromatique - ATMEL
   7  * Author: Nicolas Royer <nicolas@eukrea.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  *
  13  * Some ideas are from omap-aes.c driver.
  14  */
  15
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/slab.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/hw_random.h>
  24 #include <linux/platform_device.h>
  25
  26 #include <linux/device.h>
  27 #include <linux/init.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/scatterlist.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/of_device.h>
  34 #include <linux/delay.h>
  35 #include <linux/crypto.h>
  36 #include <crypto/scatterwalk.h>
  37 #include <crypto/algapi.h>
  38 #include <crypto/aes.h>
  39 #include <crypto/internal/aead.h>
  40 #include <linux/platform_data/crypto-atmel.h>
  41 #include <dt-bindings/dma/at91.h>
  42 #include "atmel-aes-regs.h"
  43
  44 #define ATMEL_AES_PRIORITY      300
  45
  46 #define ATMEL_AES_BUFFER_ORDER  2
  47 #define ATMEL_AES_BUFFER_SIZE   (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER)
  48
  49 #define CFB8_BLOCK_SIZE         1
  50 #define CFB16_BLOCK_SIZE        2
  51 #define CFB32_BLOCK_SIZE        4
  52 #define CFB64_BLOCK_SIZE        8
  53
  54 #define SIZE_IN_WORDS(x)        ((x) >> 2)
  55
  56 /* AES flags */
  57 /* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */
  58 #define AES_FLAGS_ENCRYPT       AES_MR_CYPHER_ENC
  59 #define AES_FLAGS_GTAGEN        AES_MR_GTAGEN
  60 #define AES_FLAGS_OPMODE_MASK   (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
  61 #define AES_FLAGS_ECB           AES_MR_OPMOD_ECB
  62 #define AES_FLAGS_CBC           AES_MR_OPMOD_CBC
  63 #define AES_FLAGS_OFB           AES_MR_OPMOD_OFB
  64 #define AES_FLAGS_CFB128        (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)
  65 #define AES_FLAGS_CFB64         (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)
  66 #define AES_FLAGS_CFB32         (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)
  67 #define AES_FLAGS_CFB16         (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
  68 #define AES_FLAGS_CFB8          (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
  69 #define AES_FLAGS_CTR           AES_MR_OPMOD_CTR
  70 #define AES_FLAGS_GCM           AES_MR_OPMOD_GCM
  71
  72 #define AES_FLAGS_MODE_MASK     (AES_FLAGS_OPMODE_MASK |        \
  73                                  AES_FLAGS_ENCRYPT |            \
  74                                  AES_FLAGS_GTAGEN)
  75
  76 #define AES_FLAGS_INIT          BIT(2)
  77 #define AES_FLAGS_BUSY          BIT(3)
  78 #define AES_FLAGS_DUMP_REG      BIT(4)
  79
  80 #define AES_FLAGS_PERSISTENT    (AES_FLAGS_INIT | AES_FLAGS_BUSY)
  81
  82 #define ATMEL_AES_QUEUE_LENGTH  50
  83
  84 #define ATMEL_AES_DMA_THRESHOLD         256
  85
  86
  87 struct atmel_aes_caps {
  88         bool                    has_dualbuff;
  89         bool                    has_cfb64;
  90         bool                    has_gcm;
  91         u32                     max_burst_size;
  92 };
  93
  94 struct atmel_aes_dev;
  95
  96
  97 typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *);
  98
  99
 100 struct atmel_aes_base_ctx {
 101         struct atmel_aes_dev    *dd;
 102         atmel_aes_fn_t          start;
 103         int                     keylen;
 104         u32                     key[AES_KEYSIZE_256 / sizeof(u32)];
 105         u16                     block_size;
 106 };
 107
 108 struct atmel_aes_ctx {
 109         struct atmel_aes_base_ctx       base;
 110 };
 111
 112 struct atmel_aes_ctr_ctx {
 113         struct atmel_aes_base_ctx       base;
 114
 115         u32                     iv[AES_BLOCK_SIZE / sizeof(u32)];
 116         size_t                  offset;
 117         struct scatterlist      src[2];
 118         struct scatterlist      dst[2];
 119 };
 120
 121 struct atmel_aes_gcm_ctx {
 122         struct atmel_aes_base_ctx       base;
 123
 124         struct scatterlist      src[2];
 125         struct scatterlist      dst[2];
 126
 127         u32                     j0[AES_BLOCK_SIZE / sizeof(u32)];
 128         u32                     tag[AES_BLOCK_SIZE / sizeof(u32)];
 129         u32                     ghash[AES_BLOCK_SIZE / sizeof(u32)];
 130         size_t                  textlen;
 131
 132         const u32               *ghash_in;
 133         u32                     *ghash_out;
 134         atmel_aes_fn_t          ghash_resume;
 135 };
 136
 137 struct atmel_aes_reqctx {
 138         unsigned long           mode;
 139 };
 140
 141 struct atmel_aes_dma {
 142         struct dma_chan         *chan;
 143         struct scatterlist      *sg;
 144         int                     nents;
 145         unsigned int            remainder;
 146         unsigned int            sg_len;
 147 };
 148
 149 struct atmel_aes_dev {
 150         struct list_head        list;
 151         unsigned long           phys_base;
 152         void __iomem            *io_base;
 153
 154         struct crypto_async_request     *areq;
 155         struct atmel_aes_base_ctx       *ctx;
 156
 157         bool                    is_async;
 158         atmel_aes_fn_t          resume;
 159         atmel_aes_fn_t          cpu_transfer_complete;
 160
 161         struct device           *dev;
 162         struct clk              *iclk;
 163         int                     irq;
 164
 165         unsigned long           flags;
 166
 167         spinlock_t              lock;
 168         struct crypto_queue     queue;
 169
 170         struct tasklet_struct   done_task;
 171         struct tasklet_struct   queue_task;
 172
 173         size_t                  total;
 174         size_t                  datalen;
 175         u32                     *data;
 176
 177         struct atmel_aes_dma    src;
 178         struct atmel_aes_dma    dst;
 179
 180         size_t                  buflen;
 181         void                    *buf;
 182         struct scatterlist      aligned_sg;
 183         struct scatterlist      *real_dst;
 184
 185         struct atmel_aes_caps   caps;
 186
 187         u32                     hw_version;
 188 };
 189
 190 struct atmel_aes_drv {
 191         struct list_head        dev_list;
 192         spinlock_t              lock;
 193 };
 194
 195 static struct atmel_aes_drv atmel_aes = {
 196         .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list),
 197         .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock),
 198 };
 199
 200 #ifdef VERBOSE_DEBUG
 201 static const char *atmel_aes_reg_name(u32 offset, char *tmp, size_t sz)
 202 {
 203         switch (offset) {
 204         case AES_CR:
 205                 return "CR";
 206
 207         case AES_MR:
 208                 return "MR";
 209
 210         case AES_ISR:
 211                 return "ISR";
 212
 213         case AES_IMR:
 214                 return "IMR";
 215
 216         case AES_IER:
 217                 return "IER";
 218
 219         case AES_IDR:
 220                 return "IDR";
 221
 222         case AES_KEYWR(0):
 223         case AES_KEYWR(1):
 224         case AES_KEYWR(2):
 225         case AES_KEYWR(3):
 226         case AES_KEYWR(4):
 227         case AES_KEYWR(5):
 228         case AES_KEYWR(6):
 229         case AES_KEYWR(7):
 230                 snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2);
 231                 break;
 232
 233         case AES_IDATAR(0):
 234         case AES_IDATAR(1):
 235         case AES_IDATAR(2):
 236         case AES_IDATAR(3):
 237                 snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2);
 238                 break;
 239
 240         case AES_ODATAR(0):
 241         case AES_ODATAR(1):
 242         case AES_ODATAR(2):
 243         case AES_ODATAR(3):
 244                 snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2);
 245                 break;
 246
 247         case AES_IVR(0):
 248         case AES_IVR(1):
 249         case AES_IVR(2):
 250         case AES_IVR(3):
 251                 snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2);
 252                 break;
 253
 254         case AES_AADLENR:
 255                 return "AADLENR";
 256
 257         case AES_CLENR:
 258                 return "CLENR";
 259
 260         case AES_GHASHR(0):
 261         case AES_GHASHR(1):
 262         case AES_GHASHR(2):
 263         case AES_GHASHR(3):
 264                 snprintf(tmp, sz, "GHASHR[%u]", (offset - AES_GHASHR(0)) >> 2);
 265                 break;
 266
 267         case AES_TAGR(0):
 268         case AES_TAGR(1):
 269         case AES_TAGR(2):
 270         case AES_TAGR(3):
 271                 snprintf(tmp, sz, "TAGR[%u]", (offset - AES_TAGR(0)) >> 2);
 272                 break;
 273
 274         case AES_CTRR:
 275                 return "CTRR";
 276
 277         case AES_GCMHR(0):
 278         case AES_GCMHR(1):
 279         case AES_GCMHR(2):
 280         case AES_GCMHR(3):
 281                 snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2);
 282                 break;
 283
 284         default:
 285                 snprintf(tmp, sz, "0x%02x", offset);
 286                 break;
 287         }
 288
 289         return tmp;
 290 }
 291 #endif /* VERBOSE_DEBUG */
 292
 293 /* Shared functions */
 294
 295 static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset)
 296 {
 297         u32 value = readl_relaxed(dd->io_base + offset);
 298
 299 #ifdef VERBOSE_DEBUG
 300         if (dd->flags & AES_FLAGS_DUMP_REG) {
 301                 char tmp[16];
 302
 303                 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value,
 304                          atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
 305         }
 306 #endif /* VERBOSE_DEBUG */
 307
 308         return value;
 309 }
 310
 311 static inline void atmel_aes_write(struct atmel_aes_dev *dd,
 312                                         u32 offset, u32 value)
 313 {
 314 #ifdef VERBOSE_DEBUG
 315         if (dd->flags & AES_FLAGS_DUMP_REG) {
 316                 char tmp[16];
 317
 318                 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value,
 319                          atmel_aes_reg_name(offset, tmp));
 320         }
 321 #endif /* VERBOSE_DEBUG */
 322
 323         writel_relaxed(value, dd->io_base + offset);
 324 }
 325
 326 static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset,
 327                                         u32 *value, int count)
 328 {
 329         for (; count--; value++, offset += 4)
 330                 *value = atmel_aes_read(dd, offset);
 331 }
 332
 333 static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset,
 334                               const u32 *value, int count)
 335 {
 336         for (; count--; value++, offset += 4)
 337                 atmel_aes_write(dd, offset, *value);
 338 }
 339
 340 static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset,
 341                                         u32 *value)
 342 {
 343         atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
 344 }
 345
 346 static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset,
 347                                          const u32 *value)
 348 {
 349         atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
 350 }
 351
 352 static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd,
 353                                                 atmel_aes_fn_t resume)
 354 {
 355         u32 isr = atmel_aes_read(dd, AES_ISR);
 356
 357         if (unlikely(isr & AES_INT_DATARDY))
 358                 return resume(dd);
 359
 360         dd->resume = resume;
 361         atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
 362         return -EINPROGRESS;
 363 }
 364
 365 static inline size_t atmel_aes_padlen(size_t len, size_t block_size)
 366 {
 367         len &= block_size - 1;
 368         return len ? block_size - len : 0;
 369 }
 370
 371 static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx)
 372 {
 373         struct atmel_aes_dev *aes_dd = NULL;
 374         struct atmel_aes_dev *tmp;
 375
 376         spin_lock_bh(&atmel_aes.lock);
 377         if (!ctx->dd) {
 378                 list_for_each_entry(tmp, &atmel_aes.dev_list, list) {
 379                         aes_dd = tmp;
 380                         break;
 381                 }
 382                 ctx->dd = aes_dd;
 383         } else {
 384                 aes_dd = ctx->dd;
 385         }
 386
 387         spin_unlock_bh(&atmel_aes.lock);
 388
 389         return aes_dd;
 390 }
 391
 392 static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
 393 {
 394         int err;
 395
 396         err = clk_enable(dd->iclk);
 397         if (err)
 398                 return err;
 399
 400         if (!(dd->flags & AES_FLAGS_INIT)) {
 401                 atmel_aes_write(dd, AES_CR, AES_CR_SWRST);
 402                 atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET);
 403                 dd->flags |= AES_FLAGS_INIT;
 404         }
 405
 406         return 0;
 407 }
 408
 409 static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd)
 410 {
 411         return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff;
 412 }
 413
 414 static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
 415 {
 416         int err;
 417
 418         err = atmel_aes_hw_init(dd);
 419         if (err)
 420                 return err;
 421
 422         dd->hw_version = atmel_aes_get_version(dd);
 423
 424         dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
 425
 426         clk_disable(dd->iclk);
 427         return 0;
 428 }
 429
 430 static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
 431                                       const struct atmel_aes_reqctx *rctx)
 432 {
 433         /* Clear all but persistent flags and set request flags. */
 434         dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
 435 }
 436
 437 static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd)
 438 {
 439         return (dd->flags & AES_FLAGS_ENCRYPT);
 440 }
 441
 442 static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
 443 {
 444         clk_disable(dd->iclk);
 445         dd->flags &= ~AES_FLAGS_BUSY;
 446
 447         if (dd->is_async)
 448                 dd->areq->complete(dd->areq, err);
 449
 450         tasklet_schedule(&dd->queue_task);
 451
 452         return err;
 453 }
 454
 455 static void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
 456                                  const u32 *iv)
 457 {
 458         u32 valmr = 0;
 459
 460         /* MR register must be set before IV registers */
 461         if (dd->ctx->keylen == AES_KEYSIZE_128)
 462                 valmr |= AES_MR_KEYSIZE_128;
 463         else if (dd->ctx->keylen == AES_KEYSIZE_192)
 464                 valmr |= AES_MR_KEYSIZE_192;
 465         else
 466                 valmr |= AES_MR_KEYSIZE_256;
 467
 468         valmr |= dd->flags & AES_FLAGS_MODE_MASK;
 469
 470         if (use_dma) {
 471                 valmr |= AES_MR_SMOD_IDATAR0;
 472                 if (dd->caps.has_dualbuff)
 473                         valmr |= AES_MR_DUALBUFF;
 474         } else {
 475                 valmr |= AES_MR_SMOD_AUTO;
 476         }
 477
 478         atmel_aes_write(dd, AES_MR, valmr);
 479
 480         atmel_aes_write_n(dd, AES_KEYWR(0), dd->ctx->key,
 481                           SIZE_IN_WORDS(dd->ctx->keylen));
 482
 483         if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
 484                 atmel_aes_write_block(dd, AES_IVR(0), iv);
 485 }
 486
 487
 488 /* CPU transfer */
 489
 490 static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd)
 491 {
 492         int err = 0;
 493         u32 isr;
 494
 495         for (;;) {
 496                 atmel_aes_read_block(dd, AES_ODATAR(0), dd->data);
 497                 dd->data += 4;
 498                 dd->datalen -= AES_BLOCK_SIZE;
 499
 500                 if (dd->datalen < AES_BLOCK_SIZE)
 501                         break;
 502
 503                 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
 504
 505                 isr = atmel_aes_read(dd, AES_ISR);
 506                 if (!(isr & AES_INT_DATARDY)) {
 507                         dd->resume = atmel_aes_cpu_transfer;
 508                         atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
 509                         return -EINPROGRESS;
 510                 }
 511         }
 512
 513         if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
 514                                  dd->buf, dd->total))
 515                 err = -EINVAL;
 516
 517         if (err)
 518                 return atmel_aes_complete(dd, err);
 519
 520         return dd->cpu_transfer_complete(dd);
 521 }
 522
 523 static int atmel_aes_cpu_start(struct atmel_aes_dev *dd,
 524                                struct scatterlist *src,
 525                                struct scatterlist *dst,
 526                                size_t len,
 527                                atmel_aes_fn_t resume)
 528 {
 529         size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE);
 530
 531         if (unlikely(len == 0))
 532                 return -EINVAL;
 533
 534         sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
 535
 536         dd->total = len;
 537         dd->real_dst = dst;
 538         dd->cpu_transfer_complete = resume;
 539         dd->datalen = len + padlen;
 540         dd->data = (u32 *)dd->buf;
 541         atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
 542         return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer);
 543 }
 544
 545
 546 /* DMA transfer */
 547
 548 static void atmel_aes_dma_callback(void *data);
 549
 550 static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd,
 551                                     struct scatterlist *sg,
 552                                     size_t len,
 553                                     struct atmel_aes_dma *dma)
 554 {
 555         int nents;
 556
 557         if (!IS_ALIGNED(len, dd->ctx->block_size))
 558                 return false;
 559
 560         for (nents = 0; sg; sg = sg_next(sg), ++nents) {
 561                 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
 562                         return false;
 563
 564                 if (len <= sg->length) {
 565                         if (!IS_ALIGNED(len, dd->ctx->block_size))
 566                                 return false;
 567
 568                         dma->nents = nents+1;
 569                         dma->remainder = sg->length - len;
 570                         sg->length = len;
 571                         return true;
 572                 }
 573
 574                 if (!IS_ALIGNED(sg->length, dd->ctx->block_size))
 575                         return false;
 576
 577                 len -= sg->length;
 578         }
 579
 580         return false;
 581 }
 582
 583 static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma)
 584 {
 585         struct scatterlist *sg = dma->sg;
 586         int nents = dma->nents;
 587
 588         if (!dma->remainder)
 589                 return;
 590
 591         while (--nents > 0 && sg)
 592                 sg = sg_next(sg);
 593
 594         if (!sg)
 595                 return;
 596
 597         sg->length += dma->remainder;
 598 }
 599
 600 static int atmel_aes_map(struct atmel_aes_dev *dd,
 601                          struct scatterlist *src,
 602                          struct scatterlist *dst,
 603                          size_t len)
 604 {
 605         bool src_aligned, dst_aligned;
 606         size_t padlen;
 607
 608         dd->total = len;
 609         dd->src.sg = src;
 610         dd->dst.sg = dst;
 611         dd->real_dst = dst;
 612
 613         src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src);
 614         if (src == dst)
 615                 dst_aligned = src_aligned;
 616         else
 617                 dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst);
 618         if (!src_aligned || !dst_aligned) {
 619                 padlen = atmel_aes_padlen(len, dd->ctx->block_size);
 620
 621                 if (dd->buflen < len + padlen)
 622                         return -ENOMEM;
 623
 624                 if (!src_aligned) {
 625                         sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
 626                         dd->src.sg = &dd->aligned_sg;
 627                         dd->src.nents = 1;
 628                         dd->src.remainder = 0;
 629                 }
 630
 631                 if (!dst_aligned) {
 632                         dd->dst.sg = &dd->aligned_sg;
 633                         dd->dst.nents = 1;
 634                         dd->dst.remainder = 0;
 635                 }
 636
 637                 sg_init_table(&dd->aligned_sg, 1);
 638                 sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen);
 639         }
 640
 641         if (dd->src.sg == dd->dst.sg) {
 642                 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
 643                                             DMA_BIDIRECTIONAL);
 644                 dd->dst.sg_len = dd->src.sg_len;
 645                 if (!dd->src.sg_len)
 646                         return -EFAULT;
 647         } else {
 648                 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
 649                                             DMA_TO_DEVICE);
 650                 if (!dd->src.sg_len)
 651                         return -EFAULT;
 652
 653                 dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents,
 654                                             DMA_FROM_DEVICE);
 655                 if (!dd->dst.sg_len) {
 656                         dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
 657                                      DMA_TO_DEVICE);
 658                         return -EFAULT;
 659                 }
 660         }
 661
 662         return 0;
 663 }
 664
 665 static void atmel_aes_unmap(struct atmel_aes_dev *dd)
 666 {
 667         if (dd->src.sg == dd->dst.sg) {
 668                 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
 669                              DMA_BIDIRECTIONAL);
 670
 671                 if (dd->src.sg != &dd->aligned_sg)
 672                         atmel_aes_restore_sg(&dd->src);
 673         } else {
 674                 dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents,
 675                              DMA_FROM_DEVICE);
 676
 677                 if (dd->dst.sg != &dd->aligned_sg)
 678                         atmel_aes_restore_sg(&dd->dst);
 679
 680                 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
 681                              DMA_TO_DEVICE);
 682
 683                 if (dd->src.sg != &dd->aligned_sg)
 684                         atmel_aes_restore_sg(&dd->src);
 685         }
 686
 687         if (dd->dst.sg == &dd->aligned_sg)
 688                 sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
 689                                     dd->buf, dd->total);
 690 }
 691
 692 static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd,
 693                                         enum dma_slave_buswidth addr_width,
 694                                         enum dma_transfer_direction dir,
 695                                         u32 maxburst)
 696 {
 697         struct dma_async_tx_descriptor *desc;
 698         struct dma_slave_config config;
 699         dma_async_tx_callback callback;
 700         struct atmel_aes_dma *dma;
 701         int err;
 702
 703         memset(&config, 0, sizeof(config));
 704         config.direction = dir;
 705         config.src_addr_width = addr_width;
 706         config.dst_addr_width = addr_width;
 707         config.src_maxburst = maxburst;
 708         config.dst_maxburst = maxburst;
 709
 710         switch (dir) {
 711         case DMA_MEM_TO_DEV:
 712                 dma = &dd->src;
 713                 callback = NULL;
 714                 config.dst_addr = dd->phys_base + AES_IDATAR(0);
 715                 break;
 716
 717         case DMA_DEV_TO_MEM:
 718                 dma = &dd->dst;
 719                 callback = atmel_aes_dma_callback;
 720                 config.src_addr = dd->phys_base + AES_ODATAR(0);
 721                 break;
 722
 723         default:
 724                 return -EINVAL;
 725         }
 726
 727         err = dmaengine_slave_config(dma->chan, &config);
 728         if (err)
 729                 return err;
 730
 731         desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir,
 732                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 733         if (!desc)
 734                 return -ENOMEM;
 735
 736         desc->callback = callback;
 737         desc->callback_param = dd;
 738         dmaengine_submit(desc);
 739         dma_async_issue_pending(dma->chan);
 740
 741         return 0;
 742 }
 743
 744 static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd,
 745                                         enum dma_transfer_direction dir)
 746 {
 747         struct atmel_aes_dma *dma;
 748
 749         switch (dir) {
 750         case DMA_MEM_TO_DEV:
 751                 dma = &dd->src;
 752                 break;
 753
 754         case DMA_DEV_TO_MEM:
 755                 dma = &dd->dst;
 756                 break;
 757
 758         default:
 759                 return;
 760         }
 761
 762         dmaengine_terminate_all(dma->chan);
 763 }
 764
 765 static int atmel_aes_dma_start(struct atmel_aes_dev *dd,
 766                                struct scatterlist *src,
 767                                struct scatterlist *dst,
 768                                size_t len,
 769                                atmel_aes_fn_t resume)
 770 {
 771         enum dma_slave_buswidth addr_width;
 772         u32 maxburst;
 773         int err;
 774
 775         switch (dd->ctx->block_size) {
 776         case CFB8_BLOCK_SIZE:
 777                 addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 778                 maxburst = 1;
 779                 break;
 780
 781         case CFB16_BLOCK_SIZE:
 782                 addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 783                 maxburst = 1;
 784                 break;
 785
 786         case CFB32_BLOCK_SIZE:
 787         case CFB64_BLOCK_SIZE:
 788                 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 789                 maxburst = 1;
 790                 break;
 791
 792         case AES_BLOCK_SIZE:
 793                 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 794                 maxburst = dd->caps.max_burst_size;
 795                 break;
 796
 797         default:
 798                 err = -EINVAL;
 799                 goto exit;
 800         }
 801
 802         err = atmel_aes_map(dd, src, dst, len);
 803         if (err)
 804                 goto exit;
 805
 806         dd->resume = resume;
 807
 808         /* Set output DMA transfer first */
 809         err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM,
 810                                            maxburst);
 811         if (err)
 812                 goto unmap;
 813
 814         /* Then set input DMA transfer */
 815         err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV,
 816                                            maxburst);
 817         if (err)
 818                 goto output_transfer_stop;
 819
 820         return -EINPROGRESS;
 821
 822 output_transfer_stop:
 823         atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
 824 unmap:
 825         atmel_aes_unmap(dd);
 826 exit:
 827         return atmel_aes_complete(dd, err);
 828 }
 829
 830 static void atmel_aes_dma_stop(struct atmel_aes_dev *dd)
 831 {
 832         atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV);
 833         atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
 834         atmel_aes_unmap(dd);
 835 }
 836
 837 static void atmel_aes_dma_callback(void *data)
 838 {
 839         struct atmel_aes_dev *dd = data;
 840
 841         atmel_aes_dma_stop(dd);
 842         dd->is_async = true;
 843         (void)dd->resume(dd);
 844 }
 845
 846 static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
 847                                   struct crypto_async_request *new_areq)
 848 {
 849         struct crypto_async_request *areq, *backlog;
 850         struct atmel_aes_base_ctx *ctx;
 851         unsigned long flags;
 852         int err, ret = 0;
 853
 854         spin_lock_irqsave(&dd->lock, flags);
 855         if (new_areq)
 856                 ret = crypto_enqueue_request(&dd->queue, new_areq);
 857         if (dd->flags & AES_FLAGS_BUSY) {
 858                 spin_unlock_irqrestore(&dd->lock, flags);
 859                 return ret;
 860         }
 861         backlog = crypto_get_backlog(&dd->queue);
 862         areq = crypto_dequeue_request(&dd->queue);
 863         if (areq)
 864                 dd->flags |= AES_FLAGS_BUSY;
 865         spin_unlock_irqrestore(&dd->lock, flags);
 866
 867         if (!areq)
 868                 return ret;
 869
 870         if (backlog)
 871                 backlog->complete(backlog, -EINPROGRESS);
 872
 873         ctx = crypto_tfm_ctx(areq->tfm);
 874
 875         dd->areq = areq;
 876         dd->ctx = ctx;
 877         dd->is_async = (areq != new_areq);
 878
 879         err = ctx->start(dd);
 880         return (dd->is_async) ? ret : err;
 881 }
 882
 883
 884 /* AES async block ciphers */
 885
 886 static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd)
 887 {
 888         return atmel_aes_complete(dd, 0);
 889 }
 890
 891 static int atmel_aes_start(struct atmel_aes_dev *dd)
 892 {
 893         struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
 894         struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
 895         bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD ||
 896                         dd->ctx->block_size != AES_BLOCK_SIZE);
 897         int err;
 898
 899         atmel_aes_set_mode(dd, rctx);
 900
 901         err = atmel_aes_hw_init(dd);
 902         if (err)
 903                 return atmel_aes_complete(dd, err);
 904
 905         atmel_aes_write_ctrl(dd, use_dma, req->info);
 906         if (use_dma)
 907                 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
 908                                            atmel_aes_transfer_complete);
 909
 910         return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
 911                                    atmel_aes_transfer_complete);
 912 }
 913
 914 static inline struct atmel_aes_ctr_ctx *
 915 atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx)
 916 {
 917         return container_of(ctx, struct atmel_aes_ctr_ctx, base);
 918 }
 919
 920 static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
 921 {
 922         struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
 923         struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
 924         struct scatterlist *src, *dst;
 925         size_t datalen;
 926         u32 ctr;
 927         u16 blocks, start, end;
 928         bool use_dma, fragmented = false;
 929
 930         /* Check for transfer completion. */
 931         ctx->offset += dd->total;
 932         if (ctx->offset >= req->nbytes)
 933                 return atmel_aes_transfer_complete(dd);
 934
 935         /* Compute data length. */
 936         datalen = req->nbytes - ctx->offset;
 937         blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
 938         ctr = be32_to_cpu(ctx->iv[3]);
 939
 940         /* Check 16bit counter overflow. */
 941         start = ctr & 0xffff;
 942         end = start + blocks - 1;
 943
 944         if (blocks >> 16 || end < start) {
 945                 ctr |= 0xffff;
 946                 datalen = AES_BLOCK_SIZE * (0x10000 - start);
 947                 fragmented = true;
 948         }
 949
 950         use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
 951
 952         /* Jump to offset. */
 953         src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset);
 954         dst = ((req->src == req->dst) ? src :
 955                scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset));
 956
 957         /* Configure hardware. */
 958         atmel_aes_write_ctrl(dd, use_dma, ctx->iv);
 959         if (unlikely(fragmented)) {
 960                 /*
 961                  * Increment the counter manually to cope with the hardware
 962                  * counter overflow.
 963                  */
 964                 ctx->iv[3] = cpu_to_be32(ctr);
 965                 crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE);
 966         }
 967
 968         if (use_dma)
 969                 return atmel_aes_dma_start(dd, src, dst, datalen,
 970                                            atmel_aes_ctr_transfer);
 971
 972         return atmel_aes_cpu_start(dd, src, dst, datalen,
 973                                    atmel_aes_ctr_transfer);
 974 }
 975
 976 static int atmel_aes_ctr_start(struct atmel_aes_dev *dd)
 977 {
 978         struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
 979         struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
 980         struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
 981         int err;
 982
 983         atmel_aes_set_mode(dd, rctx);
 984
 985         err = atmel_aes_hw_init(dd);
 986         if (err)
 987                 return atmel_aes_complete(dd, err);
 988
 989         memcpy(ctx->iv, req->info, AES_BLOCK_SIZE);
 990         ctx->offset = 0;
 991         dd->total = 0;
 992         return atmel_aes_ctr_transfer(dd);
 993 }
 994
 995 static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
 996 {
 997         struct atmel_aes_base_ctx *ctx;
 998         struct atmel_aes_reqctx *rctx;
 999         struct atmel_aes_dev *dd;
1000
1001         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
1002         switch (mode & AES_FLAGS_OPMODE_MASK) {
1003         case AES_FLAGS_CFB8:
1004                 ctx->block_size = CFB8_BLOCK_SIZE;
1005                 break;
1006
1007         case AES_FLAGS_CFB16:
1008                 ctx->block_size = CFB16_BLOCK_SIZE;
1009                 break;
1010
1011         case AES_FLAGS_CFB32:
1012                 ctx->block_size = CFB32_BLOCK_SIZE;
1013                 break;
1014
1015         case AES_FLAGS_CFB64:
1016                 ctx->block_size = CFB64_BLOCK_SIZE;
1017                 break;
1018
1019         default:
1020                 ctx->block_size = AES_BLOCK_SIZE;
1021                 break;
1022         }
1023
1024         dd = atmel_aes_find_dev(ctx);
1025         if (!dd)
1026                 return -ENODEV;
1027
1028         rctx = ablkcipher_request_ctx(req);
1029         rctx->mode = mode;
1030
1031         return atmel_aes_handle_queue(dd, &req->base);
1032 }
1033
1034 static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1035                            unsigned int keylen)
1036 {
1037         struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1038
1039         if (keylen != AES_KEYSIZE_128 &&
1040             keylen != AES_KEYSIZE_192 &&
1041             keylen != AES_KEYSIZE_256) {
1042                 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1043                 return -EINVAL;
1044         }
1045
1046         memcpy(ctx->key, key, keylen);
1047         ctx->keylen = keylen;
1048
1049         return 0;
1050 }
1051
1052 static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
1053 {
1054         return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1055 }
1056
1057 static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
1058 {
1059         return atmel_aes_crypt(req, AES_FLAGS_ECB);
1060 }
1061
1062 static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
1063 {
1064         return atmel_aes_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
1065 }
1066
1067 static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req)
1068 {
1069         return atmel_aes_crypt(req, AES_FLAGS_CBC);
1070 }
1071
1072 static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req)
1073 {
1074         return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT);
1075 }
1076
1077 static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
1078 {
1079         return atmel_aes_crypt(req, AES_FLAGS_OFB);
1080 }
1081
1082 static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
1083 {
1084         return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);
1085 }
1086
1087 static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
1088 {
1089         return atmel_aes_crypt(req, AES_FLAGS_CFB128);
1090 }
1091
1092 static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
1093 {
1094         return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);
1095 }
1096
1097 static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
1098 {
1099         return atmel_aes_crypt(req, AES_FLAGS_CFB64);
1100 }
1101
1102 static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
1103 {
1104         return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);
1105 }
1106
1107 static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
1108 {
1109         return atmel_aes_crypt(req, AES_FLAGS_CFB32);
1110 }
1111
1112 static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
1113 {
1114         return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);
1115 }
1116
1117 static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
1118 {
1119         return atmel_aes_crypt(req, AES_FLAGS_CFB16);
1120 }
1121
1122 static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
1123 {
1124         return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);
1125 }
1126
1127 static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
1128 {
1129         return atmel_aes_crypt(req, AES_FLAGS_CFB8);
1130 }
1131
1132 static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
1133 {
1134         return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT);
1135 }
1136
1137 static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req)
1138 {
1139         return atmel_aes_crypt(req, AES_FLAGS_CTR);
1140 }
1141
1142 static int atmel_aes_cra_init(struct crypto_tfm *tfm)
1143 {
1144         struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1145
1146         tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1147         ctx->base.start = atmel_aes_start;
1148
1149         return 0;
1150 }
1151
1152 static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm)
1153 {
1154         struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1155
1156         tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1157         ctx->base.start = atmel_aes_ctr_start;
1158
1159         return 0;
1160 }
1161
1162 static void atmel_aes_cra_exit(struct crypto_tfm *tfm)
1163 {
1164 }
1165
1166 static struct crypto_alg aes_algs[] = {
1167 {
1168         .cra_name               = "ecb(aes)",
1169         .cra_driver_name        = "atmel-ecb-aes",
1170         .cra_priority           = ATMEL_AES_PRIORITY,
1171         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1172         .cra_blocksize          = AES_BLOCK_SIZE,
1173         .cra_ctxsize            = sizeof(struct atmel_aes_ctx),
1174         .cra_alignmask          = 0xf,
1175         .cra_type               = &crypto_ablkcipher_type,
1176         .cra_module             = THIS_MODULE,
1177         .cra_init               = atmel_aes_cra_init,
1178         .cra_exit               = atmel_aes_cra_exit,
1179         .cra_u.ablkcipher = {
1180                 .min_keysize    = AES_MIN_KEY_SIZE,
1181                 .max_keysize    = AES_MAX_KEY_SIZE,
1182                 .setkey         = atmel_aes_setkey,
1183                 .encrypt        = atmel_aes_ecb_encrypt,
1184                 .decrypt        = atmel_aes_ecb_decrypt,
1185         }
1186 },
1187 {
1188         .cra_name               = "cbc(aes)",
1189         .cra_driver_name        = "atmel-cbc-aes",
1190         .cra_priority           = ATMEL_AES_PRIORITY,
1191         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1192         .cra_blocksize          = AES_BLOCK_SIZE,
1193         .cra_ctxsize            = sizeof(struct atmel_aes_ctx),
1194         .cra_alignmask          = 0xf,
1195         .cra_type               = &crypto_ablkcipher_type,
1196         .cra_module             = THIS_MODULE,
1197         .cra_init               = atmel_aes_cra_init,
1198         .cra_exit               = atmel_aes_cra_exit,
1199         .cra_u.ablkcipher = {
1200                 .min_keysize    = AES_MIN_KEY_SIZE,
1201                 .max_keysize    = AES_MAX_KEY_SIZE,
1202                 .ivsize         = AES_BLOCK_SIZE,
1203                 .setkey         = atmel_aes_setkey,
1204                 .encrypt        = atmel_aes_cbc_encrypt,
1205                 .decrypt        = atmel_aes_cbc_decrypt,
1206         }
1207 },
1208 {
1209         .cra_name               = "ofb(aes)",
1210         .cra_driver_name        = "atmel-ofb-aes",
1211         .cra_priority           = ATMEL_AES_PRIORITY,
1212         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1213         .cra_blocksize          = AES_BLOCK_SIZE,
1214         .cra_ctxsize            = sizeof(struct atmel_aes_ctx),
1215         .cra_alignmask          = 0xf,
1216         .cra_type               = &crypto_ablkcipher_type,
1217         .cra_module             = THIS_MODULE,
1218         .cra_init               = atmel_aes_cra_init,
1219         .cra_exit               = atmel_aes_cra_exit,
1220         .cra_u.ablkcipher = {
1221                 .min_keysize    = AES_MIN_KEY_SIZE,
1222                 .max_keysize    = AES_MAX_KEY_SIZE,
1223                 .ivsize         = AES_BLOCK_SIZE,
1224                 .setkey         = atmel_aes_setkey,
1225                 .encrypt        = atmel_aes_ofb_encrypt,
1226                 .decrypt        = atmel_aes_ofb_decrypt,
1227         }
1228 },
1229 {
1230         .cra_name               = "cfb(aes)",
1231         .cra_driver_name        = "atmel-cfb-aes",
1232         .cra_priority           = ATMEL_AES_PRIORITY,
1233         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1234         .cra_blocksize          = AES_BLOCK_SIZE,
1235         .cra_ctxsize            = sizeof(struct atmel_aes_ctx),
1236         .cra_alignmask          = 0xf,
1237         .cra_type               = &crypto_ablkcipher_type,
1238         .cra_module             = THIS_MODULE,
1239         .cra_init               = atmel_aes_cra_init,
1240         .cra_exit               = atmel_aes_cra_exit,
1241         .cra_u.ablkcipher = {
1242                 .min_keysize    = AES_MIN_KEY_SIZE,
1243                 .max_keysize    = AES_MAX_KEY_SIZE,
1244                 .ivsize         = AES_BLOCK_SIZE,
1245                 .setkey         = atmel_aes_setkey,
1246                 .encrypt        = atmel_aes_cfb_encrypt,
1247                 .decrypt        = atmel_aes_cfb_decrypt,
1248         }
1249 },
1250 {
1251         .cra_name               = "cfb32(aes)",
1252         .cra_driver_name        = "atmel-cfb32-aes",
1253         .cra_priority           = ATMEL_AES_PRIORITY,
1254         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1255         .cra_blocksize          = CFB32_BLOCK_SIZE,
1256         .cra_ctxsize            = sizeof(struct atmel_aes_ctx),
1257         .cra_alignmask          = 0x3,
1258         .cra_type               = &crypto_ablkcipher_type,
1259         .cra_module             = THIS_MODULE,
1260         .cra_init               = atmel_aes_cra_init,
1261         .cra_exit               = atmel_aes_cra_exit,
1262         .cra_u.ablkcipher = {
1263                 .min_keysize    = AES_MIN_KEY_SIZE,
1264                 .max_keysize    = AES_MAX_KEY_SIZE,
1265                 .ivsize         = AES_BLOCK_SIZE,
1266                 .setkey         = atmel_aes_setkey,
1267                 .encrypt        = atmel_aes_cfb32_encrypt,
1268                 .decrypt        = atmel_aes_cfb32_decrypt,
1269         }
1270 },
1271 {
1272         .cra_name               = "cfb16(aes)",
1273         .cra_driver_name        = "atmel-cfb16-aes",
1274         .cra_priority           = ATMEL_AES_PRIORITY,
1275         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1276         .cra_blocksize          = CFB16_BLOCK_SIZE,
1277         .cra_ctxsize            = sizeof(struct atmel_aes_ctx),
1278         .cra_alignmask          = 0x1,
1279         .cra_type               = &crypto_ablkcipher_type,
1280         .cra_module             = THIS_MODULE,
1281         .cra_init               = atmel_aes_cra_init,
1282         .cra_exit               = atmel_aes_cra_exit,
1283         .cra_u.ablkcipher = {
1284                 .min_keysize    = AES_MIN_KEY_SIZE,
1285                 .max_keysize    = AES_MAX_KEY_SIZE,
1286                 .ivsize         = AES_BLOCK_SIZE,
1287                 .setkey         = atmel_aes_setkey,
1288                 .encrypt        = atmel_aes_cfb16_encrypt,
1289                 .decrypt        = atmel_aes_cfb16_decrypt,
1290         }
1291 },
1292 {
1293         .cra_name               = "cfb8(aes)",
1294         .cra_driver_name        = "atmel-cfb8-aes",
1295         .cra_priority           = ATMEL_AES_PRIORITY,
1296         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1297         .cra_blocksize          = CFB8_BLOCK_SIZE,
1298         .cra_ctxsize            = sizeof(struct atmel_aes_ctx),
1299         .cra_alignmask          = 0x0,
1300         .cra_type               = &crypto_ablkcipher_type,
1301         .cra_module             = THIS_MODULE,
1302         .cra_init               = atmel_aes_cra_init,
1303         .cra_exit               = atmel_aes_cra_exit,
1304         .cra_u.ablkcipher = {
1305                 .min_keysize    = AES_MIN_KEY_SIZE,
1306                 .max_keysize    = AES_MAX_KEY_SIZE,
1307                 .ivsize         = AES_BLOCK_SIZE,
1308                 .setkey         = atmel_aes_setkey,
1309                 .encrypt        = atmel_aes_cfb8_encrypt,
1310                 .decrypt        = atmel_aes_cfb8_decrypt,
1311         }
1312 },
1313 {
1314         .cra_name               = "ctr(aes)",
1315         .cra_driver_name        = "atmel-ctr-aes",
1316         .cra_priority           = ATMEL_AES_PRIORITY,
1317         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1318         .cra_blocksize          = 1,
1319         .cra_ctxsize            = sizeof(struct atmel_aes_ctr_ctx),
1320         .cra_alignmask          = 0xf,
1321         .cra_type               = &crypto_ablkcipher_type,
1322         .cra_module             = THIS_MODULE,
1323         .cra_init               = atmel_aes_ctr_cra_init,
1324         .cra_exit               = atmel_aes_cra_exit,
1325         .cra_u.ablkcipher = {
1326                 .min_keysize    = AES_MIN_KEY_SIZE,
1327                 .max_keysize    = AES_MAX_KEY_SIZE,
1328                 .ivsize         = AES_BLOCK_SIZE,
1329                 .setkey         = atmel_aes_setkey,
1330                 .encrypt        = atmel_aes_ctr_encrypt,
1331                 .decrypt        = atmel_aes_ctr_decrypt,
1332         }
1333 },
1334 };
1335
1336 static struct crypto_alg aes_cfb64_alg = {
1337         .cra_name               = "cfb64(aes)",
1338         .cra_driver_name        = "atmel-cfb64-aes",
1339         .cra_priority           = ATMEL_AES_PRIORITY,
1340         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1341         .cra_blocksize          = CFB64_BLOCK_SIZE,
1342         .cra_ctxsize            = sizeof(struct atmel_aes_ctx),
1343         .cra_alignmask          = 0x7,
1344         .cra_type               = &crypto_ablkcipher_type,
1345         .cra_module             = THIS_MODULE,
1346         .cra_init               = atmel_aes_cra_init,
1347         .cra_exit               = atmel_aes_cra_exit,
1348         .cra_u.ablkcipher = {
1349                 .min_keysize    = AES_MIN_KEY_SIZE,
1350                 .max_keysize    = AES_MAX_KEY_SIZE,
1351                 .ivsize         = AES_BLOCK_SIZE,
1352                 .setkey         = atmel_aes_setkey,
1353                 .encrypt        = atmel_aes_cfb64_encrypt,
1354                 .decrypt        = atmel_aes_cfb64_decrypt,
1355         }
1356 };
1357
1358
1359 /* gcm aead functions */
1360
1361 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1362                                const u32 *data, size_t datalen,
1363                                const u32 *ghash_in, u32 *ghash_out,
1364                                atmel_aes_fn_t resume);
1365 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd);
1366 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd);
1367
1368 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd);
1369 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd);
1370 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd);
1371 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd);
1372 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd);
1373 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd);
1374 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd);
1375
1376 static inline struct atmel_aes_gcm_ctx *
1377 atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx)
1378 {
1379         return container_of(ctx, struct atmel_aes_gcm_ctx, base);
1380 }
1381
1382 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1383                                const u32 *data, size_t datalen,
1384                                const u32 *ghash_in, u32 *ghash_out,
1385                                atmel_aes_fn_t resume)
1386 {
1387         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1388
1389         dd->data = (u32 *)data;
1390         dd->datalen = datalen;
1391         ctx->ghash_in = ghash_in;
1392         ctx->ghash_out = ghash_out;
1393         ctx->ghash_resume = resume;
1394
1395         atmel_aes_write_ctrl(dd, false, NULL);
1396         return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init);
1397 }
1398
1399 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd)
1400 {
1401         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1402
1403         /* Set the data length. */
1404         atmel_aes_write(dd, AES_AADLENR, dd->total);
1405         atmel_aes_write(dd, AES_CLENR, 0);
1406
1407         /* If needed, overwrite the GCM Intermediate Hash Word Registers */
1408         if (ctx->ghash_in)
1409                 atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in);
1410
1411         return atmel_aes_gcm_ghash_finalize(dd);
1412 }
1413
1414 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd)
1415 {
1416         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1417         u32 isr;
1418
1419         /* Write data into the Input Data Registers. */
1420         while (dd->datalen > 0) {
1421                 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1422                 dd->data += 4;
1423                 dd->datalen -= AES_BLOCK_SIZE;
1424
1425                 isr = atmel_aes_read(dd, AES_ISR);
1426                 if (!(isr & AES_INT_DATARDY)) {
1427                         dd->resume = atmel_aes_gcm_ghash_finalize;
1428                         atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1429                         return -EINPROGRESS;
1430                 }
1431         }
1432
1433         /* Read the computed hash from GHASHRx. */
1434         atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out);
1435
1436         return ctx->ghash_resume(dd);
1437 }
1438
1439
1440 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd)
1441 {
1442         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1443         struct aead_request *req = aead_request_cast(dd->areq);
1444         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1445         struct atmel_aes_reqctx *rctx = aead_request_ctx(req);
1446         size_t ivsize = crypto_aead_ivsize(tfm);
1447         size_t datalen, padlen;
1448         const void *iv = req->iv;
1449         u8 *data = dd->buf;
1450         int err;
1451
1452         atmel_aes_set_mode(dd, rctx);
1453
1454         err = atmel_aes_hw_init(dd);
1455         if (err)
1456                 return atmel_aes_complete(dd, err);
1457
1458         if (likely(ivsize == 12)) {
1459                 memcpy(ctx->j0, iv, ivsize);
1460                 ctx->j0[3] = cpu_to_be32(1);
1461                 return atmel_aes_gcm_process(dd);
1462         }
1463
1464         padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE);
1465         datalen = ivsize + padlen + AES_BLOCK_SIZE;
1466         if (datalen > dd->buflen)
1467                 return atmel_aes_complete(dd, -EINVAL);
1468
1469         memcpy(data, iv, ivsize);
1470         memset(data + ivsize, 0, padlen + sizeof(u64));
1471         ((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8);
1472
1473         return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen,
1474                                    NULL, ctx->j0, atmel_aes_gcm_process);
1475 }
1476
1477 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd)
1478 {
1479         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1480         struct aead_request *req = aead_request_cast(dd->areq);
1481         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1482         bool enc = atmel_aes_is_encrypt(dd);
1483         u32 authsize;
1484
1485         /* Compute text length. */
1486         authsize = crypto_aead_authsize(tfm);
1487         ctx->textlen = req->cryptlen - (enc ? 0 : authsize);
1488
1489         /*
1490          * According to tcrypt test suite, the GCM Automatic Tag Generation
1491          * fails when both the message and its associated data are empty.
1492          */
1493         if (likely(req->assoclen != 0 || ctx->textlen != 0))
1494                 dd->flags |= AES_FLAGS_GTAGEN;
1495
1496         atmel_aes_write_ctrl(dd, false, NULL);
1497         return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length);
1498 }
1499
1500 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd)
1501 {
1502         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1503         struct aead_request *req = aead_request_cast(dd->areq);
1504         u32 j0_lsw, *j0 = ctx->j0;
1505         size_t padlen;
1506
1507         /* Write incr32(J0) into IV. */
1508         j0_lsw = j0[3];
1509         j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1);
1510         atmel_aes_write_block(dd, AES_IVR(0), j0);
1511         j0[3] = j0_lsw;
1512
1513         /* Set aad and text lengths. */
1514         atmel_aes_write(dd, AES_AADLENR, req->assoclen);
1515         atmel_aes_write(dd, AES_CLENR, ctx->textlen);
1516
1517         /* Check whether AAD are present. */
1518         if (unlikely(req->assoclen == 0)) {
1519                 dd->datalen = 0;
1520                 return atmel_aes_gcm_data(dd);
1521         }
1522
1523         /* Copy assoc data and add padding. */
1524         padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE);
1525         if (unlikely(req->assoclen + padlen > dd->buflen))
1526                 return atmel_aes_complete(dd, -EINVAL);
1527         sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen);
1528
1529         /* Write assoc data into the Input Data register. */
1530         dd->data = (u32 *)dd->buf;
1531         dd->datalen = req->assoclen + padlen;
1532         return atmel_aes_gcm_data(dd);
1533 }
1534
1535 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd)
1536 {
1537         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1538         struct aead_request *req = aead_request_cast(dd->areq);
1539         bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD);
1540         struct scatterlist *src, *dst;
1541         u32 isr, mr;
1542
1543         /* Write AAD first. */
1544         while (dd->datalen > 0) {
1545                 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1546                 dd->data += 4;
1547                 dd->datalen -= AES_BLOCK_SIZE;
1548
1549                 isr = atmel_aes_read(dd, AES_ISR);
1550                 if (!(isr & AES_INT_DATARDY)) {
1551                         dd->resume = atmel_aes_gcm_data;
1552                         atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1553                         return -EINPROGRESS;
1554                 }
1555         }
1556
1557         /* GMAC only. */
1558         if (unlikely(ctx->textlen == 0))
1559                 return atmel_aes_gcm_tag_init(dd);
1560
1561         /* Prepare src and dst scatter lists to transfer cipher/plain texts */
1562         src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen);
1563         dst = ((req->src == req->dst) ? src :
1564                scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen));
1565
1566         if (use_dma) {
1567                 /* Update the Mode Register for DMA transfers. */
1568                 mr = atmel_aes_read(dd, AES_MR);
1569                 mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF);
1570                 mr |= AES_MR_SMOD_IDATAR0;
1571                 if (dd->caps.has_dualbuff)
1572                         mr |= AES_MR_DUALBUFF;
1573                 atmel_aes_write(dd, AES_MR, mr);
1574
1575                 return atmel_aes_dma_start(dd, src, dst, ctx->textlen,
1576                                            atmel_aes_gcm_tag_init);
1577         }
1578
1579         return atmel_aes_cpu_start(dd, src, dst, ctx->textlen,
1580                                    atmel_aes_gcm_tag_init);
1581 }
1582
1583 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd)
1584 {
1585         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1586         struct aead_request *req = aead_request_cast(dd->areq);
1587         u64 *data = dd->buf;
1588
1589         if (likely(dd->flags & AES_FLAGS_GTAGEN)) {
1590                 if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) {
1591                         dd->resume = atmel_aes_gcm_tag_init;
1592                         atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY);
1593                         return -EINPROGRESS;
1594                 }
1595
1596                 return atmel_aes_gcm_finalize(dd);
1597         }
1598
1599         /* Read the GCM Intermediate Hash Word Registers. */
1600         atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash);
1601
1602         data[0] = cpu_to_be64(req->assoclen * 8);
1603         data[1] = cpu_to_be64(ctx->textlen * 8);
1604
1605         return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE,
1606                                    ctx->ghash, ctx->ghash, atmel_aes_gcm_tag);
1607 }
1608
1609 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd)
1610 {
1611         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1612         unsigned long flags;
1613
1614         /*
1615          * Change mode to CTR to complete the tag generation.
1616          * Use J0 as Initialization Vector.
1617          */
1618         flags = dd->flags;
1619         dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN);
1620         dd->flags |= AES_FLAGS_CTR;
1621         atmel_aes_write_ctrl(dd, false, ctx->j0);
1622         dd->flags = flags;
1623
1624         atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash);
1625         return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize);
1626 }
1627
1628 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd)
1629 {
1630         struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1631         struct aead_request *req = aead_request_cast(dd->areq);
1632         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1633         bool enc = atmel_aes_is_encrypt(dd);
1634         u32 offset, authsize, itag[4], *otag = ctx->tag;
1635         int err;
1636
1637         /* Read the computed tag. */
1638         if (likely(dd->flags & AES_FLAGS_GTAGEN))
1639                 atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag);
1640         else
1641                 atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag);
1642
1643         offset = req->assoclen + ctx->textlen;
1644         authsize = crypto_aead_authsize(tfm);
1645         if (enc) {
1646                 scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1);
1647                 err = 0;
1648         } else {
1649                 scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0);
1650                 err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0;
1651         }
1652
1653         return atmel_aes_complete(dd, err);
1654 }
1655
1656 static int atmel_aes_gcm_crypt(struct aead_request *req,
1657                                unsigned long mode)
1658 {
1659         struct atmel_aes_base_ctx *ctx;
1660         struct atmel_aes_reqctx *rctx;
1661         struct atmel_aes_dev *dd;
1662
1663         ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
1664         ctx->block_size = AES_BLOCK_SIZE;
1665
1666         dd = atmel_aes_find_dev(ctx);
1667         if (!dd)
1668                 return -ENODEV;
1669
1670         rctx = aead_request_ctx(req);
1671         rctx->mode = AES_FLAGS_GCM | mode;
1672
1673         return atmel_aes_handle_queue(dd, &req->base);
1674 }
1675
1676 static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
1677                                 unsigned int keylen)
1678 {
1679         struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
1680
1681         if (keylen != AES_KEYSIZE_256 &&
1682             keylen != AES_KEYSIZE_192 &&
1683             keylen != AES_KEYSIZE_128) {
1684                 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1685                 return -EINVAL;
1686         }
1687
1688         memcpy(ctx->key, key, keylen);
1689         ctx->keylen = keylen;
1690
1691         return 0;
1692 }
1693
1694 static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm,
1695                                      unsigned int authsize)
1696 {
1697         /* Same as crypto_gcm_authsize() from crypto/gcm.c */
1698         switch (authsize) {
1699         case 4:
1700         case 8:
1701         case 12:
1702         case 13:
1703         case 14:
1704         case 15:
1705         case 16:
1706                 break;
1707         default:
1708                 return -EINVAL;
1709         }
1710
1711         return 0;
1712 }
1713
1714 static int atmel_aes_gcm_encrypt(struct aead_request *req)
1715 {
1716         return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT);
1717 }
1718
1719 static int atmel_aes_gcm_decrypt(struct aead_request *req)
1720 {
1721         return atmel_aes_gcm_crypt(req, 0);
1722 }
1723
1724 static int atmel_aes_gcm_init(struct crypto_aead *tfm)
1725 {
1726         struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm);
1727
1728         crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx));
1729         ctx->base.start = atmel_aes_gcm_start;
1730
1731         return 0;
1732 }
1733
1734 static void atmel_aes_gcm_exit(struct crypto_aead *tfm)
1735 {
1736
1737 }
1738
1739 static struct aead_alg aes_gcm_alg = {
1740         .setkey         = atmel_aes_gcm_setkey,
1741         .setauthsize    = atmel_aes_gcm_setauthsize,
1742         .encrypt        = atmel_aes_gcm_encrypt,
1743         .decrypt        = atmel_aes_gcm_decrypt,
1744         .init           = atmel_aes_gcm_init,
1745         .exit           = atmel_aes_gcm_exit,
1746         .ivsize         = 12,
1747         .maxauthsize    = AES_BLOCK_SIZE,
1748
1749         .base = {
1750                 .cra_name               = "gcm(aes)",
1751                 .cra_driver_name        = "atmel-gcm-aes",
1752                 .cra_priority           = ATMEL_AES_PRIORITY,
1753                 .cra_flags              = CRYPTO_ALG_ASYNC,
1754                 .cra_blocksize          = 1,
1755                 .cra_ctxsize            = sizeof(struct atmel_aes_gcm_ctx),
1756                 .cra_alignmask          = 0xf,
1757                 .cra_module             = THIS_MODULE,
1758         },
1759 };
1760
1761
1762 /* Probe functions */
1763
1764 static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
1765 {
1766         dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER);
1767         dd->buflen = ATMEL_AES_BUFFER_SIZE;
1768         dd->buflen &= ~(AES_BLOCK_SIZE - 1);
1769
1770         if (!dd->buf) {
1771                 dev_err(dd->dev, "unable to alloc pages.\n");
1772                 return -ENOMEM;
1773         }
1774
1775         return 0;
1776 }
1777
1778 static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd)
1779 {
1780         free_page((unsigned long)dd->buf);
1781 }
1782
1783 static bool atmel_aes_filter(struct dma_chan *chan, void *slave)
1784 {
1785         struct at_dma_slave     *sl = slave;
1786
1787         if (sl && sl->dma_dev == chan->device->dev) {
1788                 chan->private = sl;
1789                 return true;
1790         } else {
1791                 return false;
1792         }
1793 }
1794
1795 static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
1796                               struct crypto_platform_data *pdata)
1797 {
1798         struct at_dma_slave *slave;
1799         int err = -ENOMEM;
1800         dma_cap_mask_t mask;
1801
1802         dma_cap_zero(mask);
1803         dma_cap_set(DMA_SLAVE, mask);
1804
1805         /* Try to grab 2 DMA channels */
1806         slave = &pdata->dma_slave->rxdata;
1807         dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
1808                                                         slave, dd->dev, "tx");
1809         if (!dd->src.chan)
1810                 goto err_dma_in;
1811
1812         slave = &pdata->dma_slave->txdata;
1813         dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
1814                                                         slave, dd->dev, "rx");
1815         if (!dd->dst.chan)
1816                 goto err_dma_out;
1817
1818         return 0;
1819
1820 err_dma_out:
1821         dma_release_channel(dd->src.chan);
1822 err_dma_in:
1823         dev_warn(dd->dev, "no DMA channel available\n");
1824         return err;
1825 }
1826
1827 static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd)
1828 {
1829         dma_release_channel(dd->dst.chan);
1830         dma_release_channel(dd->src.chan);
1831 }
1832
1833 static void atmel_aes_queue_task(unsigned long data)
1834 {
1835         struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
1836
1837         atmel_aes_handle_queue(dd, NULL);
1838 }
1839
1840 static void atmel_aes_done_task(unsigned long data)
1841 {
1842         struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
1843
1844         dd->is_async = true;
1845         (void)dd->resume(dd);
1846 }
1847
1848 static irqreturn_t atmel_aes_irq(int irq, void *dev_id)
1849 {
1850         struct atmel_aes_dev *aes_dd = dev_id;
1851         u32 reg;
1852
1853         reg = atmel_aes_read(aes_dd, AES_ISR);
1854         if (reg & atmel_aes_read(aes_dd, AES_IMR)) {
1855                 atmel_aes_write(aes_dd, AES_IDR, reg);
1856                 if (AES_FLAGS_BUSY & aes_dd->flags)
1857                         tasklet_schedule(&aes_dd->done_task);
1858                 else
1859                         dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n");
1860                 return IRQ_HANDLED;
1861         }
1862
1863         return IRQ_NONE;
1864 }
1865
1866 static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
1867 {
1868         int i;
1869
1870         if (dd->caps.has_gcm)
1871                 crypto_unregister_aead(&aes_gcm_alg);
1872
1873         if (dd->caps.has_cfb64)
1874                 crypto_unregister_alg(&aes_cfb64_alg);
1875
1876         for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
1877                 crypto_unregister_alg(&aes_algs[i]);
1878 }
1879
1880 static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
1881 {
1882         int err, i, j;
1883
1884         for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
1885                 err = crypto_register_alg(&aes_algs[i]);
1886                 if (err)
1887                         goto err_aes_algs;
1888         }
1889
1890         if (dd->caps.has_cfb64) {
1891                 err = crypto_register_alg(&aes_cfb64_alg);
1892                 if (err)
1893                         goto err_aes_cfb64_alg;
1894         }
1895
1896         if (dd->caps.has_gcm) {
1897                 err = crypto_register_aead(&aes_gcm_alg);
1898                 if (err)
1899                         goto err_aes_gcm_alg;
1900         }
1901
1902         return 0;
1903
1904 err_aes_gcm_alg:
1905         crypto_unregister_alg(&aes_cfb64_alg);
1906 err_aes_cfb64_alg:
1907         i = ARRAY_SIZE(aes_algs);
1908 err_aes_algs:
1909         for (j = 0; j < i; j++)
1910                 crypto_unregister_alg(&aes_algs[j]);
1911
1912         return err;
1913 }
1914
1915 static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
1916 {
1917         dd->caps.has_dualbuff = 0;
1918         dd->caps.has_cfb64 = 0;
1919         dd->caps.has_gcm = 0;
1920         dd->caps.max_burst_size = 1;
1921
1922         /* keep only major version number */
1923         switch (dd->hw_version & 0xff0) {
1924         case 0x500:
1925                 dd->caps.has_dualbuff = 1;
1926                 dd->caps.has_cfb64 = 1;
1927                 dd->caps.has_gcm = 1;
1928                 dd->caps.max_burst_size = 4;
1929                 break;
1930         case 0x200:
1931                 dd->caps.has_dualbuff = 1;
1932                 dd->caps.has_cfb64 = 1;
1933                 dd->caps.has_gcm = 1;
1934                 dd->caps.max_burst_size = 4;
1935                 break;
1936         case 0x130:
1937                 dd->caps.has_dualbuff = 1;
1938                 dd->caps.has_cfb64 = 1;
1939                 dd->caps.max_burst_size = 4;
1940                 break;
1941         case 0x120:
1942                 break;
1943         default:
1944                 dev_warn(dd->dev,
1945                                 "Unmanaged aes version, set minimum capabilities\n");
1946                 break;
1947         }
1948 }
1949
1950 #if defined(CONFIG_OF)
1951 static const struct of_device_id atmel_aes_dt_ids[] = {
1952         { .compatible = "atmel,at91sam9g46-aes" },
1953         { /* sentinel */ }
1954 };
1955 MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
1956
1957 static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
1958 {
1959         struct device_node *np = pdev->dev.of_node;
1960         struct crypto_platform_data *pdata;
1961
1962         if (!np) {
1963                 dev_err(&pdev->dev, "device node not found\n");
1964                 return ERR_PTR(-EINVAL);
1965         }
1966
1967         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1968         if (!pdata) {
1969                 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1970                 return ERR_PTR(-ENOMEM);
1971         }
1972
1973         pdata->dma_slave = devm_kzalloc(&pdev->dev,
1974                                         sizeof(*(pdata->dma_slave)),
1975                                         GFP_KERNEL);
1976         if (!pdata->dma_slave) {
1977                 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
1978                 devm_kfree(&pdev->dev, pdata);
1979                 return ERR_PTR(-ENOMEM);
1980         }
1981
1982         return pdata;
1983 }
1984 #else
1985 static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
1986 {
1987         return ERR_PTR(-EINVAL);
1988 }
1989 #endif
1990
1991 static int atmel_aes_probe(struct platform_device *pdev)
1992 {
1993         struct atmel_aes_dev *aes_dd;
1994         struct crypto_platform_data *pdata;
1995         struct device *dev = &pdev->dev;
1996         struct resource *aes_res;
1997         int err;
1998
1999         pdata = pdev->dev.platform_data;
2000         if (!pdata) {
2001                 pdata = atmel_aes_of_init(pdev);
2002                 if (IS_ERR(pdata)) {
2003                         err = PTR_ERR(pdata);
2004                         goto aes_dd_err;
2005                 }
2006         }
2007
2008         if (!pdata->dma_slave) {
2009                 err = -ENXIO;
2010                 goto aes_dd_err;
2011         }
2012
2013         aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL);
2014         if (aes_dd == NULL) {
2015                 dev_err(dev, "unable to alloc data struct.\n");
2016                 err = -ENOMEM;
2017                 goto aes_dd_err;
2018         }
2019
2020         aes_dd->dev = dev;
2021
2022         platform_set_drvdata(pdev, aes_dd);
2023
2024         INIT_LIST_HEAD(&aes_dd->list);
2025         spin_lock_init(&aes_dd->lock);
2026
2027         tasklet_init(&aes_dd->done_task, atmel_aes_done_task,
2028                                         (unsigned long)aes_dd);
2029         tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task,
2030                                         (unsigned long)aes_dd);
2031
2032         crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH);
2033
2034         aes_dd->irq = -1;
2035
2036         /* Get the base address */
2037         aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2038         if (!aes_res) {
2039                 dev_err(dev, "no MEM resource info\n");
2040                 err = -ENODEV;
2041                 goto res_err;
2042         }
2043         aes_dd->phys_base = aes_res->start;
2044
2045         /* Get the IRQ */
2046         aes_dd->irq = platform_get_irq(pdev,  0);
2047         if (aes_dd->irq < 0) {
2048                 dev_err(dev, "no IRQ resource info\n");
2049                 err = aes_dd->irq;
2050                 goto res_err;
2051         }
2052
2053         err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq,
2054                                IRQF_SHARED, "atmel-aes", aes_dd);
2055         if (err) {
2056                 dev_err(dev, "unable to request aes irq.\n");
2057                 goto res_err;
2058         }
2059
2060         /* Initializing the clock */
2061         aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk");
2062         if (IS_ERR(aes_dd->iclk)) {
2063                 dev_err(dev, "clock initialization failed.\n");
2064                 err = PTR_ERR(aes_dd->iclk);
2065                 goto res_err;
2066         }
2067
2068         aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
2069         if (IS_ERR(aes_dd->io_base)) {
2070                 dev_err(dev, "can't ioremap\n");
2071                 err = PTR_ERR(aes_dd->io_base);
2072                 goto res_err;
2073         }
2074
2075         err = clk_prepare(aes_dd->iclk);
2076         if (err)
2077                 goto res_err;
2078
2079         err = atmel_aes_hw_version_init(aes_dd);
2080         if (err)
2081                 goto iclk_unprepare;
2082
2083         atmel_aes_get_cap(aes_dd);
2084
2085         err = atmel_aes_buff_init(aes_dd);
2086         if (err)
2087                 goto err_aes_buff;
2088
2089         err = atmel_aes_dma_init(aes_dd, pdata);
2090         if (err)
2091                 goto err_aes_dma;
2092
2093         spin_lock(&atmel_aes.lock);
2094         list_add_tail(&aes_dd->list, &atmel_aes.dev_list);
2095         spin_unlock(&atmel_aes.lock);
2096
2097         err = atmel_aes_register_algs(aes_dd);
2098         if (err)
2099                 goto err_algs;
2100
2101         dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
2102                         dma_chan_name(aes_dd->src.chan),
2103                         dma_chan_name(aes_dd->dst.chan));
2104
2105         return 0;
2106
2107 err_algs:
2108         spin_lock(&atmel_aes.lock);
2109         list_del(&aes_dd->list);
2110         spin_unlock(&atmel_aes.lock);
2111         atmel_aes_dma_cleanup(aes_dd);
2112 err_aes_dma:
2113         atmel_aes_buff_cleanup(aes_dd);
2114 err_aes_buff:
2115 iclk_unprepare:
2116         clk_unprepare(aes_dd->iclk);
2117 res_err:
2118         tasklet_kill(&aes_dd->done_task);
2119         tasklet_kill(&aes_dd->queue_task);
2120 aes_dd_err:
2121         dev_err(dev, "initialization failed.\n");
2122
2123         return err;
2124 }
2125
2126 static int atmel_aes_remove(struct platform_device *pdev)
2127 {
2128         static struct atmel_aes_dev *aes_dd;
2129
2130         aes_dd = platform_get_drvdata(pdev);
2131         if (!aes_dd)
2132                 return -ENODEV;
2133         spin_lock(&atmel_aes.lock);
2134         list_del(&aes_dd->list);
2135         spin_unlock(&atmel_aes.lock);
2136
2137         atmel_aes_unregister_algs(aes_dd);
2138
2139         tasklet_kill(&aes_dd->done_task);
2140         tasklet_kill(&aes_dd->queue_task);
2141
2142         atmel_aes_dma_cleanup(aes_dd);
2143         atmel_aes_buff_cleanup(aes_dd);
2144
2145         clk_unprepare(aes_dd->iclk);
2146
2147         return 0;
2148 }
2149
2150 static struct platform_driver atmel_aes_driver = {
2151         .probe          = atmel_aes_probe,
2152         .remove         = atmel_aes_remove,
2153         .driver         = {
2154                 .name   = "atmel_aes",
2155                 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
2156         },
2157 };
2158
2159 module_platform_driver(atmel_aes_driver);
2160
2161 MODULE_DESCRIPTION("Atmel AES hw acceleration support.");
2162 MODULE_LICENSE("GPL v2");
2163 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");