drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * Some ideas are from old omap-sha1-md5.c driver.
  15  */
  16
  17 #define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19 #include <linux/err.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/delay.h>
  38 #include <linux/crypto.h>
  39 #include <linux/cryptohash.h>
  40 #include <crypto/scatterwalk.h>
  41 #include <crypto/algapi.h>
  42 #include <crypto/sha.h>
  43 #include <crypto/hash.h>
  44 #include <crypto/hmac.h>
  45 #include <crypto/internal/hash.h>
  46
  47 #define MD5_DIGEST_SIZE                 16
  48
  49 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  50 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  51 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  52
  53 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  54
  55 #define SHA_REG_CTRL                    0x18
  56 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  57 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  58 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  59 #define SHA_REG_CTRL_ALGO               (1 << 2)
  60 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  61 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  62
  63 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  64
  65 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  66 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  67 #define SHA_REG_MASK_IT_EN              (1 << 2)
  68 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  69 #define SHA_REG_AUTOIDLE                (1 << 0)
  70
  71 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  72 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  73
  74 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  75 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  76 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  77 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  78 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  79
  80 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  81 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  83 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  84 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  85 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  86 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  87
  88 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  89
  90 #define SHA_REG_IRQSTATUS               0x118
  91 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  93 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  95
  96 #define SHA_REG_IRQENA                  0x11C
  97 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  98 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  99 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
 100 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 101
 102 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 103
 104 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 105
 106 /* mostly device flags */
 107 #define FLAGS_BUSY              0
 108 #define FLAGS_FINAL             1
 109 #define FLAGS_DMA_ACTIVE        2
 110 #define FLAGS_OUTPUT_READY      3
 111 #define FLAGS_INIT              4
 112 #define FLAGS_CPU               5
 113 #define FLAGS_DMA_READY         6
 114 #define FLAGS_AUTO_XOR          7
 115 #define FLAGS_BE32_SHA1         8
 116 #define FLAGS_SGS_COPIED        9
 117 #define FLAGS_SGS_ALLOCED       10
 118 /* context flags */
 119 #define FLAGS_FINUP             16
 120
 121 #define FLAGS_MODE_SHIFT        18
 122 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 127 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 128 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 129
 130 #define FLAGS_HMAC              21
 131 #define FLAGS_ERROR             22
 132
 133 #define OP_UPDATE               1
 134 #define OP_FINAL                2
 135
 136 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 137 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 138
 139 #define BUFLEN                  SHA512_BLOCK_SIZE
 140 #define OMAP_SHA_DMA_THRESHOLD  256
 141
 142 struct omap_sham_dev;
 143
 144 struct omap_sham_reqctx {
 145         struct omap_sham_dev    *dd;
 146         unsigned long           flags;
 147         unsigned long           op;
 148
 149         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 150         size_t                  digcnt;
 151         size_t                  bufcnt;
 152         size_t                  buflen;
 153
 154         /* walk state */
 155         struct scatterlist      *sg;
 156         struct scatterlist      sgl[2];
 157         int                     offset; /* offset in current sg */
 158         int                     sg_len;
 159         unsigned int            total;  /* total request */
 160
 161         u8                      buffer[0] OMAP_ALIGNED;
 162 };
 163
 164 struct omap_sham_hmac_ctx {
 165         struct crypto_shash     *shash;
 166         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 167         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 168 };
 169
 170 struct omap_sham_ctx {
 171         unsigned long           flags;
 172
 173         /* fallback stuff */
 174         struct crypto_shash     *fallback;
 175
 176         struct omap_sham_hmac_ctx base[0];
 177 };
 178
 179 #define OMAP_SHAM_QUEUE_LENGTH  10
 180
 181 struct omap_sham_algs_info {
 182         struct ahash_alg        *algs_list;
 183         unsigned int            size;
 184         unsigned int            registered;
 185 };
 186
 187 struct omap_sham_pdata {
 188         struct omap_sham_algs_info      *algs_info;
 189         unsigned int    algs_info_size;
 190         unsigned long   flags;
 191         int             digest_size;
 192
 193         void            (*copy_hash)(struct ahash_request *req, int out);
 194         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 195                                       int final, int dma);
 196         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 197         int             (*poll_irq)(struct omap_sham_dev *dd);
 198         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 199
 200         u32             odigest_ofs;
 201         u32             idigest_ofs;
 202         u32             din_ofs;
 203         u32             digcnt_ofs;
 204         u32             rev_ofs;
 205         u32             mask_ofs;
 206         u32             sysstatus_ofs;
 207         u32             mode_ofs;
 208         u32             length_ofs;
 209
 210         u32             major_mask;
 211         u32             major_shift;
 212         u32             minor_mask;
 213         u32             minor_shift;
 214 };
 215
 216 struct omap_sham_dev {
 217         struct list_head        list;
 218         unsigned long           phys_base;
 219         struct device           *dev;
 220         void __iomem            *io_base;
 221         int                     irq;
 222         spinlock_t              lock;
 223         int                     err;
 224         struct dma_chan         *dma_lch;
 225         struct tasklet_struct   done_task;
 226         u8                      polling_mode;
 227         u8                      xmit_buf[BUFLEN] OMAP_ALIGNED;
 228
 229         unsigned long           flags;
 230         int                     fallback_sz;
 231         struct crypto_queue     queue;
 232         struct ahash_request    *req;
 233
 234         const struct omap_sham_pdata    *pdata;
 235 };
 236
 237 struct omap_sham_drv {
 238         struct list_head        dev_list;
 239         spinlock_t              lock;
 240         unsigned long           flags;
 241 };
 242
 243 static struct omap_sham_drv sham = {
 244         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 245         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 246 };
 247
 248 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 249 {
 250         return __raw_readl(dd->io_base + offset);
 251 }
 252
 253 static inline void omap_sham_write(struct omap_sham_dev *dd,
 254                                         u32 offset, u32 value)
 255 {
 256         __raw_writel(value, dd->io_base + offset);
 257 }
 258
 259 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 260                                         u32 value, u32 mask)
 261 {
 262         u32 val;
 263
 264         val = omap_sham_read(dd, address);
 265         val &= ~mask;
 266         val |= value;
 267         omap_sham_write(dd, address, val);
 268 }
 269
 270 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 271 {
 272         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 273
 274         while (!(omap_sham_read(dd, offset) & bit)) {
 275                 if (time_is_before_jiffies(timeout))
 276                         return -ETIMEDOUT;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 283 {
 284         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 285         struct omap_sham_dev *dd = ctx->dd;
 286         u32 *hash = (u32 *)ctx->digest;
 287         int i;
 288
 289         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 290                 if (out)
 291                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 292                 else
 293                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 294         }
 295 }
 296
 297 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 298 {
 299         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 300         struct omap_sham_dev *dd = ctx->dd;
 301         int i;
 302
 303         if (ctx->flags & BIT(FLAGS_HMAC)) {
 304                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 305                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 306                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 307                 u32 *opad = (u32 *)bctx->opad;
 308
 309                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 310                         if (out)
 311                                 opad[i] = omap_sham_read(dd,
 312                                                 SHA_REG_ODIGEST(dd, i));
 313                         else
 314                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 315                                                 opad[i]);
 316                 }
 317         }
 318
 319         omap_sham_copy_hash_omap2(req, out);
 320 }
 321
 322 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 323 {
 324         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 325         u32 *in = (u32 *)ctx->digest;
 326         u32 *hash = (u32 *)req->result;
 327         int i, d, big_endian = 0;
 328
 329         if (!hash)
 330                 return;
 331
 332         switch (ctx->flags & FLAGS_MODE_MASK) {
 333         case FLAGS_MODE_MD5:
 334                 d = MD5_DIGEST_SIZE / sizeof(u32);
 335                 break;
 336         case FLAGS_MODE_SHA1:
 337                 /* OMAP2 SHA1 is big endian */
 338                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 339                         big_endian = 1;
 340                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 341                 break;
 342         case FLAGS_MODE_SHA224:
 343                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 344                 break;
 345         case FLAGS_MODE_SHA256:
 346                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 347                 break;
 348         case FLAGS_MODE_SHA384:
 349                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 350                 break;
 351         case FLAGS_MODE_SHA512:
 352                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 353                 break;
 354         default:
 355                 d = 0;
 356         }
 357
 358         if (big_endian)
 359                 for (i = 0; i < d; i++)
 360                         hash[i] = be32_to_cpu(in[i]);
 361         else
 362                 for (i = 0; i < d; i++)
 363                         hash[i] = le32_to_cpu(in[i]);
 364 }
 365
 366 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 367 {
 368         int err;
 369
 370         err = pm_runtime_get_sync(dd->dev);
 371         if (err < 0) {
 372                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 373                 return err;
 374         }
 375
 376         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 377                 set_bit(FLAGS_INIT, &dd->flags);
 378                 dd->err = 0;
 379         }
 380
 381         return 0;
 382 }
 383
 384 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 385                                  int final, int dma)
 386 {
 387         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 388         u32 val = length << 5, mask;
 389
 390         if (likely(ctx->digcnt))
 391                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 392
 393         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 394                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 395                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 396         /*
 397          * Setting ALGO_CONST only for the first iteration
 398          * and CLOSE_HASH only for the last one.
 399          */
 400         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 401                 val |= SHA_REG_CTRL_ALGO;
 402         if (!ctx->digcnt)
 403                 val |= SHA_REG_CTRL_ALGO_CONST;
 404         if (final)
 405                 val |= SHA_REG_CTRL_CLOSE_HASH;
 406
 407         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 408                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 409
 410         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 411 }
 412
 413 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 414 {
 415 }
 416
 417 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 418 {
 419         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 420 }
 421
 422 static int get_block_size(struct omap_sham_reqctx *ctx)
 423 {
 424         int d;
 425
 426         switch (ctx->flags & FLAGS_MODE_MASK) {
 427         case FLAGS_MODE_MD5:
 428         case FLAGS_MODE_SHA1:
 429                 d = SHA1_BLOCK_SIZE;
 430                 break;
 431         case FLAGS_MODE_SHA224:
 432         case FLAGS_MODE_SHA256:
 433                 d = SHA256_BLOCK_SIZE;
 434                 break;
 435         case FLAGS_MODE_SHA384:
 436         case FLAGS_MODE_SHA512:
 437                 d = SHA512_BLOCK_SIZE;
 438                 break;
 439         default:
 440                 d = 0;
 441         }
 442
 443         return d;
 444 }
 445
 446 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 447                                     u32 *value, int count)
 448 {
 449         for (; count--; value++, offset += 4)
 450                 omap_sham_write(dd, offset, *value);
 451 }
 452
 453 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 454                                  int final, int dma)
 455 {
 456         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 457         u32 val, mask;
 458
 459         if (likely(ctx->digcnt))
 460                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 461
 462         /*
 463          * Setting ALGO_CONST only for the first iteration and
 464          * CLOSE_HASH only for the last one. Note that flags mode bits
 465          * correspond to algorithm encoding in mode register.
 466          */
 467         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 468         if (!ctx->digcnt) {
 469                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 470                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 471                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 472                 int bs, nr_dr;
 473
 474                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 475
 476                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 477                         bs = get_block_size(ctx);
 478                         nr_dr = bs / (2 * sizeof(u32));
 479                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 480                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 481                                           (u32 *)bctx->ipad, nr_dr);
 482                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 483                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 484                         ctx->digcnt += bs;
 485                 }
 486         }
 487
 488         if (final) {
 489                 val |= SHA_REG_MODE_CLOSE_HASH;
 490
 491                 if (ctx->flags & BIT(FLAGS_HMAC))
 492                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 493         }
 494
 495         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 496                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 497                SHA_REG_MODE_HMAC_KEY_PROC;
 498
 499         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 500         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 501         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 502         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 503                              SHA_REG_MASK_IT_EN |
 504                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 505                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 506 }
 507
 508 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 509 {
 510         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 511 }
 512
 513 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 514 {
 515         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 516                               SHA_REG_IRQSTATUS_INPUT_RDY);
 517 }
 518
 519 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 520                               int final)
 521 {
 522         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 523         int count, len32, bs32, offset = 0;
 524         const u32 *buffer;
 525         int mlen;
 526         struct sg_mapping_iter mi;
 527
 528         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 529                                                 ctx->digcnt, length, final);
 530
 531         dd->pdata->write_ctrl(dd, length, final, 0);
 532         dd->pdata->trigger(dd, length);
 533
 534         /* should be non-zero before next lines to disable clocks later */
 535         ctx->digcnt += length;
 536         ctx->total -= length;
 537
 538         if (final)
 539                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 540
 541         set_bit(FLAGS_CPU, &dd->flags);
 542
 543         len32 = DIV_ROUND_UP(length, sizeof(u32));
 544         bs32 = get_block_size(ctx) / sizeof(u32);
 545
 546         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 547                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 548
 549         mlen = 0;
 550
 551         while (len32) {
 552                 if (dd->pdata->poll_irq(dd))
 553                         return -ETIMEDOUT;
 554
 555                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 556                         if (!mlen) {
 557                                 sg_miter_next(&mi);
 558                                 mlen = mi.length;
 559                                 if (!mlen) {
 560                                         pr_err("sg miter failure.\n");
 561                                         return -EINVAL;
 562                                 }
 563                                 offset = 0;
 564                                 buffer = mi.addr;
 565                         }
 566                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 567                                         buffer[offset]);
 568                         mlen -= 4;
 569                 }
 570                 len32 -= min(len32, bs32);
 571         }
 572
 573         sg_miter_stop(&mi);
 574
 575         return -EINPROGRESS;
 576 }
 577
 578 static void omap_sham_dma_callback(void *param)
 579 {
 580         struct omap_sham_dev *dd = param;
 581
 582         set_bit(FLAGS_DMA_READY, &dd->flags);
 583         tasklet_schedule(&dd->done_task);
 584 }
 585
 586 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 587                               int final)
 588 {
 589         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 590         struct dma_async_tx_descriptor *tx;
 591         struct dma_slave_config cfg;
 592         int ret;
 593
 594         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 595                                                 ctx->digcnt, length, final);
 596
 597         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 598                 dev_err(dd->dev, "dma_map_sg error\n");
 599                 return -EINVAL;
 600         }
 601
 602         memset(&cfg, 0, sizeof(cfg));
 603
 604         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 605         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 606         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 607
 608         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 609         if (ret) {
 610                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 611                 return ret;
 612         }
 613
 614         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 615                                      DMA_MEM_TO_DEV,
 616                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 617
 618         if (!tx) {
 619                 dev_err(dd->dev, "prep_slave_sg failed\n");
 620                 return -EINVAL;
 621         }
 622
 623         tx->callback = omap_sham_dma_callback;
 624         tx->callback_param = dd;
 625
 626         dd->pdata->write_ctrl(dd, length, final, 1);
 627
 628         ctx->digcnt += length;
 629         ctx->total -= length;
 630
 631         if (final)
 632                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 633
 634         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 635
 636         dmaengine_submit(tx);
 637         dma_async_issue_pending(dd->dma_lch);
 638
 639         dd->pdata->trigger(dd, length);
 640
 641         return -EINPROGRESS;
 642 }
 643
 644 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 645                                    struct scatterlist *sg, int bs, int new_len)
 646 {
 647         int n = sg_nents(sg);
 648         struct scatterlist *tmp;
 649         int offset = ctx->offset;
 650
 651         if (ctx->bufcnt)
 652                 n++;
 653
 654         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 655         if (!ctx->sg)
 656                 return -ENOMEM;
 657
 658         sg_init_table(ctx->sg, n);
 659
 660         tmp = ctx->sg;
 661
 662         ctx->sg_len = 0;
 663
 664         if (ctx->bufcnt) {
 665                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 666                 tmp = sg_next(tmp);
 667                 ctx->sg_len++;
 668         }
 669
 670         while (sg && new_len) {
 671                 int len = sg->length - offset;
 672
 673                 if (offset) {
 674                         offset -= sg->length;
 675                         if (offset < 0)
 676                                 offset = 0;
 677                 }
 678
 679                 if (new_len < len)
 680                         len = new_len;
 681
 682                 if (len > 0) {
 683                         new_len -= len;
 684                         sg_set_page(tmp, sg_page(sg), len, sg->offset);
 685                         if (new_len <= 0)
 686                                 sg_mark_end(tmp);
 687                         tmp = sg_next(tmp);
 688                         ctx->sg_len++;
 689                 }
 690
 691                 sg = sg_next(sg);
 692         }
 693
 694         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 695
 696         ctx->bufcnt = 0;
 697
 698         return 0;
 699 }
 700
 701 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 702                               struct scatterlist *sg, int bs, int new_len)
 703 {
 704         int pages;
 705         void *buf;
 706         int len;
 707
 708         len = new_len + ctx->bufcnt;
 709
 710         pages = get_order(ctx->total);
 711
 712         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 713         if (!buf) {
 714                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 715                 return -ENOMEM;
 716         }
 717
 718         if (ctx->bufcnt)
 719                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 720
 721         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 722                                  ctx->total - ctx->bufcnt, 0);
 723         sg_init_table(ctx->sgl, 1);
 724         sg_set_buf(ctx->sgl, buf, len);
 725         ctx->sg = ctx->sgl;
 726         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 727         ctx->sg_len = 1;
 728         ctx->bufcnt = 0;
 729         ctx->offset = 0;
 730
 731         return 0;
 732 }
 733
 734 static int omap_sham_align_sgs(struct scatterlist *sg,
 735                                int nbytes, int bs, bool final,
 736                                struct omap_sham_reqctx *rctx)
 737 {
 738         int n = 0;
 739         bool aligned = true;
 740         bool list_ok = true;
 741         struct scatterlist *sg_tmp = sg;
 742         int new_len;
 743         int offset = rctx->offset;
 744
 745         if (!sg || !sg->length || !nbytes)
 746                 return 0;
 747
 748         new_len = nbytes;
 749
 750         if (offset)
 751                 list_ok = false;
 752
 753         if (final)
 754                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 755         else
 756                 new_len = (new_len - 1) / bs * bs;
 757
 758         if (nbytes != new_len)
 759                 list_ok = false;
 760
 761         while (nbytes > 0 && sg_tmp) {
 762                 n++;
 763
 764 #ifdef CONFIG_ZONE_DMA
 765                 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
 766                         aligned = false;
 767                         break;
 768                 }
 769 #endif
 770
 771                 if (offset < sg_tmp->length) {
 772                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 773                                 aligned = false;
 774                                 break;
 775                         }
 776
 777                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 778                                 aligned = false;
 779                                 break;
 780                         }
 781                 }
 782
 783                 if (offset) {
 784                         offset -= sg_tmp->length;
 785                         if (offset < 0) {
 786                                 nbytes += offset;
 787                                 offset = 0;
 788                         }
 789                 } else {
 790                         nbytes -= sg_tmp->length;
 791                 }
 792
 793                 sg_tmp = sg_next(sg_tmp);
 794
 795                 if (nbytes < 0) {
 796                         list_ok = false;
 797                         break;
 798                 }
 799         }
 800
 801         if (!aligned)
 802                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 803         else if (!list_ok)
 804                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 805
 806         rctx->sg_len = n;
 807         rctx->sg = sg;
 808
 809         return 0;
 810 }
 811
 812 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 813 {
 814         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 815         int bs;
 816         int ret;
 817         int nbytes;
 818         bool final = rctx->flags & BIT(FLAGS_FINUP);
 819         int xmit_len, hash_later;
 820
 821         bs = get_block_size(rctx);
 822
 823         if (update)
 824                 nbytes = req->nbytes;
 825         else
 826                 nbytes = 0;
 827
 828         rctx->total = nbytes + rctx->bufcnt;
 829
 830         if (!rctx->total)
 831                 return 0;
 832
 833         if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 834                 int len = bs - rctx->bufcnt % bs;
 835
 836                 if (len > nbytes)
 837                         len = nbytes;
 838                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 839                                          0, len, 0);
 840                 rctx->bufcnt += len;
 841                 nbytes -= len;
 842                 rctx->offset = len;
 843         }
 844
 845         if (rctx->bufcnt)
 846                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 847
 848         ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 849         if (ret)
 850                 return ret;
 851
 852         xmit_len = rctx->total;
 853
 854         if (!IS_ALIGNED(xmit_len, bs)) {
 855                 if (final)
 856                         xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
 857                 else
 858                         xmit_len = xmit_len / bs * bs;
 859         } else if (!final) {
 860                 xmit_len -= bs;
 861         }
 862
 863         hash_later = rctx->total - xmit_len;
 864         if (hash_later < 0)
 865                 hash_later = 0;
 866
 867         if (rctx->bufcnt && nbytes) {
 868                 /* have data from previous operation and current */
 869                 sg_init_table(rctx->sgl, 2);
 870                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 871
 872                 sg_chain(rctx->sgl, 2, req->src);
 873
 874                 rctx->sg = rctx->sgl;
 875
 876                 rctx->sg_len++;
 877         } else if (rctx->bufcnt) {
 878                 /* have buffered data only */
 879                 sg_init_table(rctx->sgl, 1);
 880                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
 881
 882                 rctx->sg = rctx->sgl;
 883
 884                 rctx->sg_len = 1;
 885         }
 886
 887         if (hash_later) {
 888                 int offset = 0;
 889
 890                 if (hash_later > req->nbytes) {
 891                         memcpy(rctx->buffer, rctx->buffer + xmit_len,
 892                                hash_later - req->nbytes);
 893                         offset = hash_later - req->nbytes;
 894                 }
 895
 896                 if (req->nbytes) {
 897                         scatterwalk_map_and_copy(rctx->buffer + offset,
 898                                                  req->src,
 899                                                  offset + req->nbytes -
 900                                                  hash_later, hash_later, 0);
 901                 }
 902
 903                 rctx->bufcnt = hash_later;
 904         } else {
 905                 rctx->bufcnt = 0;
 906         }
 907
 908         if (!final)
 909                 rctx->total = xmit_len;
 910
 911         return 0;
 912 }
 913
 914 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 915 {
 916         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 917
 918         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 919
 920         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 921
 922         return 0;
 923 }
 924
 925 struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
 926 {
 927         struct omap_sham_dev *dd;
 928
 929         if (ctx->dd)
 930                 return ctx->dd;
 931
 932         spin_lock_bh(&sham.lock);
 933         dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
 934         list_move_tail(&dd->list, &sham.dev_list);
 935         ctx->dd = dd;
 936         spin_unlock_bh(&sham.lock);
 937
 938         return dd;
 939 }
 940
 941 static int omap_sham_init(struct ahash_request *req)
 942 {
 943         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 944         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 945         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 946         struct omap_sham_dev *dd;
 947         int bs = 0;
 948
 949         ctx->dd = NULL;
 950
 951         dd = omap_sham_find_dev(ctx);
 952         if (!dd)
 953                 return -ENODEV;
 954
 955         ctx->flags = 0;
 956
 957         dev_dbg(dd->dev, "init: digest size: %d\n",
 958                 crypto_ahash_digestsize(tfm));
 959
 960         switch (crypto_ahash_digestsize(tfm)) {
 961         case MD5_DIGEST_SIZE:
 962                 ctx->flags |= FLAGS_MODE_MD5;
 963                 bs = SHA1_BLOCK_SIZE;
 964                 break;
 965         case SHA1_DIGEST_SIZE:
 966                 ctx->flags |= FLAGS_MODE_SHA1;
 967                 bs = SHA1_BLOCK_SIZE;
 968                 break;
 969         case SHA224_DIGEST_SIZE:
 970                 ctx->flags |= FLAGS_MODE_SHA224;
 971                 bs = SHA224_BLOCK_SIZE;
 972                 break;
 973         case SHA256_DIGEST_SIZE:
 974                 ctx->flags |= FLAGS_MODE_SHA256;
 975                 bs = SHA256_BLOCK_SIZE;
 976                 break;
 977         case SHA384_DIGEST_SIZE:
 978                 ctx->flags |= FLAGS_MODE_SHA384;
 979                 bs = SHA384_BLOCK_SIZE;
 980                 break;
 981         case SHA512_DIGEST_SIZE:
 982                 ctx->flags |= FLAGS_MODE_SHA512;
 983                 bs = SHA512_BLOCK_SIZE;
 984                 break;
 985         }
 986
 987         ctx->bufcnt = 0;
 988         ctx->digcnt = 0;
 989         ctx->total = 0;
 990         ctx->offset = 0;
 991         ctx->buflen = BUFLEN;
 992
 993         if (tctx->flags & BIT(FLAGS_HMAC)) {
 994                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 995                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 996
 997                         memcpy(ctx->buffer, bctx->ipad, bs);
 998                         ctx->bufcnt = bs;
 999                 }
1000
1001                 ctx->flags |= BIT(FLAGS_HMAC);
1002         }
1003
1004         return 0;
1005
1006 }
1007
1008 static int omap_sham_update_req(struct omap_sham_dev *dd)
1009 {
1010         struct ahash_request *req = dd->req;
1011         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1012         int err;
1013         bool final = ctx->flags & BIT(FLAGS_FINUP);
1014
1015         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1016                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1017
1018         if (ctx->total < get_block_size(ctx) ||
1019             ctx->total < dd->fallback_sz)
1020                 ctx->flags |= BIT(FLAGS_CPU);
1021
1022         if (ctx->flags & BIT(FLAGS_CPU))
1023                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1024         else
1025                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1026
1027         /* wait for dma completion before can take more data */
1028         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1029
1030         return err;
1031 }
1032
1033 static int omap_sham_final_req(struct omap_sham_dev *dd)
1034 {
1035         struct ahash_request *req = dd->req;
1036         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1037         int err = 0, use_dma = 1;
1038
1039         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1040                 /*
1041                  * faster to handle last block with cpu or
1042                  * use cpu when dma is not present.
1043                  */
1044                 use_dma = 0;
1045
1046         if (use_dma)
1047                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1048         else
1049                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1050
1051         ctx->bufcnt = 0;
1052
1053         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1054
1055         return err;
1056 }
1057
1058 static int omap_sham_finish_hmac(struct ahash_request *req)
1059 {
1060         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1061         struct omap_sham_hmac_ctx *bctx = tctx->base;
1062         int bs = crypto_shash_blocksize(bctx->shash);
1063         int ds = crypto_shash_digestsize(bctx->shash);
1064         SHASH_DESC_ON_STACK(shash, bctx->shash);
1065
1066         shash->tfm = bctx->shash;
1067         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1068
1069         return crypto_shash_init(shash) ?:
1070                crypto_shash_update(shash, bctx->opad, bs) ?:
1071                crypto_shash_finup(shash, req->result, ds, req->result);
1072 }
1073
1074 static int omap_sham_finish(struct ahash_request *req)
1075 {
1076         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1077         struct omap_sham_dev *dd = ctx->dd;
1078         int err = 0;
1079
1080         if (ctx->digcnt) {
1081                 omap_sham_copy_ready_hash(req);
1082                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1083                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1084                         err = omap_sham_finish_hmac(req);
1085         }
1086
1087         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1088
1089         return err;
1090 }
1091
1092 static void omap_sham_finish_req(struct ahash_request *req, int err)
1093 {
1094         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1095         struct omap_sham_dev *dd = ctx->dd;
1096
1097         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1098                 free_pages((unsigned long)sg_virt(ctx->sg),
1099                            get_order(ctx->sg->length + ctx->bufcnt));
1100
1101         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1102                 kfree(ctx->sg);
1103
1104         ctx->sg = NULL;
1105
1106         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1107
1108         if (!err) {
1109                 dd->pdata->copy_hash(req, 1);
1110                 if (test_bit(FLAGS_FINAL, &dd->flags))
1111                         err = omap_sham_finish(req);
1112         } else {
1113                 ctx->flags |= BIT(FLAGS_ERROR);
1114         }
1115
1116         /* atomic operation is not needed here */
1117         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1118                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1119
1120         pm_runtime_mark_last_busy(dd->dev);
1121         pm_runtime_put_autosuspend(dd->dev);
1122
1123         if (req->base.complete)
1124                 req->base.complete(&req->base, err);
1125 }
1126
1127 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1128                                   struct ahash_request *req)
1129 {
1130         struct crypto_async_request *async_req, *backlog;
1131         struct omap_sham_reqctx *ctx;
1132         unsigned long flags;
1133         int err = 0, ret = 0;
1134
1135 retry:
1136         spin_lock_irqsave(&dd->lock, flags);
1137         if (req)
1138                 ret = ahash_enqueue_request(&dd->queue, req);
1139         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1140                 spin_unlock_irqrestore(&dd->lock, flags);
1141                 return ret;
1142         }
1143         backlog = crypto_get_backlog(&dd->queue);
1144         async_req = crypto_dequeue_request(&dd->queue);
1145         if (async_req)
1146                 set_bit(FLAGS_BUSY, &dd->flags);
1147         spin_unlock_irqrestore(&dd->lock, flags);
1148
1149         if (!async_req)
1150                 return ret;
1151
1152         if (backlog)
1153                 backlog->complete(backlog, -EINPROGRESS);
1154
1155         req = ahash_request_cast(async_req);
1156         dd->req = req;
1157         ctx = ahash_request_ctx(req);
1158
1159         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1160         if (err || !ctx->total)
1161                 goto err1;
1162
1163         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1164                                                 ctx->op, req->nbytes);
1165
1166         err = omap_sham_hw_init(dd);
1167         if (err)
1168                 goto err1;
1169
1170         if (ctx->digcnt)
1171                 /* request has changed - restore hash */
1172                 dd->pdata->copy_hash(req, 0);
1173
1174         if (ctx->op == OP_UPDATE) {
1175                 err = omap_sham_update_req(dd);
1176                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1177                         /* no final() after finup() */
1178                         err = omap_sham_final_req(dd);
1179         } else if (ctx->op == OP_FINAL) {
1180                 err = omap_sham_final_req(dd);
1181         }
1182 err1:
1183         dev_dbg(dd->dev, "exit, err: %d\n", err);
1184
1185         if (err != -EINPROGRESS) {
1186                 /* done_task will not finish it, so do it here */
1187                 omap_sham_finish_req(req, err);
1188                 req = NULL;
1189
1190                 /*
1191                  * Execute next request immediately if there is anything
1192                  * in queue.
1193                  */
1194                 goto retry;
1195         }
1196
1197         return ret;
1198 }
1199
1200 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1201 {
1202         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1203         struct omap_sham_dev *dd = ctx->dd;
1204
1205         ctx->op = op;
1206
1207         return omap_sham_handle_queue(dd, req);
1208 }
1209
1210 static int omap_sham_update(struct ahash_request *req)
1211 {
1212         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1213         struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1214
1215         if (!req->nbytes)
1216                 return 0;
1217
1218         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1219                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1220                                          0, req->nbytes, 0);
1221                 ctx->bufcnt += req->nbytes;
1222                 return 0;
1223         }
1224
1225         if (dd->polling_mode)
1226                 ctx->flags |= BIT(FLAGS_CPU);
1227
1228         return omap_sham_enqueue(req, OP_UPDATE);
1229 }
1230
1231 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1232                                   const u8 *data, unsigned int len, u8 *out)
1233 {
1234         SHASH_DESC_ON_STACK(shash, tfm);
1235
1236         shash->tfm = tfm;
1237         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1238
1239         return crypto_shash_digest(shash, data, len, out);
1240 }
1241
1242 static int omap_sham_final_shash(struct ahash_request *req)
1243 {
1244         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1245         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1246         int offset = 0;
1247
1248         /*
1249          * If we are running HMAC on limited hardware support, skip
1250          * the ipad in the beginning of the buffer if we are going for
1251          * software fallback algorithm.
1252          */
1253         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1254             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1255                 offset = get_block_size(ctx);
1256
1257         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1258                                       ctx->buffer + offset,
1259                                       ctx->bufcnt - offset, req->result);
1260 }
1261
1262 static int omap_sham_final(struct ahash_request *req)
1263 {
1264         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1265
1266         ctx->flags |= BIT(FLAGS_FINUP);
1267
1268         if (ctx->flags & BIT(FLAGS_ERROR))
1269                 return 0; /* uncompleted hash is not needed */
1270
1271         /*
1272          * OMAP HW accel works only with buffers >= 9.
1273          * HMAC is always >= 9 because ipad == block size.
1274          * If buffersize is less than fallback_sz, we use fallback
1275          * SW encoding, as using DMA + HW in this case doesn't provide
1276          * any benefit.
1277          */
1278         if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1279                 return omap_sham_final_shash(req);
1280         else if (ctx->bufcnt)
1281                 return omap_sham_enqueue(req, OP_FINAL);
1282
1283         /* copy ready hash (+ finalize hmac) */
1284         return omap_sham_finish(req);
1285 }
1286
1287 static int omap_sham_finup(struct ahash_request *req)
1288 {
1289         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1290         int err1, err2;
1291
1292         ctx->flags |= BIT(FLAGS_FINUP);
1293
1294         err1 = omap_sham_update(req);
1295         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1296                 return err1;
1297         /*
1298          * final() has to be always called to cleanup resources
1299          * even if udpate() failed, except EINPROGRESS
1300          */
1301         err2 = omap_sham_final(req);
1302
1303         return err1 ?: err2;
1304 }
1305
1306 static int omap_sham_digest(struct ahash_request *req)
1307 {
1308         return omap_sham_init(req) ?: omap_sham_finup(req);
1309 }
1310
1311 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1312                       unsigned int keylen)
1313 {
1314         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1315         struct omap_sham_hmac_ctx *bctx = tctx->base;
1316         int bs = crypto_shash_blocksize(bctx->shash);
1317         int ds = crypto_shash_digestsize(bctx->shash);
1318         int err, i;
1319
1320         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1321         if (err)
1322                 return err;
1323
1324         if (keylen > bs) {
1325                 err = omap_sham_shash_digest(bctx->shash,
1326                                 crypto_shash_get_flags(bctx->shash),
1327                                 key, keylen, bctx->ipad);
1328                 if (err)
1329                         return err;
1330                 keylen = ds;
1331         } else {
1332                 memcpy(bctx->ipad, key, keylen);
1333         }
1334
1335         memset(bctx->ipad + keylen, 0, bs - keylen);
1336
1337         if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1338                 memcpy(bctx->opad, bctx->ipad, bs);
1339
1340                 for (i = 0; i < bs; i++) {
1341                         bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1342                         bctx->opad[i] ^= HMAC_OPAD_VALUE;
1343                 }
1344         }
1345
1346         return err;
1347 }
1348
1349 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1350 {
1351         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1352         const char *alg_name = crypto_tfm_alg_name(tfm);
1353
1354         /* Allocate a fallback and abort if it failed. */
1355         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1356                                             CRYPTO_ALG_NEED_FALLBACK);
1357         if (IS_ERR(tctx->fallback)) {
1358                 pr_err("omap-sham: fallback driver '%s' "
1359                                 "could not be loaded.\n", alg_name);
1360                 return PTR_ERR(tctx->fallback);
1361         }
1362
1363         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1364                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1365
1366         if (alg_base) {
1367                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1368                 tctx->flags |= BIT(FLAGS_HMAC);
1369                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1370                                                 CRYPTO_ALG_NEED_FALLBACK);
1371                 if (IS_ERR(bctx->shash)) {
1372                         pr_err("omap-sham: base driver '%s' "
1373                                         "could not be loaded.\n", alg_base);
1374                         crypto_free_shash(tctx->fallback);
1375                         return PTR_ERR(bctx->shash);
1376                 }
1377
1378         }
1379
1380         return 0;
1381 }
1382
1383 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1384 {
1385         return omap_sham_cra_init_alg(tfm, NULL);
1386 }
1387
1388 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1389 {
1390         return omap_sham_cra_init_alg(tfm, "sha1");
1391 }
1392
1393 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1394 {
1395         return omap_sham_cra_init_alg(tfm, "sha224");
1396 }
1397
1398 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1399 {
1400         return omap_sham_cra_init_alg(tfm, "sha256");
1401 }
1402
1403 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1404 {
1405         return omap_sham_cra_init_alg(tfm, "md5");
1406 }
1407
1408 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1409 {
1410         return omap_sham_cra_init_alg(tfm, "sha384");
1411 }
1412
1413 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1414 {
1415         return omap_sham_cra_init_alg(tfm, "sha512");
1416 }
1417
1418 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1419 {
1420         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1421
1422         crypto_free_shash(tctx->fallback);
1423         tctx->fallback = NULL;
1424
1425         if (tctx->flags & BIT(FLAGS_HMAC)) {
1426                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1427                 crypto_free_shash(bctx->shash);
1428         }
1429 }
1430
1431 static int omap_sham_export(struct ahash_request *req, void *out)
1432 {
1433         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1434
1435         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1436
1437         return 0;
1438 }
1439
1440 static int omap_sham_import(struct ahash_request *req, const void *in)
1441 {
1442         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1443         const struct omap_sham_reqctx *ctx_in = in;
1444
1445         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1446
1447         return 0;
1448 }
1449
1450 static struct ahash_alg algs_sha1_md5[] = {
1451 {
1452         .init           = omap_sham_init,
1453         .update         = omap_sham_update,
1454         .final          = omap_sham_final,
1455         .finup          = omap_sham_finup,
1456         .digest         = omap_sham_digest,
1457         .halg.digestsize        = SHA1_DIGEST_SIZE,
1458         .halg.base      = {
1459                 .cra_name               = "sha1",
1460                 .cra_driver_name        = "omap-sha1",
1461                 .cra_priority           = 400,
1462                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1463                                                 CRYPTO_ALG_ASYNC |
1464                                                 CRYPTO_ALG_NEED_FALLBACK,
1465                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1466                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1467                 .cra_alignmask          = OMAP_ALIGN_MASK,
1468                 .cra_module             = THIS_MODULE,
1469                 .cra_init               = omap_sham_cra_init,
1470                 .cra_exit               = omap_sham_cra_exit,
1471         }
1472 },
1473 {
1474         .init           = omap_sham_init,
1475         .update         = omap_sham_update,
1476         .final          = omap_sham_final,
1477         .finup          = omap_sham_finup,
1478         .digest         = omap_sham_digest,
1479         .halg.digestsize        = MD5_DIGEST_SIZE,
1480         .halg.base      = {
1481                 .cra_name               = "md5",
1482                 .cra_driver_name        = "omap-md5",
1483                 .cra_priority           = 400,
1484                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1485                                                 CRYPTO_ALG_ASYNC |
1486                                                 CRYPTO_ALG_NEED_FALLBACK,
1487                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1488                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1489                 .cra_alignmask          = OMAP_ALIGN_MASK,
1490                 .cra_module             = THIS_MODULE,
1491                 .cra_init               = omap_sham_cra_init,
1492                 .cra_exit               = omap_sham_cra_exit,
1493         }
1494 },
1495 {
1496         .init           = omap_sham_init,
1497         .update         = omap_sham_update,
1498         .final          = omap_sham_final,
1499         .finup          = omap_sham_finup,
1500         .digest         = omap_sham_digest,
1501         .setkey         = omap_sham_setkey,
1502         .halg.digestsize        = SHA1_DIGEST_SIZE,
1503         .halg.base      = {
1504                 .cra_name               = "hmac(sha1)",
1505                 .cra_driver_name        = "omap-hmac-sha1",
1506                 .cra_priority           = 400,
1507                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1508                                                 CRYPTO_ALG_ASYNC |
1509                                                 CRYPTO_ALG_NEED_FALLBACK,
1510                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1511                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1512                                         sizeof(struct omap_sham_hmac_ctx),
1513                 .cra_alignmask          = OMAP_ALIGN_MASK,
1514                 .cra_module             = THIS_MODULE,
1515                 .cra_init               = omap_sham_cra_sha1_init,
1516                 .cra_exit               = omap_sham_cra_exit,
1517         }
1518 },
1519 {
1520         .init           = omap_sham_init,
1521         .update         = omap_sham_update,
1522         .final          = omap_sham_final,
1523         .finup          = omap_sham_finup,
1524         .digest         = omap_sham_digest,
1525         .setkey         = omap_sham_setkey,
1526         .halg.digestsize        = MD5_DIGEST_SIZE,
1527         .halg.base      = {
1528                 .cra_name               = "hmac(md5)",
1529                 .cra_driver_name        = "omap-hmac-md5",
1530                 .cra_priority           = 400,
1531                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1532                                                 CRYPTO_ALG_ASYNC |
1533                                                 CRYPTO_ALG_NEED_FALLBACK,
1534                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1535                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1536                                         sizeof(struct omap_sham_hmac_ctx),
1537                 .cra_alignmask          = OMAP_ALIGN_MASK,
1538                 .cra_module             = THIS_MODULE,
1539                 .cra_init               = omap_sham_cra_md5_init,
1540                 .cra_exit               = omap_sham_cra_exit,
1541         }
1542 }
1543 };
1544
1545 /* OMAP4 has some algs in addition to what OMAP2 has */
1546 static struct ahash_alg algs_sha224_sha256[] = {
1547 {
1548         .init           = omap_sham_init,
1549         .update         = omap_sham_update,
1550         .final          = omap_sham_final,
1551         .finup          = omap_sham_finup,
1552         .digest         = omap_sham_digest,
1553         .halg.digestsize        = SHA224_DIGEST_SIZE,
1554         .halg.base      = {
1555                 .cra_name               = "sha224",
1556                 .cra_driver_name        = "omap-sha224",
1557                 .cra_priority           = 400,
1558                 .cra_flags              = CRYPTO_ALG_ASYNC |
1559                                                 CRYPTO_ALG_NEED_FALLBACK,
1560                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1561                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1562                 .cra_alignmask          = OMAP_ALIGN_MASK,
1563                 .cra_module             = THIS_MODULE,
1564                 .cra_init               = omap_sham_cra_init,
1565                 .cra_exit               = omap_sham_cra_exit,
1566         }
1567 },
1568 {
1569         .init           = omap_sham_init,
1570         .update         = omap_sham_update,
1571         .final          = omap_sham_final,
1572         .finup          = omap_sham_finup,
1573         .digest         = omap_sham_digest,
1574         .halg.digestsize        = SHA256_DIGEST_SIZE,
1575         .halg.base      = {
1576                 .cra_name               = "sha256",
1577                 .cra_driver_name        = "omap-sha256",
1578                 .cra_priority           = 400,
1579                 .cra_flags              = CRYPTO_ALG_ASYNC |
1580                                                 CRYPTO_ALG_NEED_FALLBACK,
1581                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1582                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1583                 .cra_alignmask          = OMAP_ALIGN_MASK,
1584                 .cra_module             = THIS_MODULE,
1585                 .cra_init               = omap_sham_cra_init,
1586                 .cra_exit               = omap_sham_cra_exit,
1587         }
1588 },
1589 {
1590         .init           = omap_sham_init,
1591         .update         = omap_sham_update,
1592         .final          = omap_sham_final,
1593         .finup          = omap_sham_finup,
1594         .digest         = omap_sham_digest,
1595         .setkey         = omap_sham_setkey,
1596         .halg.digestsize        = SHA224_DIGEST_SIZE,
1597         .halg.base      = {
1598                 .cra_name               = "hmac(sha224)",
1599                 .cra_driver_name        = "omap-hmac-sha224",
1600                 .cra_priority           = 400,
1601                 .cra_flags              = CRYPTO_ALG_ASYNC |
1602                                                 CRYPTO_ALG_NEED_FALLBACK,
1603                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1604                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1605                                         sizeof(struct omap_sham_hmac_ctx),
1606                 .cra_alignmask          = OMAP_ALIGN_MASK,
1607                 .cra_module             = THIS_MODULE,
1608                 .cra_init               = omap_sham_cra_sha224_init,
1609                 .cra_exit               = omap_sham_cra_exit,
1610         }
1611 },
1612 {
1613         .init           = omap_sham_init,
1614         .update         = omap_sham_update,
1615         .final          = omap_sham_final,
1616         .finup          = omap_sham_finup,
1617         .digest         = omap_sham_digest,
1618         .setkey         = omap_sham_setkey,
1619         .halg.digestsize        = SHA256_DIGEST_SIZE,
1620         .halg.base      = {
1621                 .cra_name               = "hmac(sha256)",
1622                 .cra_driver_name        = "omap-hmac-sha256",
1623                 .cra_priority           = 400,
1624                 .cra_flags              = CRYPTO_ALG_ASYNC |
1625                                                 CRYPTO_ALG_NEED_FALLBACK,
1626                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1627                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1628                                         sizeof(struct omap_sham_hmac_ctx),
1629                 .cra_alignmask          = OMAP_ALIGN_MASK,
1630                 .cra_module             = THIS_MODULE,
1631                 .cra_init               = omap_sham_cra_sha256_init,
1632                 .cra_exit               = omap_sham_cra_exit,
1633         }
1634 },
1635 };
1636
1637 static struct ahash_alg algs_sha384_sha512[] = {
1638 {
1639         .init           = omap_sham_init,
1640         .update         = omap_sham_update,
1641         .final          = omap_sham_final,
1642         .finup          = omap_sham_finup,
1643         .digest         = omap_sham_digest,
1644         .halg.digestsize        = SHA384_DIGEST_SIZE,
1645         .halg.base      = {
1646                 .cra_name               = "sha384",
1647                 .cra_driver_name        = "omap-sha384",
1648                 .cra_priority           = 400,
1649                 .cra_flags              = CRYPTO_ALG_ASYNC |
1650                                                 CRYPTO_ALG_NEED_FALLBACK,
1651                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1652                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1653                 .cra_alignmask          = OMAP_ALIGN_MASK,
1654                 .cra_module             = THIS_MODULE,
1655                 .cra_init               = omap_sham_cra_init,
1656                 .cra_exit               = omap_sham_cra_exit,
1657         }
1658 },
1659 {
1660         .init           = omap_sham_init,
1661         .update         = omap_sham_update,
1662         .final          = omap_sham_final,
1663         .finup          = omap_sham_finup,
1664         .digest         = omap_sham_digest,
1665         .halg.digestsize        = SHA512_DIGEST_SIZE,
1666         .halg.base      = {
1667                 .cra_name               = "sha512",
1668                 .cra_driver_name        = "omap-sha512",
1669                 .cra_priority           = 400,
1670                 .cra_flags              = CRYPTO_ALG_ASYNC |
1671                                                 CRYPTO_ALG_NEED_FALLBACK,
1672                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1673                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1674                 .cra_alignmask          = OMAP_ALIGN_MASK,
1675                 .cra_module             = THIS_MODULE,
1676                 .cra_init               = omap_sham_cra_init,
1677                 .cra_exit               = omap_sham_cra_exit,
1678         }
1679 },
1680 {
1681         .init           = omap_sham_init,
1682         .update         = omap_sham_update,
1683         .final          = omap_sham_final,
1684         .finup          = omap_sham_finup,
1685         .digest         = omap_sham_digest,
1686         .setkey         = omap_sham_setkey,
1687         .halg.digestsize        = SHA384_DIGEST_SIZE,
1688         .halg.base      = {
1689                 .cra_name               = "hmac(sha384)",
1690                 .cra_driver_name        = "omap-hmac-sha384",
1691                 .cra_priority           = 400,
1692                 .cra_flags              = CRYPTO_ALG_ASYNC |
1693                                                 CRYPTO_ALG_NEED_FALLBACK,
1694                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1695                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1696                                         sizeof(struct omap_sham_hmac_ctx),
1697                 .cra_alignmask          = OMAP_ALIGN_MASK,
1698                 .cra_module             = THIS_MODULE,
1699                 .cra_init               = omap_sham_cra_sha384_init,
1700                 .cra_exit               = omap_sham_cra_exit,
1701         }
1702 },
1703 {
1704         .init           = omap_sham_init,
1705         .update         = omap_sham_update,
1706         .final          = omap_sham_final,
1707         .finup          = omap_sham_finup,
1708         .digest         = omap_sham_digest,
1709         .setkey         = omap_sham_setkey,
1710         .halg.digestsize        = SHA512_DIGEST_SIZE,
1711         .halg.base      = {
1712                 .cra_name               = "hmac(sha512)",
1713                 .cra_driver_name        = "omap-hmac-sha512",
1714                 .cra_priority           = 400,
1715                 .cra_flags              = CRYPTO_ALG_ASYNC |
1716                                                 CRYPTO_ALG_NEED_FALLBACK,
1717                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1718                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1719                                         sizeof(struct omap_sham_hmac_ctx),
1720                 .cra_alignmask          = OMAP_ALIGN_MASK,
1721                 .cra_module             = THIS_MODULE,
1722                 .cra_init               = omap_sham_cra_sha512_init,
1723                 .cra_exit               = omap_sham_cra_exit,
1724         }
1725 },
1726 };
1727
1728 static void omap_sham_done_task(unsigned long data)
1729 {
1730         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1731         int err = 0;
1732
1733         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1734                 omap_sham_handle_queue(dd, NULL);
1735                 return;
1736         }
1737
1738         if (test_bit(FLAGS_CPU, &dd->flags)) {
1739                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1740                         goto finish;
1741         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1742                 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1743                         omap_sham_update_dma_stop(dd);
1744                         if (dd->err) {
1745                                 err = dd->err;
1746                                 goto finish;
1747                         }
1748                 }
1749                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1750                         /* hash or semi-hash ready */
1751                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1752                         goto finish;
1753                 }
1754         }
1755
1756         return;
1757
1758 finish:
1759         dev_dbg(dd->dev, "update done: err: %d\n", err);
1760         /* finish curent request */
1761         omap_sham_finish_req(dd->req, err);
1762
1763         /* If we are not busy, process next req */
1764         if (!test_bit(FLAGS_BUSY, &dd->flags))
1765                 omap_sham_handle_queue(dd, NULL);
1766 }
1767
1768 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1769 {
1770         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1771                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1772         } else {
1773                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1774                 tasklet_schedule(&dd->done_task);
1775         }
1776
1777         return IRQ_HANDLED;
1778 }
1779
1780 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1781 {
1782         struct omap_sham_dev *dd = dev_id;
1783
1784         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1785                 /* final -> allow device to go to power-saving mode */
1786                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1787
1788         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1789                                  SHA_REG_CTRL_OUTPUT_READY);
1790         omap_sham_read(dd, SHA_REG_CTRL);
1791
1792         return omap_sham_irq_common(dd);
1793 }
1794
1795 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1796 {
1797         struct omap_sham_dev *dd = dev_id;
1798
1799         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1800
1801         return omap_sham_irq_common(dd);
1802 }
1803
1804 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1805         {
1806                 .algs_list      = algs_sha1_md5,
1807                 .size           = ARRAY_SIZE(algs_sha1_md5),
1808         },
1809 };
1810
1811 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1812         .algs_info      = omap_sham_algs_info_omap2,
1813         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1814         .flags          = BIT(FLAGS_BE32_SHA1),
1815         .digest_size    = SHA1_DIGEST_SIZE,
1816         .copy_hash      = omap_sham_copy_hash_omap2,
1817         .write_ctrl     = omap_sham_write_ctrl_omap2,
1818         .trigger        = omap_sham_trigger_omap2,
1819         .poll_irq       = omap_sham_poll_irq_omap2,
1820         .intr_hdlr      = omap_sham_irq_omap2,
1821         .idigest_ofs    = 0x00,
1822         .din_ofs        = 0x1c,
1823         .digcnt_ofs     = 0x14,
1824         .rev_ofs        = 0x5c,
1825         .mask_ofs       = 0x60,
1826         .sysstatus_ofs  = 0x64,
1827         .major_mask     = 0xf0,
1828         .major_shift    = 4,
1829         .minor_mask     = 0x0f,
1830         .minor_shift    = 0,
1831 };
1832
1833 #ifdef CONFIG_OF
1834 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1835         {
1836                 .algs_list      = algs_sha1_md5,
1837                 .size           = ARRAY_SIZE(algs_sha1_md5),
1838         },
1839         {
1840                 .algs_list      = algs_sha224_sha256,
1841                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1842         },
1843 };
1844
1845 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1846         .algs_info      = omap_sham_algs_info_omap4,
1847         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1848         .flags          = BIT(FLAGS_AUTO_XOR),
1849         .digest_size    = SHA256_DIGEST_SIZE,
1850         .copy_hash      = omap_sham_copy_hash_omap4,
1851         .write_ctrl     = omap_sham_write_ctrl_omap4,
1852         .trigger        = omap_sham_trigger_omap4,
1853         .poll_irq       = omap_sham_poll_irq_omap4,
1854         .intr_hdlr      = omap_sham_irq_omap4,
1855         .idigest_ofs    = 0x020,
1856         .odigest_ofs    = 0x0,
1857         .din_ofs        = 0x080,
1858         .digcnt_ofs     = 0x040,
1859         .rev_ofs        = 0x100,
1860         .mask_ofs       = 0x110,
1861         .sysstatus_ofs  = 0x114,
1862         .mode_ofs       = 0x44,
1863         .length_ofs     = 0x48,
1864         .major_mask     = 0x0700,
1865         .major_shift    = 8,
1866         .minor_mask     = 0x003f,
1867         .minor_shift    = 0,
1868 };
1869
1870 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1871         {
1872                 .algs_list      = algs_sha1_md5,
1873                 .size           = ARRAY_SIZE(algs_sha1_md5),
1874         },
1875         {
1876                 .algs_list      = algs_sha224_sha256,
1877                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1878         },
1879         {
1880                 .algs_list      = algs_sha384_sha512,
1881                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1882         },
1883 };
1884
1885 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1886         .algs_info      = omap_sham_algs_info_omap5,
1887         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1888         .flags          = BIT(FLAGS_AUTO_XOR),
1889         .digest_size    = SHA512_DIGEST_SIZE,
1890         .copy_hash      = omap_sham_copy_hash_omap4,
1891         .write_ctrl     = omap_sham_write_ctrl_omap4,
1892         .trigger        = omap_sham_trigger_omap4,
1893         .poll_irq       = omap_sham_poll_irq_omap4,
1894         .intr_hdlr      = omap_sham_irq_omap4,
1895         .idigest_ofs    = 0x240,
1896         .odigest_ofs    = 0x200,
1897         .din_ofs        = 0x080,
1898         .digcnt_ofs     = 0x280,
1899         .rev_ofs        = 0x100,
1900         .mask_ofs       = 0x110,
1901         .sysstatus_ofs  = 0x114,
1902         .mode_ofs       = 0x284,
1903         .length_ofs     = 0x288,
1904         .major_mask     = 0x0700,
1905         .major_shift    = 8,
1906         .minor_mask     = 0x003f,
1907         .minor_shift    = 0,
1908 };
1909
1910 static const struct of_device_id omap_sham_of_match[] = {
1911         {
1912                 .compatible     = "ti,omap2-sham",
1913                 .data           = &omap_sham_pdata_omap2,
1914         },
1915         {
1916                 .compatible     = "ti,omap3-sham",
1917                 .data           = &omap_sham_pdata_omap2,
1918         },
1919         {
1920                 .compatible     = "ti,omap4-sham",
1921                 .data           = &omap_sham_pdata_omap4,
1922         },
1923         {
1924                 .compatible     = "ti,omap5-sham",
1925                 .data           = &omap_sham_pdata_omap5,
1926         },
1927         {},
1928 };
1929 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1930
1931 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1932                 struct device *dev, struct resource *res)
1933 {
1934         struct device_node *node = dev->of_node;
1935         int err = 0;
1936
1937         dd->pdata = of_device_get_match_data(dev);
1938         if (!dd->pdata) {
1939                 dev_err(dev, "no compatible OF match\n");
1940                 err = -EINVAL;
1941                 goto err;
1942         }
1943
1944         err = of_address_to_resource(node, 0, res);
1945         if (err < 0) {
1946                 dev_err(dev, "can't translate OF node address\n");
1947                 err = -EINVAL;
1948                 goto err;
1949         }
1950
1951         dd->irq = irq_of_parse_and_map(node, 0);
1952         if (!dd->irq) {
1953                 dev_err(dev, "can't translate OF irq value\n");
1954                 err = -EINVAL;
1955                 goto err;
1956         }
1957
1958 err:
1959         return err;
1960 }
1961 #else
1962 static const struct of_device_id omap_sham_of_match[] = {
1963         {},
1964 };
1965
1966 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1967                 struct device *dev, struct resource *res)
1968 {
1969         return -EINVAL;
1970 }
1971 #endif
1972
1973 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1974                 struct platform_device *pdev, struct resource *res)
1975 {
1976         struct device *dev = &pdev->dev;
1977         struct resource *r;
1978         int err = 0;
1979
1980         /* Get the base address */
1981         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1982         if (!r) {
1983                 dev_err(dev, "no MEM resource info\n");
1984                 err = -ENODEV;
1985                 goto err;
1986         }
1987         memcpy(res, r, sizeof(*res));
1988
1989         /* Get the IRQ */
1990         dd->irq = platform_get_irq(pdev, 0);
1991         if (dd->irq < 0) {
1992                 dev_err(dev, "no IRQ resource info\n");
1993                 err = dd->irq;
1994                 goto err;
1995         }
1996
1997         /* Only OMAP2/3 can be non-DT */
1998         dd->pdata = &omap_sham_pdata_omap2;
1999
2000 err:
2001         return err;
2002 }
2003
2004 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
2005                              char *buf)
2006 {
2007         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2008
2009         return sprintf(buf, "%d\n", dd->fallback_sz);
2010 }
2011
2012 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2013                               const char *buf, size_t size)
2014 {
2015         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2016         ssize_t status;
2017         long value;
2018
2019         status = kstrtol(buf, 0, &value);
2020         if (status)
2021                 return status;
2022
2023         /* HW accelerator only works with buffers > 9 */
2024         if (value < 9) {
2025                 dev_err(dev, "minimum fallback size 9\n");
2026                 return -EINVAL;
2027         }
2028
2029         dd->fallback_sz = value;
2030
2031         return size;
2032 }
2033
2034 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2035                               char *buf)
2036 {
2037         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2038
2039         return sprintf(buf, "%d\n", dd->queue.max_qlen);
2040 }
2041
2042 static ssize_t queue_len_store(struct device *dev,
2043                                struct device_attribute *attr, const char *buf,
2044                                size_t size)
2045 {
2046         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2047         ssize_t status;
2048         long value;
2049         unsigned long flags;
2050
2051         status = kstrtol(buf, 0, &value);
2052         if (status)
2053                 return status;
2054
2055         if (value < 1)
2056                 return -EINVAL;
2057
2058         /*
2059          * Changing the queue size in fly is safe, if size becomes smaller
2060          * than current size, it will just not accept new entries until
2061          * it has shrank enough.
2062          */
2063         spin_lock_irqsave(&dd->lock, flags);
2064         dd->queue.max_qlen = value;
2065         spin_unlock_irqrestore(&dd->lock, flags);
2066
2067         return size;
2068 }
2069
2070 static DEVICE_ATTR_RW(queue_len);
2071 static DEVICE_ATTR_RW(fallback);
2072
2073 static struct attribute *omap_sham_attrs[] = {
2074         &dev_attr_queue_len.attr,
2075         &dev_attr_fallback.attr,
2076         NULL,
2077 };
2078
2079 static struct attribute_group omap_sham_attr_group = {
2080         .attrs = omap_sham_attrs,
2081 };
2082
2083 static int omap_sham_probe(struct platform_device *pdev)
2084 {
2085         struct omap_sham_dev *dd;
2086         struct device *dev = &pdev->dev;
2087         struct resource res;
2088         dma_cap_mask_t mask;
2089         int err, i, j;
2090         u32 rev;
2091
2092         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2093         if (dd == NULL) {
2094                 dev_err(dev, "unable to alloc data struct.\n");
2095                 err = -ENOMEM;
2096                 goto data_err;
2097         }
2098         dd->dev = dev;
2099         platform_set_drvdata(pdev, dd);
2100
2101         INIT_LIST_HEAD(&dd->list);
2102         spin_lock_init(&dd->lock);
2103         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2104         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2105
2106         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2107                                omap_sham_get_res_pdev(dd, pdev, &res);
2108         if (err)
2109                 goto data_err;
2110
2111         dd->io_base = devm_ioremap_resource(dev, &res);
2112         if (IS_ERR(dd->io_base)) {
2113                 err = PTR_ERR(dd->io_base);
2114                 goto data_err;
2115         }
2116         dd->phys_base = res.start;
2117
2118         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2119                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2120         if (err) {
2121                 dev_err(dev, "unable to request irq %d, err = %d\n",
2122                         dd->irq, err);
2123                 goto data_err;
2124         }
2125
2126         dma_cap_zero(mask);
2127         dma_cap_set(DMA_SLAVE, mask);
2128
2129         dd->dma_lch = dma_request_chan(dev, "rx");
2130         if (IS_ERR(dd->dma_lch)) {
2131                 err = PTR_ERR(dd->dma_lch);
2132                 if (err == -EPROBE_DEFER)
2133                         goto data_err;
2134
2135                 dd->polling_mode = 1;
2136                 dev_dbg(dev, "using polling mode instead of dma\n");
2137         }
2138
2139         dd->flags |= dd->pdata->flags;
2140         sham.flags |= dd->pdata->flags;
2141
2142         pm_runtime_use_autosuspend(dev);
2143         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2144
2145         dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2146
2147         pm_runtime_enable(dev);
2148         pm_runtime_irq_safe(dev);
2149
2150         err = pm_runtime_get_sync(dev);
2151         if (err < 0) {
2152                 dev_err(dev, "failed to get sync: %d\n", err);
2153                 goto err_pm;
2154         }
2155
2156         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2157         pm_runtime_put_sync(&pdev->dev);
2158
2159         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2160                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2161                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2162
2163         spin_lock(&sham.lock);
2164         list_add_tail(&dd->list, &sham.dev_list);
2165         spin_unlock(&sham.lock);
2166
2167         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2168                 if (dd->pdata->algs_info[i].registered)
2169                         break;
2170
2171                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2172                         struct ahash_alg *alg;
2173
2174                         alg = &dd->pdata->algs_info[i].algs_list[j];
2175                         alg->export = omap_sham_export;
2176                         alg->import = omap_sham_import;
2177                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2178                                               BUFLEN;
2179                         err = crypto_register_ahash(alg);
2180                         if (err)
2181                                 goto err_algs;
2182
2183                         dd->pdata->algs_info[i].registered++;
2184                 }
2185         }
2186
2187         err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2188         if (err) {
2189                 dev_err(dev, "could not create sysfs device attrs\n");
2190                 goto err_algs;
2191         }
2192
2193         return 0;
2194
2195 err_algs:
2196         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2197                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2198                         crypto_unregister_ahash(
2199                                         &dd->pdata->algs_info[i].algs_list[j]);
2200 err_pm:
2201         pm_runtime_disable(dev);
2202         if (!dd->polling_mode)
2203                 dma_release_channel(dd->dma_lch);
2204 data_err:
2205         dev_err(dev, "initialization failed.\n");
2206
2207         return err;
2208 }
2209
2210 static int omap_sham_remove(struct platform_device *pdev)
2211 {
2212         struct omap_sham_dev *dd;
2213         int i, j;
2214
2215         dd = platform_get_drvdata(pdev);
2216         if (!dd)
2217                 return -ENODEV;
2218         spin_lock(&sham.lock);
2219         list_del(&dd->list);
2220         spin_unlock(&sham.lock);
2221         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2222                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2223                         crypto_unregister_ahash(
2224                                         &dd->pdata->algs_info[i].algs_list[j]);
2225                         dd->pdata->algs_info[i].registered--;
2226                 }
2227         tasklet_kill(&dd->done_task);
2228         pm_runtime_disable(&pdev->dev);
2229
2230         if (!dd->polling_mode)
2231                 dma_release_channel(dd->dma_lch);
2232
2233         return 0;
2234 }
2235
2236 #ifdef CONFIG_PM_SLEEP
2237 static int omap_sham_suspend(struct device *dev)
2238 {
2239         pm_runtime_put_sync(dev);
2240         return 0;
2241 }
2242
2243 static int omap_sham_resume(struct device *dev)
2244 {
2245         int err = pm_runtime_get_sync(dev);
2246         if (err < 0) {
2247                 dev_err(dev, "failed to get sync: %d\n", err);
2248                 return err;
2249         }
2250         return 0;
2251 }
2252 #endif
2253
2254 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2255
2256 static struct platform_driver omap_sham_driver = {
2257         .probe  = omap_sham_probe,
2258         .remove = omap_sham_remove,
2259         .driver = {
2260                 .name   = "omap-sham",
2261                 .pm     = &omap_sham_pm_ops,
2262                 .of_match_table = omap_sham_of_match,
2263         },
2264 };
2265
2266 module_platform_driver(omap_sham_driver);
2267
2268 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2269 MODULE_LICENSE("GPL v2");
2270 MODULE_AUTHOR("Dmitry Kasatkin");
2271 MODULE_ALIAS("platform:omap-sham");