drivers/dma/imx-sdma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // drivers/dma/imx-sdma.c
   4 //
   5 // This file contains a driver for the Freescale Smart DMA engine
   6 //
   7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   8 //
   9 // Based on code from Freescale:
  10 //
  11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  12
  13 #include <linux/init.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/bitops.h>
  18 #include <linux/mm.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched.h>
  23 #include <linux/semaphore.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firmware.h>
  28 #include <linux/slab.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/of.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_dma.h>
  35 #include <linux/workqueue.h>
  36
  37 #include <asm/irq.h>
  38 #include <linux/platform_data/dma-imx-sdma.h>
  39 #include <linux/platform_data/dma-imx.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  43
  44 #include "dmaengine.h"
  45 #include "virt-dma.h"
  46
  47 /* SDMA registers */
  48 #define SDMA_H_C0PTR            0x000
  49 #define SDMA_H_INTR             0x004
  50 #define SDMA_H_STATSTOP         0x008
  51 #define SDMA_H_START            0x00c
  52 #define SDMA_H_EVTOVR           0x010
  53 #define SDMA_H_DSPOVR           0x014
  54 #define SDMA_H_HOSTOVR          0x018
  55 #define SDMA_H_EVTPEND          0x01c
  56 #define SDMA_H_DSPENBL          0x020
  57 #define SDMA_H_RESET            0x024
  58 #define SDMA_H_EVTERR           0x028
  59 #define SDMA_H_INTRMSK          0x02c
  60 #define SDMA_H_PSW              0x030
  61 #define SDMA_H_EVTERRDBG        0x034
  62 #define SDMA_H_CONFIG           0x038
  63 #define SDMA_ONCE_ENB           0x040
  64 #define SDMA_ONCE_DATA          0x044
  65 #define SDMA_ONCE_INSTR         0x048
  66 #define SDMA_ONCE_STAT          0x04c
  67 #define SDMA_ONCE_CMD           0x050
  68 #define SDMA_EVT_MIRROR         0x054
  69 #define SDMA_ILLINSTADDR        0x058
  70 #define SDMA_CHN0ADDR           0x05c
  71 #define SDMA_ONCE_RTB           0x060
  72 #define SDMA_XTRIG_CONF1        0x070
  73 #define SDMA_XTRIG_CONF2        0x074
  74 #define SDMA_CHNENBL0_IMX35     0x200
  75 #define SDMA_CHNENBL0_IMX31     0x080
  76 #define SDMA_CHNPRI_0           0x100
  77
  78 /*
  79  * Buffer descriptor status values.
  80  */
  81 #define BD_DONE  0x01
  82 #define BD_WRAP  0x02
  83 #define BD_CONT  0x04
  84 #define BD_INTR  0x08
  85 #define BD_RROR  0x10
  86 #define BD_LAST  0x20
  87 #define BD_EXTD  0x80
  88
  89 /*
  90  * Data Node descriptor status values.
  91  */
  92 #define DND_END_OF_FRAME  0x80
  93 #define DND_END_OF_XFER   0x40
  94 #define DND_DONE          0x20
  95 #define DND_UNUSED        0x01
  96
  97 /*
  98  * IPCV2 descriptor status values.
  99  */
 100 #define BD_IPCV2_END_OF_FRAME  0x40
 101
 102 #define IPCV2_MAX_NODES        50
 103 /*
 104  * Error bit set in the CCB status field by the SDMA,
 105  * in setbd routine, in case of a transfer error
 106  */
 107 #define DATA_ERROR  0x10000000
 108
 109 /*
 110  * Buffer descriptor commands.
 111  */
 112 #define C0_ADDR             0x01
 113 #define C0_LOAD             0x02
 114 #define C0_DUMP             0x03
 115 #define C0_SETCTX           0x07
 116 #define C0_GETCTX           0x03
 117 #define C0_SETDM            0x01
 118 #define C0_SETPM            0x04
 119 #define C0_GETDM            0x02
 120 #define C0_GETPM            0x08
 121 /*
 122  * Change endianness indicator in the BD command field
 123  */
 124 #define CHANGE_ENDIANNESS   0x80
 125
 126 /*
 127  *  p_2_p watermark_level description
 128  *      Bits            Name                    Description
 129  *      0-7             Lower WML               Lower watermark level
 130  *      8               PS                      1: Pad Swallowing
 131  *                                              0: No Pad Swallowing
 132  *      9               PA                      1: Pad Adding
 133  *                                              0: No Pad Adding
 134  *      10              SPDIF                   If this bit is set both source
 135  *                                              and destination are on SPBA
 136  *      11              Source Bit(SP)          1: Source on SPBA
 137  *                                              0: Source on AIPS
 138  *      12              Destination Bit(DP)     1: Destination on SPBA
 139  *                                              0: Destination on AIPS
 140  *      13-15           ---------               MUST BE 0
 141  *      16-23           Higher WML              HWML
 142  *      24-27           N                       Total number of samples after
 143  *                                              which Pad adding/Swallowing
 144  *                                              must be done. It must be odd.
 145  *      28              Lower WML Event(LWE)    SDMA events reg to check for
 146  *                                              LWML event mask
 147  *                                              0: LWE in EVENTS register
 148  *                                              1: LWE in EVENTS2 register
 149  *      29              Higher WML Event(HWE)   SDMA events reg to check for
 150  *                                              HWML event mask
 151  *                                              0: HWE in EVENTS register
 152  *                                              1: HWE in EVENTS2 register
 153  *      30              ---------               MUST BE 0
 154  *      31              CONT                    1: Amount of samples to be
 155  *                                              transferred is unknown and
 156  *                                              script will keep on
 157  *                                              transferring samples as long as
 158  *                                              both events are detected and
 159  *                                              script must be manually stopped
 160  *                                              by the application
 161  *                                              0: The amount of samples to be
 162  *                                              transferred is equal to the
 163  *                                              count field of mode word
 164  */
 165 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
 166 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
 167 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
 168 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
 169 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
 170 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
 171 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
 172 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
 173 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
 174 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
 175
 176 #define SDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 177                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
 178                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
 179
 180 #define SDMA_DMA_DIRECTIONS     (BIT(DMA_DEV_TO_MEM) | \
 181                                  BIT(DMA_MEM_TO_DEV) | \
 182                                  BIT(DMA_DEV_TO_DEV))
 183
 184 /*
 185  * Mode/Count of data node descriptors - IPCv2
 186  */
 187 struct sdma_mode_count {
 188 #define SDMA_BD_MAX_CNT 0xffff
 189         u32 count   : 16; /* size of the buffer pointed by this BD */
 190         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 191         u32 command :  8; /* command mostly used for channel 0 */
 192 };
 193
 194 /*
 195  * Buffer descriptor
 196  */
 197 struct sdma_buffer_descriptor {
 198         struct sdma_mode_count  mode;
 199         u32 buffer_addr;        /* address of the buffer described */
 200         u32 ext_buffer_addr;    /* extended buffer address */
 201 } __attribute__ ((packed));
 202
 203 /**
 204  * struct sdma_channel_control - Channel control Block
 205  *
 206  * @current_bd_ptr:     current buffer descriptor processed
 207  * @base_bd_ptr:        first element of buffer descriptor array
 208  * @unused:             padding. The SDMA engine expects an array of 128 byte
 209  *                      control blocks
 210  */
 211 struct sdma_channel_control {
 212         u32 current_bd_ptr;
 213         u32 base_bd_ptr;
 214         u32 unused[2];
 215 } __attribute__ ((packed));
 216
 217 /**
 218  * struct sdma_state_registers - SDMA context for a channel
 219  *
 220  * @pc:         program counter
 221  * @unused1:    unused
 222  * @t:          test bit: status of arithmetic & test instruction
 223  * @rpc:        return program counter
 224  * @unused0:    unused
 225  * @sf:         source fault while loading data
 226  * @spc:        loop start program counter
 227  * @unused2:    unused
 228  * @df:         destination fault while storing data
 229  * @epc:        loop end program counter
 230  * @lm:         loop mode
 231  */
 232 struct sdma_state_registers {
 233         u32 pc     :14;
 234         u32 unused1: 1;
 235         u32 t      : 1;
 236         u32 rpc    :14;
 237         u32 unused0: 1;
 238         u32 sf     : 1;
 239         u32 spc    :14;
 240         u32 unused2: 1;
 241         u32 df     : 1;
 242         u32 epc    :14;
 243         u32 lm     : 2;
 244 } __attribute__ ((packed));
 245
 246 /**
 247  * struct sdma_context_data - sdma context specific to a channel
 248  *
 249  * @channel_state:      channel state bits
 250  * @gReg:               general registers
 251  * @mda:                burst dma destination address register
 252  * @msa:                burst dma source address register
 253  * @ms:                 burst dma status register
 254  * @md:                 burst dma data register
 255  * @pda:                peripheral dma destination address register
 256  * @psa:                peripheral dma source address register
 257  * @ps:                 peripheral dma status register
 258  * @pd:                 peripheral dma data register
 259  * @ca:                 CRC polynomial register
 260  * @cs:                 CRC accumulator register
 261  * @dda:                dedicated core destination address register
 262  * @dsa:                dedicated core source address register
 263  * @ds:                 dedicated core status register
 264  * @dd:                 dedicated core data register
 265  * @scratch0:           1st word of dedicated ram for context switch
 266  * @scratch1:           2nd word of dedicated ram for context switch
 267  * @scratch2:           3rd word of dedicated ram for context switch
 268  * @scratch3:           4th word of dedicated ram for context switch
 269  * @scratch4:           5th word of dedicated ram for context switch
 270  * @scratch5:           6th word of dedicated ram for context switch
 271  * @scratch6:           7th word of dedicated ram for context switch
 272  * @scratch7:           8th word of dedicated ram for context switch
 273  */
 274 struct sdma_context_data {
 275         struct sdma_state_registers  channel_state;
 276         u32  gReg[8];
 277         u32  mda;
 278         u32  msa;
 279         u32  ms;
 280         u32  md;
 281         u32  pda;
 282         u32  psa;
 283         u32  ps;
 284         u32  pd;
 285         u32  ca;
 286         u32  cs;
 287         u32  dda;
 288         u32  dsa;
 289         u32  ds;
 290         u32  dd;
 291         u32  scratch0;
 292         u32  scratch1;
 293         u32  scratch2;
 294         u32  scratch3;
 295         u32  scratch4;
 296         u32  scratch5;
 297         u32  scratch6;
 298         u32  scratch7;
 299 } __attribute__ ((packed));
 300
 301
 302 struct sdma_engine;
 303
 304 /**
 305  * struct sdma_desc - descriptor structor for one transfer
 306  * @vd:                 descriptor for virt dma
 307  * @num_bd:             number of descriptors currently handling
 308  * @bd_phys:            physical address of bd
 309  * @buf_tail:           ID of the buffer that was processed
 310  * @buf_ptail:          ID of the previous buffer that was processed
 311  * @period_len:         period length, used in cyclic.
 312  * @chn_real_count:     the real count updated from bd->mode.count
 313  * @chn_count:          the transfer count set
 314  * @sdmac:              sdma_channel pointer
 315  * @bd:                 pointer of allocate bd
 316  */
 317 struct sdma_desc {
 318         struct virt_dma_desc    vd;
 319         unsigned int            num_bd;
 320         dma_addr_t              bd_phys;
 321         unsigned int            buf_tail;
 322         unsigned int            buf_ptail;
 323         unsigned int            period_len;
 324         unsigned int            chn_real_count;
 325         unsigned int            chn_count;
 326         struct sdma_channel     *sdmac;
 327         struct sdma_buffer_descriptor *bd;
 328 };
 329
 330 /**
 331  * struct sdma_channel - housekeeping for a SDMA channel
 332  *
 333  * @vc:                 virt_dma base structure
 334  * @desc:               sdma description including vd and other special member
 335  * @sdma:               pointer to the SDMA engine for this channel
 336  * @channel:            the channel number, matches dmaengine chan_id + 1
 337  * @direction:          transfer type. Needed for setting SDMA script
 338  * @slave_config        Slave configuration
 339  * @peripheral_type:    Peripheral type. Needed for setting SDMA script
 340  * @event_id0:          aka dma request line
 341  * @event_id1:          for channels that use 2 events
 342  * @word_size:          peripheral access size
 343  * @pc_from_device:     script address for those device_2_memory
 344  * @pc_to_device:       script address for those memory_2_device
 345  * @device_to_device:   script address for those device_2_device
 346  * @pc_to_pc:           script address for those memory_2_memory
 347  * @flags:              loop mode or not
 348  * @per_address:        peripheral source or destination address in common case
 349  *                      destination address in p_2_p case
 350  * @per_address2:       peripheral source address in p_2_p case
 351  * @event_mask:         event mask used in p_2_p script
 352  * @watermark_level:    value for gReg[7], some script will extend it from
 353  *                      basic watermark such as p_2_p
 354  * @shp_addr:           value for gReg[6]
 355  * @per_addr:           value for gReg[2]
 356  * @status:             status of dma channel
 357  * @data:               specific sdma interface structure
 358  * @bd_pool:            dma_pool for bd
 359  */
 360 struct sdma_channel {
 361         struct virt_dma_chan            vc;
 362         struct sdma_desc                *desc;
 363         struct sdma_engine              *sdma;
 364         unsigned int                    channel;
 365         enum dma_transfer_direction             direction;
 366         struct dma_slave_config         slave_config;
 367         enum sdma_peripheral_type       peripheral_type;
 368         unsigned int                    event_id0;
 369         unsigned int                    event_id1;
 370         enum dma_slave_buswidth         word_size;
 371         unsigned int                    pc_from_device, pc_to_device;
 372         unsigned int                    device_to_device;
 373         unsigned int                    pc_to_pc;
 374         unsigned long                   flags;
 375         dma_addr_t                      per_address, per_address2;
 376         unsigned long                   event_mask[2];
 377         unsigned long                   watermark_level;
 378         u32                             shp_addr, per_addr;
 379         enum dma_status                 status;
 380         struct imx_dma_data             data;
 381         struct work_struct              terminate_worker;
 382 };
 383
 384 #define IMX_DMA_SG_LOOP         BIT(0)
 385
 386 #define MAX_DMA_CHANNELS 32
 387 #define MXC_SDMA_DEFAULT_PRIORITY 1
 388 #define MXC_SDMA_MIN_PRIORITY 1
 389 #define MXC_SDMA_MAX_PRIORITY 7
 390
 391 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 392
 393 /**
 394  * struct sdma_firmware_header - Layout of the firmware image
 395  *
 396  * @magic:              "SDMA"
 397  * @version_major:      increased whenever layout of struct
 398  *                      sdma_script_start_addrs changes.
 399  * @version_minor:      firmware minor version (for binary compatible changes)
 400  * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
 401  * @num_script_addrs:   Number of script addresses in this image
 402  * @ram_code_start:     offset of SDMA ram image in this firmware image
 403  * @ram_code_size:      size of SDMA ram image
 404  * @script_addrs:       Stores the start address of the SDMA scripts
 405  *                      (in SDMA memory space)
 406  */
 407 struct sdma_firmware_header {
 408         u32     magic;
 409         u32     version_major;
 410         u32     version_minor;
 411         u32     script_addrs_start;
 412         u32     num_script_addrs;
 413         u32     ram_code_start;
 414         u32     ram_code_size;
 415 };
 416
 417 struct sdma_driver_data {
 418         int chnenbl0;
 419         int num_events;
 420         struct sdma_script_start_addrs  *script_addrs;
 421 };
 422
 423 struct sdma_engine {
 424         struct device                   *dev;
 425         struct device_dma_parameters    dma_parms;
 426         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 427         struct sdma_channel_control     *channel_control;
 428         void __iomem                    *regs;
 429         struct sdma_context_data        *context;
 430         dma_addr_t                      context_phys;
 431         struct dma_device               dma_device;
 432         struct clk                      *clk_ipg;
 433         struct clk                      *clk_ahb;
 434         spinlock_t                      channel_0_lock;
 435         u32                             script_number;
 436         struct sdma_script_start_addrs  *script_addrs;
 437         const struct sdma_driver_data   *drvdata;
 438         u32                             spba_start_addr;
 439         u32                             spba_end_addr;
 440         unsigned int                    irq;
 441         dma_addr_t                      bd0_phys;
 442         struct sdma_buffer_descriptor   *bd0;
 443 };
 444
 445 static int sdma_config_write(struct dma_chan *chan,
 446                        struct dma_slave_config *dmaengine_cfg,
 447                        enum dma_transfer_direction direction);
 448
 449 static struct sdma_driver_data sdma_imx31 = {
 450         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 451         .num_events = 32,
 452 };
 453
 454 static struct sdma_script_start_addrs sdma_script_imx25 = {
 455         .ap_2_ap_addr = 729,
 456         .uart_2_mcu_addr = 904,
 457         .per_2_app_addr = 1255,
 458         .mcu_2_app_addr = 834,
 459         .uartsh_2_mcu_addr = 1120,
 460         .per_2_shp_addr = 1329,
 461         .mcu_2_shp_addr = 1048,
 462         .ata_2_mcu_addr = 1560,
 463         .mcu_2_ata_addr = 1479,
 464         .app_2_per_addr = 1189,
 465         .app_2_mcu_addr = 770,
 466         .shp_2_per_addr = 1407,
 467         .shp_2_mcu_addr = 979,
 468 };
 469
 470 static struct sdma_driver_data sdma_imx25 = {
 471         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 472         .num_events = 48,
 473         .script_addrs = &sdma_script_imx25,
 474 };
 475
 476 static struct sdma_driver_data sdma_imx35 = {
 477         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 478         .num_events = 48,
 479 };
 480
 481 static struct sdma_script_start_addrs sdma_script_imx51 = {
 482         .ap_2_ap_addr = 642,
 483         .uart_2_mcu_addr = 817,
 484         .mcu_2_app_addr = 747,
 485         .mcu_2_shp_addr = 961,
 486         .ata_2_mcu_addr = 1473,
 487         .mcu_2_ata_addr = 1392,
 488         .app_2_per_addr = 1033,
 489         .app_2_mcu_addr = 683,
 490         .shp_2_per_addr = 1251,
 491         .shp_2_mcu_addr = 892,
 492 };
 493
 494 static struct sdma_driver_data sdma_imx51 = {
 495         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 496         .num_events = 48,
 497         .script_addrs = &sdma_script_imx51,
 498 };
 499
 500 static struct sdma_script_start_addrs sdma_script_imx53 = {
 501         .ap_2_ap_addr = 642,
 502         .app_2_mcu_addr = 683,
 503         .mcu_2_app_addr = 747,
 504         .uart_2_mcu_addr = 817,
 505         .shp_2_mcu_addr = 891,
 506         .mcu_2_shp_addr = 960,
 507         .uartsh_2_mcu_addr = 1032,
 508         .spdif_2_mcu_addr = 1100,
 509         .mcu_2_spdif_addr = 1134,
 510         .firi_2_mcu_addr = 1193,
 511         .mcu_2_firi_addr = 1290,
 512 };
 513
 514 static struct sdma_driver_data sdma_imx53 = {
 515         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 516         .num_events = 48,
 517         .script_addrs = &sdma_script_imx53,
 518 };
 519
 520 static struct sdma_script_start_addrs sdma_script_imx6q = {
 521         .ap_2_ap_addr = 642,
 522         .uart_2_mcu_addr = 817,
 523         .mcu_2_app_addr = 747,
 524         .per_2_per_addr = 6331,
 525         .uartsh_2_mcu_addr = 1032,
 526         .mcu_2_shp_addr = 960,
 527         .app_2_mcu_addr = 683,
 528         .shp_2_mcu_addr = 891,
 529         .spdif_2_mcu_addr = 1100,
 530         .mcu_2_spdif_addr = 1134,
 531 };
 532
 533 static struct sdma_driver_data sdma_imx6q = {
 534         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 535         .num_events = 48,
 536         .script_addrs = &sdma_script_imx6q,
 537 };
 538
 539 static struct sdma_script_start_addrs sdma_script_imx7d = {
 540         .ap_2_ap_addr = 644,
 541         .uart_2_mcu_addr = 819,
 542         .mcu_2_app_addr = 749,
 543         .uartsh_2_mcu_addr = 1034,
 544         .mcu_2_shp_addr = 962,
 545         .app_2_mcu_addr = 685,
 546         .shp_2_mcu_addr = 893,
 547         .spdif_2_mcu_addr = 1102,
 548         .mcu_2_spdif_addr = 1136,
 549 };
 550
 551 static struct sdma_driver_data sdma_imx7d = {
 552         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 553         .num_events = 48,
 554         .script_addrs = &sdma_script_imx7d,
 555 };
 556
 557 static const struct platform_device_id sdma_devtypes[] = {
 558         {
 559                 .name = "imx25-sdma",
 560                 .driver_data = (unsigned long)&sdma_imx25,
 561         }, {
 562                 .name = "imx31-sdma",
 563                 .driver_data = (unsigned long)&sdma_imx31,
 564         }, {
 565                 .name = "imx35-sdma",
 566                 .driver_data = (unsigned long)&sdma_imx35,
 567         }, {
 568                 .name = "imx51-sdma",
 569                 .driver_data = (unsigned long)&sdma_imx51,
 570         }, {
 571                 .name = "imx53-sdma",
 572                 .driver_data = (unsigned long)&sdma_imx53,
 573         }, {
 574                 .name = "imx6q-sdma",
 575                 .driver_data = (unsigned long)&sdma_imx6q,
 576         }, {
 577                 .name = "imx7d-sdma",
 578                 .driver_data = (unsigned long)&sdma_imx7d,
 579         }, {
 580                 /* sentinel */
 581         }
 582 };
 583 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 584
 585 static const struct of_device_id sdma_dt_ids[] = {
 586         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 587         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 588         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 589         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 590         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 591         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 592         { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
 593         { /* sentinel */ }
 594 };
 595 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 596
 597 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 598 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 599 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 600 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 601
 602 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 603 {
 604         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 605         return chnenbl0 + event * 4;
 606 }
 607
 608 static int sdma_config_ownership(struct sdma_channel *sdmac,
 609                 bool event_override, bool mcu_override, bool dsp_override)
 610 {
 611         struct sdma_engine *sdma = sdmac->sdma;
 612         int channel = sdmac->channel;
 613         unsigned long evt, mcu, dsp;
 614
 615         if (event_override && mcu_override && dsp_override)
 616                 return -EINVAL;
 617
 618         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 619         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 620         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 621
 622         if (dsp_override)
 623                 __clear_bit(channel, &dsp);
 624         else
 625                 __set_bit(channel, &dsp);
 626
 627         if (event_override)
 628                 __clear_bit(channel, &evt);
 629         else
 630                 __set_bit(channel, &evt);
 631
 632         if (mcu_override)
 633                 __clear_bit(channel, &mcu);
 634         else
 635                 __set_bit(channel, &mcu);
 636
 637         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 638         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 639         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 640
 641         return 0;
 642 }
 643
 644 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 645 {
 646         writel(BIT(channel), sdma->regs + SDMA_H_START);
 647 }
 648
 649 /*
 650  * sdma_run_channel0 - run a channel and wait till it's done
 651  */
 652 static int sdma_run_channel0(struct sdma_engine *sdma)
 653 {
 654         int ret;
 655         u32 reg;
 656
 657         sdma_enable_channel(sdma, 0);
 658
 659         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
 660                                                 reg, !(reg & 1), 1, 500);
 661         if (ret)
 662                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 663
 664         /* Set bits of CONFIG register with dynamic context switching */
 665         if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
 666                 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
 667
 668         return ret;
 669 }
 670
 671 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 672                 u32 address)
 673 {
 674         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 675         void *buf_virt;
 676         dma_addr_t buf_phys;
 677         int ret;
 678         unsigned long flags;
 679
 680         buf_virt = dma_alloc_coherent(NULL,
 681                         size,
 682                         &buf_phys, GFP_KERNEL);
 683         if (!buf_virt) {
 684                 return -ENOMEM;
 685         }
 686
 687         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 688
 689         bd0->mode.command = C0_SETPM;
 690         bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
 691         bd0->mode.count = size / 2;
 692         bd0->buffer_addr = buf_phys;
 693         bd0->ext_buffer_addr = address;
 694
 695         memcpy(buf_virt, buf, size);
 696
 697         ret = sdma_run_channel0(sdma);
 698
 699         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 700
 701         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 702
 703         return ret;
 704 }
 705
 706 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 707 {
 708         struct sdma_engine *sdma = sdmac->sdma;
 709         int channel = sdmac->channel;
 710         unsigned long val;
 711         u32 chnenbl = chnenbl_ofs(sdma, event);
 712
 713         val = readl_relaxed(sdma->regs + chnenbl);
 714         __set_bit(channel, &val);
 715         writel_relaxed(val, sdma->regs + chnenbl);
 716 }
 717
 718 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 719 {
 720         struct sdma_engine *sdma = sdmac->sdma;
 721         int channel = sdmac->channel;
 722         u32 chnenbl = chnenbl_ofs(sdma, event);
 723         unsigned long val;
 724
 725         val = readl_relaxed(sdma->regs + chnenbl);
 726         __clear_bit(channel, &val);
 727         writel_relaxed(val, sdma->regs + chnenbl);
 728 }
 729
 730 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
 731 {
 732         return container_of(t, struct sdma_desc, vd.tx);
 733 }
 734
 735 static void sdma_start_desc(struct sdma_channel *sdmac)
 736 {
 737         struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
 738         struct sdma_desc *desc;
 739         struct sdma_engine *sdma = sdmac->sdma;
 740         int channel = sdmac->channel;
 741
 742         if (!vd) {
 743                 sdmac->desc = NULL;
 744                 return;
 745         }
 746         sdmac->desc = desc = to_sdma_desc(&vd->tx);
 747         /*
 748          * Do not delete the node in desc_issued list in cyclic mode, otherwise
 749          * the desc allocated will never be freed in vchan_dma_desc_free_list
 750          */
 751         if (!(sdmac->flags & IMX_DMA_SG_LOOP))
 752                 list_del(&vd->node);
 753
 754         sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
 755         sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
 756         sdma_enable_channel(sdma, sdmac->channel);
 757 }
 758
 759 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 760 {
 761         struct sdma_buffer_descriptor *bd;
 762         int error = 0;
 763         enum dma_status old_status = sdmac->status;
 764
 765         /*
 766          * loop mode. Iterate over descriptors, re-setup them and
 767          * call callback function.
 768          */
 769         while (sdmac->desc) {
 770                 struct sdma_desc *desc = sdmac->desc;
 771
 772                 bd = &desc->bd[desc->buf_tail];
 773
 774                 if (bd->mode.status & BD_DONE)
 775                         break;
 776
 777                 if (bd->mode.status & BD_RROR) {
 778                         bd->mode.status &= ~BD_RROR;
 779                         sdmac->status = DMA_ERROR;
 780                         error = -EIO;
 781                 }
 782
 783                /*
 784                 * We use bd->mode.count to calculate the residue, since contains
 785                 * the number of bytes present in the current buffer descriptor.
 786                 */
 787
 788                 desc->chn_real_count = bd->mode.count;
 789                 bd->mode.status |= BD_DONE;
 790                 bd->mode.count = desc->period_len;
 791                 desc->buf_ptail = desc->buf_tail;
 792                 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
 793
 794                 /*
 795                  * The callback is called from the interrupt context in order
 796                  * to reduce latency and to avoid the risk of altering the
 797                  * SDMA transaction status by the time the client tasklet is
 798                  * executed.
 799                  */
 800                 spin_unlock(&sdmac->vc.lock);
 801                 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
 802                 spin_lock(&sdmac->vc.lock);
 803
 804                 if (error)
 805                         sdmac->status = old_status;
 806         }
 807 }
 808
 809 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
 810 {
 811         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 812         struct sdma_buffer_descriptor *bd;
 813         int i, error = 0;
 814
 815         sdmac->desc->chn_real_count = 0;
 816         /*
 817          * non loop mode. Iterate over all descriptors, collect
 818          * errors and call callback function
 819          */
 820         for (i = 0; i < sdmac->desc->num_bd; i++) {
 821                 bd = &sdmac->desc->bd[i];
 822
 823                  if (bd->mode.status & (BD_DONE | BD_RROR))
 824                         error = -EIO;
 825                  sdmac->desc->chn_real_count += bd->mode.count;
 826         }
 827
 828         if (error)
 829                 sdmac->status = DMA_ERROR;
 830         else
 831                 sdmac->status = DMA_COMPLETE;
 832 }
 833
 834 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 835 {
 836         struct sdma_engine *sdma = dev_id;
 837         unsigned long stat;
 838
 839         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 840         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 841         /* channel 0 is special and not handled here, see run_channel0() */
 842         stat &= ~1;
 843
 844         while (stat) {
 845                 int channel = fls(stat) - 1;
 846                 struct sdma_channel *sdmac = &sdma->channel[channel];
 847                 struct sdma_desc *desc;
 848
 849                 spin_lock(&sdmac->vc.lock);
 850                 desc = sdmac->desc;
 851                 if (desc) {
 852                         if (sdmac->flags & IMX_DMA_SG_LOOP) {
 853                                 sdma_update_channel_loop(sdmac);
 854                         } else {
 855                                 mxc_sdma_handle_channel_normal(sdmac);
 856                                 vchan_cookie_complete(&desc->vd);
 857                                 sdma_start_desc(sdmac);
 858                         }
 859                 }
 860
 861                 spin_unlock(&sdmac->vc.lock);
 862                 __clear_bit(channel, &stat);
 863         }
 864
 865         return IRQ_HANDLED;
 866 }
 867
 868 /*
 869  * sets the pc of SDMA script according to the peripheral type
 870  */
 871 static void sdma_get_pc(struct sdma_channel *sdmac,
 872                 enum sdma_peripheral_type peripheral_type)
 873 {
 874         struct sdma_engine *sdma = sdmac->sdma;
 875         int per_2_emi = 0, emi_2_per = 0;
 876         /*
 877          * These are needed once we start to support transfers between
 878          * two peripherals or memory-to-memory transfers
 879          */
 880         int per_2_per = 0, emi_2_emi = 0;
 881
 882         sdmac->pc_from_device = 0;
 883         sdmac->pc_to_device = 0;
 884         sdmac->device_to_device = 0;
 885         sdmac->pc_to_pc = 0;
 886
 887         switch (peripheral_type) {
 888         case IMX_DMATYPE_MEMORY:
 889                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 890                 break;
 891         case IMX_DMATYPE_DSP:
 892                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 893                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 894                 break;
 895         case IMX_DMATYPE_FIRI:
 896                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 897                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 898                 break;
 899         case IMX_DMATYPE_UART:
 900                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 901                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 902                 break;
 903         case IMX_DMATYPE_UART_SP:
 904                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 905                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 906                 break;
 907         case IMX_DMATYPE_ATA:
 908                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 909                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 910                 break;
 911         case IMX_DMATYPE_CSPI:
 912         case IMX_DMATYPE_EXT:
 913         case IMX_DMATYPE_SSI:
 914         case IMX_DMATYPE_SAI:
 915                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 916                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 917                 break;
 918         case IMX_DMATYPE_SSI_DUAL:
 919                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 920                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 921                 break;
 922         case IMX_DMATYPE_SSI_SP:
 923         case IMX_DMATYPE_MMC:
 924         case IMX_DMATYPE_SDHC:
 925         case IMX_DMATYPE_CSPI_SP:
 926         case IMX_DMATYPE_ESAI:
 927         case IMX_DMATYPE_MSHC_SP:
 928                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 929                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 930                 break;
 931         case IMX_DMATYPE_ASRC:
 932                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 933                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 934                 per_2_per = sdma->script_addrs->per_2_per_addr;
 935                 break;
 936         case IMX_DMATYPE_ASRC_SP:
 937                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 938                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 939                 per_2_per = sdma->script_addrs->per_2_per_addr;
 940                 break;
 941         case IMX_DMATYPE_MSHC:
 942                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 943                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 944                 break;
 945         case IMX_DMATYPE_CCM:
 946                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 947                 break;
 948         case IMX_DMATYPE_SPDIF:
 949                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 950                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 951                 break;
 952         case IMX_DMATYPE_IPU_MEMORY:
 953                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 954                 break;
 955         default:
 956                 break;
 957         }
 958
 959         sdmac->pc_from_device = per_2_emi;
 960         sdmac->pc_to_device = emi_2_per;
 961         sdmac->device_to_device = per_2_per;
 962         sdmac->pc_to_pc = emi_2_emi;
 963 }
 964
 965 static int sdma_load_context(struct sdma_channel *sdmac)
 966 {
 967         struct sdma_engine *sdma = sdmac->sdma;
 968         int channel = sdmac->channel;
 969         int load_address;
 970         struct sdma_context_data *context = sdma->context;
 971         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 972         int ret;
 973         unsigned long flags;
 974
 975         if (sdmac->direction == DMA_DEV_TO_MEM)
 976                 load_address = sdmac->pc_from_device;
 977         else if (sdmac->direction == DMA_DEV_TO_DEV)
 978                 load_address = sdmac->device_to_device;
 979         else if (sdmac->direction == DMA_MEM_TO_MEM)
 980                 load_address = sdmac->pc_to_pc;
 981         else
 982                 load_address = sdmac->pc_to_device;
 983
 984         if (load_address < 0)
 985                 return load_address;
 986
 987         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 988         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 989         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 990         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 991         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 992         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 993
 994         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 995
 996         memset(context, 0, sizeof(*context));
 997         context->channel_state.pc = load_address;
 998
 999         /* Send by context the event mask,base address for peripheral
1000          * and watermark level
1001          */
1002         context->gReg[0] = sdmac->event_mask[1];
1003         context->gReg[1] = sdmac->event_mask[0];
1004         context->gReg[2] = sdmac->per_addr;
1005         context->gReg[6] = sdmac->shp_addr;
1006         context->gReg[7] = sdmac->watermark_level;
1007
1008         bd0->mode.command = C0_SETDM;
1009         bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
1010         bd0->mode.count = sizeof(*context) / 4;
1011         bd0->buffer_addr = sdma->context_phys;
1012         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1013         ret = sdma_run_channel0(sdma);
1014
1015         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1016
1017         return ret;
1018 }
1019
1020 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1021 {
1022         return container_of(chan, struct sdma_channel, vc.chan);
1023 }
1024
1025 static int sdma_disable_channel(struct dma_chan *chan)
1026 {
1027         struct sdma_channel *sdmac = to_sdma_chan(chan);
1028         struct sdma_engine *sdma = sdmac->sdma;
1029         int channel = sdmac->channel;
1030
1031         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1032         sdmac->status = DMA_ERROR;
1033
1034         return 0;
1035 }
1036 static void sdma_channel_terminate_work(struct work_struct *work)
1037 {
1038         struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1039                                                   terminate_worker);
1040         unsigned long flags;
1041         LIST_HEAD(head);
1042
1043         /*
1044          * According to NXP R&D team a delay of one BD SDMA cost time
1045          * (maximum is 1ms) should be added after disable of the channel
1046          * bit, to ensure SDMA core has really been stopped after SDMA
1047          * clients call .device_terminate_all.
1048          */
1049         usleep_range(1000, 2000);
1050
1051         spin_lock_irqsave(&sdmac->vc.lock, flags);
1052         vchan_get_all_descriptors(&sdmac->vc, &head);
1053         sdmac->desc = NULL;
1054         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1055         vchan_dma_desc_free_list(&sdmac->vc, &head);
1056 }
1057
1058 static int sdma_disable_channel_async(struct dma_chan *chan)
1059 {
1060         struct sdma_channel *sdmac = to_sdma_chan(chan);
1061
1062         sdma_disable_channel(chan);
1063
1064         if (sdmac->desc)
1065                 schedule_work(&sdmac->terminate_worker);
1066
1067         return 0;
1068 }
1069
1070 static void sdma_channel_synchronize(struct dma_chan *chan)
1071 {
1072         struct sdma_channel *sdmac = to_sdma_chan(chan);
1073
1074         vchan_synchronize(&sdmac->vc);
1075
1076         flush_work(&sdmac->terminate_worker);
1077 }
1078
1079 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1080 {
1081         struct sdma_engine *sdma = sdmac->sdma;
1082
1083         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1084         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1085
1086         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1087         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1088
1089         if (sdmac->event_id0 > 31)
1090                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1091
1092         if (sdmac->event_id1 > 31)
1093                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1094
1095         /*
1096          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1097          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1098          * r0(event_mask[1]) and r1(event_mask[0]).
1099          */
1100         if (lwml > hwml) {
1101                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1102                                                 SDMA_WATERMARK_LEVEL_HWML);
1103                 sdmac->watermark_level |= hwml;
1104                 sdmac->watermark_level |= lwml << 16;
1105                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1106         }
1107
1108         if (sdmac->per_address2 >= sdma->spba_start_addr &&
1109                         sdmac->per_address2 <= sdma->spba_end_addr)
1110                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1111
1112         if (sdmac->per_address >= sdma->spba_start_addr &&
1113                         sdmac->per_address <= sdma->spba_end_addr)
1114                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1115
1116         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1117 }
1118
1119 static int sdma_config_channel(struct dma_chan *chan)
1120 {
1121         struct sdma_channel *sdmac = to_sdma_chan(chan);
1122         int ret;
1123
1124         sdma_disable_channel(chan);
1125
1126         sdmac->event_mask[0] = 0;
1127         sdmac->event_mask[1] = 0;
1128         sdmac->shp_addr = 0;
1129         sdmac->per_addr = 0;
1130
1131         switch (sdmac->peripheral_type) {
1132         case IMX_DMATYPE_DSP:
1133                 sdma_config_ownership(sdmac, false, true, true);
1134                 break;
1135         case IMX_DMATYPE_MEMORY:
1136                 sdma_config_ownership(sdmac, false, true, false);
1137                 break;
1138         default:
1139                 sdma_config_ownership(sdmac, true, true, false);
1140                 break;
1141         }
1142
1143         sdma_get_pc(sdmac, sdmac->peripheral_type);
1144
1145         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1146                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1147                 /* Handle multiple event channels differently */
1148                 if (sdmac->event_id1) {
1149                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1150                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1151                                 sdma_set_watermarklevel_for_p2p(sdmac);
1152                 } else
1153                         __set_bit(sdmac->event_id0, sdmac->event_mask);
1154
1155                 /* Address */
1156                 sdmac->shp_addr = sdmac->per_address;
1157                 sdmac->per_addr = sdmac->per_address2;
1158         } else {
1159                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1160         }
1161
1162         ret = sdma_load_context(sdmac);
1163
1164         return ret;
1165 }
1166
1167 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1168                 unsigned int priority)
1169 {
1170         struct sdma_engine *sdma = sdmac->sdma;
1171         int channel = sdmac->channel;
1172
1173         if (priority < MXC_SDMA_MIN_PRIORITY
1174             || priority > MXC_SDMA_MAX_PRIORITY) {
1175                 return -EINVAL;
1176         }
1177
1178         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1179
1180         return 0;
1181 }
1182
1183 static int sdma_request_channel0(struct sdma_engine *sdma)
1184 {
1185         int ret = -EBUSY;
1186
1187         sdma->bd0 = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdma->bd0_phys,
1188                                         GFP_NOWAIT);
1189         if (!sdma->bd0) {
1190                 ret = -ENOMEM;
1191                 goto out;
1192         }
1193
1194         sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1195         sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1196
1197         sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1198         return 0;
1199 out:
1200
1201         return ret;
1202 }
1203
1204
1205 static int sdma_alloc_bd(struct sdma_desc *desc)
1206 {
1207         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1208         int ret = 0;
1209
1210         desc->bd = dma_zalloc_coherent(NULL, bd_size, &desc->bd_phys,
1211                                         GFP_NOWAIT);
1212         if (!desc->bd) {
1213                 ret = -ENOMEM;
1214                 goto out;
1215         }
1216 out:
1217         return ret;
1218 }
1219
1220 static void sdma_free_bd(struct sdma_desc *desc)
1221 {
1222         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1223
1224         dma_free_coherent(NULL, bd_size, desc->bd, desc->bd_phys);
1225 }
1226
1227 static void sdma_desc_free(struct virt_dma_desc *vd)
1228 {
1229         struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1230
1231         sdma_free_bd(desc);
1232         kfree(desc);
1233 }
1234
1235 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1236 {
1237         struct sdma_channel *sdmac = to_sdma_chan(chan);
1238         struct imx_dma_data *data = chan->private;
1239         struct imx_dma_data mem_data;
1240         int prio, ret;
1241
1242         /*
1243          * MEMCPY may never setup chan->private by filter function such as
1244          * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1245          * Please note in any other slave case, you have to setup chan->private
1246          * with 'struct imx_dma_data' in your own filter function if you want to
1247          * request dma channel by dma_request_channel() rather than
1248          * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1249          * to warn you to correct your filter function.
1250          */
1251         if (!data) {
1252                 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1253                 mem_data.priority = 2;
1254                 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1255                 mem_data.dma_request = 0;
1256                 mem_data.dma_request2 = 0;
1257                 data = &mem_data;
1258
1259                 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1260         }
1261
1262         switch (data->priority) {
1263         case DMA_PRIO_HIGH:
1264                 prio = 3;
1265                 break;
1266         case DMA_PRIO_MEDIUM:
1267                 prio = 2;
1268                 break;
1269         case DMA_PRIO_LOW:
1270         default:
1271                 prio = 1;
1272                 break;
1273         }
1274
1275         sdmac->peripheral_type = data->peripheral_type;
1276         sdmac->event_id0 = data->dma_request;
1277         sdmac->event_id1 = data->dma_request2;
1278
1279         ret = clk_enable(sdmac->sdma->clk_ipg);
1280         if (ret)
1281                 return ret;
1282         ret = clk_enable(sdmac->sdma->clk_ahb);
1283         if (ret)
1284                 goto disable_clk_ipg;
1285
1286         ret = sdma_set_channel_priority(sdmac, prio);
1287         if (ret)
1288                 goto disable_clk_ahb;
1289
1290         return 0;
1291
1292 disable_clk_ahb:
1293         clk_disable(sdmac->sdma->clk_ahb);
1294 disable_clk_ipg:
1295         clk_disable(sdmac->sdma->clk_ipg);
1296         return ret;
1297 }
1298
1299 static void sdma_free_chan_resources(struct dma_chan *chan)
1300 {
1301         struct sdma_channel *sdmac = to_sdma_chan(chan);
1302         struct sdma_engine *sdma = sdmac->sdma;
1303
1304         sdma_disable_channel_async(chan);
1305
1306         sdma_channel_synchronize(chan);
1307
1308         if (sdmac->event_id0)
1309                 sdma_event_disable(sdmac, sdmac->event_id0);
1310         if (sdmac->event_id1)
1311                 sdma_event_disable(sdmac, sdmac->event_id1);
1312
1313         sdmac->event_id0 = 0;
1314         sdmac->event_id1 = 0;
1315
1316         sdma_set_channel_priority(sdmac, 0);
1317
1318         clk_disable(sdma->clk_ipg);
1319         clk_disable(sdma->clk_ahb);
1320 }
1321
1322 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1323                                 enum dma_transfer_direction direction, u32 bds)
1324 {
1325         struct sdma_desc *desc;
1326
1327         desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1328         if (!desc)
1329                 goto err_out;
1330
1331         sdmac->status = DMA_IN_PROGRESS;
1332         sdmac->direction = direction;
1333         sdmac->flags = 0;
1334
1335         desc->chn_count = 0;
1336         desc->chn_real_count = 0;
1337         desc->buf_tail = 0;
1338         desc->buf_ptail = 0;
1339         desc->sdmac = sdmac;
1340         desc->num_bd = bds;
1341
1342         if (sdma_alloc_bd(desc))
1343                 goto err_desc_out;
1344
1345         /* No slave_config called in MEMCPY case, so do here */
1346         if (direction == DMA_MEM_TO_MEM)
1347                 sdma_config_ownership(sdmac, false, true, false);
1348
1349         if (sdma_load_context(sdmac))
1350                 goto err_desc_out;
1351
1352         return desc;
1353
1354 err_desc_out:
1355         kfree(desc);
1356 err_out:
1357         return NULL;
1358 }
1359
1360 static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1361                 struct dma_chan *chan, dma_addr_t dma_dst,
1362                 dma_addr_t dma_src, size_t len, unsigned long flags)
1363 {
1364         struct sdma_channel *sdmac = to_sdma_chan(chan);
1365         struct sdma_engine *sdma = sdmac->sdma;
1366         int channel = sdmac->channel;
1367         size_t count;
1368         int i = 0, param;
1369         struct sdma_buffer_descriptor *bd;
1370         struct sdma_desc *desc;
1371
1372         if (!chan || !len)
1373                 return NULL;
1374
1375         dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1376                 &dma_src, &dma_dst, len, channel);
1377
1378         desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1379                                         len / SDMA_BD_MAX_CNT + 1);
1380         if (!desc)
1381                 return NULL;
1382
1383         do {
1384                 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1385                 bd = &desc->bd[i];
1386                 bd->buffer_addr = dma_src;
1387                 bd->ext_buffer_addr = dma_dst;
1388                 bd->mode.count = count;
1389                 desc->chn_count += count;
1390                 bd->mode.command = 0;
1391
1392                 dma_src += count;
1393                 dma_dst += count;
1394                 len -= count;
1395                 i++;
1396
1397                 param = BD_DONE | BD_EXTD | BD_CONT;
1398                 /* last bd */
1399                 if (!len) {
1400                         param |= BD_INTR;
1401                         param |= BD_LAST;
1402                         param &= ~BD_CONT;
1403                 }
1404
1405                 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1406                                 i, count, bd->buffer_addr,
1407                                 param & BD_WRAP ? "wrap" : "",
1408                                 param & BD_INTR ? " intr" : "");
1409
1410                 bd->mode.status = param;
1411         } while (len);
1412
1413         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1414 }
1415
1416 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1417                 struct dma_chan *chan, struct scatterlist *sgl,
1418                 unsigned int sg_len, enum dma_transfer_direction direction,
1419                 unsigned long flags, void *context)
1420 {
1421         struct sdma_channel *sdmac = to_sdma_chan(chan);
1422         struct sdma_engine *sdma = sdmac->sdma;
1423         int i, count;
1424         int channel = sdmac->channel;
1425         struct scatterlist *sg;
1426         struct sdma_desc *desc;
1427
1428         sdma_config_write(chan, &sdmac->slave_config, direction);
1429
1430         desc = sdma_transfer_init(sdmac, direction, sg_len);
1431         if (!desc)
1432                 goto err_out;
1433
1434         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1435                         sg_len, channel);
1436
1437         for_each_sg(sgl, sg, sg_len, i) {
1438                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1439                 int param;
1440
1441                 bd->buffer_addr = sg->dma_address;
1442
1443                 count = sg_dma_len(sg);
1444
1445                 if (count > SDMA_BD_MAX_CNT) {
1446                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1447                                         channel, count, SDMA_BD_MAX_CNT);
1448                         goto err_bd_out;
1449                 }
1450
1451                 bd->mode.count = count;
1452                 desc->chn_count += count;
1453
1454                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1455                         goto err_bd_out;
1456
1457                 switch (sdmac->word_size) {
1458                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1459                         bd->mode.command = 0;
1460                         if (count & 3 || sg->dma_address & 3)
1461                                 goto err_bd_out;
1462                         break;
1463                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1464                         bd->mode.command = 2;
1465                         if (count & 1 || sg->dma_address & 1)
1466                                 goto err_bd_out;
1467                         break;
1468                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1469                         bd->mode.command = 1;
1470                         break;
1471                 default:
1472                         goto err_bd_out;
1473                 }
1474
1475                 param = BD_DONE | BD_EXTD | BD_CONT;
1476
1477                 if (i + 1 == sg_len) {
1478                         param |= BD_INTR;
1479                         param |= BD_LAST;
1480                         param &= ~BD_CONT;
1481                 }
1482
1483                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1484                                 i, count, (u64)sg->dma_address,
1485                                 param & BD_WRAP ? "wrap" : "",
1486                                 param & BD_INTR ? " intr" : "");
1487
1488                 bd->mode.status = param;
1489         }
1490
1491         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1492 err_bd_out:
1493         sdma_free_bd(desc);
1494         kfree(desc);
1495 err_out:
1496         sdmac->status = DMA_ERROR;
1497         return NULL;
1498 }
1499
1500 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1501                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1502                 size_t period_len, enum dma_transfer_direction direction,
1503                 unsigned long flags)
1504 {
1505         struct sdma_channel *sdmac = to_sdma_chan(chan);
1506         struct sdma_engine *sdma = sdmac->sdma;
1507         int num_periods = buf_len / period_len;
1508         int channel = sdmac->channel;
1509         int i = 0, buf = 0;
1510         struct sdma_desc *desc;
1511
1512         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1513
1514         sdma_config_write(chan, &sdmac->slave_config, direction);
1515
1516         desc = sdma_transfer_init(sdmac, direction, num_periods);
1517         if (!desc)
1518                 goto err_out;
1519
1520         desc->period_len = period_len;
1521
1522         sdmac->flags |= IMX_DMA_SG_LOOP;
1523
1524         if (period_len > SDMA_BD_MAX_CNT) {
1525                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1526                                 channel, period_len, SDMA_BD_MAX_CNT);
1527                 goto err_bd_out;
1528         }
1529
1530         while (buf < buf_len) {
1531                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1532                 int param;
1533
1534                 bd->buffer_addr = dma_addr;
1535
1536                 bd->mode.count = period_len;
1537
1538                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1539                         goto err_bd_out;
1540                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1541                         bd->mode.command = 0;
1542                 else
1543                         bd->mode.command = sdmac->word_size;
1544
1545                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1546                 if (i + 1 == num_periods)
1547                         param |= BD_WRAP;
1548
1549                 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1550                                 i, period_len, (u64)dma_addr,
1551                                 param & BD_WRAP ? "wrap" : "",
1552                                 param & BD_INTR ? " intr" : "");
1553
1554                 bd->mode.status = param;
1555
1556                 dma_addr += period_len;
1557                 buf += period_len;
1558
1559                 i++;
1560         }
1561
1562         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1563 err_bd_out:
1564         sdma_free_bd(desc);
1565         kfree(desc);
1566 err_out:
1567         sdmac->status = DMA_ERROR;
1568         return NULL;
1569 }
1570
1571 static int sdma_config_write(struct dma_chan *chan,
1572                        struct dma_slave_config *dmaengine_cfg,
1573                        enum dma_transfer_direction direction)
1574 {
1575         struct sdma_channel *sdmac = to_sdma_chan(chan);
1576
1577         if (direction == DMA_DEV_TO_MEM) {
1578                 sdmac->per_address = dmaengine_cfg->src_addr;
1579                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1580                         dmaengine_cfg->src_addr_width;
1581                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1582         } else if (direction == DMA_DEV_TO_DEV) {
1583                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1584                 sdmac->per_address = dmaengine_cfg->dst_addr;
1585                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1586                         SDMA_WATERMARK_LEVEL_LWML;
1587                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1588                         SDMA_WATERMARK_LEVEL_HWML;
1589                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1590         } else {
1591                 sdmac->per_address = dmaengine_cfg->dst_addr;
1592                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1593                         dmaengine_cfg->dst_addr_width;
1594                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1595         }
1596         sdmac->direction = direction;
1597         return sdma_config_channel(chan);
1598 }
1599
1600 static int sdma_config(struct dma_chan *chan,
1601                        struct dma_slave_config *dmaengine_cfg)
1602 {
1603         struct sdma_channel *sdmac = to_sdma_chan(chan);
1604
1605         memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
1606
1607         /* Set ENBLn earlier to make sure dma request triggered after that */
1608         if (sdmac->event_id0) {
1609                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1610                         return -EINVAL;
1611                 sdma_event_enable(sdmac, sdmac->event_id0);
1612         }
1613
1614         if (sdmac->event_id1) {
1615                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1616                         return -EINVAL;
1617                 sdma_event_enable(sdmac, sdmac->event_id1);
1618         }
1619
1620         return 0;
1621 }
1622
1623 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1624                                       dma_cookie_t cookie,
1625                                       struct dma_tx_state *txstate)
1626 {
1627         struct sdma_channel *sdmac = to_sdma_chan(chan);
1628         struct sdma_desc *desc;
1629         u32 residue;
1630         struct virt_dma_desc *vd;
1631         enum dma_status ret;
1632         unsigned long flags;
1633
1634         ret = dma_cookie_status(chan, cookie, txstate);
1635         if (ret == DMA_COMPLETE || !txstate)
1636                 return ret;
1637
1638         spin_lock_irqsave(&sdmac->vc.lock, flags);
1639         vd = vchan_find_desc(&sdmac->vc, cookie);
1640         if (vd) {
1641                 desc = to_sdma_desc(&vd->tx);
1642                 if (sdmac->flags & IMX_DMA_SG_LOOP)
1643                         residue = (desc->num_bd - desc->buf_ptail) *
1644                                 desc->period_len - desc->chn_real_count;
1645                 else
1646                         residue = desc->chn_count - desc->chn_real_count;
1647         } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
1648                 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count;
1649         } else {
1650                 residue = 0;
1651         }
1652         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1653
1654         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1655                          residue);
1656
1657         return sdmac->status;
1658 }
1659
1660 static void sdma_issue_pending(struct dma_chan *chan)
1661 {
1662         struct sdma_channel *sdmac = to_sdma_chan(chan);
1663         unsigned long flags;
1664
1665         spin_lock_irqsave(&sdmac->vc.lock, flags);
1666         if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1667                 sdma_start_desc(sdmac);
1668         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1669 }
1670
1671 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1672 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1673 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1674 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1675
1676 static void sdma_add_scripts(struct sdma_engine *sdma,
1677                 const struct sdma_script_start_addrs *addr)
1678 {
1679         s32 *addr_arr = (u32 *)addr;
1680         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1681         int i;
1682
1683         /* use the default firmware in ROM if missing external firmware */
1684         if (!sdma->script_number)
1685                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1686
1687         if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1688                                   / sizeof(s32)) {
1689                 dev_err(sdma->dev,
1690                         "SDMA script number %d not match with firmware.\n",
1691                         sdma->script_number);
1692                 return;
1693         }
1694
1695         for (i = 0; i < sdma->script_number; i++)
1696                 if (addr_arr[i] > 0)
1697                         saddr_arr[i] = addr_arr[i];
1698 }
1699
1700 static void sdma_load_firmware(const struct firmware *fw, void *context)
1701 {
1702         struct sdma_engine *sdma = context;
1703         const struct sdma_firmware_header *header;
1704         const struct sdma_script_start_addrs *addr;
1705         unsigned short *ram_code;
1706
1707         if (!fw) {
1708                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1709                 /* In this case we just use the ROM firmware. */
1710                 return;
1711         }
1712
1713         if (fw->size < sizeof(*header))
1714                 goto err_firmware;
1715
1716         header = (struct sdma_firmware_header *)fw->data;
1717
1718         if (header->magic != SDMA_FIRMWARE_MAGIC)
1719                 goto err_firmware;
1720         if (header->ram_code_start + header->ram_code_size > fw->size)
1721                 goto err_firmware;
1722         switch (header->version_major) {
1723         case 1:
1724                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1725                 break;
1726         case 2:
1727                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1728                 break;
1729         case 3:
1730                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1731                 break;
1732         case 4:
1733                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1734                 break;
1735         default:
1736                 dev_err(sdma->dev, "unknown firmware version\n");
1737                 goto err_firmware;
1738         }
1739
1740         addr = (void *)header + header->script_addrs_start;
1741         ram_code = (void *)header + header->ram_code_start;
1742
1743         clk_enable(sdma->clk_ipg);
1744         clk_enable(sdma->clk_ahb);
1745         /* download the RAM image for SDMA */
1746         sdma_load_script(sdma, ram_code,
1747                         header->ram_code_size,
1748                         addr->ram_code_start_addr);
1749         clk_disable(sdma->clk_ipg);
1750         clk_disable(sdma->clk_ahb);
1751
1752         sdma_add_scripts(sdma, addr);
1753
1754         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1755                         header->version_major,
1756                         header->version_minor);
1757
1758 err_firmware:
1759         release_firmware(fw);
1760 }
1761
1762 #define EVENT_REMAP_CELLS 3
1763
1764 static int sdma_event_remap(struct sdma_engine *sdma)
1765 {
1766         struct device_node *np = sdma->dev->of_node;
1767         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1768         struct property *event_remap;
1769         struct regmap *gpr;
1770         char propname[] = "fsl,sdma-event-remap";
1771         u32 reg, val, shift, num_map, i;
1772         int ret = 0;
1773
1774         if (IS_ERR(np) || !gpr_np)
1775                 goto out;
1776
1777         event_remap = of_find_property(np, propname, NULL);
1778         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1779         if (!num_map) {
1780                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1781                 goto out;
1782         } else if (num_map % EVENT_REMAP_CELLS) {
1783                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1784                                 propname, EVENT_REMAP_CELLS);
1785                 ret = -EINVAL;
1786                 goto out;
1787         }
1788
1789         gpr = syscon_node_to_regmap(gpr_np);
1790         if (IS_ERR(gpr)) {
1791                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1792                 ret = PTR_ERR(gpr);
1793                 goto out;
1794         }
1795
1796         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1797                 ret = of_property_read_u32_index(np, propname, i, &reg);
1798                 if (ret) {
1799                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1800                                         propname, i);
1801                         goto out;
1802                 }
1803
1804                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1805                 if (ret) {
1806                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1807                                         propname, i + 1);
1808                         goto out;
1809                 }
1810
1811                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1812                 if (ret) {
1813                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1814                                         propname, i + 2);
1815                         goto out;
1816                 }
1817
1818                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1819         }
1820
1821 out:
1822         if (gpr_np)
1823                 of_node_put(gpr_np);
1824
1825         return ret;
1826 }
1827
1828 static int sdma_get_firmware(struct sdma_engine *sdma,
1829                 const char *fw_name)
1830 {
1831         int ret;
1832
1833         ret = reject_firmware_nowait(THIS_MODULE,
1834                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1835                         GFP_KERNEL, sdma, sdma_load_firmware);
1836
1837         return ret;
1838 }
1839
1840 static int sdma_init(struct sdma_engine *sdma)
1841 {
1842         int i, ret;
1843         dma_addr_t ccb_phys;
1844
1845         ret = clk_enable(sdma->clk_ipg);
1846         if (ret)
1847                 return ret;
1848         ret = clk_enable(sdma->clk_ahb);
1849         if (ret)
1850                 goto disable_clk_ipg;
1851
1852         /* Be sure SDMA has not started yet */
1853         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1854
1855         sdma->channel_control = dma_alloc_coherent(NULL,
1856                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1857                         sizeof(struct sdma_context_data),
1858                         &ccb_phys, GFP_KERNEL);
1859
1860         if (!sdma->channel_control) {
1861                 ret = -ENOMEM;
1862                 goto err_dma_alloc;
1863         }
1864
1865         sdma->context = (void *)sdma->channel_control +
1866                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1867         sdma->context_phys = ccb_phys +
1868                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1869
1870         /* Zero-out the CCB structures array just allocated */
1871         memset(sdma->channel_control, 0,
1872                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1873
1874         /* disable all channels */
1875         for (i = 0; i < sdma->drvdata->num_events; i++)
1876                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1877
1878         /* All channels have priority 0 */
1879         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1880                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1881
1882         ret = sdma_request_channel0(sdma);
1883         if (ret)
1884                 goto err_dma_alloc;
1885
1886         sdma_config_ownership(&sdma->channel[0], false, true, false);
1887
1888         /* Set Command Channel (Channel Zero) */
1889         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1890
1891         /* Set bits of CONFIG register but with static context switching */
1892         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1893         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1894
1895         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1896
1897         /* Initializes channel's priorities */
1898         sdma_set_channel_priority(&sdma->channel[0], 7);
1899
1900         clk_disable(sdma->clk_ipg);
1901         clk_disable(sdma->clk_ahb);
1902
1903         return 0;
1904
1905 err_dma_alloc:
1906         clk_disable(sdma->clk_ahb);
1907 disable_clk_ipg:
1908         clk_disable(sdma->clk_ipg);
1909         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1910         return ret;
1911 }
1912
1913 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1914 {
1915         struct sdma_channel *sdmac = to_sdma_chan(chan);
1916         struct imx_dma_data *data = fn_param;
1917
1918         if (!imx_dma_is_general_purpose(chan))
1919                 return false;
1920
1921         sdmac->data = *data;
1922         chan->private = &sdmac->data;
1923
1924         return true;
1925 }
1926
1927 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1928                                    struct of_dma *ofdma)
1929 {
1930         struct sdma_engine *sdma = ofdma->of_dma_data;
1931         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1932         struct imx_dma_data data;
1933
1934         if (dma_spec->args_count != 3)
1935                 return NULL;
1936
1937         data.dma_request = dma_spec->args[0];
1938         data.peripheral_type = dma_spec->args[1];
1939         data.priority = dma_spec->args[2];
1940         /*
1941          * init dma_request2 to zero, which is not used by the dts.
1942          * For P2P, dma_request2 is init from dma_request_channel(),
1943          * chan->private will point to the imx_dma_data, and in
1944          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1945          * be set to sdmac->event_id1.
1946          */
1947         data.dma_request2 = 0;
1948
1949         return dma_request_channel(mask, sdma_filter_fn, &data);
1950 }
1951
1952 static int sdma_probe(struct platform_device *pdev)
1953 {
1954         const struct of_device_id *of_id =
1955                         of_match_device(sdma_dt_ids, &pdev->dev);
1956         struct device_node *np = pdev->dev.of_node;
1957         struct device_node *spba_bus;
1958         const char *fw_name;
1959         int ret;
1960         int irq;
1961         struct resource *iores;
1962         struct resource spba_res;
1963         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1964         int i;
1965         struct sdma_engine *sdma;
1966         s32 *saddr_arr;
1967         const struct sdma_driver_data *drvdata = NULL;
1968
1969         if (of_id)
1970                 drvdata = of_id->data;
1971         else if (pdev->id_entry)
1972                 drvdata = (void *)pdev->id_entry->driver_data;
1973
1974         if (!drvdata) {
1975                 dev_err(&pdev->dev, "unable to find driver data\n");
1976                 return -EINVAL;
1977         }
1978
1979         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1980         if (ret)
1981                 return ret;
1982
1983         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1984         if (!sdma)
1985                 return -ENOMEM;
1986
1987         spin_lock_init(&sdma->channel_0_lock);
1988
1989         sdma->dev = &pdev->dev;
1990         sdma->drvdata = drvdata;
1991
1992         irq = platform_get_irq(pdev, 0);
1993         if (irq < 0)
1994                 return irq;
1995
1996         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1997         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1998         if (IS_ERR(sdma->regs))
1999                 return PTR_ERR(sdma->regs);
2000
2001         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2002         if (IS_ERR(sdma->clk_ipg))
2003                 return PTR_ERR(sdma->clk_ipg);
2004
2005         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2006         if (IS_ERR(sdma->clk_ahb))
2007                 return PTR_ERR(sdma->clk_ahb);
2008
2009         ret = clk_prepare(sdma->clk_ipg);
2010         if (ret)
2011                 return ret;
2012
2013         ret = clk_prepare(sdma->clk_ahb);
2014         if (ret)
2015                 goto err_clk;
2016
2017         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
2018                                sdma);
2019         if (ret)
2020                 goto err_irq;
2021
2022         sdma->irq = irq;
2023
2024         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2025         if (!sdma->script_addrs) {
2026                 ret = -ENOMEM;
2027                 goto err_irq;
2028         }
2029
2030         /* initially no scripts available */
2031         saddr_arr = (s32 *)sdma->script_addrs;
2032         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
2033                 saddr_arr[i] = -EINVAL;
2034
2035         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2036         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2037         dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2038
2039         INIT_LIST_HEAD(&sdma->dma_device.channels);
2040         /* Initialize channel parameters */
2041         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2042                 struct sdma_channel *sdmac = &sdma->channel[i];
2043
2044                 sdmac->sdma = sdma;
2045
2046                 sdmac->channel = i;
2047                 sdmac->vc.desc_free = sdma_desc_free;
2048                 INIT_WORK(&sdmac->terminate_worker,
2049                                 sdma_channel_terminate_work);
2050                 /*
2051                  * Add the channel to the DMAC list. Do not add channel 0 though
2052                  * because we need it internally in the SDMA driver. This also means
2053                  * that channel 0 in dmaengine counting matches sdma channel 1.
2054                  */
2055                 if (i)
2056                         vchan_init(&sdmac->vc, &sdma->dma_device);
2057         }
2058
2059         ret = sdma_init(sdma);
2060         if (ret)
2061                 goto err_init;
2062
2063         ret = sdma_event_remap(sdma);
2064         if (ret)
2065                 goto err_init;
2066
2067         if (sdma->drvdata->script_addrs)
2068                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2069         if (pdata && pdata->script_addrs)
2070                 sdma_add_scripts(sdma, pdata->script_addrs);
2071
2072         sdma->dma_device.dev = &pdev->dev;
2073
2074         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2075         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2076         sdma->dma_device.device_tx_status = sdma_tx_status;
2077         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2078         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2079         sdma->dma_device.device_config = sdma_config;
2080         sdma->dma_device.device_terminate_all = sdma_disable_channel_async;
2081         sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2082         sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2083         sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2084         sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2085         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2086         sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2087         sdma->dma_device.device_issue_pending = sdma_issue_pending;
2088         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
2089         dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2090
2091         platform_set_drvdata(pdev, sdma);
2092
2093         ret = dma_async_device_register(&sdma->dma_device);
2094         if (ret) {
2095                 dev_err(&pdev->dev, "unable to register\n");
2096                 goto err_init;
2097         }
2098
2099         if (np) {
2100                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2101                 if (ret) {
2102                         dev_err(&pdev->dev, "failed to register controller\n");
2103                         goto err_register;
2104                 }
2105
2106                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
2107                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
2108                 if (!ret) {
2109                         sdma->spba_start_addr = spba_res.start;
2110                         sdma->spba_end_addr = spba_res.end;
2111                 }
2112                 of_node_put(spba_bus);
2113         }
2114
2115         /*
2116          * Kick off firmware loading as the very last step:
2117          * attempt to load firmware only if we're not on the error path, because
2118          * the firmware callback requires a fully functional and allocated sdma
2119          * instance.
2120          */
2121         if (pdata) {
2122                 ret = sdma_get_firmware(sdma, pdata->fw_name);
2123                 if (ret)
2124                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
2125         } else {
2126                 /*
2127                  * Because that device tree does not encode ROM script address,
2128                  * the RAM script in firmware is mandatory for device tree
2129                  * probe, otherwise it fails.
2130                  */
2131                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2132                                               &fw_name);
2133                 if (ret) {
2134                         dev_warn(&pdev->dev, "failed to get firmware name\n");
2135                 } else {
2136                         ret = sdma_get_firmware(sdma, fw_name);
2137                         if (ret)
2138                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2139                 }
2140         }
2141
2142         return 0;
2143
2144 err_register:
2145         dma_async_device_unregister(&sdma->dma_device);
2146 err_init:
2147         kfree(sdma->script_addrs);
2148 err_irq:
2149         clk_unprepare(sdma->clk_ahb);
2150 err_clk:
2151         clk_unprepare(sdma->clk_ipg);
2152         return ret;
2153 }
2154
2155 static int sdma_remove(struct platform_device *pdev)
2156 {
2157         struct sdma_engine *sdma = platform_get_drvdata(pdev);
2158         int i;
2159
2160         devm_free_irq(&pdev->dev, sdma->irq, sdma);
2161         dma_async_device_unregister(&sdma->dma_device);
2162         kfree(sdma->script_addrs);
2163         clk_unprepare(sdma->clk_ahb);
2164         clk_unprepare(sdma->clk_ipg);
2165         /* Kill the tasklet */
2166         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2167                 struct sdma_channel *sdmac = &sdma->channel[i];
2168
2169                 tasklet_kill(&sdmac->vc.task);
2170                 sdma_free_chan_resources(&sdmac->vc.chan);
2171         }
2172
2173         platform_set_drvdata(pdev, NULL);
2174         return 0;
2175 }
2176
2177 static struct platform_driver sdma_driver = {
2178         .driver         = {
2179                 .name   = "imx-sdma",
2180                 .of_match_table = sdma_dt_ids,
2181         },
2182         .id_table       = sdma_devtypes,
2183         .remove         = sdma_remove,
2184         .probe          = sdma_probe,
2185 };
2186
2187 module_platform_driver(sdma_driver);
2188
2189 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2190 MODULE_DESCRIPTION("i.MX SDMA driver");
2191 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2192 /*(DEBLOBBED)*/
2193 #endif
2194 #if IS_ENABLED(CONFIG_SOC_IMX7D)
2195 /*(DEBLOBBED)*/
2196 #endif
2197 MODULE_LICENSE("GPL");