drivers/edac/ghes_edac.c

   1 /*
   2  * GHES/EDAC Linux driver
   3  *
   4  * This file may be distributed under the terms of the GNU General Public
   5  * License version 2.
   6  *
   7  * Copyright (c) 2013 by Mauro Carvalho Chehab
   8  *
   9  * Red Hat Inc. http://www.redhat.com
  10  */
  11
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <acpi/ghes.h>
  15 #include <linux/edac.h>
  16 #include <linux/dmi.h>
  17 #include "edac_module.h"
  18 #include <ras/ras_event.h>
  19
  20 struct ghes_edac_pvt {
  21         struct list_head list;
  22         struct ghes *ghes;
  23         struct mem_ctl_info *mci;
  24
  25         /* Buffers for the error handling routine */
  26         char detail_location[240];
  27         char other_detail[160];
  28         char msg[80];
  29 };
  30
  31 static atomic_t ghes_init = ATOMIC_INIT(0);
  32 static struct ghes_edac_pvt *ghes_pvt;
  33
  34 /*
  35  * Sync with other, potentially concurrent callers of
  36  * ghes_edac_report_mem_error(). We don't know what the
  37  * "inventive" firmware would do.
  38  */
  39 static DEFINE_SPINLOCK(ghes_lock);
  40
  41 /* "ghes_edac.force_load=1" skips the platform check */
  42 static bool __read_mostly force_load;
  43 module_param(force_load, bool, 0);
  44
  45 /* Memory Device - Type 17 of SMBIOS spec */
  46 struct memdev_dmi_entry {
  47         u8 type;
  48         u8 length;
  49         u16 handle;
  50         u16 phys_mem_array_handle;
  51         u16 mem_err_info_handle;
  52         u16 total_width;
  53         u16 data_width;
  54         u16 size;
  55         u8 form_factor;
  56         u8 device_set;
  57         u8 device_locator;
  58         u8 bank_locator;
  59         u8 memory_type;
  60         u16 type_detail;
  61         u16 speed;
  62         u8 manufacturer;
  63         u8 serial_number;
  64         u8 asset_tag;
  65         u8 part_number;
  66         u8 attributes;
  67         u32 extended_size;
  68         u16 conf_mem_clk_speed;
  69 } __attribute__((__packed__));
  70
  71 struct ghes_edac_dimm_fill {
  72         struct mem_ctl_info *mci;
  73         unsigned count;
  74 };
  75
  76 static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
  77 {
  78         int *num_dimm = arg;
  79
  80         if (dh->type == DMI_ENTRY_MEM_DEVICE)
  81                 (*num_dimm)++;
  82 }
  83
  84 static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
  85 {
  86         struct ghes_edac_dimm_fill *dimm_fill = arg;
  87         struct mem_ctl_info *mci = dimm_fill->mci;
  88
  89         if (dh->type == DMI_ENTRY_MEM_DEVICE) {
  90                 struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
  91                 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
  92                                                        mci->n_layers,
  93                                                        dimm_fill->count, 0, 0);
  94                 u16 rdr_mask = BIT(7) | BIT(13);
  95
  96                 if (entry->size == 0xffff) {
  97                         pr_info("Can't get DIMM%i size\n",
  98                                 dimm_fill->count);
  99                         dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
 100                 } else if (entry->size == 0x7fff) {
 101                         dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
 102                 } else {
 103                         if (entry->size & BIT(15))
 104                                 dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
 105                         else
 106                                 dimm->nr_pages = MiB_TO_PAGES(entry->size);
 107                 }
 108
 109                 switch (entry->memory_type) {
 110                 case 0x12:
 111                         if (entry->type_detail & BIT(13))
 112                                 dimm->mtype = MEM_RDDR;
 113                         else
 114                                 dimm->mtype = MEM_DDR;
 115                         break;
 116                 case 0x13:
 117                         if (entry->type_detail & BIT(13))
 118                                 dimm->mtype = MEM_RDDR2;
 119                         else
 120                                 dimm->mtype = MEM_DDR2;
 121                         break;
 122                 case 0x14:
 123                         dimm->mtype = MEM_FB_DDR2;
 124                         break;
 125                 case 0x18:
 126                         if (entry->type_detail & BIT(12))
 127                                 dimm->mtype = MEM_NVDIMM;
 128                         else if (entry->type_detail & BIT(13))
 129                                 dimm->mtype = MEM_RDDR3;
 130                         else
 131                                 dimm->mtype = MEM_DDR3;
 132                         break;
 133                 case 0x1a:
 134                         if (entry->type_detail & BIT(12))
 135                                 dimm->mtype = MEM_NVDIMM;
 136                         else if (entry->type_detail & BIT(13))
 137                                 dimm->mtype = MEM_RDDR4;
 138                         else
 139                                 dimm->mtype = MEM_DDR4;
 140                         break;
 141                 default:
 142                         if (entry->type_detail & BIT(6))
 143                                 dimm->mtype = MEM_RMBS;
 144                         else if ((entry->type_detail & rdr_mask) == rdr_mask)
 145                                 dimm->mtype = MEM_RDR;
 146                         else if (entry->type_detail & BIT(7))
 147                                 dimm->mtype = MEM_SDR;
 148                         else if (entry->type_detail & BIT(9))
 149                                 dimm->mtype = MEM_EDO;
 150                         else
 151                                 dimm->mtype = MEM_UNKNOWN;
 152                 }
 153
 154                 /*
 155                  * Actually, we can only detect if the memory has bits for
 156                  * checksum or not
 157                  */
 158                 if (entry->total_width == entry->data_width)
 159                         dimm->edac_mode = EDAC_NONE;
 160                 else
 161                         dimm->edac_mode = EDAC_SECDED;
 162
 163                 dimm->dtype = DEV_UNKNOWN;
 164                 dimm->grain = 128;              /* Likely, worse case */
 165
 166                 /*
 167                  * FIXME: It shouldn't be hard to also fill the DIMM labels
 168                  */
 169
 170                 if (dimm->nr_pages) {
 171                         edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
 172                                 dimm_fill->count, edac_mem_types[dimm->mtype],
 173                                 PAGES_TO_MiB(dimm->nr_pages),
 174                                 (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
 175                         edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
 176                                 entry->memory_type, entry->type_detail,
 177                                 entry->total_width, entry->data_width);
 178                 }
 179
 180                 dimm_fill->count++;
 181         }
 182 }
 183
 184 void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
 185 {
 186         enum hw_event_mc_err_type type;
 187         struct edac_raw_error_desc *e;
 188         struct mem_ctl_info *mci;
 189         struct ghes_edac_pvt *pvt = ghes_pvt;
 190         unsigned long flags;
 191         char *p;
 192         u8 grain_bits;
 193
 194         if (!pvt)
 195                 return;
 196
 197         /*
 198          * We can do the locking below because GHES defers error processing
 199          * from NMI to IRQ context. Whenever that changes, we'd at least
 200          * know.
 201          */
 202         if (WARN_ON_ONCE(in_nmi()))
 203                 return;
 204
 205         spin_lock_irqsave(&ghes_lock, flags);
 206
 207         mci = pvt->mci;
 208         e = &mci->error_desc;
 209
 210         /* Cleans the error report buffer */
 211         memset(e, 0, sizeof (*e));
 212         e->error_count = 1;
 213         e->grain = 1;
 214         strcpy(e->label, "unknown label");
 215         e->msg = pvt->msg;
 216         e->other_detail = pvt->other_detail;
 217         e->top_layer = -1;
 218         e->mid_layer = -1;
 219         e->low_layer = -1;
 220         *pvt->other_detail = '\0';
 221         *pvt->msg = '\0';
 222
 223         switch (sev) {
 224         case GHES_SEV_CORRECTED:
 225                 type = HW_EVENT_ERR_CORRECTED;
 226                 break;
 227         case GHES_SEV_RECOVERABLE:
 228                 type = HW_EVENT_ERR_UNCORRECTED;
 229                 break;
 230         case GHES_SEV_PANIC:
 231                 type = HW_EVENT_ERR_FATAL;
 232                 break;
 233         default:
 234         case GHES_SEV_NO:
 235                 type = HW_EVENT_ERR_INFO;
 236         }
 237
 238         edac_dbg(1, "error validation_bits: 0x%08llx\n",
 239                  (long long)mem_err->validation_bits);
 240
 241         /* Error type, mapped on e->msg */
 242         if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
 243                 p = pvt->msg;
 244                 switch (mem_err->error_type) {
 245                 case 0:
 246                         p += sprintf(p, "Unknown");
 247                         break;
 248                 case 1:
 249                         p += sprintf(p, "No error");
 250                         break;
 251                 case 2:
 252                         p += sprintf(p, "Single-bit ECC");
 253                         break;
 254                 case 3:
 255                         p += sprintf(p, "Multi-bit ECC");
 256                         break;
 257                 case 4:
 258                         p += sprintf(p, "Single-symbol ChipKill ECC");
 259                         break;
 260                 case 5:
 261                         p += sprintf(p, "Multi-symbol ChipKill ECC");
 262                         break;
 263                 case 6:
 264                         p += sprintf(p, "Master abort");
 265                         break;
 266                 case 7:
 267                         p += sprintf(p, "Target abort");
 268                         break;
 269                 case 8:
 270                         p += sprintf(p, "Parity Error");
 271                         break;
 272                 case 9:
 273                         p += sprintf(p, "Watchdog timeout");
 274                         break;
 275                 case 10:
 276                         p += sprintf(p, "Invalid address");
 277                         break;
 278                 case 11:
 279                         p += sprintf(p, "Mirror Broken");
 280                         break;
 281                 case 12:
 282                         p += sprintf(p, "Memory Sparing");
 283                         break;
 284                 case 13:
 285                         p += sprintf(p, "Scrub corrected error");
 286                         break;
 287                 case 14:
 288                         p += sprintf(p, "Scrub uncorrected error");
 289                         break;
 290                 case 15:
 291                         p += sprintf(p, "Physical Memory Map-out event");
 292                         break;
 293                 default:
 294                         p += sprintf(p, "reserved error (%d)",
 295                                      mem_err->error_type);
 296                 }
 297         } else {
 298                 strcpy(pvt->msg, "unknown error");
 299         }
 300
 301         /* Error address */
 302         if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
 303                 e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
 304                 e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
 305         }
 306
 307         /* Error grain */
 308         if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
 309                 e->grain = ~mem_err->physical_addr_mask + 1;
 310
 311         /* Memory error location, mapped on e->location */
 312         p = e->location;
 313         if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
 314                 p += sprintf(p, "node:%d ", mem_err->node);
 315         if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
 316                 p += sprintf(p, "card:%d ", mem_err->card);
 317         if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
 318                 p += sprintf(p, "module:%d ", mem_err->module);
 319         if (mem_err->validation_bits & CPER_MEM_VALID_RANK_NUMBER)
 320                 p += sprintf(p, "rank:%d ", mem_err->rank);
 321         if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
 322                 p += sprintf(p, "bank:%d ", mem_err->bank);
 323         if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
 324                 p += sprintf(p, "row:%d ", mem_err->row);
 325         if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
 326                 p += sprintf(p, "col:%d ", mem_err->column);
 327         if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
 328                 p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
 329         if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
 330                 const char *bank = NULL, *device = NULL;
 331                 dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
 332                 if (bank != NULL && device != NULL)
 333                         p += sprintf(p, "DIMM location:%s %s ", bank, device);
 334                 else
 335                         p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
 336                                      mem_err->mem_dev_handle);
 337         }
 338         if (p > e->location)
 339                 *(p - 1) = '\0';
 340
 341         /* All other fields are mapped on e->other_detail */
 342         p = pvt->other_detail;
 343         if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
 344                 u64 status = mem_err->error_status;
 345
 346                 p += sprintf(p, "status(0x%016llx): ", (long long)status);
 347                 switch ((status >> 8) & 0xff) {
 348                 case 1:
 349                         p += sprintf(p, "Error detected internal to the component ");
 350                         break;
 351                 case 16:
 352                         p += sprintf(p, "Error detected in the bus ");
 353                         break;
 354                 case 4:
 355                         p += sprintf(p, "Storage error in DRAM memory ");
 356                         break;
 357                 case 5:
 358                         p += sprintf(p, "Storage error in TLB ");
 359                         break;
 360                 case 6:
 361                         p += sprintf(p, "Storage error in cache ");
 362                         break;
 363                 case 7:
 364                         p += sprintf(p, "Error in one or more functional units ");
 365                         break;
 366                 case 8:
 367                         p += sprintf(p, "component failed self test ");
 368                         break;
 369                 case 9:
 370                         p += sprintf(p, "Overflow or undervalue of internal queue ");
 371                         break;
 372                 case 17:
 373                         p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
 374                         break;
 375                 case 18:
 376                         p += sprintf(p, "Improper access error ");
 377                         break;
 378                 case 19:
 379                         p += sprintf(p, "Access to a memory address which is not mapped to any component ");
 380                         break;
 381                 case 20:
 382                         p += sprintf(p, "Loss of Lockstep ");
 383                         break;
 384                 case 21:
 385                         p += sprintf(p, "Response not associated with a request ");
 386                         break;
 387                 case 22:
 388                         p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
 389                         break;
 390                 case 23:
 391                         p += sprintf(p, "Detection of a PATH_ERROR ");
 392                         break;
 393                 case 25:
 394                         p += sprintf(p, "Bus operation timeout ");
 395                         break;
 396                 case 26:
 397                         p += sprintf(p, "A read was issued to data that has been poisoned ");
 398                         break;
 399                 default:
 400                         p += sprintf(p, "reserved ");
 401                         break;
 402                 }
 403         }
 404         if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
 405                 p += sprintf(p, "requestorID: 0x%016llx ",
 406                              (long long)mem_err->requestor_id);
 407         if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
 408                 p += sprintf(p, "responderID: 0x%016llx ",
 409                              (long long)mem_err->responder_id);
 410         if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
 411                 p += sprintf(p, "targetID: 0x%016llx ",
 412                              (long long)mem_err->responder_id);
 413         if (p > pvt->other_detail)
 414                 *(p - 1) = '\0';
 415
 416         /* Sanity-check driver-supplied grain value. */
 417         if (WARN_ON_ONCE(!e->grain))
 418                 e->grain = 1;
 419
 420         grain_bits = fls_long(e->grain - 1);
 421
 422         /* Generate the trace event */
 423         snprintf(pvt->detail_location, sizeof(pvt->detail_location),
 424                  "APEI location: %s %s", e->location, e->other_detail);
 425         trace_mc_event(type, e->msg, e->label, e->error_count,
 426                        mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
 427                        (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
 428                        grain_bits, e->syndrome, pvt->detail_location);
 429
 430         edac_raw_mc_handle_error(type, mci, e);
 431         spin_unlock_irqrestore(&ghes_lock, flags);
 432 }
 433
 434 /*
 435  * Known systems that are safe to enable this module.
 436  */
 437 static struct acpi_platform_list plat_list[] = {
 438         {"HPE   ", "Server  ", 0, ACPI_SIG_FADT, all_versions},
 439         { } /* End */
 440 };
 441
 442 int ghes_edac_register(struct ghes *ghes, struct device *dev)
 443 {
 444         bool fake = false;
 445         int rc, num_dimm = 0;
 446         struct mem_ctl_info *mci;
 447         struct edac_mc_layer layers[1];
 448         struct ghes_edac_dimm_fill dimm_fill;
 449         int idx = -1;
 450
 451         if (IS_ENABLED(CONFIG_X86)) {
 452                 /* Check if safe to enable on this system */
 453                 idx = acpi_match_platform_list(plat_list);
 454                 if (!force_load && idx < 0)
 455                         return -ENODEV;
 456         } else {
 457                 idx = 0;
 458         }
 459
 460         /*
 461          * We have only one logical memory controller to which all DIMMs belong.
 462          */
 463         if (atomic_inc_return(&ghes_init) > 1)
 464                 return 0;
 465
 466         /* Get the number of DIMMs */
 467         dmi_walk(ghes_edac_count_dimms, &num_dimm);
 468
 469         /* Check if we've got a bogus BIOS */
 470         if (num_dimm == 0) {
 471                 fake = true;
 472                 num_dimm = 1;
 473         }
 474
 475         layers[0].type = EDAC_MC_LAYER_ALL_MEM;
 476         layers[0].size = num_dimm;
 477         layers[0].is_virt_csrow = true;
 478
 479         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
 480         if (!mci) {
 481                 pr_info("Can't allocate memory for EDAC data\n");
 482                 return -ENOMEM;
 483         }
 484
 485         ghes_pvt        = mci->pvt_info;
 486         ghes_pvt->ghes  = ghes;
 487         ghes_pvt->mci   = mci;
 488
 489         mci->pdev = dev;
 490         mci->mtype_cap = MEM_FLAG_EMPTY;
 491         mci->edac_ctl_cap = EDAC_FLAG_NONE;
 492         mci->edac_cap = EDAC_FLAG_NONE;
 493         mci->mod_name = "ghes_edac.c";
 494         mci->ctl_name = "ghes_edac";
 495         mci->dev_name = "ghes";
 496
 497         if (fake) {
 498                 pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
 499                 pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
 500                 pr_info("work on such system. Use this driver with caution\n");
 501         } else if (idx < 0) {
 502                 pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
 503                 pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
 504                 pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
 505                 pr_info("If you find incorrect reports, please contact your hardware vendor\n");
 506                 pr_info("to correct its BIOS.\n");
 507                 pr_info("This system has %d DIMM sockets.\n", num_dimm);
 508         }
 509
 510         if (!fake) {
 511                 dimm_fill.count = 0;
 512                 dimm_fill.mci = mci;
 513                 dmi_walk(ghes_edac_dmidecode, &dimm_fill);
 514         } else {
 515                 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
 516                                                        mci->n_layers, 0, 0, 0);
 517
 518                 dimm->nr_pages = 1;
 519                 dimm->grain = 128;
 520                 dimm->mtype = MEM_UNKNOWN;
 521                 dimm->dtype = DEV_UNKNOWN;
 522                 dimm->edac_mode = EDAC_SECDED;
 523         }
 524
 525         rc = edac_mc_add_mc(mci);
 526         if (rc < 0) {
 527                 pr_info("Can't register at EDAC core\n");
 528                 edac_mc_free(mci);
 529                 return -ENODEV;
 530         }
 531         return 0;
 532 }
 533
 534 void ghes_edac_unregister(struct ghes *ghes)
 535 {
 536         struct mem_ctl_info *mci;
 537
 538         if (!ghes_pvt)
 539                 return;
 540
 541         if (atomic_dec_return(&ghes_init))
 542                 return;
 543
 544         mci = ghes_pvt->mci;
 545         ghes_pvt = NULL;
 546         edac_mc_del_mc(mci->pdev);
 547         edac_mc_free(mci);
 548 }