2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2016 Freescale Semiconductor Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
17 #include <linux/of_gpio.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/slab.h>
22 #include <linux/irq.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/bitops.h>
26 #define MPC8XXX_GPIO_PINS 32
34 #define GPIO_ICR2 0x18
36 struct mpc8xxx_gpio_chip {
41 int (*direction_output)(struct gpio_chip *chip,
42 unsigned offset, int value);
44 struct irq_domain *irq;
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
50 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
51 * This inline helper give the right bitmask for a certain line.
53 static inline u32 mpc_pin2mask(unsigned int offset)
55 return BIT(31 - offset);
58 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
59 * defined as output cannot be determined by reading GPDAT register,
60 * so we use shadow data register instead. The status of input pins
61 * is determined by reading GPDAT register.
63 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
66 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
67 u32 out_mask, out_shadow;
69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
71 out_shadow = gc->bgpio_data & out_mask;
73 return !!((val | out_shadow) & mpc_pin2mask(gpio));
76 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
77 unsigned int gpio, int val)
79 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
80 /* GPIO 28..31 are input only on MPC5121 */
84 return mpc8xxx_gc->direction_output(gc, gpio, val);
87 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
88 unsigned int gpio, int val)
90 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
91 /* GPIO 0..3 are input only on MPC5125 */
95 return mpc8xxx_gc->direction_output(gc, gpio, val);
98 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
100 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
102 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
103 return irq_create_mapping(mpc8xxx_gc->irq, offset);
108 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
110 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
111 struct irq_chip *chip = irq_desc_get_chip(desc);
112 struct gpio_chip *gc = &mpc8xxx_gc->gc;
115 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
116 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
118 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
121 chip->irq_eoi(&desc->irq_data);
124 static void mpc8xxx_irq_unmask(struct irq_data *d)
126 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
127 struct gpio_chip *gc = &mpc8xxx_gc->gc;
130 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
132 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
133 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
134 | mpc_pin2mask(irqd_to_hwirq(d)));
136 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
139 static void mpc8xxx_irq_mask(struct irq_data *d)
141 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
142 struct gpio_chip *gc = &mpc8xxx_gc->gc;
145 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
147 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
148 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
149 & ~mpc_pin2mask(irqd_to_hwirq(d)));
151 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
154 static void mpc8xxx_irq_ack(struct irq_data *d)
156 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
157 struct gpio_chip *gc = &mpc8xxx_gc->gc;
159 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
160 mpc_pin2mask(irqd_to_hwirq(d)));
163 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
165 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
166 struct gpio_chip *gc = &mpc8xxx_gc->gc;
170 case IRQ_TYPE_EDGE_FALLING:
171 case IRQ_TYPE_LEVEL_LOW:
172 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
173 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
174 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
175 | mpc_pin2mask(irqd_to_hwirq(d)));
176 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
179 case IRQ_TYPE_EDGE_BOTH:
180 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
181 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
182 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
183 & ~mpc_pin2mask(irqd_to_hwirq(d)));
184 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
194 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
196 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
197 struct gpio_chip *gc = &mpc8xxx_gc->gc;
198 unsigned long gpio = irqd_to_hwirq(d);
204 reg = mpc8xxx_gc->regs + GPIO_ICR;
205 shift = (15 - gpio) * 2;
207 reg = mpc8xxx_gc->regs + GPIO_ICR2;
208 shift = (15 - (gpio % 16)) * 2;
212 case IRQ_TYPE_EDGE_FALLING:
213 case IRQ_TYPE_LEVEL_LOW:
214 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
215 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
217 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
220 case IRQ_TYPE_EDGE_RISING:
221 case IRQ_TYPE_LEVEL_HIGH:
222 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
223 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
225 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
228 case IRQ_TYPE_EDGE_BOTH:
229 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
230 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
231 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
241 static struct irq_chip mpc8xxx_irq_chip = {
242 .name = "mpc8xxx-gpio",
243 .irq_unmask = mpc8xxx_irq_unmask,
244 .irq_mask = mpc8xxx_irq_mask,
245 .irq_ack = mpc8xxx_irq_ack,
246 /* this might get overwritten in mpc8xxx_probe() */
247 .irq_set_type = mpc8xxx_irq_set_type,
250 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
251 irq_hw_number_t hwirq)
253 irq_set_chip_data(irq, h->host_data);
254 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
259 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
260 .map = mpc8xxx_gpio_irq_map,
261 .xlate = irq_domain_xlate_twocell,
264 struct mpc8xxx_gpio_devtype {
265 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
266 int (*gpio_get)(struct gpio_chip *, unsigned int);
267 int (*irq_set_type)(struct irq_data *, unsigned int);
270 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
271 .gpio_dir_out = mpc5121_gpio_dir_out,
272 .irq_set_type = mpc512x_irq_set_type,
275 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
276 .gpio_dir_out = mpc5125_gpio_dir_out,
277 .irq_set_type = mpc512x_irq_set_type,
280 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
281 .gpio_get = mpc8572_gpio_get,
284 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
285 .irq_set_type = mpc8xxx_irq_set_type,
288 static const struct of_device_id mpc8xxx_gpio_ids[] = {
289 { .compatible = "fsl,mpc8349-gpio", },
290 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
291 { .compatible = "fsl,mpc8610-gpio", },
292 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
293 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
294 { .compatible = "fsl,pq3-gpio", },
295 { .compatible = "fsl,qoriq-gpio", },
299 static int mpc8xxx_probe(struct platform_device *pdev)
301 struct device_node *np = pdev->dev.of_node;
302 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
303 struct gpio_chip *gc;
304 const struct mpc8xxx_gpio_devtype *devtype =
305 of_device_get_match_data(&pdev->dev);
308 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
312 platform_set_drvdata(pdev, mpc8xxx_gc);
314 raw_spin_lock_init(&mpc8xxx_gc->lock);
316 mpc8xxx_gc->regs = of_iomap(np, 0);
317 if (!mpc8xxx_gc->regs)
320 gc = &mpc8xxx_gc->gc;
321 gc->parent = &pdev->dev;
323 if (of_property_read_bool(np, "little-endian")) {
324 ret = bgpio_init(gc, &pdev->dev, 4,
325 mpc8xxx_gc->regs + GPIO_DAT,
327 mpc8xxx_gc->regs + GPIO_DIR, NULL,
331 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
333 ret = bgpio_init(gc, &pdev->dev, 4,
334 mpc8xxx_gc->regs + GPIO_DAT,
336 mpc8xxx_gc->regs + GPIO_DIR, NULL,
338 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
341 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
344 mpc8xxx_gc->direction_output = gc->direction_output;
347 devtype = &mpc8xxx_gpio_devtype_default;
350 * It's assumed that only a single type of gpio controller is available
351 * on the current machine, so overwriting global data is fine.
353 if (devtype->irq_set_type)
354 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
356 if (devtype->gpio_dir_out)
357 gc->direction_output = devtype->gpio_dir_out;
358 if (devtype->gpio_get)
359 gc->get = devtype->gpio_get;
361 gc->to_irq = mpc8xxx_gpio_to_irq;
363 ret = gpiochip_add_data(gc, mpc8xxx_gc);
365 pr_err("%pOF: GPIO chip registration failed with status %d\n",
370 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
371 if (!mpc8xxx_gc->irqn)
374 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
375 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
376 if (!mpc8xxx_gc->irq)
379 /* ack and mask all irqs */
380 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
381 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
383 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
384 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
387 iounmap(mpc8xxx_gc->regs);
391 static int mpc8xxx_remove(struct platform_device *pdev)
393 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
395 if (mpc8xxx_gc->irq) {
396 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
397 irq_domain_remove(mpc8xxx_gc->irq);
400 gpiochip_remove(&mpc8xxx_gc->gc);
401 iounmap(mpc8xxx_gc->regs);
406 static struct platform_driver mpc8xxx_plat_driver = {
407 .probe = mpc8xxx_probe,
408 .remove = mpc8xxx_remove,
410 .name = "gpio-mpc8xxx",
411 .of_match_table = mpc8xxx_gpio_ids,
415 static int __init mpc8xxx_init(void)
417 return platform_driver_register(&mpc8xxx_plat_driver);
420 arch_initcall(mpc8xxx_init);