drivers/gpio/gpio-omap.c

   1 /*
   2  * Support functions for OMAP GPIO
   3  *
   4  * Copyright (C) 2003-2005 Nokia Corporation
   5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * Copyright (C) 2009 Texas Instruments
   8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/pm.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/gpio.h>
  28 #include <linux/bitops.h>
  29 #include <linux/platform_data/gpio-omap.h>
  30
  31 #define OFF_MODE        1
  32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
  33
  34 static LIST_HEAD(omap_gpio_list);
  35
  36 struct gpio_regs {
  37         u32 irqenable1;
  38         u32 irqenable2;
  39         u32 wake_en;
  40         u32 ctrl;
  41         u32 oe;
  42         u32 leveldetect0;
  43         u32 leveldetect1;
  44         u32 risingdetect;
  45         u32 fallingdetect;
  46         u32 dataout;
  47         u32 debounce;
  48         u32 debounce_en;
  49 };
  50
  51 struct gpio_bank {
  52         struct list_head node;
  53         void __iomem *base;
  54         int irq;
  55         u32 non_wakeup_gpios;
  56         u32 enabled_non_wakeup_gpios;
  57         struct gpio_regs context;
  58         u32 saved_datain;
  59         u32 level_mask;
  60         u32 toggle_mask;
  61         raw_spinlock_t lock;
  62         raw_spinlock_t wa_lock;
  63         struct gpio_chip chip;
  64         struct clk *dbck;
  65         u32 mod_usage;
  66         u32 irq_usage;
  67         u32 dbck_enable_mask;
  68         bool dbck_enabled;
  69         struct device *dev;
  70         bool is_mpuio;
  71         bool dbck_flag;
  72         bool loses_context;
  73         bool context_valid;
  74         int stride;
  75         u32 width;
  76         int context_loss_count;
  77         int power_mode;
  78         bool workaround_enabled;
  79
  80         void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
  81         int (*get_context_loss_count)(struct device *dev);
  82
  83         struct omap_gpio_reg_offs *regs;
  84 };
  85
  86 #define GPIO_MOD_CTRL_BIT       BIT(0)
  87
  88 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
  89 #define LINE_USED(line, offset) (line & (BIT(offset)))
  90
  91 static void omap_gpio_unmask_irq(struct irq_data *d);
  92
  93 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
  94 {
  95         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  96         return container_of(chip, struct gpio_bank, chip);
  97 }
  98
  99 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
 100                                     int is_input)
 101 {
 102         void __iomem *reg = bank->base;
 103         u32 l;
 104
 105         reg += bank->regs->direction;
 106         l = readl_relaxed(reg);
 107         if (is_input)
 108                 l |= BIT(gpio);
 109         else
 110                 l &= ~(BIT(gpio));
 111         writel_relaxed(l, reg);
 112         bank->context.oe = l;
 113 }
 114
 115
 116 /* set data out value using dedicate set/clear register */
 117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
 118                                       int enable)
 119 {
 120         void __iomem *reg = bank->base;
 121         u32 l = BIT(offset);
 122
 123         if (enable) {
 124                 reg += bank->regs->set_dataout;
 125                 bank->context.dataout |= l;
 126         } else {
 127                 reg += bank->regs->clr_dataout;
 128                 bank->context.dataout &= ~l;
 129         }
 130
 131         writel_relaxed(l, reg);
 132 }
 133
 134 /* set data out value using mask register */
 135 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
 136                                        int enable)
 137 {
 138         void __iomem *reg = bank->base + bank->regs->dataout;
 139         u32 gpio_bit = BIT(offset);
 140         u32 l;
 141
 142         l = readl_relaxed(reg);
 143         if (enable)
 144                 l |= gpio_bit;
 145         else
 146                 l &= ~gpio_bit;
 147         writel_relaxed(l, reg);
 148         bank->context.dataout = l;
 149 }
 150
 151 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
 152 {
 153         void __iomem *reg = bank->base + bank->regs->datain;
 154
 155         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 156 }
 157
 158 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
 159 {
 160         void __iomem *reg = bank->base + bank->regs->dataout;
 161
 162         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 163 }
 164
 165 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
 166 {
 167         int l = readl_relaxed(base + reg);
 168
 169         if (set)
 170                 l |= mask;
 171         else
 172                 l &= ~mask;
 173
 174         writel_relaxed(l, base + reg);
 175 }
 176
 177 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
 178 {
 179         if (bank->dbck_enable_mask && !bank->dbck_enabled) {
 180                 clk_enable(bank->dbck);
 181                 bank->dbck_enabled = true;
 182
 183                 writel_relaxed(bank->dbck_enable_mask,
 184                              bank->base + bank->regs->debounce_en);
 185         }
 186 }
 187
 188 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
 189 {
 190         if (bank->dbck_enable_mask && bank->dbck_enabled) {
 191                 /*
 192                  * Disable debounce before cutting it's clock. If debounce is
 193                  * enabled but the clock is not, GPIO module seems to be unable
 194                  * to detect events and generate interrupts at least on OMAP3.
 195                  */
 196                 writel_relaxed(0, bank->base + bank->regs->debounce_en);
 197
 198                 clk_disable(bank->dbck);
 199                 bank->dbck_enabled = false;
 200         }
 201 }
 202
 203 /**
 204  * omap2_set_gpio_debounce - low level gpio debounce time
 205  * @bank: the gpio bank we're acting upon
 206  * @offset: the gpio number on this @bank
 207  * @debounce: debounce time to use
 208  *
 209  * OMAP's debounce time is in 31us steps
 210  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
 211  * so we need to convert and round up to the closest unit.
 212  */
 213 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
 214                                     unsigned debounce)
 215 {
 216         void __iomem            *reg;
 217         u32                     val;
 218         u32                     l;
 219         bool                    enable = !!debounce;
 220
 221         if (!bank->dbck_flag)
 222                 return;
 223
 224         if (enable) {
 225                 debounce = DIV_ROUND_UP(debounce, 31) - 1;
 226                 debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
 227         }
 228
 229         l = BIT(offset);
 230
 231         clk_enable(bank->dbck);
 232         reg = bank->base + bank->regs->debounce;
 233         writel_relaxed(debounce, reg);
 234
 235         reg = bank->base + bank->regs->debounce_en;
 236         val = readl_relaxed(reg);
 237
 238         if (enable)
 239                 val |= l;
 240         else
 241                 val &= ~l;
 242         bank->dbck_enable_mask = val;
 243
 244         writel_relaxed(val, reg);
 245         clk_disable(bank->dbck);
 246         /*
 247          * Enable debounce clock per module.
 248          * This call is mandatory because in omap_gpio_request() when
 249          * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
 250          * runtime callbck fails to turn on dbck because dbck_enable_mask
 251          * used within _gpio_dbck_enable() is still not initialized at
 252          * that point. Therefore we have to enable dbck here.
 253          */
 254         omap_gpio_dbck_enable(bank);
 255         if (bank->dbck_enable_mask) {
 256                 bank->context.debounce = debounce;
 257                 bank->context.debounce_en = val;
 258         }
 259 }
 260
 261 /**
 262  * omap_clear_gpio_debounce - clear debounce settings for a gpio
 263  * @bank: the gpio bank we're acting upon
 264  * @offset: the gpio number on this @bank
 265  *
 266  * If a gpio is using debounce, then clear the debounce enable bit and if
 267  * this is the only gpio in this bank using debounce, then clear the debounce
 268  * time too. The debounce clock will also be disabled when calling this function
 269  * if this is the only gpio in the bank using debounce.
 270  */
 271 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
 272 {
 273         u32 gpio_bit = BIT(offset);
 274
 275         if (!bank->dbck_flag)
 276                 return;
 277
 278         if (!(bank->dbck_enable_mask & gpio_bit))
 279                 return;
 280
 281         bank->dbck_enable_mask &= ~gpio_bit;
 282         bank->context.debounce_en &= ~gpio_bit;
 283         writel_relaxed(bank->context.debounce_en,
 284                      bank->base + bank->regs->debounce_en);
 285
 286         if (!bank->dbck_enable_mask) {
 287                 bank->context.debounce = 0;
 288                 writel_relaxed(bank->context.debounce, bank->base +
 289                              bank->regs->debounce);
 290                 clk_disable(bank->dbck);
 291                 bank->dbck_enabled = false;
 292         }
 293 }
 294
 295 /*
 296  * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
 297  * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
 298  * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
 299  * are capable waking up the system from off mode.
 300  */
 301 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
 302 {
 303         u32 no_wake = bank->non_wakeup_gpios;
 304
 305         if (no_wake)
 306                 return !!(~no_wake & gpio_mask);
 307
 308         return false;
 309 }
 310
 311 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
 312                                                 unsigned trigger)
 313 {
 314         void __iomem *base = bank->base;
 315         u32 gpio_bit = BIT(gpio);
 316
 317         omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
 318                       trigger & IRQ_TYPE_LEVEL_LOW);
 319         omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
 320                       trigger & IRQ_TYPE_LEVEL_HIGH);
 321         omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
 322                       trigger & IRQ_TYPE_EDGE_RISING);
 323         omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
 324                       trigger & IRQ_TYPE_EDGE_FALLING);
 325
 326         bank->context.leveldetect0 =
 327                         readl_relaxed(bank->base + bank->regs->leveldetect0);
 328         bank->context.leveldetect1 =
 329                         readl_relaxed(bank->base + bank->regs->leveldetect1);
 330         bank->context.risingdetect =
 331                         readl_relaxed(bank->base + bank->regs->risingdetect);
 332         bank->context.fallingdetect =
 333                         readl_relaxed(bank->base + bank->regs->fallingdetect);
 334
 335         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 336                 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
 337                 bank->context.wake_en =
 338                         readl_relaxed(bank->base + bank->regs->wkup_en);
 339         }
 340
 341         /* This part needs to be executed always for OMAP{34xx, 44xx} */
 342         if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
 343                 /*
 344                  * Log the edge gpio and manually trigger the IRQ
 345                  * after resume if the input level changes
 346                  * to avoid irq lost during PER RET/OFF mode
 347                  * Applies for omap2 non-wakeup gpio and all omap3 gpios
 348                  */
 349                 if (trigger & IRQ_TYPE_EDGE_BOTH)
 350                         bank->enabled_non_wakeup_gpios |= gpio_bit;
 351                 else
 352                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 353         }
 354
 355         bank->level_mask =
 356                 readl_relaxed(bank->base + bank->regs->leveldetect0) |
 357                 readl_relaxed(bank->base + bank->regs->leveldetect1);
 358 }
 359
 360 #ifdef CONFIG_ARCH_OMAP1
 361 /*
 362  * This only applies to chips that can't do both rising and falling edge
 363  * detection at once.  For all other chips, this function is a noop.
 364  */
 365 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 366 {
 367         void __iomem *reg = bank->base;
 368         u32 l = 0;
 369
 370         if (!bank->regs->irqctrl)
 371                 return;
 372
 373         reg += bank->regs->irqctrl;
 374
 375         l = readl_relaxed(reg);
 376         if ((l >> gpio) & 1)
 377                 l &= ~(BIT(gpio));
 378         else
 379                 l |= BIT(gpio);
 380
 381         writel_relaxed(l, reg);
 382 }
 383 #else
 384 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 385 #endif
 386
 387 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
 388                                     unsigned trigger)
 389 {
 390         void __iomem *reg = bank->base;
 391         void __iomem *base = bank->base;
 392         u32 l = 0;
 393
 394         if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
 395                 omap_set_gpio_trigger(bank, gpio, trigger);
 396         } else if (bank->regs->irqctrl) {
 397                 reg += bank->regs->irqctrl;
 398
 399                 l = readl_relaxed(reg);
 400                 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 401                         bank->toggle_mask |= BIT(gpio);
 402                 if (trigger & IRQ_TYPE_EDGE_RISING)
 403                         l |= BIT(gpio);
 404                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 405                         l &= ~(BIT(gpio));
 406                 else
 407                         return -EINVAL;
 408
 409                 writel_relaxed(l, reg);
 410         } else if (bank->regs->edgectrl1) {
 411                 if (gpio & 0x08)
 412                         reg += bank->regs->edgectrl2;
 413                 else
 414                         reg += bank->regs->edgectrl1;
 415
 416                 gpio &= 0x07;
 417                 l = readl_relaxed(reg);
 418                 l &= ~(3 << (gpio << 1));
 419                 if (trigger & IRQ_TYPE_EDGE_RISING)
 420                         l |= 2 << (gpio << 1);
 421                 if (trigger & IRQ_TYPE_EDGE_FALLING)
 422                         l |= BIT(gpio << 1);
 423
 424                 /* Enable wake-up during idle for dynamic tick */
 425                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
 426                 bank->context.wake_en =
 427                         readl_relaxed(bank->base + bank->regs->wkup_en);
 428                 writel_relaxed(l, reg);
 429         }
 430         return 0;
 431 }
 432
 433 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
 434 {
 435         if (bank->regs->pinctrl) {
 436                 void __iomem *reg = bank->base + bank->regs->pinctrl;
 437
 438                 /* Claim the pin for MPU */
 439                 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
 440         }
 441
 442         if (bank->regs->ctrl && !BANK_USED(bank)) {
 443                 void __iomem *reg = bank->base + bank->regs->ctrl;
 444                 u32 ctrl;
 445
 446                 ctrl = readl_relaxed(reg);
 447                 /* Module is enabled, clocks are not gated */
 448                 ctrl &= ~GPIO_MOD_CTRL_BIT;
 449                 writel_relaxed(ctrl, reg);
 450                 bank->context.ctrl = ctrl;
 451         }
 452 }
 453
 454 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
 455 {
 456         void __iomem *base = bank->base;
 457
 458         if (bank->regs->wkup_en &&
 459             !LINE_USED(bank->mod_usage, offset) &&
 460             !LINE_USED(bank->irq_usage, offset)) {
 461                 /* Disable wake-up during idle for dynamic tick */
 462                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
 463                 bank->context.wake_en =
 464                         readl_relaxed(bank->base + bank->regs->wkup_en);
 465         }
 466
 467         if (bank->regs->ctrl && !BANK_USED(bank)) {
 468                 void __iomem *reg = bank->base + bank->regs->ctrl;
 469                 u32 ctrl;
 470
 471                 ctrl = readl_relaxed(reg);
 472                 /* Module is disabled, clocks are gated */
 473                 ctrl |= GPIO_MOD_CTRL_BIT;
 474                 writel_relaxed(ctrl, reg);
 475                 bank->context.ctrl = ctrl;
 476         }
 477 }
 478
 479 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
 480 {
 481         void __iomem *reg = bank->base + bank->regs->direction;
 482
 483         return readl_relaxed(reg) & BIT(offset);
 484 }
 485
 486 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
 487 {
 488         if (!LINE_USED(bank->mod_usage, offset)) {
 489                 omap_enable_gpio_module(bank, offset);
 490                 omap_set_gpio_direction(bank, offset, 1);
 491         }
 492         bank->irq_usage |= BIT(offset);
 493 }
 494
 495 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
 496 {
 497         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 498         int retval;
 499         unsigned long flags;
 500         unsigned offset = d->hwirq;
 501
 502         if (type & ~IRQ_TYPE_SENSE_MASK)
 503                 return -EINVAL;
 504
 505         if (!bank->regs->leveldetect0 &&
 506                 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 507                 return -EINVAL;
 508
 509         raw_spin_lock_irqsave(&bank->lock, flags);
 510         retval = omap_set_gpio_triggering(bank, offset, type);
 511         if (retval) {
 512                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 513                 goto error;
 514         }
 515         omap_gpio_init_irq(bank, offset);
 516         if (!omap_gpio_is_input(bank, offset)) {
 517                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 518                 retval = -EINVAL;
 519                 goto error;
 520         }
 521         raw_spin_unlock_irqrestore(&bank->lock, flags);
 522
 523         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 524                 irq_set_handler_locked(d, handle_level_irq);
 525         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 526                 irq_set_handler_locked(d, handle_edge_irq);
 527
 528         return 0;
 529
 530 error:
 531         return retval;
 532 }
 533
 534 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 535 {
 536         void __iomem *reg = bank->base;
 537
 538         reg += bank->regs->irqstatus;
 539         writel_relaxed(gpio_mask, reg);
 540
 541         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 542         if (bank->regs->irqstatus2) {
 543                 reg = bank->base + bank->regs->irqstatus2;
 544                 writel_relaxed(gpio_mask, reg);
 545         }
 546
 547         /* Flush posted write for the irq status to avoid spurious interrupts */
 548         readl_relaxed(reg);
 549 }
 550
 551 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
 552                                              unsigned offset)
 553 {
 554         omap_clear_gpio_irqbank(bank, BIT(offset));
 555 }
 556
 557 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
 558 {
 559         void __iomem *reg = bank->base;
 560         u32 l;
 561         u32 mask = (BIT(bank->width)) - 1;
 562
 563         reg += bank->regs->irqenable;
 564         l = readl_relaxed(reg);
 565         if (bank->regs->irqenable_inv)
 566                 l = ~l;
 567         l &= mask;
 568         return l;
 569 }
 570
 571 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 572 {
 573         void __iomem *reg = bank->base;
 574         u32 l;
 575
 576         if (bank->regs->set_irqenable) {
 577                 reg += bank->regs->set_irqenable;
 578                 l = gpio_mask;
 579                 bank->context.irqenable1 |= gpio_mask;
 580         } else {
 581                 reg += bank->regs->irqenable;
 582                 l = readl_relaxed(reg);
 583                 if (bank->regs->irqenable_inv)
 584                         l &= ~gpio_mask;
 585                 else
 586                         l |= gpio_mask;
 587                 bank->context.irqenable1 = l;
 588         }
 589
 590         writel_relaxed(l, reg);
 591 }
 592
 593 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 594 {
 595         void __iomem *reg = bank->base;
 596         u32 l;
 597
 598         if (bank->regs->clr_irqenable) {
 599                 reg += bank->regs->clr_irqenable;
 600                 l = gpio_mask;
 601                 bank->context.irqenable1 &= ~gpio_mask;
 602         } else {
 603                 reg += bank->regs->irqenable;
 604                 l = readl_relaxed(reg);
 605                 if (bank->regs->irqenable_inv)
 606                         l |= gpio_mask;
 607                 else
 608                         l &= ~gpio_mask;
 609                 bank->context.irqenable1 = l;
 610         }
 611
 612         writel_relaxed(l, reg);
 613 }
 614
 615 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
 616                                            unsigned offset, int enable)
 617 {
 618         if (enable)
 619                 omap_enable_gpio_irqbank(bank, BIT(offset));
 620         else
 621                 omap_disable_gpio_irqbank(bank, BIT(offset));
 622 }
 623
 624 /*
 625  * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
 626  * 1510 does not seem to have a wake-up register. If JTAG is connected
 627  * to the target, system will wake up always on GPIO events. While
 628  * system is running all registered GPIO interrupts need to have wake-up
 629  * enabled. When system is suspended, only selected GPIO interrupts need
 630  * to have wake-up enabled.
 631  */
 632 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
 633                                 int enable)
 634 {
 635         u32 gpio_bit = BIT(offset);
 636         unsigned long flags;
 637
 638         if (bank->non_wakeup_gpios & gpio_bit) {
 639                 dev_err(bank->dev,
 640                         "Unable to modify wakeup on non-wakeup GPIO%d\n",
 641                         offset);
 642                 return -EINVAL;
 643         }
 644
 645         raw_spin_lock_irqsave(&bank->lock, flags);
 646         if (enable)
 647                 bank->context.wake_en |= gpio_bit;
 648         else
 649                 bank->context.wake_en &= ~gpio_bit;
 650
 651         writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
 652         raw_spin_unlock_irqrestore(&bank->lock, flags);
 653
 654         return 0;
 655 }
 656
 657 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 658 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 659 {
 660         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 661         unsigned offset = d->hwirq;
 662         int ret;
 663
 664         ret = omap_set_gpio_wakeup(bank, offset, enable);
 665         if (!ret)
 666                 ret = irq_set_irq_wake(bank->irq, enable);
 667
 668         return ret;
 669 }
 670
 671 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 672 {
 673         struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
 674         unsigned long flags;
 675
 676         /*
 677          * If this is the first gpio_request for the bank,
 678          * enable the bank module.
 679          */
 680         if (!BANK_USED(bank))
 681                 pm_runtime_get_sync(bank->dev);
 682
 683         raw_spin_lock_irqsave(&bank->lock, flags);
 684         omap_enable_gpio_module(bank, offset);
 685         bank->mod_usage |= BIT(offset);
 686         raw_spin_unlock_irqrestore(&bank->lock, flags);
 687
 688         return 0;
 689 }
 690
 691 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 692 {
 693         struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
 694         unsigned long flags;
 695
 696         raw_spin_lock_irqsave(&bank->lock, flags);
 697         bank->mod_usage &= ~(BIT(offset));
 698         if (!LINE_USED(bank->irq_usage, offset)) {
 699                 omap_set_gpio_direction(bank, offset, 1);
 700                 omap_clear_gpio_debounce(bank, offset);
 701         }
 702         omap_disable_gpio_module(bank, offset);
 703         raw_spin_unlock_irqrestore(&bank->lock, flags);
 704
 705         /*
 706          * If this is the last gpio to be freed in the bank,
 707          * disable the bank module.
 708          */
 709         if (!BANK_USED(bank))
 710                 pm_runtime_put(bank->dev);
 711 }
 712
 713 /*
 714  * We need to unmask the GPIO bank interrupt as soon as possible to
 715  * avoid missing GPIO interrupts for other lines in the bank.
 716  * Then we need to mask-read-clear-unmask the triggered GPIO lines
 717  * in the bank to avoid missing nested interrupts for a GPIO line.
 718  * If we wait to unmask individual GPIO lines in the bank after the
 719  * line's interrupt handler has been run, we may miss some nested
 720  * interrupts.
 721  */
 722 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
 723 {
 724         void __iomem *isr_reg = NULL;
 725         u32 isr;
 726         unsigned int bit;
 727         struct gpio_bank *bank = gpiobank;
 728         unsigned long wa_lock_flags;
 729         unsigned long lock_flags;
 730
 731         isr_reg = bank->base + bank->regs->irqstatus;
 732         if (WARN_ON(!isr_reg))
 733                 goto exit;
 734
 735         pm_runtime_get_sync(bank->dev);
 736
 737         while (1) {
 738                 u32 isr_saved, level_mask = 0;
 739                 u32 enabled;
 740
 741                 raw_spin_lock_irqsave(&bank->lock, lock_flags);
 742
 743                 enabled = omap_get_gpio_irqbank_mask(bank);
 744                 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
 745
 746                 if (bank->level_mask)
 747                         level_mask = bank->level_mask & enabled;
 748
 749                 /* clear edge sensitive interrupts before handler(s) are
 750                 called so that we don't miss any interrupt occurred while
 751                 executing them */
 752                 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
 753                 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
 754                 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
 755
 756                 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 757
 758                 if (!isr)
 759                         break;
 760
 761                 while (isr) {
 762                         bit = __ffs(isr);
 763                         isr &= ~(BIT(bit));
 764
 765                         raw_spin_lock_irqsave(&bank->lock, lock_flags);
 766                         /*
 767                          * Some chips can't respond to both rising and falling
 768                          * at the same time.  If this irq was requested with
 769                          * both flags, we need to flip the ICR data for the IRQ
 770                          * to respond to the IRQ for the opposite direction.
 771                          * This will be indicated in the bank toggle_mask.
 772                          */
 773                         if (bank->toggle_mask & (BIT(bit)))
 774                                 omap_toggle_gpio_edge_triggering(bank, bit);
 775
 776                         raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 777
 778                         raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
 779
 780                         generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
 781                                                             bit));
 782
 783                         raw_spin_unlock_irqrestore(&bank->wa_lock,
 784                                                    wa_lock_flags);
 785                 }
 786         }
 787 exit:
 788         pm_runtime_put(bank->dev);
 789         return IRQ_HANDLED;
 790 }
 791
 792 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
 793 {
 794         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 795         unsigned long flags;
 796         unsigned offset = d->hwirq;
 797
 798         raw_spin_lock_irqsave(&bank->lock, flags);
 799
 800         if (!LINE_USED(bank->mod_usage, offset))
 801                 omap_set_gpio_direction(bank, offset, 1);
 802         else if (!omap_gpio_is_input(bank, offset))
 803                 goto err;
 804         omap_enable_gpio_module(bank, offset);
 805         bank->irq_usage |= BIT(offset);
 806
 807         raw_spin_unlock_irqrestore(&bank->lock, flags);
 808         omap_gpio_unmask_irq(d);
 809
 810         return 0;
 811 err:
 812         raw_spin_unlock_irqrestore(&bank->lock, flags);
 813         return -EINVAL;
 814 }
 815
 816 static void omap_gpio_irq_shutdown(struct irq_data *d)
 817 {
 818         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 819         unsigned long flags;
 820         unsigned offset = d->hwirq;
 821
 822         raw_spin_lock_irqsave(&bank->lock, flags);
 823         bank->irq_usage &= ~(BIT(offset));
 824         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 825         omap_clear_gpio_irqstatus(bank, offset);
 826         omap_set_gpio_irqenable(bank, offset, 0);
 827         if (!LINE_USED(bank->mod_usage, offset))
 828                 omap_clear_gpio_debounce(bank, offset);
 829         omap_disable_gpio_module(bank, offset);
 830         raw_spin_unlock_irqrestore(&bank->lock, flags);
 831 }
 832
 833 static void omap_gpio_irq_bus_lock(struct irq_data *data)
 834 {
 835         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 836
 837         if (!BANK_USED(bank))
 838                 pm_runtime_get_sync(bank->dev);
 839 }
 840
 841 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
 842 {
 843         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 844
 845         /*
 846          * If this is the last IRQ to be freed in the bank,
 847          * disable the bank module.
 848          */
 849         if (!BANK_USED(bank))
 850                 pm_runtime_put(bank->dev);
 851 }
 852
 853 static void omap_gpio_ack_irq(struct irq_data *d)
 854 {
 855         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 856         unsigned offset = d->hwirq;
 857
 858         omap_clear_gpio_irqstatus(bank, offset);
 859 }
 860
 861 static void omap_gpio_mask_irq(struct irq_data *d)
 862 {
 863         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 864         unsigned offset = d->hwirq;
 865         unsigned long flags;
 866
 867         raw_spin_lock_irqsave(&bank->lock, flags);
 868         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 869         omap_set_gpio_irqenable(bank, offset, 0);
 870         raw_spin_unlock_irqrestore(&bank->lock, flags);
 871 }
 872
 873 static void omap_gpio_unmask_irq(struct irq_data *d)
 874 {
 875         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 876         unsigned offset = d->hwirq;
 877         u32 trigger = irqd_get_trigger_type(d);
 878         unsigned long flags;
 879
 880         raw_spin_lock_irqsave(&bank->lock, flags);
 881         omap_set_gpio_irqenable(bank, offset, 1);
 882
 883         /*
 884          * For level-triggered GPIOs, clearing must be done after the source
 885          * is cleared, thus after the handler has run. OMAP4 needs this done
 886          * after enabing the interrupt to clear the wakeup status.
 887          */
 888         if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
 889             trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 890                 omap_clear_gpio_irqstatus(bank, offset);
 891
 892         if (trigger)
 893                 omap_set_gpio_triggering(bank, offset, trigger);
 894
 895         raw_spin_unlock_irqrestore(&bank->lock, flags);
 896 }
 897
 898 /*---------------------------------------------------------------------*/
 899
 900 static int omap_mpuio_suspend_noirq(struct device *dev)
 901 {
 902         struct platform_device *pdev = to_platform_device(dev);
 903         struct gpio_bank        *bank = platform_get_drvdata(pdev);
 904         void __iomem            *mask_reg = bank->base +
 905                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 906         unsigned long           flags;
 907
 908         raw_spin_lock_irqsave(&bank->lock, flags);
 909         writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
 910         raw_spin_unlock_irqrestore(&bank->lock, flags);
 911
 912         return 0;
 913 }
 914
 915 static int omap_mpuio_resume_noirq(struct device *dev)
 916 {
 917         struct platform_device *pdev = to_platform_device(dev);
 918         struct gpio_bank        *bank = platform_get_drvdata(pdev);
 919         void __iomem            *mask_reg = bank->base +
 920                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 921         unsigned long           flags;
 922
 923         raw_spin_lock_irqsave(&bank->lock, flags);
 924         writel_relaxed(bank->context.wake_en, mask_reg);
 925         raw_spin_unlock_irqrestore(&bank->lock, flags);
 926
 927         return 0;
 928 }
 929
 930 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
 931         .suspend_noirq = omap_mpuio_suspend_noirq,
 932         .resume_noirq = omap_mpuio_resume_noirq,
 933 };
 934
 935 /* use platform_driver for this. */
 936 static struct platform_driver omap_mpuio_driver = {
 937         .driver         = {
 938                 .name   = "mpuio",
 939                 .pm     = &omap_mpuio_dev_pm_ops,
 940         },
 941 };
 942
 943 static struct platform_device omap_mpuio_device = {
 944         .name           = "mpuio",
 945         .id             = -1,
 946         .dev = {
 947                 .driver = &omap_mpuio_driver.driver,
 948         }
 949         /* could list the /proc/iomem resources */
 950 };
 951
 952 static inline void omap_mpuio_init(struct gpio_bank *bank)
 953 {
 954         platform_set_drvdata(&omap_mpuio_device, bank);
 955
 956         if (platform_driver_register(&omap_mpuio_driver) == 0)
 957                 (void) platform_device_register(&omap_mpuio_device);
 958 }
 959
 960 /*---------------------------------------------------------------------*/
 961
 962 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 963 {
 964         struct gpio_bank *bank;
 965         unsigned long flags;
 966         void __iomem *reg;
 967         int dir;
 968
 969         bank = container_of(chip, struct gpio_bank, chip);
 970         reg = bank->base + bank->regs->direction;
 971         raw_spin_lock_irqsave(&bank->lock, flags);
 972         dir = !!(readl_relaxed(reg) & BIT(offset));
 973         raw_spin_unlock_irqrestore(&bank->lock, flags);
 974         return dir;
 975 }
 976
 977 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
 978 {
 979         struct gpio_bank *bank;
 980         unsigned long flags;
 981
 982         bank = container_of(chip, struct gpio_bank, chip);
 983         raw_spin_lock_irqsave(&bank->lock, flags);
 984         omap_set_gpio_direction(bank, offset, 1);
 985         raw_spin_unlock_irqrestore(&bank->lock, flags);
 986         return 0;
 987 }
 988
 989 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
 990 {
 991         struct gpio_bank *bank;
 992
 993         bank = container_of(chip, struct gpio_bank, chip);
 994
 995         if (omap_gpio_is_input(bank, offset))
 996                 return omap_get_gpio_datain(bank, offset);
 997         else
 998                 return omap_get_gpio_dataout(bank, offset);
 999 }
1000
1001 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1002 {
1003         struct gpio_bank *bank;
1004         unsigned long flags;
1005
1006         bank = container_of(chip, struct gpio_bank, chip);
1007         raw_spin_lock_irqsave(&bank->lock, flags);
1008         bank->set_dataout(bank, offset, value);
1009         omap_set_gpio_direction(bank, offset, 0);
1010         raw_spin_unlock_irqrestore(&bank->lock, flags);
1011         return 0;
1012 }
1013
1014 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1015                               unsigned debounce)
1016 {
1017         struct gpio_bank *bank;
1018         unsigned long flags;
1019
1020         bank = container_of(chip, struct gpio_bank, chip);
1021
1022         raw_spin_lock_irqsave(&bank->lock, flags);
1023         omap2_set_gpio_debounce(bank, offset, debounce);
1024         raw_spin_unlock_irqrestore(&bank->lock, flags);
1025
1026         return 0;
1027 }
1028
1029 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1030 {
1031         struct gpio_bank *bank;
1032         unsigned long flags;
1033
1034         bank = container_of(chip, struct gpio_bank, chip);
1035         raw_spin_lock_irqsave(&bank->lock, flags);
1036         bank->set_dataout(bank, offset, value);
1037         raw_spin_unlock_irqrestore(&bank->lock, flags);
1038 }
1039
1040 /*---------------------------------------------------------------------*/
1041
1042 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1043 {
1044         static bool called;
1045         u32 rev;
1046
1047         if (called || bank->regs->revision == USHRT_MAX)
1048                 return;
1049
1050         rev = readw_relaxed(bank->base + bank->regs->revision);
1051         pr_info("OMAP GPIO hardware version %d.%d\n",
1052                 (rev >> 4) & 0x0f, rev & 0x0f);
1053
1054         called = true;
1055 }
1056
1057 static void omap_gpio_mod_init(struct gpio_bank *bank)
1058 {
1059         void __iomem *base = bank->base;
1060         u32 l = 0xffffffff;
1061
1062         if (bank->width == 16)
1063                 l = 0xffff;
1064
1065         if (bank->is_mpuio) {
1066                 writel_relaxed(l, bank->base + bank->regs->irqenable);
1067                 return;
1068         }
1069
1070         omap_gpio_rmw(base, bank->regs->irqenable, l,
1071                       bank->regs->irqenable_inv);
1072         omap_gpio_rmw(base, bank->regs->irqstatus, l,
1073                       !bank->regs->irqenable_inv);
1074         if (bank->regs->debounce_en)
1075                 writel_relaxed(0, base + bank->regs->debounce_en);
1076
1077         /* Save OE default value (0xffffffff) in the context */
1078         bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1079          /* Initialize interface clk ungated, module enabled */
1080         if (bank->regs->ctrl)
1081                 writel_relaxed(0, base + bank->regs->ctrl);
1082 }
1083
1084 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1085 {
1086         static int gpio;
1087         int irq_base = 0;
1088         int ret;
1089
1090         /*
1091          * REVISIT eventually switch from OMAP-specific gpio structs
1092          * over to the generic ones
1093          */
1094         bank->chip.request = omap_gpio_request;
1095         bank->chip.free = omap_gpio_free;
1096         bank->chip.get_direction = omap_gpio_get_direction;
1097         bank->chip.direction_input = omap_gpio_input;
1098         bank->chip.get = omap_gpio_get;
1099         bank->chip.direction_output = omap_gpio_output;
1100         bank->chip.set_debounce = omap_gpio_debounce;
1101         bank->chip.set = omap_gpio_set;
1102         if (bank->is_mpuio) {
1103                 bank->chip.label = "mpuio";
1104                 if (bank->regs->wkup_en)
1105                         bank->chip.dev = &omap_mpuio_device.dev;
1106                 bank->chip.base = OMAP_MPUIO(0);
1107         } else {
1108                 bank->chip.label = "gpio";
1109                 bank->chip.base = gpio;
1110         }
1111         bank->chip.ngpio = bank->width;
1112
1113         ret = gpiochip_add(&bank->chip);
1114         if (ret) {
1115                 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1116                 return ret;
1117         }
1118
1119         if (!bank->is_mpuio)
1120                 gpio += bank->width;
1121
1122 #ifdef CONFIG_ARCH_OMAP1
1123         /*
1124          * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1125          * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1126          */
1127         irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1128         if (irq_base < 0) {
1129                 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1130                 return -ENODEV;
1131         }
1132 #endif
1133
1134         /* MPUIO is a bit different, reading IRQ status clears it */
1135         if (bank->is_mpuio) {
1136                 irqc->irq_ack = dummy_irq_chip.irq_ack;
1137                 if (!bank->regs->wkup_en)
1138                         irqc->irq_set_wake = NULL;
1139         }
1140
1141         ret = gpiochip_irqchip_add(&bank->chip, irqc,
1142                                    irq_base, handle_bad_irq,
1143                                    IRQ_TYPE_NONE);
1144
1145         if (ret) {
1146                 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1147                 gpiochip_remove(&bank->chip);
1148                 return -ENODEV;
1149         }
1150
1151         gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1152
1153         ret = devm_request_irq(bank->dev, bank->irq, omap_gpio_irq_handler,
1154                                0, dev_name(bank->dev), bank);
1155         if (ret)
1156                 gpiochip_remove(&bank->chip);
1157
1158         return ret;
1159 }
1160
1161 static const struct of_device_id omap_gpio_match[];
1162
1163 static int omap_gpio_probe(struct platform_device *pdev)
1164 {
1165         struct device *dev = &pdev->dev;
1166         struct device_node *node = dev->of_node;
1167         const struct of_device_id *match;
1168         const struct omap_gpio_platform_data *pdata;
1169         struct resource *res;
1170         struct gpio_bank *bank;
1171         struct irq_chip *irqc;
1172         int ret;
1173
1174         match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1175
1176         pdata = match ? match->data : dev_get_platdata(dev);
1177         if (!pdata)
1178                 return -EINVAL;
1179
1180         bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1181         if (!bank) {
1182                 dev_err(dev, "Memory alloc failed\n");
1183                 return -ENOMEM;
1184         }
1185
1186         irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1187         if (!irqc)
1188                 return -ENOMEM;
1189
1190         irqc->irq_startup = omap_gpio_irq_startup,
1191         irqc->irq_shutdown = omap_gpio_irq_shutdown,
1192         irqc->irq_ack = omap_gpio_ack_irq,
1193         irqc->irq_mask = omap_gpio_mask_irq,
1194         irqc->irq_unmask = omap_gpio_unmask_irq,
1195         irqc->irq_set_type = omap_gpio_irq_type,
1196         irqc->irq_set_wake = omap_gpio_wake_enable,
1197         irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1198         irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1199         irqc->name = dev_name(&pdev->dev);
1200
1201         bank->irq = platform_get_irq(pdev, 0);
1202         if (bank->irq <= 0) {
1203                 if (!bank->irq)
1204                         bank->irq = -ENXIO;
1205                 if (bank->irq != -EPROBE_DEFER)
1206                         dev_err(dev,
1207                                 "can't get irq resource ret=%d\n", bank->irq);
1208                 return bank->irq;
1209         }
1210
1211         bank->dev = dev;
1212         bank->chip.dev = dev;
1213         bank->chip.owner = THIS_MODULE;
1214         bank->dbck_flag = pdata->dbck_flag;
1215         bank->stride = pdata->bank_stride;
1216         bank->width = pdata->bank_width;
1217         bank->is_mpuio = pdata->is_mpuio;
1218         bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1219         bank->regs = pdata->regs;
1220 #ifdef CONFIG_OF_GPIO
1221         bank->chip.of_node = of_node_get(node);
1222 #endif
1223         if (node) {
1224                 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1225                         bank->loses_context = true;
1226         } else {
1227                 bank->loses_context = pdata->loses_context;
1228
1229                 if (bank->loses_context)
1230                         bank->get_context_loss_count =
1231                                 pdata->get_context_loss_count;
1232         }
1233
1234         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1235                 bank->set_dataout = omap_set_gpio_dataout_reg;
1236         else
1237                 bank->set_dataout = omap_set_gpio_dataout_mask;
1238
1239         raw_spin_lock_init(&bank->lock);
1240         raw_spin_lock_init(&bank->wa_lock);
1241
1242         /* Static mapping, never released */
1243         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1244         bank->base = devm_ioremap_resource(dev, res);
1245         if (IS_ERR(bank->base)) {
1246                 return PTR_ERR(bank->base);
1247         }
1248
1249         if (bank->dbck_flag) {
1250                 bank->dbck = devm_clk_get(bank->dev, "dbclk");
1251                 if (IS_ERR(bank->dbck)) {
1252                         dev_err(bank->dev,
1253                                 "Could not get gpio dbck. Disable debounce\n");
1254                         bank->dbck_flag = false;
1255                 } else {
1256                         clk_prepare(bank->dbck);
1257                 }
1258         }
1259
1260         platform_set_drvdata(pdev, bank);
1261
1262         pm_runtime_enable(bank->dev);
1263         pm_runtime_irq_safe(bank->dev);
1264         pm_runtime_get_sync(bank->dev);
1265
1266         if (bank->is_mpuio)
1267                 omap_mpuio_init(bank);
1268
1269         omap_gpio_mod_init(bank);
1270
1271         ret = omap_gpio_chip_init(bank, irqc);
1272         if (ret) {
1273                 pm_runtime_put_sync(bank->dev);
1274                 pm_runtime_disable(bank->dev);
1275                 return ret;
1276         }
1277
1278         omap_gpio_show_rev(bank);
1279
1280         pm_runtime_put(bank->dev);
1281
1282         list_add_tail(&bank->node, &omap_gpio_list);
1283
1284         return 0;
1285 }
1286
1287 static int omap_gpio_remove(struct platform_device *pdev)
1288 {
1289         struct gpio_bank *bank = platform_get_drvdata(pdev);
1290
1291         list_del(&bank->node);
1292         gpiochip_remove(&bank->chip);
1293         pm_runtime_disable(bank->dev);
1294         if (bank->dbck_flag)
1295                 clk_unprepare(bank->dbck);
1296
1297         return 0;
1298 }
1299
1300 #ifdef CONFIG_ARCH_OMAP2PLUS
1301
1302 #if defined(CONFIG_PM)
1303 static void omap_gpio_restore_context(struct gpio_bank *bank);
1304
1305 static int omap_gpio_runtime_suspend(struct device *dev)
1306 {
1307         struct platform_device *pdev = to_platform_device(dev);
1308         struct gpio_bank *bank = platform_get_drvdata(pdev);
1309         u32 l1 = 0, l2 = 0;
1310         unsigned long flags;
1311         u32 wake_low, wake_hi;
1312
1313         raw_spin_lock_irqsave(&bank->lock, flags);
1314
1315         /*
1316          * Only edges can generate a wakeup event to the PRCM.
1317          *
1318          * Therefore, ensure any wake-up capable GPIOs have
1319          * edge-detection enabled before going idle to ensure a wakeup
1320          * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1321          * NDA TRM 25.5.3.1)
1322          *
1323          * The normal values will be restored upon ->runtime_resume()
1324          * by writing back the values saved in bank->context.
1325          */
1326         wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1327         if (wake_low)
1328                 writel_relaxed(wake_low | bank->context.fallingdetect,
1329                              bank->base + bank->regs->fallingdetect);
1330         wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1331         if (wake_hi)
1332                 writel_relaxed(wake_hi | bank->context.risingdetect,
1333                              bank->base + bank->regs->risingdetect);
1334
1335         if (!bank->enabled_non_wakeup_gpios)
1336                 goto update_gpio_context_count;
1337
1338         if (bank->power_mode != OFF_MODE) {
1339                 bank->power_mode = 0;
1340                 goto update_gpio_context_count;
1341         }
1342         /*
1343          * If going to OFF, remove triggering for all
1344          * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1345          * generated.  See OMAP2420 Errata item 1.101.
1346          */
1347         bank->saved_datain = readl_relaxed(bank->base +
1348                                                 bank->regs->datain);
1349         l1 = bank->context.fallingdetect;
1350         l2 = bank->context.risingdetect;
1351
1352         l1 &= ~bank->enabled_non_wakeup_gpios;
1353         l2 &= ~bank->enabled_non_wakeup_gpios;
1354
1355         writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1356         writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1357
1358         bank->workaround_enabled = true;
1359
1360 update_gpio_context_count:
1361         if (bank->get_context_loss_count)
1362                 bank->context_loss_count =
1363                                 bank->get_context_loss_count(bank->dev);
1364
1365         omap_gpio_dbck_disable(bank);
1366         raw_spin_unlock_irqrestore(&bank->lock, flags);
1367
1368         return 0;
1369 }
1370
1371 static void omap_gpio_init_context(struct gpio_bank *p);
1372
1373 static int omap_gpio_runtime_resume(struct device *dev)
1374 {
1375         struct platform_device *pdev = to_platform_device(dev);
1376         struct gpio_bank *bank = platform_get_drvdata(pdev);
1377         u32 l = 0, gen, gen0, gen1;
1378         unsigned long flags;
1379         int c;
1380
1381         raw_spin_lock_irqsave(&bank->lock, flags);
1382
1383         /*
1384          * On the first resume during the probe, the context has not
1385          * been initialised and so initialise it now. Also initialise
1386          * the context loss count.
1387          */
1388         if (bank->loses_context && !bank->context_valid) {
1389                 omap_gpio_init_context(bank);
1390
1391                 if (bank->get_context_loss_count)
1392                         bank->context_loss_count =
1393                                 bank->get_context_loss_count(bank->dev);
1394         }
1395
1396         omap_gpio_dbck_enable(bank);
1397
1398         /*
1399          * In ->runtime_suspend(), level-triggered, wakeup-enabled
1400          * GPIOs were set to edge trigger also in order to be able to
1401          * generate a PRCM wakeup.  Here we restore the
1402          * pre-runtime_suspend() values for edge triggering.
1403          */
1404         writel_relaxed(bank->context.fallingdetect,
1405                      bank->base + bank->regs->fallingdetect);
1406         writel_relaxed(bank->context.risingdetect,
1407                      bank->base + bank->regs->risingdetect);
1408
1409         if (bank->loses_context) {
1410                 if (!bank->get_context_loss_count) {
1411                         omap_gpio_restore_context(bank);
1412                 } else {
1413                         c = bank->get_context_loss_count(bank->dev);
1414                         if (c != bank->context_loss_count) {
1415                                 omap_gpio_restore_context(bank);
1416                         } else {
1417                                 raw_spin_unlock_irqrestore(&bank->lock, flags);
1418                                 return 0;
1419                         }
1420                 }
1421         }
1422
1423         if (!bank->workaround_enabled) {
1424                 raw_spin_unlock_irqrestore(&bank->lock, flags);
1425                 return 0;
1426         }
1427
1428         l = readl_relaxed(bank->base + bank->regs->datain);
1429
1430         /*
1431          * Check if any of the non-wakeup interrupt GPIOs have changed
1432          * state.  If so, generate an IRQ by software.  This is
1433          * horribly racy, but it's the best we can do to work around
1434          * this silicon bug.
1435          */
1436         l ^= bank->saved_datain;
1437         l &= bank->enabled_non_wakeup_gpios;
1438
1439         /*
1440          * No need to generate IRQs for the rising edge for gpio IRQs
1441          * configured with falling edge only; and vice versa.
1442          */
1443         gen0 = l & bank->context.fallingdetect;
1444         gen0 &= bank->saved_datain;
1445
1446         gen1 = l & bank->context.risingdetect;
1447         gen1 &= ~(bank->saved_datain);
1448
1449         /* FIXME: Consider GPIO IRQs with level detections properly! */
1450         gen = l & (~(bank->context.fallingdetect) &
1451                                          ~(bank->context.risingdetect));
1452         /* Consider all GPIO IRQs needed to be updated */
1453         gen |= gen0 | gen1;
1454
1455         if (gen) {
1456                 u32 old0, old1;
1457
1458                 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1459                 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1460
1461                 if (!bank->regs->irqstatus_raw0) {
1462                         writel_relaxed(old0 | gen, bank->base +
1463                                                 bank->regs->leveldetect0);
1464                         writel_relaxed(old1 | gen, bank->base +
1465                                                 bank->regs->leveldetect1);
1466                 }
1467
1468                 if (bank->regs->irqstatus_raw0) {
1469                         writel_relaxed(old0 | l, bank->base +
1470                                                 bank->regs->leveldetect0);
1471                         writel_relaxed(old1 | l, bank->base +
1472                                                 bank->regs->leveldetect1);
1473                 }
1474                 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1475                 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1476         }
1477
1478         bank->workaround_enabled = false;
1479         raw_spin_unlock_irqrestore(&bank->lock, flags);
1480
1481         return 0;
1482 }
1483 #endif /* CONFIG_PM */
1484
1485 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1486 void omap2_gpio_prepare_for_idle(int pwr_mode)
1487 {
1488         struct gpio_bank *bank;
1489
1490         list_for_each_entry(bank, &omap_gpio_list, node) {
1491                 if (!BANK_USED(bank) || !bank->loses_context)
1492                         continue;
1493
1494                 bank->power_mode = pwr_mode;
1495
1496                 pm_runtime_put_sync_suspend(bank->dev);
1497         }
1498 }
1499
1500 void omap2_gpio_resume_after_idle(void)
1501 {
1502         struct gpio_bank *bank;
1503
1504         list_for_each_entry(bank, &omap_gpio_list, node) {
1505                 if (!BANK_USED(bank) || !bank->loses_context)
1506                         continue;
1507
1508                 pm_runtime_get_sync(bank->dev);
1509         }
1510 }
1511 #endif
1512
1513 #if defined(CONFIG_PM)
1514 static void omap_gpio_init_context(struct gpio_bank *p)
1515 {
1516         struct omap_gpio_reg_offs *regs = p->regs;
1517         void __iomem *base = p->base;
1518
1519         p->context.ctrl         = readl_relaxed(base + regs->ctrl);
1520         p->context.oe           = readl_relaxed(base + regs->direction);
1521         p->context.wake_en      = readl_relaxed(base + regs->wkup_en);
1522         p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1523         p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1524         p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1525         p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1526         p->context.irqenable1   = readl_relaxed(base + regs->irqenable);
1527         p->context.irqenable2   = readl_relaxed(base + regs->irqenable2);
1528
1529         if (regs->set_dataout && p->regs->clr_dataout)
1530                 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1531         else
1532                 p->context.dataout = readl_relaxed(base + regs->dataout);
1533
1534         p->context_valid = true;
1535 }
1536
1537 static void omap_gpio_restore_context(struct gpio_bank *bank)
1538 {
1539         writel_relaxed(bank->context.wake_en,
1540                                 bank->base + bank->regs->wkup_en);
1541         writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1542         writel_relaxed(bank->context.leveldetect0,
1543                                 bank->base + bank->regs->leveldetect0);
1544         writel_relaxed(bank->context.leveldetect1,
1545                                 bank->base + bank->regs->leveldetect1);
1546         writel_relaxed(bank->context.risingdetect,
1547                                 bank->base + bank->regs->risingdetect);
1548         writel_relaxed(bank->context.fallingdetect,
1549                                 bank->base + bank->regs->fallingdetect);
1550         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1551                 writel_relaxed(bank->context.dataout,
1552                                 bank->base + bank->regs->set_dataout);
1553         else
1554                 writel_relaxed(bank->context.dataout,
1555                                 bank->base + bank->regs->dataout);
1556         writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1557
1558         if (bank->dbck_enable_mask) {
1559                 writel_relaxed(bank->context.debounce, bank->base +
1560                                         bank->regs->debounce);
1561                 writel_relaxed(bank->context.debounce_en,
1562                                         bank->base + bank->regs->debounce_en);
1563         }
1564
1565         writel_relaxed(bank->context.irqenable1,
1566                                 bank->base + bank->regs->irqenable);
1567         writel_relaxed(bank->context.irqenable2,
1568                                 bank->base + bank->regs->irqenable2);
1569 }
1570 #endif /* CONFIG_PM */
1571 #else
1572 #define omap_gpio_runtime_suspend NULL
1573 #define omap_gpio_runtime_resume NULL
1574 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1575 #endif
1576
1577 static const struct dev_pm_ops gpio_pm_ops = {
1578         SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1579                                                                         NULL)
1580 };
1581
1582 #if defined(CONFIG_OF)
1583 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1584         .revision =             OMAP24XX_GPIO_REVISION,
1585         .direction =            OMAP24XX_GPIO_OE,
1586         .datain =               OMAP24XX_GPIO_DATAIN,
1587         .dataout =              OMAP24XX_GPIO_DATAOUT,
1588         .set_dataout =          OMAP24XX_GPIO_SETDATAOUT,
1589         .clr_dataout =          OMAP24XX_GPIO_CLEARDATAOUT,
1590         .irqstatus =            OMAP24XX_GPIO_IRQSTATUS1,
1591         .irqstatus2 =           OMAP24XX_GPIO_IRQSTATUS2,
1592         .irqenable =            OMAP24XX_GPIO_IRQENABLE1,
1593         .irqenable2 =           OMAP24XX_GPIO_IRQENABLE2,
1594         .set_irqenable =        OMAP24XX_GPIO_SETIRQENABLE1,
1595         .clr_irqenable =        OMAP24XX_GPIO_CLEARIRQENABLE1,
1596         .debounce =             OMAP24XX_GPIO_DEBOUNCE_VAL,
1597         .debounce_en =          OMAP24XX_GPIO_DEBOUNCE_EN,
1598         .ctrl =                 OMAP24XX_GPIO_CTRL,
1599         .wkup_en =              OMAP24XX_GPIO_WAKE_EN,
1600         .leveldetect0 =         OMAP24XX_GPIO_LEVELDETECT0,
1601         .leveldetect1 =         OMAP24XX_GPIO_LEVELDETECT1,
1602         .risingdetect =         OMAP24XX_GPIO_RISINGDETECT,
1603         .fallingdetect =        OMAP24XX_GPIO_FALLINGDETECT,
1604 };
1605
1606 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1607         .revision =             OMAP4_GPIO_REVISION,
1608         .direction =            OMAP4_GPIO_OE,
1609         .datain =               OMAP4_GPIO_DATAIN,
1610         .dataout =              OMAP4_GPIO_DATAOUT,
1611         .set_dataout =          OMAP4_GPIO_SETDATAOUT,
1612         .clr_dataout =          OMAP4_GPIO_CLEARDATAOUT,
1613         .irqstatus =            OMAP4_GPIO_IRQSTATUS0,
1614         .irqstatus2 =           OMAP4_GPIO_IRQSTATUS1,
1615         .irqstatus_raw0 =       OMAP4_GPIO_IRQSTATUSRAW0,
1616         .irqstatus_raw1 =       OMAP4_GPIO_IRQSTATUSRAW1,
1617         .irqenable =            OMAP4_GPIO_IRQSTATUSSET0,
1618         .irqenable2 =           OMAP4_GPIO_IRQSTATUSSET1,
1619         .set_irqenable =        OMAP4_GPIO_IRQSTATUSSET0,
1620         .clr_irqenable =        OMAP4_GPIO_IRQSTATUSCLR0,
1621         .debounce =             OMAP4_GPIO_DEBOUNCINGTIME,
1622         .debounce_en =          OMAP4_GPIO_DEBOUNCENABLE,
1623         .ctrl =                 OMAP4_GPIO_CTRL,
1624         .wkup_en =              OMAP4_GPIO_IRQWAKEN0,
1625         .leveldetect0 =         OMAP4_GPIO_LEVELDETECT0,
1626         .leveldetect1 =         OMAP4_GPIO_LEVELDETECT1,
1627         .risingdetect =         OMAP4_GPIO_RISINGDETECT,
1628         .fallingdetect =        OMAP4_GPIO_FALLINGDETECT,
1629 };
1630
1631 static const struct omap_gpio_platform_data omap2_pdata = {
1632         .regs = &omap2_gpio_regs,
1633         .bank_width = 32,
1634         .dbck_flag = false,
1635 };
1636
1637 static const struct omap_gpio_platform_data omap3_pdata = {
1638         .regs = &omap2_gpio_regs,
1639         .bank_width = 32,
1640         .dbck_flag = true,
1641 };
1642
1643 static const struct omap_gpio_platform_data omap4_pdata = {
1644         .regs = &omap4_gpio_regs,
1645         .bank_width = 32,
1646         .dbck_flag = true,
1647 };
1648
1649 static const struct of_device_id omap_gpio_match[] = {
1650         {
1651                 .compatible = "ti,omap4-gpio",
1652                 .data = &omap4_pdata,
1653         },
1654         {
1655                 .compatible = "ti,omap3-gpio",
1656                 .data = &omap3_pdata,
1657         },
1658         {
1659                 .compatible = "ti,omap2-gpio",
1660                 .data = &omap2_pdata,
1661         },
1662         { },
1663 };
1664 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1665 #endif
1666
1667 static struct platform_driver omap_gpio_driver = {
1668         .probe          = omap_gpio_probe,
1669         .remove         = omap_gpio_remove,
1670         .driver         = {
1671                 .name   = "omap_gpio",
1672                 .pm     = &gpio_pm_ops,
1673                 .of_match_table = of_match_ptr(omap_gpio_match),
1674         },
1675 };
1676
1677 /*
1678  * gpio driver register needs to be done before
1679  * machine_init functions access gpio APIs.
1680  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1681  */
1682 static int __init omap_gpio_drv_reg(void)
1683 {
1684         return platform_driver_register(&omap_gpio_driver);
1685 }
1686 postcore_initcall(omap_gpio_drv_reg);
1687
1688 static void __exit omap_gpio_exit(void)
1689 {
1690         platform_driver_unregister(&omap_gpio_driver);
1691 }
1692 module_exit(omap_gpio_exit);
1693
1694 MODULE_DESCRIPTION("omap gpio driver");
1695 MODULE_ALIAS("platform:gpio-omap");
1696 MODULE_LICENSE("GPL v2");