drivers/gpio/gpio-tb10x.c

   1 /* Abilis Systems MODULE DESCRIPTION
   2  *
   3  * Copyright (C) Abilis Systems 2013
   4  *
   5  * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
   6  *          Christian Ruppert <christian.ruppert@abilis.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/gpio/driver.h>
  26 #include <linux/slab.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqdomain.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/of.h>
  32 #include <linux/of_platform.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pinctrl/consumer.h>
  36
  37 #define TB10X_GPIO_DIR_IN       (0x00000000)
  38 #define TB10X_GPIO_DIR_OUT      (0x00000001)
  39 #define OFFSET_TO_REG_DDR       (0x00)
  40 #define OFFSET_TO_REG_DATA      (0x04)
  41 #define OFFSET_TO_REG_INT_EN    (0x08)
  42 #define OFFSET_TO_REG_CHANGE    (0x0C)
  43 #define OFFSET_TO_REG_WRMASK    (0x10)
  44 #define OFFSET_TO_REG_INT_TYPE  (0x14)
  45
  46
  47 /**
  48  * @spinlock: used for atomic read/modify/write of registers
  49  * @base: register base address
  50  * @domain: IRQ domain of GPIO generated interrupts managed by this controller
  51  * @irq: Interrupt line of parent interrupt controller
  52  * @gc: gpio_chip structure associated to this GPIO controller
  53  */
  54 struct tb10x_gpio {
  55         spinlock_t spinlock;
  56         void __iomem *base;
  57         struct irq_domain *domain;
  58         int irq;
  59         struct gpio_chip gc;
  60 };
  61
  62 static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
  63 {
  64         return ioread32(gpio->base + offs);
  65 }
  66
  67 static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
  68                                 u32 val)
  69 {
  70         iowrite32(val, gpio->base + offs);
  71 }
  72
  73 static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
  74                                 u32 mask, u32 val)
  75 {
  76         u32 r;
  77         unsigned long flags;
  78
  79         spin_lock_irqsave(&gpio->spinlock, flags);
  80
  81         r = tb10x_reg_read(gpio, offs);
  82         r = (r & ~mask) | (val & mask);
  83
  84         tb10x_reg_write(gpio, offs, r);
  85
  86         spin_unlock_irqrestore(&gpio->spinlock, flags);
  87 }
  88
  89 static int tb10x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
  90 {
  91         struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
  92         int mask = BIT(offset);
  93         int val = TB10X_GPIO_DIR_IN << offset;
  94
  95         tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
  96
  97         return 0;
  98 }
  99
 100 static int tb10x_gpio_get(struct gpio_chip *chip, unsigned offset)
 101 {
 102         struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
 103         int val;
 104
 105         val = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_DATA);
 106
 107         if (val & BIT(offset))
 108                 return 1;
 109         else
 110                 return 0;
 111 }
 112
 113 static void tb10x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 114 {
 115         struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
 116         int mask = BIT(offset);
 117         int val = value << offset;
 118
 119         tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DATA, mask, val);
 120 }
 121
 122 static int tb10x_gpio_direction_out(struct gpio_chip *chip,
 123                                         unsigned offset, int value)
 124 {
 125         struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
 126         int mask = BIT(offset);
 127         int val = TB10X_GPIO_DIR_OUT << offset;
 128
 129         tb10x_gpio_set(chip, offset, value);
 130         tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
 131
 132         return 0;
 133 }
 134
 135 static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 136 {
 137         struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
 138
 139         return irq_create_mapping(tb10x_gpio->domain, offset);
 140 }
 141
 142 static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
 143 {
 144         if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
 145                 pr_err("Only (both) edge triggered interrupts supported.\n");
 146                 return -EINVAL;
 147         }
 148
 149         irqd_set_trigger_type(data, type);
 150
 151         return IRQ_SET_MASK_OK;
 152 }
 153
 154 static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
 155 {
 156         struct tb10x_gpio *tb10x_gpio = data;
 157         u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
 158         u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
 159         const unsigned long bits = r & m;
 160         int i;
 161
 162         for_each_set_bit(i, &bits, 32)
 163                 generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
 164
 165         return IRQ_HANDLED;
 166 }
 167
 168 static int tb10x_gpio_probe(struct platform_device *pdev)
 169 {
 170         struct tb10x_gpio *tb10x_gpio;
 171         struct resource *mem;
 172         struct device_node *dn = pdev->dev.of_node;
 173         int ret = -EBUSY;
 174         u32 ngpio;
 175
 176         if (!dn)
 177                 return -EINVAL;
 178
 179         if (of_property_read_u32(dn, "abilis,ngpio", &ngpio))
 180                 return -EINVAL;
 181
 182         tb10x_gpio = devm_kzalloc(&pdev->dev, sizeof(*tb10x_gpio), GFP_KERNEL);
 183         if (tb10x_gpio == NULL)
 184                 return -ENOMEM;
 185
 186         spin_lock_init(&tb10x_gpio->spinlock);
 187
 188         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 189         tb10x_gpio->base = devm_ioremap_resource(&pdev->dev, mem);
 190         if (IS_ERR(tb10x_gpio->base))
 191                 return PTR_ERR(tb10x_gpio->base);
 192
 193         tb10x_gpio->gc.label            =
 194                 devm_kasprintf(&pdev->dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
 195         if (!tb10x_gpio->gc.label)
 196                 return -ENOMEM;
 197
 198         tb10x_gpio->gc.parent           = &pdev->dev;
 199         tb10x_gpio->gc.owner            = THIS_MODULE;
 200         tb10x_gpio->gc.direction_input  = tb10x_gpio_direction_in;
 201         tb10x_gpio->gc.get              = tb10x_gpio_get;
 202         tb10x_gpio->gc.direction_output = tb10x_gpio_direction_out;
 203         tb10x_gpio->gc.set              = tb10x_gpio_set;
 204         tb10x_gpio->gc.request          = gpiochip_generic_request;
 205         tb10x_gpio->gc.free             = gpiochip_generic_free;
 206         tb10x_gpio->gc.base             = -1;
 207         tb10x_gpio->gc.ngpio            = ngpio;
 208         tb10x_gpio->gc.can_sleep        = false;
 209
 210
 211         ret = devm_gpiochip_add_data(&pdev->dev, &tb10x_gpio->gc, tb10x_gpio);
 212         if (ret < 0) {
 213                 dev_err(&pdev->dev, "Could not add gpiochip.\n");
 214                 return ret;
 215         }
 216
 217         platform_set_drvdata(pdev, tb10x_gpio);
 218
 219         if (of_find_property(dn, "interrupt-controller", NULL)) {
 220                 struct irq_chip_generic *gc;
 221
 222                 ret = platform_get_irq(pdev, 0);
 223                 if (ret < 0) {
 224                         dev_err(&pdev->dev, "No interrupt specified.\n");
 225                         return ret;
 226                 }
 227
 228                 tb10x_gpio->gc.to_irq   = tb10x_gpio_to_irq;
 229                 tb10x_gpio->irq         = ret;
 230
 231                 ret = devm_request_irq(&pdev->dev, ret, tb10x_gpio_irq_cascade,
 232                                 IRQF_TRIGGER_NONE | IRQF_SHARED,
 233                                 dev_name(&pdev->dev), tb10x_gpio);
 234                 if (ret != 0)
 235                         return ret;
 236
 237                 tb10x_gpio->domain = irq_domain_add_linear(dn,
 238                                                 tb10x_gpio->gc.ngpio,
 239                                                 &irq_generic_chip_ops, NULL);
 240                 if (!tb10x_gpio->domain) {
 241                         return -ENOMEM;
 242                 }
 243
 244                 ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
 245                                 tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
 246                                 handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
 247                                 IRQ_GC_INIT_MASK_CACHE);
 248                 if (ret)
 249                         return ret;
 250
 251                 gc = tb10x_gpio->domain->gc->gc[0];
 252                 gc->reg_base                         = tb10x_gpio->base;
 253                 gc->chip_types[0].type               = IRQ_TYPE_EDGE_BOTH;
 254                 gc->chip_types[0].chip.irq_ack       = irq_gc_ack_set_bit;
 255                 gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
 256                 gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
 257                 gc->chip_types[0].chip.irq_set_type  = tb10x_gpio_irq_set_type;
 258                 gc->chip_types[0].regs.ack           = OFFSET_TO_REG_CHANGE;
 259                 gc->chip_types[0].regs.mask          = OFFSET_TO_REG_INT_EN;
 260         }
 261
 262         return 0;
 263 }
 264
 265 static int tb10x_gpio_remove(struct platform_device *pdev)
 266 {
 267         struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
 268
 269         if (tb10x_gpio->gc.to_irq) {
 270                 irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
 271                                         BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
 272                 kfree(tb10x_gpio->domain->gc);
 273                 irq_domain_remove(tb10x_gpio->domain);
 274         }
 275
 276         return 0;
 277 }
 278
 279 static const struct of_device_id tb10x_gpio_dt_ids[] = {
 280         { .compatible = "abilis,tb10x-gpio" },
 281         { }
 282 };
 283 MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
 284
 285 static struct platform_driver tb10x_gpio_driver = {
 286         .probe          = tb10x_gpio_probe,
 287         .remove         = tb10x_gpio_remove,
 288         .driver = {
 289                 .name   = "tb10x-gpio",
 290                 .of_match_table = tb10x_gpio_dt_ids,
 291         }
 292 };
 293
 294 module_platform_driver(tb10x_gpio_driver);
 295 MODULE_LICENSE("GPL");
 296 MODULE_DESCRIPTION("tb10x gpio.");
 297 MODULE_VERSION("0.0.1");